ARM R4F Bedienungsanleitung

Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0363E (ID013010) Cortex ™ -R4 and Cortex-R4F Revision: r1p3 T echnical Reference Manual[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. ii ID013010 Non-Confidential, Unrestricted Access Cortex-R4 and Cortex-R4F T echnical Reference Manua l Copyright © 2009 ARM Limited. All rights reserved. Release Information The following changes have been made to this book. Proprietary Notice W ords and logos marked with ® or ™[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. iii ID013010 Non-Confidential, Unrestricted Access Content s Cortex-R4 and Cortex-R4F T echnical Reference Manual Preface About this book .............. .............. ............ .............. .............. .............. ........... ........... xvii Feedback ......... ..........[...]

Contents ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. iv ID013010 Non-Confidential, Unrestricted Access 2.10 Unaligned an d mixed-endian data a ccess sup port ........... ...................... ............ ... 2-28 2.11 Big-endian instruction support ... .............. .............. .............. .............. .............[...]

Contents ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. v ID013010 Non-Confidential, Unrestricted Access 11.4 Debug register descriptions ............ ............................ .............. ............ ............... 11-10 11.5 Management registers ......... .............. .............. .............. .............. .....[...]

Contents ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. vi ID013010 Non-Confidential, Unrestricted Access A.7 Dual core interface signals .. .................... ........... .............. ........... .............. ............ A-16 A.8 Debug interface signals ....... .............................................................[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. vii ID013010 Non-Confidential, Unrestricted Access List of T ables Cortex-R4 and Cortex-R4F T echnical Reference Manual Change History .............. ............................ .......................................... ............................ ...... ......... ii Table 1-1 Con[...]

List of Tables ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. viii ID013010 Non-Confidential, Unrestricted Access Table 4-16 Instruction Set Attributes Register 2 bit functions ......... .............. .............. ............... .............. ... 4-29 Table 4-17 Instruction Set Attributes Register 3 bit functions ......... .[...]

List of Tables ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. ix ID013010 Non-Confidential, Unrestricted Access Table 8-6 Tag RAM bit de scriptions, no parity or ECC .. .......... .............. ........... .............. ........... .............. . 8 - 2 6 Table 8-7 Cache sizes and tag RAM organization .......... ..............[...]

List of Tables ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. x ID013010 Non-Confidential, Unrestricted Access Table 11-6 CP14 debug register map ............... ........ .............. ........... .............. ........... ............... ...... .. ....... 11-10 Table 11-7 Debug ID Register f unctions ................ .........[...]

List of Tables ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xi ID013010 Non-Confidential, Unrestricted Access Table 14-5 QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavio r ............ ........... ............ 14-9 Table 14-6 Media data-processing instruct ions cycle timing behavior ............. .............. ...[...]

List of Tables ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xii ID013010 Non-Confidential, Unrestricted Access Table A-18 FPU signals ......................... .............. ...... .............. ........... .............. ........... ........... ............ ......... A-23 Table C-1 Differences between issue B and issue C ...[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xiii ID013010 Non-Confidential, Unrestricted Access List of Figures Cortex-R4 and Cortex-R4F T echnical Reference Manual Key to timing diagram conventions .................... .............. ........... .............. ............ .............. ........ . xix Figure 1-1 Processor bl[...]

List of Figures ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xiv ID013010 Non-Confidential, Unrestricted Access Figure 4-16 Memory Model Feature Reg ister 1 format ...... .................... ........... .............. ............ .............. . .. 4-23 Figure 4-17 Memory Model Feature Reg ister 2 format ...... .............[...]

List of Figures ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xv ID013010 Non-Confidential, Unrestricted Access Figure 11-3 Debug ROM Address Reg ister format ............ .................... .............. ........... .............. ............ . 11-1 2 Figure 11-4 Debug Self Address Offse t Register format .. ...............[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xvi ID013010 Non-Confidential, Unrestricted Access Preface This preface introduces the Cortex-R4 and Cortex-R4F T echnical Reference Manual . It contains the following sections: • About this book on page xvii • Feedback on page xxi.[...]

Preface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xvii ID013010 Non-Confidential, Unrestricted Access About this book This is the T echnical Refer ence Manua l (TRM) for the Cortex-R4 and Cortex-R4F processors. In this book the generic term processor means both the Cortex-R4 and Cortex-R4F processors. Any differences between[...]

Preface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xviii ID013010 Non-Confidential, Unrestricted Access Read this for a descriptio n of the Memory Pr otection Unit (MPU) and the access permissions process. Chapter 8 Level One Memory System Read this for a description of the Level One (L1) memory system. Chapter 10 Power Contr[...]

Preface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xix ID013010 Non-Confidential, Unrestricted Access monospace Denotes text that you can enter at the keyboard, such as comma nds, file and program names, and source code. monospace Denotes a permitted abbreviation for a com mand or option. Y ou can enter the underlined text in[...]

Preface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xx ID013010 Non-Confidential, Unrestricted Access Prefix R Denotes AXI read data channel signals. Prefix W Denotes AXI write data channel signals. Further reading This section lists publi cations by ARM and by third parties. See http://infocenter.arm.com for access to ARM doc[...]

Preface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xxi ID013010 Non-Confidential, Unrestricted Access Feedback ARM welcomes feedback o n this product and its documentation. Feedback on this produc t If you have any comments or suggestions about this product, contact yo ur supplier and give: • The product name. • The produ[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-1 ID013010 Non-Confidential, Unrestricted Access Chapter 1 Introduction This chapter introduces the pr ocessor and its features. It c ontains the following sections: • About the pr ocessor on p age 1-2 • About the ar chitecture on page 1-3 • Components of the pr ocessor on pa[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-2 ID013010 Non-Confidential, Unrestricted Access 1.1 About the processor The processor is a mid-range CPU fo r us e in deeply-embedded systems. The features of th e processor include: • An integer unit with integral EmbeddedICE-R T lo gic. • High-speed Advanced Mic[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-3 ID013010 Non-Confidential, Unrestricted Access 1.2 About the architecture The processor implements th e ARMv7-R architecture and AR Mv7 debug architecture. In addition, the Cortex-R4F processor implements the VFPv3-D16 architecture. This includes the VFPv3 instr ucti[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-4 ID013010 Non-Confidential, Unrestricted Access 1.3 Component s of the processor This section describes the main components of the processor: • Data Pr ocessing Unit on page 1-5 • Load/stor e unit on page 1-5 • Pr efetch unit on page 1-5 • L1 memory system on [...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-5 ID013010 Non-Confidential, Unrestricted Access 1.3.1 Dat a Processing Unit The DPU holds most of the program-visible stat e of the processor , such as general-purpose registers, status registers and control registers. It decodes and executes instructions, operating o[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-6 ID013010 Non-Confidential, Unrestricted Access Instruction and da t a caches Y ou can configure the processor to include separate instruction and data caches. The caches have the following features: • Support for independent confi guration of the inst ruction and d[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-7 ID013010 Non-Confidential, Unrestricted Access • 512KB •1 M B •2 M B •4 M B •8 M B . The TCMs are external to the processor . This provides flexibili ty in optimizing the TCM subsystem for performance, power, and RAM type. The INITRAMA and INITRAMB pins ena[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-8 ID013010 Non-Confidential, Unrestricted Access 1.3.6 Deb ug The processor has a CoreSight compliant Advanced Peripheral Bus version 3 (APBv3) d ebug interface. This permits system access to debug resources, for example, the setting of watchpoints and b reakpoints. Th[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-9 ID013010 Non-Confidential, Unrestricted Access The EmbeddedICE-R T logic supports two modes of debug operation: Halt mode On a debug event, such as a breakpoint or watchpoin t, the debug logic stops the processor and forces it into debug state. Th is enables you to e[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-10 ID013010 Non-Confidential, Unrestricted Access RFE Return from exception us ing data from the stack. CPS Change processor state, such as interr upt mask setting and clearing, and mo de changes.[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-11 ID013010 Non-Confidential, Unrestricted Access 1.4 External interfaces of the processor The processor has the following interfaces for external access: • APB Debug interface • ETM interface • T est interface . For more information on these interfaces and how t[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-12 ID013010 Non-Confidential, Unrestricted Access 1.5 Power management The processor includes several microarchitect ural features to re duce energy consumption: • Accurate branch and return prediction, reduci ng the number of incorrect instruction fetch and decode o[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-13 ID013010 Non-Confidential, Unrestricted Access 1.6 Configurable options T able 1- 1 shows the features of the proce ssor that can be conf igured using either build-configuratio n or pin-configuration. See Pr oduct documentation, desig n flow , and ar chitectur e on [...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-14 ID013010 Non-Confidential, Unrestricted Access BTCM No BTCM ports - Build and pin One BTCM port (B0TCM) No error checking Parity error checking 32-bit ECC error checking 64-bit ECC error checking Build 4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, [...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-15 ID013010 Non-Confidential, Unrestricted Access T able 1-2 describes the various features that can be p in-configured to be either enab led or disabled at reset. It also shows which CP15 regi ster field provides softwa re confi guration of the feature when the proces[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-16 ID013010 Non-Confidential, Unrestricted Access TCM external errors A TCM external error enable A TCMECEN BTCM external error enable, for B0TC M and B1TCM independently B0TCMECEN/ B1TCMECEN TCM load/store-64 (read-modify-write) behavior A TCM load/store-64 enable b A[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-17 ID013010 Non-Confidential, Unrestricted Access 1.7 Execution pipeline st ages The following stages make up the pipeline: • the Fetch stages • the Decode stages • an Issue stage • the three or four Execution stages. Figure 1-2 shows the Fetch and Decode pipel[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-18 ID013010 Non-Confidential, Unrestricted Access Figure 1-4 Cortex-R4F I ssue and Execution p ipeline st ages The names of the common pipeline stages and their functions are: Iss Register read and instructi on issue to execute stages. Ex Execute stages. Wr W rite-back[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-19 ID013010 Non-Confidential, Unrestricted Access 1.8 Redundant core comp arison The processor can be implemented with a second, redundant copy of most of the logic. This second core shares the input pins and the cache RAMs of the master core, so only one set of cache [...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-20 ID013010 Non-Confidential, Unrestricted Access 1.9 T est features The processor is delivered as fu lly-synthesizable R TL and is a fu lly-static design. Scan-chain s and test wrappers for production test can be inserted int o the design by the synthesi s tools durin[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-21 ID013010 Non-Confidential, Unrestricted Access 1.10 Product documentation, de sign flow , and architecture This section describes the content o f the product documents, how they relate to the desi gn flow , and the relevant architectural standards and protocols. Not[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-22 ID013010 Non-Confidential, Unrestricted Access 3. Programming. The system programme r develops the software required to co nfigure and initialize the processor, and possibly tests the required application software on the processor . Each of these stages can be perfo[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-23 ID013010 Non-Confidential, Unrestricted Access • The properties of memory accesses . • The debug architecture you can use to debug the processor . The TRM gives more informatio n about the implem ented debug features. The Cortex-R4 processor implements the ARMv7[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-24 ID013010 Non-Confidential, Unrestricted Access 1.1 1 Product revision information This manual is for major revision 1 of the processor . At the time of release, this includes the r1p0, r1p1, r1p2, and r1p3 releases, althou gh th e vast majority of the information in[...]

Introduction ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-25 ID013010 Non-Confidential, Unrestricted Access T able 1-3 shows the mappings between th ese various numbers, for all releases. 1.1 1.2 Architectural information The ARM Architecture includes a number of re gisters that identify the version of the architecture and so[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-1 ID013010 Non-Confidential, Unrestricted Access Chapter 2 Programmer ’ s Model This chapter describes the pro cessor registers and provides an overview for programming the microprocessor . It contains the following sections: • About the pr ogrammer ’ s model on page 2-2 • [...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-2 ID013010 Non-Confidential, Unrestricted Access 2.1 About the programmer ’ s model The processor implements the ARMv 7-R architecture that provides: • the 32-bit ARM instruction set • the extended Thumb instruction set introduced in ARMv6T2, that uses Th[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-3 ID013010 Non-Confidential, Unrestricted Access 2.2 Instruction set st ates The processor has two instruction set states: ARM state The processor executes 32-bit, word-alig ned ARM instructions in this state. Thumb st ate The processor executes 32-bit and 16-b[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-4 ID013010 Non-Confidential, Unrestricted Access 2.3 Operating modes In each state there are se ven modes of operation: • User (USR) mode is the usual mode for the execution of ARM or Thumb programs. It is used for executing most application programs. • Fas[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-5 ID013010 Non-Confidential, Unrestricted Access 2.4 Dat a types The processor supports these data types: • doubleword, 64-bit • word, 32-bit • halfword, 16-bit • byte, 8-bit. Note • When any of these types are described as unsigned, the N-bit data va[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-6 ID013010 Non-Confidential, Unrestricted Access 2.5 Memory format s The processor views memory as a linear collectio n of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first st o red word, and bytes 4-7 hold the second stored wor[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-7 ID013010 Non-Confidential, Unrestricted Access 2.6 Registers The processor has a total of 37 program registers: • 31 general-purpose 32-bit registers • six 32-bit status registers. These registers are not all accessi ble at the same time. The pro cessor s[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-8 ID013010 Non-Confidential, Unrestricted Access For more information, see the ARM Architectur e Refer ence Manual . In Privileged modes, another regist er , the Saved Pr ogram S tatus Register (SPSR), is accessible. This contains the condition code flags, stat[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-9 ID013010 Non-Confidential, Unrestricted Access Figure 2-3 Re gister organi zation Note For 16-bit Thumb instructions, the high registers, R8–R 15, are not part of the standard register set. Y ou can use special variants of the MOV instruction to transfer a [...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-10 ID013010 Non-Confidential, Unrestricted Access 2.7 Program st atus registers The processor contains one CPSR and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • [...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-11 ID013010 Non-Confidential, Unrestricted Access • MRRC2 • PLD • RFE • SETEND • SRS • STC2 . In Thumb state, the processor can only execute the Branch in struction conditionally . Other instructions can be m ade conditional by placing them in t he [...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-12 ID013010 Non-Confidential, Unrestricted Access For more information on the operation of the IT execution st ate bits, see the ARM Ar chitectur e Refer ence Manual . 2.7.4 T he J bit The J bit in the CPSR returns 0 when read. Note Y ou cannot use an MSR to ch[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-13 ID013010 Non-Confidential, Unrestricted Access Note GE bit is 1 if A op B ≥ C, otherwise 0. The SEL instruction uses GE[3:0] to select which source register supplies each byte of its result. Note • For unsigned operations, the usual ARM rules det ermine [...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-14 ID013010 Non-Confidential, Unrestricted Access 2.7.1 1 The M bi t s M[4:0] are the mode bits. These bits determ ine the processor operati ng mode as T able 2-3 shows. Note • In Privileged mode an il legal value programme d into M[4:0] causes the processor [...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-15 ID013010 Non-Confidential, Unrestricted Access Bits in Figure 2-4 on page 2-10 that are in this category are A, I, F , and M[4:0].[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-16 ID013010 Non-Confidential, Unrestricted Access 2.8 Exceptions Exceptions are taken whenever the normal flow of a program must temp orarily halt, for example, to service an interrupt from a peripheral. Before attemp ting to handle an exception, the processor [...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-17 ID013010 Non-Confidential, Unrestricted Access T aking an exception When taking an excepti on the processo r: 1. Preserves the address of the next instructio n in the appropriate LR. When the exception is taken from: ARM state The processor writes the addr e[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-18 ID013010 Non-Confidential, Unrestricted Access Because SVC handlers are always expected to return after the SVC instruction, th e IT execution state bits are automatically advanc ed when an exception is taken prior to copying the CPSR into the SPSR. 2.8.2 Re[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-19 ID013010 Non-Confidential, Unrestricted Access Y ou can disable IRQ exception s within a Privileged mode by setting the CPSR.I bit to b1. See Pr ogram status r egisters on page 2-10. IRQ interrupt s are au tomatically disabled wh en an IRQ occurs, by setting[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-20 ID013010 Non-Confidential, Unrestricted Access LIL behavior enables accesses to Normal memo ry , including multiword accesses and external accesses, to be abandoned part-w ay through execution so that the processor can react to a pending interrupt fast er th[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-21 ID013010 Non-Confidential, Unrestricted Access Figure 2-5 Interrupt entry sequenc e For information on the I and F bits that Figure 2-5 shows, see Pr ogram status r egisters on page 2-10. For information on the V and VE bits that Figure 2-5 show s, see c1, S[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-22 ID013010 Non-Confidential, Unrestricted Access 2.8.4 Abo rts When the processor's memory system cannot co mplete a memory access successfully , an abort is generate d. Aborts can occur for a number of re asons, for example: • a permission fault indica[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-23 ID013010 Non-Confidential, Unrestricted Access Imprecise abort s An imprecise abort, also known as an asynch ronous abort, is one for which the exception is taken on a later instruction to the instruction that generated the aborting memory access. The abort [...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-24 ID013010 Non-Confidential, Unrestricted Access • perform the appropriate data transfers on behalf of the aborted instructi on and return to the instruction after the abandoned instru ction • treat the error as fatal and terminate the process. If the abor[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-25 ID013010 Non-Confidential, Unrestricted Access 2.8.6 Undefined instruction When an instru ction is encountered whi ch is UNDEFINED, or is for the VFP when the VFP is not enabled, the processor takes the Undefined instruction exception. Software can use this [...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-26 ID013010 Non-Confidential, Unrestricted Access Note If the EmbeddedICE-R T logic is configu red into Halt debug-mode, a breakpoint instruction causes the processor to enter debug state. See Halting debug-mode debugging on page 11-3. 2.8.8 E xception vectors [...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-27 ID013010 Non-Confidential, Unrestricted Access 2.9 Acceleration of execution environment s Because the ARMv7-R archit ecture requires Jazelle ® software compatibility , t hree Jazelle registers are implemented in the processor . T able 2-7 shows the Jazelle[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-28 ID013010 Non-Confidential, Unrestricted Access 2.10 Unaligned and mixed- endian dat a access support The processor supports unaligned memory accesses. Unaligned memory accesses was introduced with ARMv6. Bit [22] of c1, Control Register is always 1. The proc[...]

Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-29 ID013010 Non-Confidential, Unrestricted Access 2.1 1 Big-endian instruction support The processor supports little-endian or big-endi an instruction format, and is depe ndent on the setting of the CFGIE pi n . T h i s i s r e f l e c t e d i n bi t [ 3 1 ] o [...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 3-1 ID013010 Non-Confidential, Unrestricted Access Chapter 3 Processor Initialization, Reset s, and Clocking Before you can run application software on the processor, it must be reset and initialized, including loading the appropriate software-c onfiguration. This chapter descri bes [...]

Processor Initialization, Resets, and Clocking ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 3-2 ID013010 Non-Confidential, Unrestricted Access 3.1 Initialization Most of the architectural register s in the processor , such as r0 -r14, and s0 -s31 and d0-d15 when floating-point is included, are not reset. Because of this, you mu[...]

Processor Initialization, Resets, and Clocking ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 3-3 ID013010 Non-Confidential, Unrestricted Access • enable the FPU by setting the EN-b it in the FPEXC register , see Floating-Point Exception Register , FPEXC on page 12-7. Note Floating-poin t logic is only avail a ble with the Cort[...]

Processor Initialization, Resets, and Clocking ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 3-4 ID013010 Non-Confidential, Unrestricted Access DMA into TCM The SoC includes a Dir ect Memory Access (DMA) device that reads data from a ROM, and writes it to the TC Ms through the AX I slave interface. Write to TCM dir ectly fr om d[...]

Processor Initialization, Resets, and Clocking ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 3-5 ID013010 Non-Confidential, Unrestricted Access • T urn on 64-bit store beha vior using CP15. See c15, Secondary Auxiliary Control Register on page 4-41. • W rite to the TCM using any store instruc tions, or any AXI writ e transac[...]

Processor Initialization, Resets, and Clocking ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 3-6 ID013010 Non-Confidential, Unrestricted Access 3.2 Reset s The processor has the following reset inputs: nRESET This signal is the main p rocessor reset th at initiali zes the majori ty of the processor logic. PRESETDBGn This signal [...]

Processor Initialization, Resets, and Clocking ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 3-7 ID013010 Non-Confidential, Unrestricted Access 3.3 Reset modes The reset signals in the processor enable you to re set different parts of the design independently . T able 3-1 shows the reset signals, and the combin ations and p ossi[...]

Processor Initialization, Resets, and Clocking ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 3-8 ID013010 Non-Confidential, Unrestricted Access 3.3.2 Proce ssor reset A processor or warm reset initializes the majority of the processor , excluding the EmbeddedICE-R T logic. Processor reset is typical ly used for resetting a syste[...]

Processor Initialization, Resets, and Clocking ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 3-9 ID013010 Non-Confidential, Unrestricted Access 3.4 Clocking The processor has two functional clock inputs. Externally to the processor , you must connect together CLKIN and FREECLKIN . In addition, there is the PCLKDBG clock for the [...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-1 ID013010 Non-Confidential, Unrestricted Access Chapter 4 System Control Coprocessor This chapter describes the purpose of the system control coprocessor , its structure, operation, and how to use it. It contains the following sections: • About the system contr ol copr ocessor o[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-2 ID013010 Non-Confidential, Unrestricted Access 4.1 About the system control coprocessor This section gives an overview of the system control coprocesso r . For more info rmation of the registers in the system control coprocessor , see System contr ol co[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-3 ID013010 Non-Confidential, Unrestricted Access T able 4-1 System contro l coprocessor regist er functions Function Register/operation Reference to descriptio n System control and configuration Control c1, System Contr ol Register on page 4-35 Auxiliary [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-4 ID013010 Non-Confidential, Unrestricted Access 4.1.2 System control and configura tion The system control and configuration regist ers provide ov erall management of: • memory functionality • interrupt behavior • exception handling • program flo[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-5 ID013010 Non-Confidential, Unrestricted Access 4.1.3 MPU control and configuratio n The MPU control and configuration registers: • control program access to memory • designate areas of memory as either: — Normal, Non-cacheable — Normal, Cacheabl[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-6 ID013010 Non-Confidential, Unrestricted Access Figure 4-3 Cache contr ol and configuration register s Cache control and configuration registers behave as: • a set of numbers, with values that describe aspects of the caches • a set of bits that enab [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-7 ID013010 Non-Confidential, Unrestricted Access Figure 4-5 System perfor mance monitor registers System performance monito ring counts system events, such as cache misses, pipeline stalls, and other related features to enable system develope rs to profil[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-8 ID013010 Non-Confidential, Unrestricted Access Y ou can only change the cache size to a size su pported by the cache RAMs implemented in your design.[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-9 ID013010 Non-Confidential, Unrestricted Access 4.2 System control coprocessor registers This section describes all of the registers in the system control coprocessor . The section presents a summary of the registers an d descriptions in regi ster order [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-10 ID013010 Non-Confidential, Unrestricted Access c8-c15 0-7 Undefined - - - 1 c0 0 Current Cache Size ID Read-only - cd page 4-32 1 Current Cache Level ID Read-only 0x09000003 c page 4-34 2-7 Undefined - - - c1-c15 0-7 2 c0 0 Cache Size Selec tion Read/w[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-11 ID013010 Non-Confidential, Unrestricted Access 1-7 Undefined - - - c3-c15 1-7 c7 0 c0 0-3 Undefined - - - 4 NOP , previously W ait For Interrupt W rite-only - page 4-54 5-7 Undefined - - - c1-c4 0-7 c5 0 Invalidate entire instruction cache W rite-only [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-12 ID013010 Non-Confidential, Unrestricted Access c7 0 c 1 1 1 Clean data cache line by physical address to Point-of-Uni fication W rite-only - page 4-55 2-7 Undefined - - - c12-c13 0-7 c14 0 1 Clean and inva lidate data cache line by physical address to [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-13 ID013010 Non-Confidential, Unrestricted Access c14 0 User Enable Read/write 0x00000000 page 6-15 1 Interrupt Enable Set Read /write Unpredictable page 6-16 c14 2 Interrupt Enable Clear Read/write Unpredictable page 6-17 3-7 Undefined - - - c15 0-7 c10 [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-14 ID013010 Non-Confidential, Unrestricted Access 4.2.2 c 0, Main ID Regist er The Main ID Register returns the device ID code that contains info rmation about th e processor . The Main ID Register is: • a read-only register • accessible in Privileged[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-15 ID013010 Non-Confidential, Unrestricted Access The contents of the Main ID Register depend on the specific implemen tation. T able 4-3 shows how the bit values correspond with the Main ID Register function s. Note If an MRC instruction is executed with[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-16 ID013010 Non-Confidential, Unrestricted Access T able 4-4 shows how the bit values correspond wit h the Cache T ype Register functions. T o access the Cache T ype Re gister , read CP15 with: MRC p15, 0, <Rd>, c0, c0, 1 ; Returns cache details 4.2[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-17 ID013010 Non-Confidential, Unrestricted Access T o access the TCM T ype Register , read CP15 with: MRC p15, 0, <Rd>, c0, c0, 2 ; Returns TCM type register Note • The A TCM and BTCM fields in the TCM T ype Register occupy the same space as the I[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-18 ID013010 Non-Confidential, Unrestricted Access MRC p15, 0, <Rd>, c0, c0, 4 ; Returns MPU details 4.2.6 c0, Multiprocessor ID Register The Multiprocessor ID Register enable s cores to be recognized and characterized within a multiprocessor system.[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-19 ID013010 Non-Confidential, Unrestricted Access T able 4-7 shows how th e bit values correspond wi th the Processor Feature Register 0 functi ons. T o access the Processor Feature Re gister 0 read CP15 wit h: MRC p15, 0, <Rd>, c0, c1, 0 ; Read Pro[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-20 ID013010 Non-Confidential, Unrestricted Access T o access the Processor Feature Re gister 1 read CP15 wit h: MRC p15, 0, <Rd>, c0, c1, 1 ; Read Processor Feature Register 1 4.2.8 c 0, Debug Featur e Register 0 The Debug Feature Register 0 provide[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-21 ID013010 Non-Confidential, Unrestricted Access T o access the Debug Feature Register 0 read CP15 with: MRC p15, 0, <Rd>, c0, c1, 2 ; Read Debug Feature Register 0 4.2.9 c0, Auxiliary Feature Register 0 The Auxiliary Feature Register 0 provides ad[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-22 ID013010 Non-Confidential, Unrestricted Access Figure 4-15 Memory Model Feature Register 0 form at T able 4-10 shows how the bit values correspond with the Memory Model Feature Register 0 functions. T o access the Memory Model Feat ure Register 0 read [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-23 ID013010 Non-Confidential, Unrestricted Access Figure 4-16 Memory Model Feature Register 1 form at T able 4-1 1 shows how the bit values correspond with the Memory Model Feature Register 1 functions. T o access the Memory Model Feat ure Register 1 read[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-24 ID013010 Non-Confidential, Unrestricted Access c0, Memory Model Feature Regist er 2, MMFR2 The Memory Model Feature Regist er 2 provides information about the memo ry model, memory management, and cache support op erations of the processor . The Memory[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-25 ID013010 Non-Confidential, Unrestricted Access T o access the Memory Model Feat ure Register 2 read CP15 with: MRC p15, 0, <Rd>, c0, c1, 6 ; Read Memory Model Feature Register 2. c0, Memory Model Feature Regist er 3, MMFR3 The Memory Model Featur[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-26 ID013010 Non-Confidential, Unrestricted Access 4.2.1 1 Instruction Set Attributes Regist ers There are eight Instruction Set A ttributes Registers, ISAR0 to ISAR7, but three of these are currently unused. This section describes: • c0, Instruction Set[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-27 ID013010 Non-Confidential, Unrestricted Access T o access the Instruction Set Attributes Register 0, read CP15 with: MRC p15, 0, <Rd>, c0, c2, 0 ; Read Instruction Set Attributes Register 0 c0, Instruction Se t Attributes Register 1, ISAR1 The In[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-28 ID013010 Non-Confidential, Unrestricted Access T able 4-15 shows how the bit values corresp ond wi th the Instruction Set Attributes Register 1 functions. T o access the Instruction Set Attri butes Register 1 read CP15 with: MRC p15, 0, <Rd>, c0,[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-29 ID013010 Non-Confidential, Unrestricted Access Figure 4-21 shows the bit arrangement for Instructio n Set Attributes Register 2. Figure 4-21 Instruction Set Attributes Regi ster 2 format T able 4-16 shows how the bit values corresp ond wi th the Instru[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-30 ID013010 Non-Confidential, Unrestricted Access c0, Instruction Se t Attributes Register 3, ISAR3 The Instruction Set Attributes Register 3 p rovides information about the instruction set that the processor supports beyond the basic set. The Instruction[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-31 ID013010 Non-Confidential, Unrestricted Access T o access the Instruction Set Attri butes Register 3 read CP15 with: MRC p15, 0, <Rd>, c0, c2, 3 ; Read Instruction Set Attributes Register 3 c0, Instruction Se t Attributes Register 4, ISAR4 The In[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-32 ID013010 Non-Confidential, Unrestricted Access T o access the Instruction Set Attri butes Register 4 read CP15 with: MRC p15, 0, <Rd>, c0, c2, 4 ; Read Instruction Set Attributes Register 4 c0, Instructio n Set Attributes Regis ters 5-7 The Instr[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-33 ID013010 Non-Confidential, Unrestricted Access Figure 4-24 Current Cache Size Iden tification Register format T able 4-19 shows how the bit values correspond with the Cu rrent C ache Size Identification Register . The LineSize field is encoded as 2 les[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-34 ID013010 Non-Confidential, Unrestricted Access T o access the Current Cache Size Identif ication Register read CP15 with: MRC p15, 1, <Rd>, c0, c0, 0 ; Read Current Cache Size Identification Register 4.2.13 c0, Current Cache Level ID Regist er Th[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-35 ID013010 Non-Confidential, Unrestricted Access 4.2.14 c0, Cache Size Se lection Regi ster The Cache Size Selection Register holds the value that the processo r uses to select the Current Cache Size Identificati on Register to use. The Cache Size Select[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-36 ID013010 Non-Confidential, Unrestricted Access Figure 4-27 System Cont rol Register format T able 4-23 shows the purpos es of the individual bits in the System Contro l Register . TRE IE TE AFE NMFI SBZ EE VE Z RR SBZ SBO BR SBO FI DZ SBZ M 31 30 29 28[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-37 ID013010 Non-Confidential, Unrestricted Access T o use the System Control Register ARM r ecommends that you us e a read-modify-write technique. T o access the System Control Register , read or write CP15 w ith: MRC p15, 0, <Rd>, c1, c0, 0 ; Read [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-38 ID013010 Non-Confidential, Unrestricted Access Attempts to read or write the System Contro l Re gister from User mode results in an Und efined exception. 4.2.16 Aux iliary Control Reg isters The Auxiliary Control Registers control: • branc h predicti[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-39 ID013010 Non-Confidential, Unrestricted Access [28] DIADI a Case A dual issue control: 0 = Enabled. This is the reset val ue. 1 = Disabled. [27] B1TCMPCEN B1TCM parity or ECC check enable: 0 = Disabled 1 = Enabled. The primary input P ARECCENRAM[2] b d[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-40 ID013010 Non-Confidential, Unrestricted Access [17] RSDIS Return stack disable: 0 = Normal return stack operati on. This is the reset value. 1 = Return stack disabled. [16:15] BP This field controls the branch prediction policy: b00 = Normal operation.[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-41 ID013010 Non-Confidential, Unrestricted Access T o access the Auxiliary Control Regi ster , read or wr ite CP15 w ith: MRC p15, 0, <Rd>, c1, c0, 1 ; Read Auxiliary Control Register MCR p15, 0, <Rd>, c1, c0, 1 ; Write Auxiliary Control Regis[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-42 ID013010 Non-Confidential, Unrestricted Access Figure 4-29 Secondary Auxiliar y Control Register form at T able 4-25 shows ho w the bit values correspond with the Secondary Auxiliary Con trol Register functions. Reserved 31 22 21 19 18 17 16 15 14 13 1[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-43 ID013010 Non-Confidential, Unrestricted Access [16] DOOFMACS Out-of-order FMACS control. c 0 = Enabled. This is the reset value. 1 = Disabled. [15:14] Reserved SBZ. [13] IXC Floating-point inexact exception output mask. c 0 = Mask floating-point in exa[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-44 ID013010 Non-Confidential, Unrestricted Access T o access the Secondary Auxiliary Contro l Register , read or write CP15 with: MRC p15, 0, <Rd>, c15, c0, 0 ; Read Secondary Auxiliary Control Register MCR p15, 0, <Rd>, c15, c0, 0 ; Write Sec[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-45 ID013010 Non-Confidential, Unrestricted Access T able 4-26 shows how the bit values corresp ond with the Coprocessor Access Register functions. T o access the Coprocessor Access Regi ster , read or write CP15 with: MRC p15, 0, <Rd>, c1, c0, 2 ; R[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-46 ID013010 Non-Confidential, Unrestricted Access The Data Fault Status Register is: • a read/write register • accessible in Privileged mode only . Figure 4-31 shows the bit arrangement in the Data Fau lt Status Register . Figure 4-31 Data Fault St at[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-47 ID013010 Non-Confidential, Unrestricted Access Figure 4-32 Instruction Fault St atus Register format T able 4-29 shows how the bit values corresp ond with the Instruction Fault Status Register functions. T o access the IFSR read or write CP15 with: MRC[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-48 ID013010 Non-Confidential, Unrestricted Access Figure 4-33 Auxiliary fault status registers format T able 4-30 shows ho w the bit values correspond with the auxiliary fault status register functi ons. T o access the auxiliary fault status re gisters, r[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-49 ID013010 Non-Confidential, Unrestricted Access The Data Fault Address Register bits [31: 0] contain the address wh ere the precise abort occurred. T o access the DF AR read or write CP15 with: MRC p15, 0, <Rd>, c6, c0, 0 ; Read Data Fault Address[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-50 ID013010 Non-Confidential, Unrestricted Access CP15, c9 sets the locatio n of the TCM base address. For more information see c9, BTCM Region Register on page 4-57 and c9, A TCM Region Register on page 4-58. c6, MPU Region Base Address Registers The MPU[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-51 ID013010 Non-Confidential, Unrestricted Access Figure 4-35 MPU Region Size and Enable Reg isters format T able 4-32 shows how the bit values correspond with the MPU Region Size and Enable Registers. T o access an MPU Region Size and Enable Register , r[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-52 ID013010 Non-Confidential, Unrestricted Access The MPU Region Access Control Registers are: • read/write registers • accessible in Privileged mode only . Figure 4-36 shows the arrangement of bits in the register . Figure 4-36 MPU Region Acces s Con[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-53 ID013010 Non-Confidential, Unrestricted Access T o access the MPU Region Access Contro l Registers read or write CP15 with: MRC p15, 0, <Rd>, c6, c1, 4 ; Read Region access control Register MCR p15, 0, <Rd>, c6, c1, 4 ; Write Region access [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-54 ID013010 Non-Confidential, Unrestricted Access 4.2.20 Ca che ope rations The purpose of c7 is to manage the associat ed caches. The maintenance operations are formed into two management groups: • Set and W ay: — clean — invalidate — clean and i[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-55 ID013010 Non-Confidential, Unrestricted Access Figure 4-38 Cache operatio ns In addition to the register c7 cache manage ment functions in this processor , an Invalidate all data caches operation is provided as a c15 operation. For convenience, that c1[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-56 ID013010 Non-Confidential, Unrestricted Access Figure 4-39 c7 format for Set and W ay T able 4-36 shows how t he bit values correspond with the Cache Operation functions for Set and W ay format operations. T able 4-37 shows the cache sizes and the resu[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-57 ID013010 Non-Confidential, Unrestricted Access T able 4-38 sh ows how the bit values correspond wi th the address format fo r invalidate and clean operations . Dat a Synchronization Ba rrier operation The purpose of the Data Synchronization Barrier ope[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-58 ID013010 Non-Confidential, Unrestricted Access Figure 4-41 BTCM Region Registers T able 4-39 shows how the bit values correspond with the BTCM Region Register . T o access the BTCM Region Register , read or write CP15 with: MRC p15, 0, <Rd>, c9, [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-59 ID013010 Non-Confidential, Unrestricted Access Figure 4-42 A TCM Region Register s T able 4-40 shows how the bit values correspond with the A TCM Regio n Register . T o access the A TC M Region Regist er , read or write CP15 with: MRC p15, 0, <Rd>[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-60 ID013010 Non-Confidential, Unrestricted Access The Slave Port Control Register is: • a read/write register • accessible in User and Privileged mode. Figure 4-43 shows the arrangement of bits in the register . Figure 4-43 Slave Port Control Register[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-61 ID013010 Non-Confidential, Unrestricted Access The Context ID Register , bits [31:0] contain the process ID number . T o use the Context ID Register , read or write CP15 with: MRC p15, 0, <Rd>, c13, c0, 1 ; Read Context ID Register MCR p15, 0, &l[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-62 ID013010 Non-Confidential, Unrestricted Access 4.2.28 V alidation R egisters The processor implements a set of validation registers. This section describes: • c15, nV AL IRQ Enable Set Register • c15, nV AL FIQ Enable Set Register on page 4-63 • [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-63 ID013010 Non-Confidential, Unrestricted Access On reads, this register returns the current set ting. On writ es , interrupt requests can be enabled. If an interrupt request has been enabled it is di sabled by writing to t h e nV AL IRQ Enable Clear Reg[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-64 ID013010 Non-Confidential, Unrestricted Access c15, nV AL Reset Enable Set Register The nV AL Reset Enable Set Register enables any of the PMC Registers, PMC0-PMC 2, and CCNT , to generate a reset request on overflow . If enabled, the reset request is [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-65 ID013010 Non-Confidential, Unrestricted Access The nV AL Debug Request Enable Set Register is: • A read/write register . • Always accessible in Privileged mode. The USEREN Register determines access, see c9, User Enable Register on page 6-15. Figur[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-66 ID013010 Non-Confidential, Unrestricted Access Figure 4-48 nV AL IR Q Enable Clear Register format T able 4-46 shows how the bit values correspond with the nV AL IRQ Enable Clear Register . T o access the nV AL IRQ Enable Clear Register , read or write[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-67 ID013010 Non-Confidential, Unrestricted Access T able 4-47 shows how the bit val ues correspond with th e FIQ Enable Clear Regist er . T o access the FIQ Enable Clear Re gister , read or write CP15 with: MRC p15, 0, <Rd>, c15, c1, 5 ; Read FIQ En[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-68 ID013010 Non-Confidential, Unrestricted Access T o access the nV AL Reset Enable Clear Register , read or write CP15 with: MRC p15, 0, <Rd>, c15, c1, 6 ; Read nVAL Reset Enable Clear Register MCR p15, 0, <Rd>, c15, c1, 6 ; Write nVAL Reset [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-69 ID013010 Non-Confidential, Unrestricted Access T o access the nV AL Debug Request Enable Clear Register , read or write CP15 with: MRC p15, 0, <Rd>, c15, c1, 7 ; Read nVAL Debug Request Enable Clear Register MCR p15, 0, <Rd>, c15, c1, 7 ; W[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-70 ID013010 Non-Confidential, Unrestricted Access Note The nV AL Cache Size Override Register can only be used to select cache sizes for which the appropriate RAM has been integrated. Lar ger cache sizes require deeper data and tag RAMs, and smaller cache[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-71 ID013010 Non-Confidential, Unrestricted Access T able 4-52 shows how the bit values corresp ond to the CFLR when it indicates a correctable cache error . Figure 4-54 sh ows the bit arrangement of the CF LR when it indicates a correctable TCM error . Fi[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-72 ID013010 Non-Confidential, Unrestricted Access 4.2.30 Buil d Options Registers Build options registers reflect th e build configuration options used to bui ld the processor . They do not reflect any pin-configuration optio ns. These registers are: • [...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-73 ID013010 Non-Confidential, Unrestricted Access Figure 4-56 Build Options 2 Regis ter format T able 4-55 shows how the bit val ues correspond with th e Build Options 2 Register . 31 25 24 23 22 21 19 17 16 14 13 12 1 1 7 6 3 0 26 27 28 30 29 10 20 9 4 5[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-74 ID013010 Non-Confidential, Unrestricted Access [25:24] BTCM_ES Indicates whethe r an error scheme is impleme nted on the BTCM interface(s): 00 = no error scheme 01 = 8-bit parity logic 10 = 32-bit error detection and correction 1 1 = 64-bit error detec[...]

System Control Coprocessor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-75 ID013010 Non-Confidential, Unrestricted Access T o access the Build Options 2 Regi ster , write CP15 with: MRC p15, 0, <Rd>, c15, c2, 1 ; read Build Options 2 Register [6:5] DCACHE_ES Indicates whether an error sc heme is implemented for the data[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 5-1 ID013010 Non-Confidential, Unrestricted Access Chapter 5 Prefetch Unit This chapter describes how the PreFetch Unit (PFU), in conjunction wi th the DPU, uses program flow prediction to locate branches in the instructio n stream and the strategies used to determine if a branch is [...]

Prefetch Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 5-2 ID013010 Non-Confidential, Unrestricted Access 5.1 About the prefetch unit The purpose of the PFU is to: • perform speculative fetch of instructions ah ead of the DPU by predicting the outcome of branch instructions • format instruction data in a way that aids t[...]

Prefetch Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 5-3 ID013010 Non-Confidential, Unrestricted Access 5.2 Branch prediction The PFU normally fetch es instructions from sequ ential addresses. If a branch instruction is fetched, the next instruction to be fetched can only be determined with certai nty after the instructio[...]

Prefetch Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 5-4 ID013010 Non-Confidential, Unrestricted Access 5.2.2 Branch predictor Branch prediction in the processor is dynam ic and is based around a global history prediction scheme. In addition, there is extra logic to handle predictions that thrash and to predict the end of[...]

Prefetch Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 5-5 ID013010 Non-Confidential, Unrestricted Access 5.3 Return st ack The call-return stack predicts pr ocedural returns that are program flow changes such as loads, and branch register . The dynami c branch predictor determines if conditional procedure returns are predi[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-1 ID013010 Non-Confidential, Unrestricted Access Chapter 6 Event s and Performance Monitor This chapter describes the Performance Monitoring Unit (PMU) and event bus interface. It contains the following sections: • About the events on page 6-2 • About the PMU on p age 6-6 • P[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-2 ID013010 Non-Confidential, Unrestricted Access 6.1 About the event s The processor includes logic to de tect various events that can o ccur , for example, a cache mis s. These events provide useful info rmation about the behavior of the processor th[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-3 ID013010 Non-Confidential, Unrestricted Access [8] Exception re turn architecturall y executed. This event occurs on every exception return, for example, RFE , MOVS PC , LDM PC^ . - 0x0A [9] Change to Context ID executed. - 0x0B [10] Software change[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-4 ID013010 Non-Confidential, Unrestricted Access [22] Instruction cache tag RAM parity or ECC error (correctable). Y es 0x4A [23] Instruction cache data RAM pari ty or ECC error (correctable). Y es 0x4B [24] Data cache tag or dirty RAM parity error or[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-5 ID013010 Non-Confidential, Unrestricted Access [43] TCM correctable ECC error reported by load/store unit. Y es 0x6A [44] TCM correctable ECC error reported by prefetch unit. Y es 0x6B [45] TCM parity or fatal ECC error reported by AXI slave interfa[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-6 ID013010 Non-Confidential, Unrestricted Access 6.2 About the PMU The PMU consists of three event counting regist ers, one cycle counting regist er and 12 CP15 registers, for controlling and in terrogating the counters. The performan ce monitoring re[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-7 ID013010 Non-Confidential, Unrestricted Access 6.3 Performance moni toring registers The performance monitorin g registers are described in: • c9, Performance Monitor Control Register • c9, Count Enable Set Register on page 6-8 • c9, Count Ena[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-8 ID013010 Non-Confidential, Unrestricted Access The PMNC Register is always accessible in Pr ivileged mode. T o access the register , read or write CP1 5 with: MRC p15, 0, <Rd>, c9, c12, 0 ; Read PMNC Register MCR p15, 0, <Rd>, c9, c12, 0[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-9 ID013010 Non-Confidential, Unrestricted Access Figure 6- 2 CNTEN S Register format T able 6-3 shows how the bit values correspond wit h the CNTENS Register . T o access the CNTENS Register , read or write CP15 with: MRC p15, 0, <Rd>, c9, c12, [...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-10 ID013010 Non-Confidential, Unrestricted Access Figure 6-3 CNTENC Register format T able 6-4 shows how the bit values correspond wit h the CNTENC Register . T o access the CNTENC Register , read or writ e CP15 with: MRC p15, 0, <Rd>, c9, c12, [...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-11 ID013010 Non-Confidential, Unrestricted Access Figure 6-4 FLAG Register format T able 6-5 shows how the bit values correspond wit h the FLAG Register . T o access the FLAG Register , read or write CP15 with: MRC p15, 0, <Rd>, c9, c12, 3 ; Rea[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-12 ID013010 Non-Confidential, Unrestricted Access If you attempt to use the SWINCR Register to increment a performance monito r count register when the counter event is set to a value ot her than 0x00 the result is Unpredictable. Figure 6-5 shows the [...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-13 ID013010 Non-Confidential, Unrestricted Access T able 6-7 shows how the bit values correspo nd with the PMNXSEL Register functions. Any values programmed in the PMNXSEL Register other than those specified in T able 6-7 are Unpredictable. T o access[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-14 ID013010 Non-Confidential, Unrestricted Access Figure 6-7 EVTSELx Register format T able 6-8 shows how the bit values correspond wit h the EVTSELx Register . T o access the EVTSELx Register , read or writ e CP15 with: MRC p15, 0, <Rd>, c9, c1[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-15 ID013010 Non-Confidential, Unrestricted Access 6.3.9 c9, Performance Monit or Count Registers There are three PMC Registers (P MC0-PMC2) in the processor . E ach PMC Register , as selected by the PMNXSEL Register , counts instances of an event sele[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-16 ID013010 Non-Confidential, Unrestricted Access Note For more information on access permissions to th e performance monitor re gisters and validation registers, see the ARM Ar chitectur e Refer ence Manual . T o access the USEREN Register , read or [...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-17 ID013010 Non-Confidential, Unrestricted Access MRC p15, 0, <Rd>, c9, c14, 1 ; Read INTENS Register MCR p15, 0, <Rd>, c9, c14, 1 ; Write INTENS Register If this unit generates an interrupt, the processor asserts the pin nPMUIR Q . Y ou c[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-18 ID013010 Non-Confidential, Unrestricted Access T o access the INTENC Register , read or write CP15 with: MRC p15, 0, <Rd>, c9, c14, 2 ; Read INTENC Register MCR p15, 0, <Rd>, c9, c14, 2 ; Write INTENC Register[...]

Events and Performance Monitor ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-19 ID013010 Non-Confidential, Unrestricted Access 6.4 Event bus interface The event bus, EVNTBUS , is used to signal when an event has occurred. The event bus includes most, but not all, of the events that can be counted by the perform ance monitoring[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-1 ID013010 Non-Confidential, Unrestricted Access Chapter 7 Memory Protection Unit This chapter describes the Memory Pr otection Unit ( MPU ). It contains the following sections : • About the MPU on p age 7-2 • Memory types on page 7-7 • Region attributes on page 7-9 • MPU i[...]

Memory Protection Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-2 ID013010 Non-Confidential, Unrestricted Access 7.1 About the MPU The MPU works with the L1 memo ry system to control accesses to and from L1 and external memory . For a full architectural de scription of the MPU, see the ARM Ar chitectur e Reference Manual [...]

Memory Protection Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-3 ID013010 Non-Confidential, Unrestricted Access This section describes: • Memory r egions • Overlapping regions on page 7-4 • Backgr ound r egions on page 7-6 • TCM r egions on page 7-6. 7.1.1 M emory region s Before the MPU is en abled, you must pro[...]

Memory Protection Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-4 ID013010 Non-Confidential, Unrestricted Access Region attributes Each region has a number of attributes associat ed with it. These cont rol how a memory access is performed when the processor accesses an ad dress that falls within a given region. The attrib[...]

Memory Protection Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-5 ID013010 Non-Confidential, Unrestricted Access Figure 7-1 Overlapping memory regions Example of using regions th at overlap Y ou can use overlapp ing regions fo r stack protection. For example: • allocate to region 1 the a ppropriate size for all stacks ?[...]

Memory Protection Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-6 ID013010 Non-Confidential, Unrestricted Access Figure 7-3 Overlapping subregion of memory 7.1.3 Background regions Overlapping reg ions increase the flexibil ity of how the regio ns can be mapped onto physical memory devices in the system. Y ou can also use[...]

Memory Protection Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-7 ID013010 Non-Confidential, Unrestricted Access 7.2 Memory types The ARM Architecture defines a set of memory ty pes with characteristics that are suited to particular devices. There are three mutua lly exclusive memory type attri butes: • Strongly Ordered[...]

Memory Protection Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-8 ID013010 Non-Confidential, Unrestricted Access T o ensure optimum perform ance, you must understand the architectural semantics of the different memory types. Use Device memory type for appropriate memory region s, typically peripherals, and only use Strong[...]

Memory Protection Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-9 ID013010 Non-Confidential, Unrestricted Access 7.3 Region attributes Each region has a number of attributes associat ed with it. These cont rol how a memory access is performed when the processor accesses an ad dress that falls within a given region. The at[...]

Memory Protection Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-10 ID013010 Non-Confidential, Unrestricted Access 7.3.1 Cacheable me mory policies When TEX[2] == 1, the memory region is Cacheab le memory , and the rest of the encoding defines the Inner and Outer cache policies: TEX[1:0] defines the Outer cache policy C,B [...]

Memory Protection Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-11 ID013010 Non-Confidential, Unrestricted Access 7.4 MPU interaction with memory system This section describes how to enable and disable the MPU. After you enable or disable the MPU, the pipeline must be flushed using ISB and DSB instructions to ensure that [...]

Memory Protection Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-12 ID013010 Non-Confidential, Unrestricted Access 7.5 MPU fault s The MPU can generate three types of fault: • Backgr ound fault • Permission fault • Alignment fault . When a fault occurs, the memory access or instruction fetch is precisely aborted, and[...]

Memory Protection Unit ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-13 ID013010 Non-Confidential, Unrestricted Access 7.6 MPU sof tware-accessible registers Figure 4-2 on page 4-5 shows the CP15 registers that control the MPU. When the MPU is not present, the c6 , MPU memory r egion pr ogramming r egisters on page 4-49 read a[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-1 ID013010 Non-Confidential, Unrestricted Access Chapter 8 Level One Memory System This chapter describes the proce ssor Level one (L1) memo ry system. It contai ns the following sections: • About the L1 memory system on page 8-2 • About the err or detection and corr ection sch[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-2 ID013010 Non-Confidential, Unrestricted Access 8.1 About the L1 memory system The processor L1 memory system can be configur ed durin g implementation and in tegration. It can consist of: • separate instruction and data caches • multiple T igh tly-Coup[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-3 ID013010 Non-Confidential, Unrestricted Access Figure 8-1 L1 memory system block diagram AXI master Instruction cache controller and RAMs Data cache controller and RAMs B0TCM AXI bus AXI bus External T ightly-Coupled Memory (TCM) AXI slave Data Processing [...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-4 ID013010 Non-Confidential, Unrestricted Access 8.2 About the error detect ion and correction schemes In silicon devices, stray radiation and other eff ects can cause the data stored in a RAM to be corrupted. The TCMs and caches on Cortex-R4 can be configur[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-5 ID013010 Non-Confidential, Unrestricted Access 8.2.2 Erro r checking and co rrection The processor supports Err or Checking and Corr ection (ECC) schemes for either 64-bit s or 32-bits of data, and these hav e similar properties, although though the size o[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-6 ID013010 Non-Confidential, Unrestricted Access 8.2.5 Error co rrection When a correctable error is detected in data th at has been read from a RAM, the processor has various ways of generating the correct data, whi ch follow two schemes: Correct inline The[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-7 ID013010 Non-Confidential, Unrestricted Access 8.3 Fault handling Faults can occur on instruction fetches for the fo llowing reasons: • MPU background fault • MPU permission fault • External AXI slave error (SL VERR) • External AXI decode error (DE[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-8 ID013010 Non-Confidential, Unrestricted Access External fault s A memory access performed through the AXI master interface can generate two different types of error response, a slave erro r (SL VERR) or decode error (DECERR). These are known as external er[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-9 ID013010 Non-Confidential, Unrestricted Access Debug event s The debug logic in the processor can be configured to generate breakpoints or vector capture events on instruction fetches, and watchpoints on data accesses. If the processor is software-configur[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-10 ID013010 Non-Confidential, Unrestricted Access Precise abor t exceptions The following registers ar e updated when a precise abort exception is taken: Fault Address Register There are two fault address registers, one for prefetch aborts (IF AR ) and one f[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-11 ID013010 Non-Confidential, Unrestricted Access reprogramming the MPU to r eflect this. Al tern atively , an imprecise external abort might indicate that a software error m eant that a store instruction occu rred to an unma pped memory address. Such an abo[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-12 ID013010 Non-Confidential, Unrestricted Access When the processor is in debug halt-state, any co rrectable error is correct ed as appropriate, but the memory access is not repeated to fetch the co rrect data, therefore th e instruction generating the erro[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-13 ID013010 Non-Confidential, Unrestricted Access 8.4 About the TCMs The processor has two TCM interfaces to suppor t the connection of local memories. The A TCM interface has one TCM port. The BTCM interf ace can support one or two TCM ports. Each TCM port [...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-14 ID013010 Non-Confidential, Unrestricted Access 8.4.2 A TCM and BTCM configuration The TCM interfaces are configured du ring implementa tion and integration. Y ou can configure the A TCM interface to be removed, and not included in the processor design. If[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-15 ID013010 Non-Confidential, Unrestricted Access Handling TCM p arity errors If a TCM interface has been built with parity erro r checking, you can enable this by s etting the appropriate bits in the Auxiliary Control Register . See c1, Auxiliary Contr ol R[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-16 ID013010 Non-Confidential, Unrestricted Access When either the LSU or the AXI slave interface is performing a read-modify-write operation on a TCM port, various internal data hazards exist for either the AXI-slave interface or the LSU. In these cases, add[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-17 ID013010 Non-Confidential, Unrestricted Access In addition, an external error detection scheme might require that data is read and written in particular sized chunks. The load /store-64 feature, when enabled for a particular TCM interface, causes all load[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-18 ID013010 Non-Confidential, Unrestricted Access 8.5 About the caches The L1 memory system can be configured to include instruction and data caches of varying sizes. Y ou can configure whether the cache controller is included and, if it is, configure the si[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-19 ID013010 Non-Confidential, Unrestricted Access Store bu ffer merging The store buffer has mer ging capab ilities. If a previous write acce ss has updated an entry , other write accesses on the same line can mer ge into this entry . Merging is only possibl[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-20 ID013010 Non-Confidential, Unrestricted Access • Invalidate by Set/W ay combination • Clean by address (MV A) • Clean by Set/W ay combination • Clean and Invalidate by address (MV A) • Clean and Invalidate by Set/W ay combination • Data Memory[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-21 ID013010 Non-Confidential, Unrestricted Access Address decoder fault s The error detection schemes described in this section provide protection again st errors that occur in the data stored in the cache RAMs. Each RAM normally includes a decode r which en[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-22 ID013010 Non-Confidential, Unrestricted Access Handling cache ECC errors T able 8-3 shows the behavior of the processor on a cache ECC error , depending on bits [5:3] of the Auxiliary Control Register, see Auxiliary Contr ol Registers on page 4-3 8. See D[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-23 ID013010 Non-Confidential, Unrestricted Access Errors on instruction cache read All parity or ECC erro rs detected on instruction cache r eads are correctable. If aborts are enabled, a precise prefetch ab ort exception occurs . The instruc tion F AR gives[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-24 ID013010 Non-Confidential, Unrestricted Access • Invalidate data cache by set/way • Clean data cache by addr ess • Clean data cache by set/way on page 8-25 • Clean and invalidate data cache by address on page 8-25 • Clean and invalidate data cac[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-25 ID013010 Non-Confidential, Unrestricted Access Any detected error is signaled wit h the appropriate event. Clean data cache b y set/way This operation does not requ ire a cache lookup. It refers to a particular cache line. The tag and dirty RAMs for the c[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-26 ID013010 Non-Confidential, Unrestricted Access Any uncorrectable errors found cause an imprecise abort. An imprecise abort can also be raised on a correctable error if aborts on RAM errors are enabled in the Auxiliary Control Regi ster . Any detected erro[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-27 ID013010 Non-Confidential, Unrestricted Access T able 8-7 shows the tag RAM cache sizes and associ ated RAM organization, assuming no parity or ECC. For parity , the width of the tag RAMs mu st be increased by one bit. For ECC, the wi dth of the tag RAMs [...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-28 ID013010 Non-Confidential, Unrestricted Access • W rite a line to the ev iction buffer in one cycle, a 256-bit read access. • Fill a line in one cycle from the linefill buffe r , a 256-bit write access. Figure 8-3 shows a cach e look-up being perf orm[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-29 ID013010 Non-Confidential, Unrestricted Access Data RAM sizes without pa rity or ECC implemented T able 8-9 shows the organization for instruc tion and data caches when ne ither parity nor ECC is implemented. Data RAM sizes with parity implemen ted T able[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-30 ID013010 Non-Confidential, Unrestricted Access T able 8-13 shows the organization of the data cache RAM bits when parity is implemented. Parity bits are grouped together in bits[35: 32] so that data and parity bits are easily differentiated. W ith this de[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-31 ID013010 Non-Confidential, Unrestricted Access T able 8-15 shows the organization for the data cache when ECC is implemented. For ECC error detection, seven bits are added per 32 bits, so seven bits are added for each RAM bank. T able 8-16 shows the organ[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-32 ID013010 Non-Confidential, Unrestricted Access The following code is an ex ample of disabling the caches: MRC p15, 0, R1, c1, c0, 0 ; Read System Control Register configuration data BIC R1, R1, #0x1 <<12 ; instruction cache disable BIC R1, R1, #0x1 [...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-33 ID013010 Non-Confidential, Unrestricted Access ; Clean entire data cache. This routine will depend on the data cache size. It can be omitted if it is known that the data cache has no dirty data (e.g. if the cache has not been enabled yet). MRC p15, 0, r1,[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-34 ID013010 Non-Confidential, Unrestricted Access 8.6 Internal exclusive monitor The processor L1 memory system has an internal exclusive monitor . This is a two state, open and exclusive, state machine that manages load/store exclusive ( LDREXB , LDREXH , L[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-35 ID013010 Non-Confidential, Unrestricted Access 8.7 Memory types and L1 memory system behavior The behavior of the L1 memory system depends on the type attribute of the memory that is being accessed: • Only Normal, Non-shared memo ry can be cached in the[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-36 ID013010 Non-Confidential, Unrestricted Access 8.8 Error detection event s The processor generates a number of events relate d to the internal error detection and correction schemes in the TCMs and caches. For more informat ion, see T able 6-1 on page 6-2[...]

Level One Memory System ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-37 ID013010 Non-Confidential, Unrestricted Access generates an event. See T able 6-1 on page 6- 2 to see which events are CFLR-related. For correctable cache errors, the CLFR does not record whether the error occu rred in the data RAM or tag/dirty RAM. This [...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-1 ID013010 Non-Confidential, Unrestricted Access Chapter 9 Level T wo Interface This chapter describes the features of the Level two (L2) interface not covered in the AMBA AX I Pr otocol Specification . It contains the following sections: • About the L2 interface on page 9-2 • [...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-2 ID013010 Non-Confidential, Unrestricted Access 9.1 About the L2 interface This section describes the processor L2 interface. The L2 interf ace consists of AXI master and AXI slave interfaces. The processor is designed fo r use in larger chip designs using the [...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-3 ID013010 Non-Confidential, Unrestricted Access 9.2 AXI master interface The processor has a single AXI master inte rface, with one port which is used for: • I-cache linefills • D-cache linefills and evictions • Non-cacheable (NC) Normal-type memory instr[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-4 ID013010 Non-Confidential, Unrestricted Access 9.2.1 Identifiers for AXI bus acc esses Accesses on the AXI bus use ID values as follows: Outstanding write/read access on differ ent IDs This means, for example, that a Non-cacheable (NC) read and linefills can b[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-5 ID013010 Non-Confidential, Unrestricted Access 9.2.4 Eviction buffer As soon as a linefill is requested, the sel ected evicted cache line is loaded into the EV iction Buffer (EVB). The EVB forwards this info rmation to the AXI bus when possible. The EVB has a [...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-6 ID013010 Non-Confidential, Unrestricted Access Memory system implicat ions for AXI accesses The attributes of the memory being accessed can af fect an AXI access. The L1 memory syste m can cache any Normal memory addres s that is marked as either: • Cacheabl[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-7 ID013010 Non-Confidential, Unrestricted Access 9.3 AXI master interface transfers The processor conforms to the AX I specification, but it does not ge nerate all the AXI transaction types that the specificati on permits. This section describes the ty pes of AX[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-8 ID013010 Non-Confidential, Unrestricted Access 9.3.1 Res trictions on AXI transfers The Cortex-R4 AXI master interf ace applies the following restric tions to the AX I transactions it generates: • A burst never transfers more than 32 bytes. • The burst len[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-9 ID013010 Non-Confidential, Unrestricted Access LDRH T able 9-5 shows the values of ARADDRM , ARBURST M , ARSIZEM , and ARLENM fo r a Non-cacheable LDRH from halfwords 0-3 in Strongly Ordered or Device memory . Note A load of a halfword from Strongly Ordered or[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-10 ID013010 Non-Confidential, Unrestricted Access LDM that transfer s five registers T able 9-7 shows the values of ARADDRM , ARBURST M , ARSIZEM , and ARLENM fo r a Non-cacheable LDM that transfers five registers (an LDM 5) in S trong ly Ordere d or De vice mem[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-11 ID013010 Non-Confidential, Unrestricted Access STRB T able 9-8 shows the values of A W ADDRM , A WBURSTM , A WSIZEM , and AW L E N M for an STRB to Strongly Ordered or Device memory over the AXI master port. STRH T able 9-9 shows the values of A W ADDRM , A W[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-12 ID013010 Non-Confidential, Unrestricted Access STR or STM of one register T able 9-10 show s the values of A W ADDRM , AW B U R S T M , A WSIZEM , and A WLENM for an STR or an STM that transfers one register (an STM 1) over the AXI master port to Strongly Ord[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-13 ID013010 Non-Confidential, Unrestricted Access 9.3.3 Linefills Loads and instruction fetches from Normal, C acheable memory that do not hit in the cache generate a cache linefill when th e appropriate cache is enabled. T able 9-12 shows the values of ARADDRM [...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-14 ID013010 Non-Confidential, Unrestricted Access T able 9-15 shows possibl e values of ARADDRM , ARBURSTM , ARSIZEM , and ARLENM for a Non-cacheable LDR or an LDM that transfers one register , an LDM 1. T able 9-16 show possible values of ARADDR M , ARBURSTM , [...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-15 ID013010 Non-Confidential, Unrestricted Access 9.3.6 Non-cacheable or write- through writes Store instructions to Non-cacheable or write-through Normal memo ry generate AXI bursts that are not necessarily the same size or length as the instruction implies. Th[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-16 ID013010 Non-Confidential, Unrestricted Access T able 9-18 shows possible values of A W AD DRM , AW B U R S T M , A WSIZEM , and A W LENM for an STR or an STM that transfers one register , an STM 1, to Normal memory through the AXI master port. 9.3.7 AXI tran[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-17 ID013010 Non-Confidential, Unrestricted Access • If the data comes from two cache lines, then there are two AXI transactions. For example, for LDMIA R10, {R0-R5} with R10 = 0x1010 , the interface might gene rate one burst of two 64-bit reads, and one burst [...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-18 ID013010 Non-Confidential, Unrestricted Access Example 9-1 Write merging MOV r0, #0x4000 STRH r1, [r0, #0x18]; Store a halfword at 0x4018 STR r2, [r0, #0xC] ; Store a word at 0x400C STMIA r0, {r4-r7} ; Store four words at 0x400 0 STRB r3, [r0, #0x1D]; Store a[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-19 ID013010 Non-Confidential, Unrestricted Access The transactions shown in T able 9-2 4 on page 9- 18 show this behavior . They are provided as examples only , and are not an exhaustive descri ption of the AXI transactions. Depending on the state of the process[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-20 ID013010 Non-Confidential, Unrestricted Access 9.4 AXI slave interface The processor has a single AXI slave interface, with one port. The port is 64 bits wide and conforms to the AXI standa rd as descri bed in the AMBA AXI Pr otocol Specification . W ithin th[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-21 ID013010 Non-Confidential, Unrestricted Access 9.4.2 TCM p arity and ECC support The TCMs can support parity or ECC, as described in TCM internal err o r detection and corr ection on page 8-14. If a write tr ansaction is issued to the AXI slave, the slave int[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-22 ID013010 Non-Confidential, Unrestricted Access 9.4.6 AXI slave characteristic s This section describes the capabil ities of the AXI slave interface, and the attributes of its AXI port. Y ou must not make any other assumptions about the behavior of the AXI sla[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-23 ID013010 Non-Confidential, Unrestricted Access 9.5 Enabling or di sabling AXI slave accesses This section describes how to enable or disable AXI slave a ccesses to the cache RAMs. When caches are accessible by the AXI slave interface, th e caches are cons ide[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-24 ID013010 Non-Confidential, Unrestricted Access 9.6 Accessing RAMs using th e AXI slave interface This section describes how to access the TCM and cache RAMs using the AXI slave interface. T able 9-26 shows the bits of the ARUSERS or AW U S E R S inputs to use[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-25 ID013010 Non-Confidential, Unrestricted Access 9.6.1 TCM RAM access T able 9-27 shows the deco de of the ARUSERS[3:0] signal, and the state of the address signals for accessing the TCM RAMs. The table also shows the SLBTCMSB configuration input signal that de[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-26 ID013010 Non-Confidential, Unrestricted Access • There is no TCM present. The mapping of bus addresses to ARU SERS and ARADDRS is determined when t he processor is integrated. Y ou must understand this mapping to use of the AXI-slave interf ace within your [...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-27 ID013010 Non-Confidential, Unrestricted Access Note Y ou can only access the cache RAMs using 32-bit or 64-bit AXI transfers. Using an 8-bit or a 16-bit transfer size generates a SL VERR error response. Dat a RAM access The following tables s hows the data fo[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-28 ID013010 Non-Confidential, Unrestricted Access T able 9-33 Data format, instruction cache and data cache, with p arity Dat a bit Desc ription [63:50] Not used, read-as-zero [49] Parity bit for data value [31:24] or [63:56] [48] Parity bit for data value [23:1[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-29 ID013010 Non-Confidential, Unrestricted Access T ag RAM access The following tables show the data formats for tag RAM accesses: • T able 9-36 shows the format for read acce sses when neither parity nor ECC is implemented • T able 9-37 shows the format for[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-30 ID013010 Non-Confidential, Unrestricted Access Note For tag RAM writes, only bits [23:0] of the da ta bus are used. If two tag RAMs are written at the same time, they are both wri tten with the same data. T o write only one tag RA M using the AXI Slave, selec[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-31 ID013010 Non-Confidential, Unrestricted Access Dirty RAM access The following tables s how the data format for accessing the dirty RAM: • T able 9-42 shows the format when parity is implemented, or no error scheme is implemented • T able 9-43 shows the fo[...]

Level Two Interface ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-32 ID013010 Non-Confidential, Unrestricted Access Other examples of accessing ca che RAMs Normally ARADDRS[18:15] is a one-hot field, and only accesses one RAM at a time. However , if you want to access two tag RAMs, su ch as banks 0 and 2 or banks 1 and 3 at th[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 10-1 ID013010 Non-Confidential, Unrestricted Access Chapter 10 Power Control This chapter describes the processor power control functions. It contains the follow ing sections: • About power contr ol on page 10-2 • Power management on page 10-3.[...]

Power Control ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 10-2 ID013010 Non-Confidential, Unrestricted Access 10.1 About power control The features of the pr ocessor that improve en ergy ef ficiency include: • branch and return prediction, red ucing the number of incorrect instruction fetch and decode operations • the cach[...]

Power Control ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 10-3 ID013010 Non-Confidential, Unrestricted Access 10.2 Power man agement The processor supports four levels of p ower management. This section describes: • Run mode • S tandby mode • Dormant mode • Shutdown mode • Communication to the Power Management Contro[...]

Power Control ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 10-4 ID013010 Non-Confidential, Unrestricted Access disabled and finish with a Data Synchronizati on Barrier operation. When all the s tate of the processor is saved the processor executes a WFI instruction. The ST ANDBYWFI signal is asserted to indicate that the pr oce[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-1 ID013010 Non-Confidential, Unrestricted Access Chapter 1 1 Debug This chapter describes the processor debug unit. These features assi st the development of application software, operating systems, and hard ware. This chapter contains the following sections: • Debug systems on [...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-2 ID013010 Non-Confidential, Unrestricted Access 1 1.1 Debug systems The Cortex-R4 processor is one component of a debug system. Fi gure 1 1- 1 show s a typical system. Figure 1 1-1 T ypical de bug system This typical system has three parts, described in the following sectio[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-3 ID013010 Non-Confidential, Unrestricted Access 1 1.2 About the debug unit The processor debug unit assists in debugging software runnin g on the processor . Y ou can use the processor debug unit, in combination with a software debugger program, to debug: • application so[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-4 ID013010 Non-Confidential, Unrestricted Access • data address comparators for triggering watchpoints, see W atchpoint V alue Registers on page 1 1-26 and W atchpoint C ontr ol Registers on page 11-26 • a bidirectional Debug Communicatio n Channel (DCC), see Debug commu[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-5 ID013010 Non-Confidential, Unrestricted Access 1 1.3 Debug register interface Y ou can access the processor debug re gister map using the APB slave port. This is the only way to get full access to the proces sor debug capability . ARM recomm ends that if your system requir[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-6 ID013010 Non-Confidential, Unrestricted Access Note The CP14 debug instructions are defined as having Opcode_1 set to 0. 1 1.3.4 Memory-mapped reg isters T able 1 1-3 shows the complete list of memory -mapped registers accessible at the APB slave interface. Note Y ou m ust[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-7 ID013010 Non-Confidential, Unrestricted Access 1 1.3.5 Memory addresses for breakpoint s and watc hpoint s The V ector C atch Register (VCR) sets breakp oints on ex ception vectors as instruction addresses. 0x080 c32 R W DTRRX Data T ransfer Register on page 1 1- 18 0x084 [...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-8 ID013010 Non-Confidential, Unrestricted Access The W atchpoint Fault Addr ess Register (WF A R) reads an address and a process or state dependent offset, +8 for ARM and +4 for Thu mb. 1 1.3.6 Power domains The processor has a single power domain. Theref ore, it does n ot s[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-9 ID013010 Non-Confidential, Unrestricted Access OS Lock The processor do es not support OS Lock. Note • These locks are set to their reset values only o n reset of the debug l ogic, provided by PRESETDBGn . • Y ou must set the P ADDRDBG31 input signal to 1 for acce sses[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-10 ID013010 Non-Confidential, Unrestricted Access 1 1.4 Debug register descriptions T able 11-5 shows definitions of terms used in t he register descripti ons. 1 1.4.1 Accessing debug re gisters T o access the CP14 debug registers you set Opcode_1 and Op code_2 to zero. The [...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-11 ID013010 Non-Confidential, Unrestricted Access The Debug ID Register is: •i n C P 1 4 c 0 • a 32 bit read-only register • accessible in User and Privileged modes. Figure 1 1-2 shows the bit arrangement of the DID R. Figure 1 1-2 Debug ID Regi ster format T able 11-7[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-12 ID013010 Non-Confidential, Unrestricted Access T o use the Debug ID Register , read CP14 c0 with: MRC p14, 0, <Rd>, c0, c0, 0 ; Read Debug ID Register 1 1.4.3 CP14 c0, Debug ROM Address Register The Debug ROM Address Register is a read-onl y register that returns a [...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-13 ID013010 Non-Confidential, Unrestricted Access The Debug Self Address Offset Register is: • in CP14 c0, sub-register c2 • a 32 bit read-only register • accessible in User and Privileged modes. Figure 1 1-4 shows the bit arrangement of the Debug Self Address Offset R[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-14 ID013010 Non-Confidential, Unrestricted Access 1 1.4.5 CP14 c1, Debug St atus and Control Register The DSCR contains status and contro l information about the debug unit. Figure 1 1-5 shows the bit arrangement of the DSCR. Figure 1 1-5 Debug St atus and Control Reg ister [...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-15 ID013010 Non-Confidential, Unrestricted Access [24] InstrCompl Instruction complete read-only bit. This flag determines whet her the processor has completed execution of an instru ction issued through the APB port. 0 = processor is currently executing an instruction fetch[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-16 ID013010 Non-Confidential, Unrestricted Access [13] ARM Execute ARM instruction enable bit: 0 = disabled, this is the reset value 1 = enabled. If this bit is set and an ITR write succeeds, the processor fetches an instruc tion from the ITR for execution. If this bit is se[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-17 ID013010 Non-Confidential, Unrestricted Access T o use the Debug Status and Control Re gister , read or write CP14 c1 with: MRC p14, 0, <Rd>, c0, c1, 0 ; Read Debug Status and Control Register MCR p14, 0, <Rd>, c0, c1, 0 ; Write Debug Status and Control Regist[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-18 ID013010 Non-Confidential, Unrestricted Access • writes to ITR are ignored if InstrCompl_l is set to b0 • following a successful write to DTRRX, DTRRXfull and DTRRXfull_l are set to b1 • following a successful read fr om DTR TX, DTR TXfull and DTR TXfull_l are clear[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-19 ID013010 Non-Confidential, Unrestricted Access T able 11- 11 shows how the bit values correspond with the DTRRX and DTR TX functions. 1 1.4.7 W atchpoint Fau lt Address Register The W atchpoint Fault Addr ess Register (WF A R) is a read/write register that holds the addre[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-20 ID013010 Non-Confidential, Unrestricted Access Figure 1 1-7 V ector Ca tch Register form at If one of the bits in this register is set and the instruction at the corresponding vector is committed for executi on, the pro cessor either enters debug st ate or takes a debug e[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-21 ID013010 Non-Confidential, Unrestricted Access 1 1.4.9 Debug St ate Cache Control Register The DSCCR controls the L1 cache behavior when the processor is in debug state. Figure 1 1-8 shows the bit arrangement of the DSCCR. Figure 1 1-8 Debug S t ate Cache Co ntrol Registe[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-22 ID013010 Non-Confidential, Unrestricted Access 1 1.4.1 1 Debug Run Control Regist er The DRCR requests th e processor to enter or leave de bug state. It also clears the sticky exception bits pres ent in the DSCR. Figure 1 1-9 shows the bit arrangement of the DRCR. Figure [...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-23 ID013010 Non-Confidential, Unrestricted Access 1 1.4.12 Breakpoint V alue Registers Each BVR is associated with a Br eakpo int Contr ol Register (BCR). BCR y is the corresponding control register for BVR y . A pair of breakpoint regist ers, BVR y/BCR y , is called a Br ea[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-24 ID013010 Non-Confidential, Unrestricted Access T able 11- 17 shows how the bit values corresp ond with the Breakpoint Control Registers functions. T able 1 1- 17 Breakpoint Control Registers fun ctions Bits Field Function [31:29] Reserved Do not modify on writes. On reads[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-25 ID013010 Non-Confidential, Unrestricted Access [8:5] Byte address select For breakpoints programmed to match an instruction address, the debugger must write a word-aligned address to the BVR. Y ou can then use this field to program the breakpoint so it hits only if certai[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-26 ID013010 Non-Confidential, Unrestricted Access 1 1.4.14 Watchpoint V alue Registers Each WVR is asso ciated with a W atchpoint Control Register (WCR). WCR y is the corresponding register for WVR y . A pair of wa tchpoint register s, WVR y and WCR y , is called a W atchpoi[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-27 ID013010 Non-Confidential, Unrestricted Access Figure 1 1- 1 1 W atchpoint Control Registers forma t T able 11-20 shows how the bit values correspond with the W atchpoint Con trol Registers functions. Reserved Linked BRP Byte address select L/S P W Reserved W atchpoint ad[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-28 ID013010 Non-Confidential, Unrestricted Access 1 1.4.16 Operating System Lock St atus Register The Operating System Lock S tatus Register (OSLSR) contains status informatio n about the locked debug reg isters. Figure 1 1- 12 on page 1 1-29 shows the bit arrangement of the[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-29 ID013010 Non-Confidential, Unrestricted Access Figure 1 1- 12 OS Lock Status Register format T able 11-21 shows how the bit values correspond with the OS Lock Status Register functions. 1 1.4.17 Authentication S t atus Regist er The Authentication Status Register is a rea[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-30 ID013010 Non-Confidential, Unrestricted Access 1 1.4.18 Device Power-down and Reset Control Regist er The PRCR is a read/write register that controls reset and power-down related functionality . Figure 1 1- 14 shows the bit arrangement of the PRCR. Figure 1 1- 1 4 PRCR fo[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-31 ID013010 Non-Confidential, Unrestricted Access Figure 1 1- 15 PRSR format T able 11-24 shows how the bit values co rrespond with the PRSR functions. 31 0 3 Reserved 21 4 Sticky reset status Reset status Sticky power-down status Power-down status T able 1 1-24 PRSR functio[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-32 ID013010 Non-Confidential, Unrestricted Access 1 1.5 Management registers The Management Registers d efine the standard ized set of registers that all CoreSight components implement. This sec tion describes these registers. T able 1 1-25 shows the contents of the Manageme[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-33 ID013010 Non-Confidential, Unrestricted Access 1 1.5.2 Claim Registers The Claim T ag Set Register and the Claim T ag Cl ear Register enable an external debugger to claim debug resources. Claim T ag Set Register Figure 1 1- 16 shows the bit arrangement of the Claim T ag S[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-34 ID013010 Non-Confidential, Unrestricted Access W riting b1 to a specific claim tag set bit sets that claim tag. Writing b0 to a specific claim tag bit has no effect. This register always reads 0xFF , indicating eight claim tags are implemented. Claim T ag Clear Register F[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-35 ID013010 Non-Confidential, Unrestricted Access T able 11-29 shows how the bit values correspond with the Lock Status Register functions. 1 1.5.5 Device T ype Register The Device T ype Register is a read-only register that indicates the type of debug component. Figure 1 1-[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-36 ID013010 Non-Confidential, Unrestricted Access T able 11-31 shows the offset value, register numb er, and description t hat are associated with each Peripheral Identif ication Register . T able 11-32 shows fields that are in th e Peripheral Identification Registers. T abl[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-37 ID013010 Non-Confidential, Unrestricted Access T able 11-34 shows how the bit values correspond with the Peripheral ID Regi ster 1 functions. T able 11-35 shows how the bit values correspond with the Peripheral ID Regi ster 2 functions. T able 11-36 shows how the bit valu[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-38 ID013010 Non-Confidential, Unrestricted Access T able 1 1-38 shows the of fset valu e, register number , and value that are associated with each Component Identification Regist er . T able 1 1-38 Component Id entification Registers Offset (hex) Register number V a lue Des[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-39 ID013010 Non-Confidential, Unrestricted Access 1 1.6 Debug events A processor responds to a deb ug event in one of th e following ways: • ignores the debug event • takes a debug exception • enters debug state. This section describes: • Softwar e debug event • Ha[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-40 ID013010 Non-Confidential, Unrestricted Access 1 1.6.2 Halting debug event The debugger or the system can cause the processo r to enter into debu g state by triggering any of the following halti ng debug events: • assertion of the EDBGRQ signal, an External Debug Reques[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-41 ID013010 Non-Confidential, Unrestricted Access 1 1.7 Debug exception The processor takes a debug exception when a software debug event occurs while in Monitor debug-mode. Prefetch Abort and Data Abort V ector catch debug events are ignored. The debug software must careful[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-42 ID013010 Non-Confidential, Unrestricted Access T able 11-40 shows the values in the link register after exceptions. The following sections describe: • Effect of debug exceptions on CP15 r egisters and WF AR • A voiding unrecoverable states on page 1 1-43. 1 1.7.1 Effe[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-43 ID013010 Non-Confidential, Unrestricted Access 1 1.7.2 A voiding unrecoverable st ates The processor ignores vector catch debug events on the Prefetch or Data Abort vectors while in Monitor debug-mode because these events would otherwise put the processor in an unrecovera[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-44 ID013010 Non-Confidential, Unrestricted Access 1 1.8 Debug state The debug state enabl es an external agent, usually a d ebugger , to control the processor following a debug event. While in debug state, the processor behaves as follows: • The DSCR[0] core halted bit is [...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-45 ID013010 Non-Confidential, Unrestricted Access 1 1.8.2 Behavior of the PC and CPSR in debug st ate The behavior of the PC and CPSR registers while the processor is in debug state is as follows: • The PC is frozen on entry to debug state. That is, it does not increment o[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-46 ID013010 Non-Confidential, Unrestricted Access 1 1.8.3 Executing instruct ions in debug s t ate In debug state, the processor execute s instructions issued through the Instruction T ransfer Register (ITR). Before the debugger can force the pr ocessor to execute any instru[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-47 ID013010 Non-Confidential, Unrestricted Access 1 1.8.7 Coprocessor instructions CP14 and CP15 instructions can always be ex ecuted in debug state regardless of processo r mode. 1 1.8.8 Effect of debug st ate on non -invasive debug The processor non-invasive debug features[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-48 ID013010 Non-Confidential, Unrestricted Access Precise Data abort When a precise Data Abort occurs in debug state, the behavior of the processor is as follows: • PC, CPSR, SPSR_abt, and R14_abt are unchanged • the processor remains in debu g state • DSCR[6], sticky [...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-49 ID013010 Non-Confidential, Unrestricted Access 6. Sets the DSCR[1] core restarted flag to 1.[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-50 ID013010 Non-Confidential, Unrestricted Access 1 1.9 Cache debug This section describes cache debug. It consists of: • Cache pollution in debug state • Cache coher ency in debug state • Cache usage pr ofiling . 1 1.9.1 Cache pollution in debug st ate If bit [0] of t[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-51 ID013010 Non-Confidential, Unrestricted Access 1 1.10 External debug interface The system can access memory -mapped debug regi sters through the processor APB slave port. This section describes the APB interface and th e miscellaneous debug input and output signals: • A[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-52 ID013010 Non-Confidential, Unrestricted Access DBGSELF ADDR The DBGSELF ADDR signal specifies bits [3 1:12] of the offset from the debug ROM physical address to the physical address where the processor APB port is m apped to the base of the 4KB debug register map. This is[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-53 ID013010 Non-Confidential, Unrestricted Access If software running on t he processor has cont rol over an external device that drives the authentication signals, it must make the change using a safe sequence: 1. Execute an implementation-specific sequence of instructions [...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-54 ID013010 Non-Confidential, Unrestricted Access 1 1.1 1 Using the debug functionality This section provides some examp les of using the processor debug functionality , both from the point of view of a softw are engineer writing code to run on an ARM processor and of a deve[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-55 ID013010 Non-Confidential, Unrestricted Access 1 1.1 1.1 Debug communications channel There are two ways that an ex ternal debugger can send data to or receive data from the processor: • The debug communications channel, when the pr ocessor is not in debu g state. It is[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-56 ID013010 Non-Confidential, Unrestricted Access Sof tware acc ess to the DCC Software running on the processor that sends data to the debugger through the target-to-host channel can use the sequence of instructions that Example 1 1-2 shows. Example 1 1-2 T arg et to host d[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-57 ID013010 Non-Confidential, Unrestricted Access { // Step 1. Poll DSCR until DTRRXfull is clear. repeat { dscr := ReadDebugRegister(34); } until (!(dscr & (1<<30))); // Step 2. Write the value to DTRRX. WriteDebugRegister(32, dtr_val); } While the processo r is r[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-58 ID013010 Non-Confidential, Unrestricted Access For a simple breakpoint , you can program t he settings for the other con trol bits as T able 1 1-43 shows: Example 1 1-7 shows the sequence of instruct ions for setting a simple breakpoint. Example 1 1-7 Setting a simple bre[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-59 ID013010 Non-Confidential, Unrestricted Access For a simple watchpoint, you can program the settings fo r the other control bits as T able 11-44 shows: Example 1 1-8 shows the code for setting a simple aligned watchpoint. Example 1 1-8 Setting a s imple aligned watchpoint[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-60 ID013010 Non-Confidential, Unrestricted Access T able 11-45 shows some examples. Example 1 1-9 shows the code for setting a simple unaligned watchp oint. Example 1 1-9 Setting a s imple unalig ned watchpoi nt bool SetSimpleWatchpoint(int watch_num, uint32 address, int siz[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-61 ID013010 Non-Confidential, Unrestricted Access Example 1 1- 10 shows the code for single-stepp ing off an instruction. Example 1 1-10 Single-stepping off an in struction SingleStepOff(uint32 address) { bkpt := FindUnusedBreakpointWithMismatchCapability(); SetComplexBreakp[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-62 ID013010 Non-Confidential, Unrestricted Access dscr := ReadDebugRegister(34); } until (dscr & (1<<19)); } // Step 4. Read the entire processor state. The function ReadAllRegisters // reads all general-purpose registers for al l processor mode, and saves // the d[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-63 ID013010 Non-Confidential, Unrestricted Access WritePC(state->pc); // Step 4. Writing the PC corrupts R0 therefore, restore R0 now. WriteRegister(0, state->r0); // Step 5. Write the restart request bit in the DRCR. WriteDebugRegister(36, 1<<1); // Step 6. Poll[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-64 ID013010 Non-Confidential, Unrestricted Access } Reading the PC in debug st ate Example 1 1- 15 shows the code to read the PC. Example 1 1- 15 Reading the PC ReadPC() { // Step 1. Save R0 saved_r0 := ReadRegister(0); // Step 2. Execute the instruction MOV r0, pc through t[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-65 ID013010 Non-Confidential, Unrestricted Access Example 1 1- 17 Writing the CPSR WriteCPSR(uint32 cpsr_val) { // Step 1. Save R0. saved_r0 := ReadRegister(0); // Step 2. Write the new CPSR value to R0. WriteRegister(0, cpsr_val); // Step 3. Execute instruction MSR R0, CPSR[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-66 ID013010 Non-Confidential, Unrestricted Access { return false; } } Note Y ou can use a similar sequence to read a halfword of memory and to write to memory . T o read or write blocks of memory , substitute the data instruction with one that uses post-indexed addressing. F[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-67 ID013010 Non-Confidential, Unrestricted Access // Step 2. Write the address to R0. WriteRegister(0, address); // Step 3. Execute instruction LDC p14, c5, [R0] through the ITR. ExecuteARMInstruction(0xED905E00); // Step 4. Read the value from the DTR directly. datum := Rea[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-68 ID013010 Non-Confidential, Unrestricted Access WriteDebugRegister(32, value); // Step 2. Write the opcode for MRC p14, 0, Rd, c5, c0 to the ITR. // Write stalls until the ITR is ready. WriteDebugRegister(33, 0xEE100E15 + (Rd<<12)); } Note T o transfer a register to [...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-69 ID013010 Non-Confidential, Unrestricted Access } Example 1 1-26 shows the sequence for writing a block of words to memory . Example 1 1-26 W riting a block of wo rds to memory (fast download) WriteWords(uint32 address, bool &aborted, uint32 *data, int nwords) { // Ste[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-70 ID013010 Non-Confidential, Unrestricted Access // Step 1. Save R0. saved_r0 := ReadRegister(0); // Step 2. Execute instruction MCR p15, 0, R0, c0, c1, 0 through the ITR. ExecuteARMInstruction(0xEE000010 + (CPnum<<8) + (opc1<<21) + (CRn<<16) + CRm + (opc2[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-71 ID013010 Non-Confidential, Unrestricted Access 1 1.12 Debugging systems with ener gy management capa bilities The processor offers functionality for debugging systems with energy-man agement capabilities. This section describes scenarios where the OS takes energy-saving m[...]

Debug ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-72 ID013010 Non-Confidential, Unrestricted Access • Attaching the debugger for a post mortem debug session is not possible because setting the DBGNOPWRDWN signal to 1 m ight not cause the pro cessor to power up. The effect of setting DBGN OPWRDWN to 1 when the processor is[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-1 ID013010 Non-Confidential, Unrestricted Access Chapter 12 FPU Programmer ’ s Model This chapter describes the programmer ’ s model of the Floating Poin t Unit (FPU). The Cortex-R 4F processor is a Cortex-R4 processor that includes t he optional FPU. In this chapter, the gene[...]

FPU Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-2 ID013010 Non-Confidential, Unrestricted Access 12.1 About the F PU programmer ’ s model The FPU implements the VFPv3- D16 architecture and the Comm on VFP Sub-Architecture v2. This includes the instruct ion set of the VFPv3 architecture. See the ARM Ar[...]

FPU Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-3 ID013010 Non-Confidential, Unrestricted Access 12.2 General-purpose registers The FPU implements a VFP register bank. This bank is distinct from the ARM register bank. Y ou can reference the V FP register bank using two explicitly al iased views. Figure [...]

FPU Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-4 ID013010 Non-Confidential, Unrestricted Access 12.3 System registers The VFPv3 architecture describes the following system registers: • Floating-Point System ID Register , FPSID o n page 12-5 • Floating-Point Status and Contr ol Register , FPSCR on p[...]

FPU Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-5 ID013010 Non-Confidential, Unrestricted Access Note All hardware ID informati on is privileged access only: FPSID is privileged access only This is a change in VFPv3 compared to VFPv2. MVFR registers ar e privileged access only User code must issue a sys[...]

FPU Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-6 ID013010 Non-Confidential, Unrestricted Access 12.3.2 Floating-Poin t St atus and Control Register , FPSCR FPSCR is a read/write register that can be acce ssed in both Privileged a nd nonprivileged modes. All bits describe d as DNM in Figure 12-3 are res[...]

FPU Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-7 ID013010 Non-Confidential, Unrestricted Access 12.3.3 Floating-Poin t Exception Re gister , FPEXC The FPEXC Register is a read/write re gister accessible in Privileged modes only . The EN bit, FPEXC[30], is the VFP enable bit. Clearing EN d isables VFP f[...]

FPU Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-8 ID013010 Non-Confidential, Unrestricted Access T able 12-5 shows how the bit values correspond with the FPEXC Register functions. 12.3.4 Media and VFP Feature Regist ers, MVFR0 and MVFR1 The VFP Feature Registers, MVFR0 and MVFR1, are read-only register [...]

FPU Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-9 ID013010 Non-Confidential, Unrestricted Access Figure 12-6 MVFR1 Register form at T able 12-7 shows how the bit values correspond with the MVFR1 Register . FZ Reserved I DN SP LS 31 20 19 16 15 12 1 1 8 7 4 3 0 T able 12-7 MV FR1 Register bit fu nctions [...]

FPU Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-10 ID013010 Non-Confidential, Unrestricted Access 12.4 Modes of operation The FPU provides three modes of operation to accommodate a variety of applications: • Full-compliance mode • Flush-to-zero mode • Default NaN mode 12.4.1 Full-compliance mode I[...]

FPU Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-11 ID013010 Non-Confidential, Unrestricted Access 12.5 Compliance with the IEEE 754 standard When Default NaN (DN) and Flush-to-Zer o (FZ) modes are disabled, the VFP fun ctionality is compliant with the IEEE 7 54 standard in hardware . No support co de is[...]

FPU Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-12 ID013010 Non-Confidential, Unrestricted Access • In default NaN mode, arit hmetic CDP instructions involving NaN operand s return the default NaN regardle ss of the fractions of any NaN operands. SNaNs in an arithmetic CDP operation set the IOC flag, [...]

FPU Programmer’s Model ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-13 ID013010 Non-Confidential, Unrestricted Access 12.5.3 Exceptions The FPU implements the VFPv3 ar chitecture and sets the cumula tive exception stat us flag in the FPSCR register as required for each instructio n. The FPU does not s upport user-mode trap[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 13-1 ID013010 Non-Confidential, Unrestricted Access Chapter 13 Integration T est Registers This chapter describes how to use the Integration T e st Registers in the pro cessor . It contains the following sections: • About Integration T est Registers on page 13-2 • Pr ogramming an[...]

Integration Test Registers ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 13-2 ID013010 Non-Confidential, Unrestricted Access 13.1 About Integ ration T est Registers The processor contains Integratio n T est Registers that enable you to verify integration of th e design and enable topolog y detection of the design using debug too[...]

Integration Test Registers ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 13-3 ID013010 Non-Confidential, Unrestricted Access 13.2 Programming and reading Integration T est Registers The Integration T est Register s are programmed using the de bug APB interface. For more information on using the debu g APB interface see Chapter 1[...]

Integration Test Registers ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 13-4 ID013010 Non-Confidential, Unrestricted Access 13.3 Summary of the processor regist ers used for integration testing T able 13-1 lists the processor Integration T est Registers and the Integration Mode Contr ol Register (ITCTRL). T able 13-1 Integr ati[...]

Integration Test Registers ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 13-5 ID013010 Non-Confidential, Unrestricted Access 13.4 Processor integration testing This section describes the behavior and use of the Integration T est Regi sters that are in the processor . It also describes the Integration Mode Control Register that c[...]

Integration Test Registers ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 13-6 ID013010 Non-Confidential, Unrestricted Access This section describes: • Using the Integration T est Reg isters • Performing integra tion testing • ITETMIF Register (ETM interface) on page 13-7 • ITMISCOUT Register (Miscellaneous Outputs) on pa[...]

Integration Test Registers ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 13-7 ID013010 Non-Confidential, Unrestricted Access 13.4.3 ITETMIF Register (ETM interface) The ITETMIF Register at of fset 0xED8 is write-only . Figure 13-1 shows the register bit assignments. Figure 13-1 ITETMIF Reg ister bit assignments T able 13-4 shows[...]

Integration Test Registers ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 13-8 ID013010 Non-Confidential, Unrestricted Access 13.4.4 ITMISCOUT Register (Miscellaneous Output s) The ITMISCOUT Register at of fset 0xEF8 is write-only . Figu re 13-2 shows the register bit assignments. Figure 13-2 ITMISCO UT Register b it assignment s[...]

Integration Test Registers ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 13-9 ID013010 Non-Confidential, Unrestricted Access Figure 13-3 ITMI SCIN Register bit assign ments T able 13-6 lists the register bit assignments for the ITMISCIN Register . 13.4.6 Integration Mode Contr ol Register (ITCTRL) The ITCTRL Register , register [...]

Integration Test Registers ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 13-10 ID013010 Non-Confidential, Unrestricted Access T able 13-7 shows the fields of the ITCTRL Register . W riting to the ITCTRL register controls whether the processor is in its default functional mode, or in integration mode, where the inputs an d output[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-1 ID013010 Non-Confidential, Unrestricted Access Chapter 14 Cycle T imings and Interlock Behavior This chapter describes the cycle timin gs and interlock behavior of inst ructions on the processor . It contains the following sections: • About cycle timings and interlock behavior[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-2 ID013010 Non-Confidential, Unrestricted Access • Floating-point do uble-pr ecision data pr ocessing instructions on page 14-33 • Dual issue on page 14-34.[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-3 ID013010 Non-Confidential, Unrestricted Access 14.1 About cycle timings and interlock behav ior Complex inst ruction dependencies an d memory system interactions make it impossible to describe briefly the exact cycle timing behavior for all i[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-4 ID013010 Non-Confidential, Unrestricted Access ADD R3, R3, R1 LSL#6 ;plus one because Register R1 is Early The following sequence where R1 is a Late Reg takes two cycles: LDR R1, [R2] ;Result latency two minus one cycles STR R1, [R3] ;no pena[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-5 ID013010 Non-Confidential, Unrestricted Access 14.1.5 Assembler language syntax The syntax used throug hout this chapter is un if ied assembler and the timing s apply to ARM and Thumb instructions. Early Reg T he specified registers are requi[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-6 ID013010 Non-Confidential, Unrestricted Access 14.2 Register interlock examples T able 14-2 shows register interlock exam ples using LDR and ADD instructions. LDR instructions take one cycle, have a result late ncy of two, and require their b[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-7 ID013010 Non-Confidential, Unrestricted Access 14.3 Data processing instructions This section describes the cycle tim ing behavior for the ADC , ADD , ADDW , AND , ASR , BIC , CLZ , CMN , CMP , EOR , LSL , LSR , MOV , MOVT , MOVW , MVN , ORN [...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-8 ID013010 Non-Confidential, Unrestricted Access 14.3.3 Exam ple interlock s Most data processing instruct ions are single-c ycle and can be execute d back-to-b ack without interlock cycles, even if there are data depende ncies between them. Th[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-9 ID013010 Non-Confidential, Unrestricted Access 14.4 QADD , QDADD, QSUB, and QDS UB instructions This section describes the cycle timing behavi or for the QADD , QDADD , QSUB , and QDSUB instructions. These instructions perfo rm saturating ari[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-10 ID013010 Non-Confidential, Unrestricted Access 14.5 Media data-processing T able 14-6 shows media data-processing instruct ions and gives their cycle timing behavior . All media data-processing inst ruct ions are single-cycle issue in struct[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-11 ID013010 Non-Confidential, Unrestricted Access 14.6 Sum of Ab solute Differences (SAD) T able 14-7 shows SAD instructions and gives their cycle timi ng behavior . 14.6.1 Exam ple interlock s T able 14-8 shows interlock exam ples using USAD8 [...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-12 ID013010 Non-Confidential, Unrestricted Access 14.7 Multiplies Most multiply operations cannot forward their result early , excep t as the accumulate value for a subsequent multiply . Fo r a subsequent multiply accumulate the resu lt is avai[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-13 ID013010 Non-Confidential, Unrestricted Access Note Result Latency is one less if the result is us ed as the accumulate value for a subsequent multiply accumulate. This only a pplies if the result is the same width as the accumulate value, t[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-14 ID013010 Non-Confidential, Unrestricted Access 14.8 Divide This section describes the cycle timing behavior of the UDIV and SDIV instructions. The divider unit is separate to the main execute pipeline so the UDIV and SDIV instructions requir[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-15 ID013010 Non-Confidential, Unrestricted Access 14.9 Branches This section describes the cy cle timing behavior for the B , BL , BLX , BX , BXJ , CBNZ , CBZ , TBB , and TBH instructions. Branches are subject to dynamic and return stack predic[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-16 ID013010 Non-Confidential, Unrestricted Access 14.10 Processor state up dating in structions This section describes the cycle timing behavior fo r the MSR , MRS , CPS , and SETEND instructions. T able 14-11 shows processor state updating in [...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-17 ID013010 Non-Confidential, Unrestricted Access 14.1 1 Single load and store instructions This section describes the cycle timing behavior for LDR , LDRHT , LDRSBT , LDRSHT , LDRT , LDRB , LDRBT , LDRSB , LDRH , LDRSH , STR , STRT , STRB , ST[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-18 ID013010 Non-Confidential, Unrestricted Access Only cycle times for aligned accesses are given because Unaligned accesses to the PC are not supported. The processor includes a 4-entr y return stack that can predic t procedure retu rns. Any L[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-19 ID013010 Non-Confidential, Unrestricted Access LDR R6, [R2, #0X10]! LDR R7, [R2, #0X20]![...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-20 ID013010 Non-Confidential, Unrestricted Access 14.12 Load and Store Double instructions This section describes the cycle timing behavior fo r the LDRD and STRD instructions. The LDRD and STRD instructions: • Are normally single-cycle issue[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-21 ID013010 Non-Confidential, Unrestricted Access 14.13 Load and Store Multiple instructions This section describes the cycle timing behavior fo r the LDM , STM , PUSH , and POP instructions. These instruction s take multiple cycles to issue, a[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-22 ID013010 Non-Confidential, Unrestricted Access 14.13.2 Load Multiples, where th e PC is in the register list The processor includes a 4-en try return stack that can pr edict procedure returns. Any LDM to the PC that does not restore the SPSR[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-23 ID013010 Non-Confidential, Unrestricted Access PUSH {R1-R7} ADD R10,R10,R7 Note In the examples, R0 and sp are 64-bit aligned addresses. The instructions PUSH and POP always use the sp register for the base address.[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-24 ID013010 Non-Confidential, Unrestricted Access 14.14 RF E and SRS instructions This section describes the cycle timing for the RFE and SRS instructions. These instructions: • return from an exception and save exception return state respect[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-25 ID013010 Non-Confidential, Unrestricted Access 14.15 Synchronization instructions This section describes the cycle timing behavior fo r the CLREX , DMB , DSB , ISB , LDREX , LDREXB , LDREXD , LDREXH , STREX , STREXB , STREXD , STREXH , SWP ,[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-26 ID013010 Non-Confidential, Unrestricted Access 14.16 Co processor instructions This section describes the cycle timing behavior fo r the MCR and MRC instructions to CP14, the debug coprocessor or CP15, the system control coprocessor . The pr[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-27 ID013010 Non-Confidential, Unrestricted Access 14.17 SVC, BKPT , Undefined, and Prefetch Aborted instructions This section describes the cycle timing behavior fo r SVC , Undefined instruction, BKPT and Prefetch Abort. In all cases the except[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-28 ID013010 Non-Confidential, Unrestricted Access 14.18 Miscellaneous instructions T able 14-23 show s the cycle timing behavior for If-Then (IT) and No OPeration (N OP) instructions. The DBG , PLI , SEV , WFE , and YIELD instructions are all t[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-29 ID013010 Non-Confidential, Unrestricted Access 14.19 Floating-point regist er transfer instructions This section describes the cycle timing b ehavior for the various VFP inst ruction which transfer data between the VFP register fi le and the[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-30 ID013010 Non-Confidential, Unrestricted Access 14.20 Floating-point lo ad/store instructions This section describes the cycle timi ng behavior fo r all load and store instructions that operate on the VFP register file: • The base address r[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-31 ID013010 Non-Confidential, Unrestricted Access First address not 64-bit aligned VLDM{mode}.32 <Rn>{!}, {s1} 11 1 1 - VLDM{mode}.32 <Rn>{!}, {s1,s2 } 2 2 1,2 2 - VLDM{mode}.32 <Rn>{!}, {s1-s3 } 2 3 1,2,2 3 - VLDM{mode}.32 &l[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-32 ID013010 Non-Confidential, Unrestricted Access 14.21 Floating -point single-precis ion dat a processing instructions This section describes the cycle timing behavior fo r all single-precision VFP CDP instructions. This includes arithmetic in[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-33 ID013010 Non-Confidential, Unrestricted Access 14.22 Floating-point dou ble-precision dat a processing instructions This section describes the cycle timing behavior for all double-precision VFP CDP instructions. This includes arithmetic inst[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-34 ID013010 Non-Confidential, Unrestricted Access 14.23 Du al issue T o increase instruction throughput, the processo r can issue certain pairs of instructions simultaneously . This is called dual issue. When this happen s, the instruction with[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-35 ID013010 Non-Confidential, Unrestricted Access 14.23.2 Permitted co mbinations T able 14-28 lists t he permitted instruction com binations. Any instruction can be conditional or flag-setting unless otherw ise stated. Only the exact instructi[...]

Cycle Timings and Interlock Behavior ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-36 ID013010 Non-Confidential, Unrestricted Access Case F2_st b VSTR.F32 n As for Case B1. Any single-precision CDP i , excluding multiply-accumula te instructions o . 32-bit transfers to and from the floating-point register file l . Case F2D b [...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-1 ID013010 Non-Confidential, Unrestricted Access Chapter 15 AC Characteristics This chapter gives the timing parameters for the processor . It contain s the following sections: • Pr ocessor timing on page 15-2 • Pr ocessor timing parameters on page 15-3.[...]

AC Characteristics ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-2 ID013010 Non-Confidential, Unrestricted Access 15.1 Processor timing The AXI bus interface of the processor conforms to the AMBA AXI Specification . For the relevant timing of the AXI wr ite and read transfers, and the error response, see the AMBA AXI Pr otoco[...]

AC Characteristics ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-3 ID013010 Non-Confidential, Unrestricted Access 15.2 Processor timing parameters This section describes the input and output port timing parameters for the processor . The maximum timing parameter or constraint dela y for each processor sign al applied to the S[...]

AC Characteristics ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-4 ID013010 Non-Confidential, Unrestricted Access T able 15-3 shows the timing parameters for the interrupt input ports. T able 15-4 shows the input timing paramet ers for the AXI master port. Clock uncertainty 20% P ARL VRAM Clock uncertainty 20% ENTCM1IF Clock [...]

AC Characteristics ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-5 ID013010 Non-Confidential, Unrestricted Access T able 15-5 shows the input timi ng parameters for the AXI slave port. Clock uncertainty 60% RV A L I D M Clock uncertainty 60% BP AR ITYM Clock uncertainty 60% RP ARITYM T able 15-5 AXI slave input port timing pa[...]

AC Characteristics ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-6 ID013010 Non-Confidential, Unrestricted Access T able 15-6 shows the input timi ng parameters for the debug input ports. T able 15-7 shows the input timing paramet ers for the ETM input ports. Clock uncertainty 60% AW P A R I T Y S Clock uncertainty 60% WP ARI[...]

AC Characteristics ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-7 ID013010 Non-Confidential, Unrestricted Access T able 15-8 shows the timing parameters for the test input ports. T able 15-9 shows the timing parameters for the TCM interface input ports. T able 15-8 T est input ports timing p arameters Input dela y minimum In[...]

AC Characteristics ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-8 ID013010 Non-Confidential, Unrestricted Access The timing parameters for the dual-redundant core compare logic input con trol buses, DCCMINP[7:0] and DCCMINP2[7:0 ] , are implementation-defi ned. Contact the implementer of the macrocell you are working wi th. [...]

AC Characteristics ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-9 ID013010 Non-Confidential, Unrestricted Access T able 15-13 show s the timing parameters for t he AXI slave output ports. Clock uncertainty 60% A WPROTM[2:0] Clock uncertainty 60% A WUSERM[4:0] Clock uncertainty 60% AW V A L I D M Clock uncertainty 60% WIDM[3:[...]

AC Characteristics ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-10 ID013010 Non-Confidential, Unrestricted Access T able 15-14 shows the timing parameters for the debug interface output ports. Clock uncertainty 60% BRESPS[1:0] Clock uncertainty 60% BV ALIDS Clock uncertainty 60% ARREADYS Clock uncertainty 60% RIDS[7:0] Clock[...]

AC Characteristics ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-11 ID013010 Non-Confidential, Unrestricted Access T able 15-15 shows the timing parameters for the ETM interface output ports. T able 15-16 shows the timing parameters for the test output po rts. T able 15-17 shows the timing parameters for the TCM interface out[...]

AC Characteristics ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-12 ID013010 Non-Confidential, Unrestricted Access T able 15-18 shows the timing parameters for the FPU output signals. Clock uncertainty 45% A TCADDRPTY Clock uncertainty 45% B0TCEN0 Clock uncertainty 45% B0TCEN1 Clock uncertainty 45% B0TCADDR[22:3] Clock uncert[...]

AC Characteristics ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-13 ID013010 Non-Confidential, Unrestricted Access The timing parameters for the dual-redundant core compare logic output buses, DCCMOUT[7:0] and D CCMOUT2[7:0] , are implementation-de fined. Contact the implementer of the macro cell you are working with.[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-1 ID013010 Non-Confidential, Unrestricted Access Appendix A Processor Signal Descriptions This appendix describes the processor signals. It contains th e following sections: • About the pr ocessor signal descriptions on p age A-2 • Global signals on page A-3 • Configuration s[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-2 ID013010 Non-Confidential, Unrestricted Access A.1 About the processor signal descriptions The tables in this appendix list t he processor signals, along with their dim ensions and direction, input or output, and a high-level descripti on. Each table[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-3 ID013010 Non-Confidential, Unrestricted Access A.2 Global signals T able A-1 shows the processor global sign als. The free clock is ungated, with minima l insertion delay , because it clocks the clock gating circuits. Therefore, you must ensure that [...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-4 ID013010 Non-Confidential, Unrestricted Access A.3 Configuration signals T able A-2 shows the processor configuration sign als. T able A-2 Config uration signals Signal Direction Clocking Description VINITHI Input T ie-off, Reset Reset V -bit value. [...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-5 ID013010 Non-Confidential, Unrestricted Access CFGBTCMSZ[3:0] Input T ie-of f Selects the BTCM size. The encodings for the TCM sizes are: b0000 = 0KB b001 1 = 4KB b0100 = 8KB b0101 = 16KB b01 10 = 32KB b01 1 1 = 64KB b1000 = 128KB b1001 = 256KB b1010[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-6 ID013010 Non-Confidential, Unrestricted Access ERRENRAM[2:0] Input T ie-of f, Reset TCMs external error enable. T ie each bit high to enable the external error signals for each TCM at reset. Use the following values: 2: B1TCM 1: B0TCM 0: A TCM See Au[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-7 ID013010 Non-Confidential, Unrestricted Access A.4 Interrupt signals, incl uding VIC interface signals T able A-3 shows the Interrupt signals incl uding signals used on the VIC interface. T able A-3 Inte rrupt sign als Signal Direction Clocking Descr[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-8 ID013010 Non-Confidential, Unrestricted Access A.5 L2 interface signals This section describes the pr ocessor L2 interface AXI signal s. For more information on Advanced Micr ocontr oller Bus Ar chitecture (AMBA) AXI signals s ee the AMBA AXI Pr otoc[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-9 ID013010 Non-Confidential, Unrestricted Access AW VA L I D M Output CLKIN Indicates add ress a nd control are valid. W rite data channel WDA T AM[63:0] Output CLKIN Write data. WIDM[3:0] Output CLKIN The identification tag for the write data group of[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-10 ID013010 Non-Confidential, Unrestricted Access A.5.2 AXI master port error detection signals T able A-5 shows the AXI master port error detecti on signals. these signals are only generate d if the processor is configured to in clude AXI bus parity .[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-11 ID013010 Non-Confidential, Unrestricted Access A WBURSTS[1:0] Input CLKIN W rite burst type. A WIDS[7:0] Input CLKIN The identification tag for the write address group of signals. A WLENS[3:0] Input CLKIN W rite transfer burst length. The transfer b[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-12 ID013010 Non-Confidential, Unrestricted Access A.5.4 AXI slave port error detect ion signals T able A-7 shows the AXI slave port error detect ion signals. These signals are only generated if the processor is configured to in clude AXI bus parity . S[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-13 ID013010 Non-Confidential, Unrestricted Access A.6 TCM interface signals T able A-8 shows the A TCM port signals. T able A-9 shows the B0TCM port signals. T able A-8 A TCM port si gnals Name Direction Clo cking Description A TCDA T AIN [63:0] Input [...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-14 ID013010 Non-Confidential, Unrestricted Access T able A-10 shows the B1TCM port signals. B0TCLA TEERROR Input CLKIN Late error from B0TCM a B0TCRETR Y Input CLK IN Access to B1TCM must be retried a B0TCADDRPTY Output CLKIN Parity formed from B0TCM a[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-15 ID013010 Non-Confidential, Unrestricted Access B1TCADDR [22:3] Output CLKIN Address for B1TCM data RAM B1TCBYTEWR [7:0] Output CLKIN Byte strobes for direct write B1TCSEQ Output CLKIN B1TCM RAM access is sequential B1TCDA T AOUT [63:0] Output CLKIN [...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-16 ID013010 Non-Confidential, Unrestricted Access A.7 Dual core interface signals T able A-1 1 shows the dual redundant core interface signals. T able A-1 1 Dual core interface signals Signal Direction Clocking Description DCCMINP[7:0] Input - a a. Imp[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-17 ID013010 Non-Confidential, Unrestricted Access A.8 Debug interface signals T able A-12 shows the debug interface signals. W ith the exception of PCLKDBG , PCLKENDBG and PRESETDBGn , all these signals are only sampled or driven on PCLKDBG edges when [...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-18 ID013010 Non-Confidential, Unrestricted Access DBGROMADDR V Input T ie-off D ebug ROM physical address valid DBGSELF ADDR[31:12] Input Tie-of f Debug self-address of fset DBGSELF ADDR V Input T ie-off D ebug self-address of fset valid a. Not availab[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-19 ID013010 Non-Confidential, Unrestricted Access A.9 ETM interface signals T able A-14 shows the ETM interface signals. T able A-14 ETM interface signals Signal Directio n Clocking Description ETMICTL[13:0] Output CLKIN ETM instruction control bus ETM[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-20 ID013010 Non-Confidential, Unrestricted Access A.10 T e st signals T able A-15 shows the test signals. T able A-15 T est signals Signal Direction Clocking Descriptio n SE Input - a a. Design for test only . Scan Enable RSTBYP ASS Input - a Bypass pi[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-21 ID013010 Non-Confidential, Unrestricted Access A.1 1 MBIST signals T able A-16 shows the MBIST signals. T able A-16 MBIST signals Signal Direction Clocking Description MBTESTON Input CLKIN MB IST test is enabled MBISTDIN[77:0] Input CLKIN MBIST data[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-22 ID013010 Non-Confidential, Unrestricted Access A.12 V alidation signals T able A-17 shows the validation signals. T able A-17 V alidation signals Signal Direction Clockin g Descr iption V ALEDBGRQ Output CLKIN Debug request nV ALIRQ Output CLKIN Req[...]

Processor Signal Descriptions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-23 ID013010 Non-Confidential, Unrestricted Access A.13 FPU signals T able A-18 shows the FPU signals. These signals are only driven if the processor is configured to include the floating-point log ic. T able A-18 FPU signals Signal Direction Clockin g [...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. B-1 ID013010 Non-Confidential, Unrestricted Access Appendix B ECC Schemes This appendix describes som e of the advantages and disadvant ages of the different Err or Checking and Corr ection (ECC) schemes for the TCMs. It contain s the following section: • ECC scheme selection gu id[...]

ECC Schemes ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. B-2 ID013010 Non-Confidential, Unrestricted Access B.1 ECC scheme selection guidelines When deciding to i mplement a Cortex-R4 processor with an ECC scheme on one or both of the TCM interfaces, give careful consid eration between using 32-bit or 64-bit ECC. T o calculate [...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. C-1 ID013010 Non-Confidential, Unrestricted Access Appendix C Revisions This appendix describes the technical changes between rel eased issues of this book. T able C-1 Differences between iss ue B and issue C Change Location Clarified the description of Thumb- 2 technology and Thumb [...]

Revisions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. C-2 ID013010 Non-Confidential, Unrestricted Access Updated reset value information for: • Cache T ype Register • MPU T ype Register • Instruction Set Attributes Register 1 • Instruction Set Attributes Register 4 • Current Cac he Size Identification Reg ister • C[...]

Revisions ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. C-3 ID013010 Non-Confidential, Unrestricted Access Added section Dormant mode on page 10-3 Updated the permitted instruction combinations T able 14-28 on page 14-35 Updated the descriptions for COMMRX and COMMTX signals T able A-13 on page A-17 T able C-2 Differences betwee[...]

ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-1 ID013010 Non-Confidential, Unrestricted Access Glossary This glossary describes some of the terms and ab breviations used in this manual. Where t erms can have several meanings, the meaning presented here is intended. Abort A mechanism that indicates to a processor that t[...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-2 ID013010 Non-Confidential, Unrestricted Access Advanced High-pe rformance Bus (AHB) The AMBA Advanced High-perfo rmance Bus system connects embe dded processors such as an ARM core to high-performance periph eral s, DMA controllers, on-chip memory , and interface[...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-3 ID013010 Non-Confidential, Unrestricted Access • the master and slave interface conventions for AXI components. AXI terminology Th e following AXI terms ar e general. They apply to both masters and slaves: Active read transaction A transaction for which the rea[...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-4 ID013010 Non-Confidential, Unrestricted Access Read ID wi dth The number of bits in the ARID bus. Read issuing capability The maximum number of act ive read transactions that a master interface can generate. Write ID capability The maximum nu mber of dif f erent [...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-5 ID013010 Non-Confidential, Unrestricted Access Base register write-back Updating the contents of the base register used in an instruction ta r get address calculation so that the modified address is changed to the next hi gher or lower sequential address in memor[...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-6 ID013010 Non-Confidential, Unrestricted Access Byte invariant In a byte-invariant system, the address of eac h byte of memory remains unchanged when switching between little-endian and big-endian opera tion. When a data item larger than a byte is loaded from or s[...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-7 ID013010 Non-Confidential, Unrestricted Access Clean A cache line that has not been modified while it is in the cache is said to be clean. T o clean a cache is to write dirty cache entries into main me mory . If a cache line is clean, it is not written on a cache[...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-8 ID013010 Non-Confidential, Unrestricted Access Cycles Per instructio n (CPI) Cycles per instruction (or clocks per instructi on) is a measure of th e number of computer instructions that can be performed in one cloc k cycle. This figure of merit can be used to co[...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-9 ID013010 Non-Confidential, Unrestricted Access Enabled exception An exception is enabled when its exception enable bit in the FPCSR is set. When an enabled exception occurs, a trap to the us er handler is taken. An operation th at generates an exception condition[...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-10 ID013010 Non-Confidential, Unrestricted Access Illegal instructio n An instruction that is architecturally Undefined. Implementation-defined Means that the behavior is not architecturally defined, but shou ld be defined and documented by individual impl ementati[...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-11 ID013010 Non-Confidential, Unrestricted Access Load Store Unit (LSU) The part of a processor that ha ndles load and s tore transfers. LSU See Load Store Unit. Macrocell A complex logic block with a de fined interface and beha vior . A typical VLSI system compris[...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-12 ID013010 Non-Confidential, Unrestricted Access Reserved A field in a control register or instruction fo rmat is reserved if the field is to be defined by the implementation, or produces Unpredictab le results if the contents of the field are not zero. These fiel[...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-13 ID013010 Non-Confidential, Unrestricted Access Str id e The stride field, FPSCR[21:20 ], specifies the incremen t applied to register ad dresses in short vector operations. A stride of 0 0, specifying an increment of +1, causes a short vector operation to increm[...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-14 ID013010 Non-Confidential, Unrestricted Access Unsupported valu es Specific data values that are not processed by the hardware but bounced to the support code for completion. These data can include infiniti es, NaNs, subnormal values, and zeros. An implementatio[...]

Glossary ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossa ry-15 ID013010 Non-Confidential, Unrestricted Access Write-through (WT) In a write-through cache, data is written to main me mory at the same time as the cache is updated. WT See W rite-through. Cache terminology diagram The figure below illustrates the follo wing cac[...]