National CP3BT26 manual

©2004 National Semiconductor Corporation www.national.com CP3BT26 Connectivity Processor with Bluetooth and Dual CAN Interfaces PRELIMINAR Y MA Y 2004 CP3BT26 Repr ogrammable Connectivity Pr ocessor with Bluetooth ® , USB, and CAN Interfaces 1.0 General Description The CP3BT26 connectivity processor combines high perfor- mance with the massive in[...]

www.national.com 2 CP3BT26 T able of Contents 1.0 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 CR16C CPU Core . . . . . . . . . . . . . . . . . . . . [...]

3 www.national.com CP3BT26 2.0 Features CPU Features  Fully static RISC processor core, capable of oper ating from 0 to 24 MHz with zero w ait/hol d states  Minimum 41.7 ns instruction cycle time with a 24-MHz in- ter nal clock frequency , based on a 12-MHz e xter nal input  47 independently vectored peripheral in terr upts On-Chip Memory [...]

www.national.com 4 CP3BT26 3.0 Device Overview The CP3BT26 connectivity p rocessor is a complete micro- computer with all system timi ng, interrupt logic, progr am memor y , data memor y , and I/O por ts included on-chip , mak- ing it well-suited to a wide range of embedded application s. The bloc k diagram on page 1 shows the major on-chip com- po[...]

5 www.national.com CP3BT26 3.7 BLUETOOTH LLC The integrated hardware Bluetooth Lower Link Controller (LLC) complies to the Bluetooth Specification V e rsion 1.1 and integrates the f ollowing functions:  4.5K-byte dedicated Bluetooth Data RAM  1K-byte dedicated Bluetooth Sequencer RAM  Suppor t of all Blueto oth 1.1 pack et types  Suppor[...]

www.national.com 6 CP3BT26 3.14 RANDOM NUMBER GENERATOR RNG periphe ral f or use in T r usted Computer P eriphe ral Ap- plications (TCP A) to improve t he authenticity , integr ity , and privacy of Internet-based communication and commerce. 3.15 MICROWIRE/SPI The Microwire/SPI (MWSPI) interface module suppor ts syn- chronous serial communications w[...]

7 www.national.com CP3BT26 3.21 P OWER MAN AGEMENT The P ower Management Module (PMM) improves the effi- ciency of the device b y cha nging the operating mode and power consumption to match the required le vel of activity . The device can oper ate in any of four po wer modes: — Active : The device operates at full speed using the high-frequency c[...]

www.national.com 8 CP3BT26 4.0 Signal Descriptions Figure 1. CP3BT26 Device SIgnals Some pins ma y be enabled as general-pur pose I/O-por t pins or as alter nate functions associated wi th specific pe- ripherals or interfaces. These pins ma y be indi vidually con- figured as por t pins, e ven when the associated peripheral or interf a ce is enabled[...]

9 www.national.com CP3BT26 Table 2 CP3BT26 LQFP-128 Signal Descriptions Name Pins I/O Primary Function Alterna te Name Alternate Functio n X1CKI 1 In put 12 MHz Oscillator Input BBCLK BB reference cloc k for the RF Interface X1CK O 1 Output 12 MHz Oscillator Output None None X2CKI 1 In put 32 kHz Oscillator Input None None X2CK O 1 Output 32 kHz Os[...]

www.national.com 10 CP3BT26 ADC3 1 I/O ADC Input Channel 3 TSY - T ouchscreen Y - co ntact ADC4 1 I/O ADC Input Channel 4 MUXOUT0 Analog Multiple xer Output 0 ADC5 1 I/O ADC Input Channel 5 MUXOUT1 Analog Multiple xer Output 1 ADC6 1 Input ADC Input Channel 6 None None ADC7 1 Input ADC Input Channel 7 ADCIN ADC Input (in MUX mode) VREFP 1 Input ADC[...]

11 www.national.com CP3BT26 PG4 1 I/O Generic I/O SD A T BT Serial I/F Data PG5 1 I/O Generic I/O SLE BT Serial I/F Load Enable Output PG6 1 I/O Generic I/O WUI10 Multi-Input W ake-Up Channel 10 BTSEQ2 B luetooth Sequencer Status PG7 1 I/O Generic I/O T A Multi Function Timer Port A BTSEQ3 B luetooth Sequencer Status PH0 1 I/O Generic I/O RXD1 U AR[...]

www.national.com 12 CP3BT26 Table 3 CP3BT26 LQFP-144 Signal Descriptions Name Pins I/O Primar y Function Alternate Name Alternate Function X1CKI 1 Inpu t 12 MHz Oscillator Input BBCLK BB re f erence clock for the RF Interf ace X1CK O 1 Output 12 MHz Oscillator Output None None X2CKI 1 Inpu t 32 kHz Oscillator Input None None X2CK O 1 Output 32 kHz [...]

13 www.national.com CP3BT26 ADC3 1 I/O ADC Input Channel 3 TSY - T ouchscreen Y - contac t ADC4 1 I/O ADC Input Channel 4 MUXOUT0 Analog Multiplex er Output 0 ADC5 1 I/O ADC Input Channel 5 MUXOUT1 Analog Multiplex er Output 1 ADC6 1 Input ADC Input Channel 6 None None ADC7 1 Input ADC Input Channel 7 ADCIN ADC Input (in MUX mode) VREFP 1 Input ADC[...]

www.national.com 14 CP3BT26 PF6 1 I/O Gener ic I/O STD AAI T ransmit Data Output TIO7 V ersa tile Timer Channel 7 PF7 1 I/O Gener ic I/O SRD AAI Receive Data Input TIO8 V ersa tile Timer Channel 8 PG0 1 I/O Gener ic I/O RFSYNC BT A C Correla tion/TX Enable Output PG1 1 I/O Gener ic I/O RFCE BT RF Chip Enable Output PG2 1 I/O Ge neric I/O BTSEQ1 Blu[...]

15 www.national.com CP3BT26 5.0 CPU Arc hitecture The CP3BT26 use s the CR16C third-gene ration 16-bit CompactRISC processor core. The CPU implements a Re- duced Instructi on Set Computer (RISC) architecture that al- lows an eff ective e xecution rate of up to one instruction per clock cycle . For a detailed desc ription of the CPU16C archi- tectur[...]

www.national.com 16 CP3BT26 5.2.4 Interrupt Base Register (INTB ASE) The INTBASE register holds t he address of the dispatch ta- ble f or exceptions . The dispatch table can be located any- where in the CPU ad dress space. When loading the INTBASE register , bits 31 to 24 and bit 0 must written with 0. 5.3 PROCESSOR STATUS REGISTER (PSR) The PSR pr[...]

17 www.national.com CP3BT26 5.4 CONFIGURATION REGISTER (CFG) The CFG register is use d to enable or disable various oper- ating modes and to con trol optional on -chip caches. Be- cause the CP3BT26 does not hav e cache memor y , the cache control bits in the CFG regi ster are reser ved. All CFG bits are cleared on reset. ED The Extended Dispatch bi[...]

www.national.com 18 CP3BT26 5.5 ADDRESSING MODES The CR16C CPU core implements a load/store architec- ture, in which ari thmetic and logical in structio ns operate on register operands. Memor y operands are made accessible in registers using load and store instr uctions. F or effici ent implementation of I/O-intensive embedded applications, the arc[...]

19 www.national.com CP3BT26 5.6 STACKS A stack is a last-in, first-out data structure f or dynamic stor- age of data and addresses. A stack consists of a block of memor y used to hold the data a nd a pointer to the top of th e stack. As more data is pushed onto a stack, the stac k grows downw ard in memor y . The CR16C suppor t s two types of stack[...]

www.national.com 20 CP3BT26 Table 5 Instruction Set Summary Mnemonic Oper ands Descript ion MO Vi Rsrc/imm, Rdest Mov e MO VXB Rsrc, Rdest Mov e with sign extension MO VZB Rsrc, Rdest Move with zero e xte nsion MO VXW Rsrc, RPdest Mov e with sign extension MO VZW Rsrc, RPdest Mov e with zero e xte nsion MO VD imm, RPdest Mov e immediate to register[...]

21 www.national.com CP3BT26 ASHUD Rsrc/imm, RPdest Arithmetic left/righ t shift LSHi Rsrc/imm, Rdest Logical left/r ight shift LSHD Rsrc/imm, RPdest Logical left/right shift SBITi Iposition, disp(Rb ase) Set a bit in memor y (Because this instruction trea ts the destination as a read- modify-write o perand, it not be u sed to set bits in write- onl[...]

www.national.com 22 CP3BT26 RETX Retur n from exception PUSH imm, Rsr c, RA Push “imm” n umber of registers on user stack, star ting with Rsrc and possibly including RA POP imm, Rdest, RA Rest ore “imm” number of registers from user stack, star ting with Rdest an d possibly including RA POPRET imm, Rdest, RA Restore registers (similar to PO[...]

23 www.national.com CP3BT26 ST ORMP imm3 Store 1 to 8 registers (R2-R5, R8-R11) to memor y star ting at (R7,R6) DI Disable maskab le interr upts EI Enable maskab le interr upts EIW AIT Enable maskable interrupts and wait f or interr upt NOP No operation W AIT W ait for interrupt Table 5 Instruction Set Summary Mnemonic Oper ands Descript ion[...]

www.national.com 24 CP3BT26 6.0 Memory The CP3BT26 suppor ts a unif or m 16M-byte linear address space. T able 6 lists the types of memor y and per ipherals that occupy this memor y space . Unlisted ad dress ranges are reser ved and must not be read or written. The BIU zones are regions of the addr ess space that share th e same control bits in the[...]

25 www.national.com CP3BT26 6.2 BUS INTERFACE U NIT (BIU) The BIU controls the interface between the CPU core bus and those on-chip module s which are mapped i nto BIU zones. These on-chip modules are the flash program mem- or y and the I/O zone. The BIU controls the configured pa- rameters f or bus access (suc h as the number of wait states f or m[...]

www.national.com 26 CP3BT26 6.4.2 I/O Z one Configur ation Register (IOCFG) The IOCFG register is a word-wide, read/write register that controls the timing and bus characteristics of accesses to the 256-byte I/O Zone memor y space (FF FB00 h to FF FBFFh). The registers associated with Po r t B and P or t C re- side in the I/O memor y arra y . At re[...]

27 www.national.com CP3BT26 IPRE The Preliminar y Idle bit controls whether an idle cycle is inser ted prior to the current bus cycle, when the ne w bus cycle accesses a dif- f erent zone. No idle cycles are required f or on- chip accesses . 0 – No idle cycle (recomme nded). 1 – Idle cycle inser ted. 6.4.4 Static Zone 1 Config uration Register [...]

www.national.com 28 CP3BT26 FRE The Fa st Re ad Enable bit controls whether f ast read bus cycles are used. A fast read op- eration takes one cloc k cycle. A nor mal read operation tak es at least two clock cycles . 0 – Nor mal read cycles. 1 – F ast read cycles. IPST The P ost Idle bit controls whether an id le cycle f ollows the current bus c[...]

29 www.national.com CP3BT26 7.0 System Configuration Registers The system configuration regi sters control and provide sta- tus for cer tain aspects of device setup and operation, such as indicating the states sampled from the ENV[2:0] inp uts. The system c onfiguration registers are list ed in T able 9. 7.1 MODULE CONFIGURATION REGISTER (MCFG) The[...]

www.national.com 30 CP3BT26 7.2 MODULE STATUS REGISTER (MST A T) The MST A T register is a byte-wide, read-only register that indicates the general status of the device . The MCFG regis- ter format is shown below . OENV2:0 The Operating Environment bits hold the states sa mpled from the ENV[ 2:0] input pins at reset. These states are controlled by [...]

31 www.national.com CP3BT26 8.0 Flash Memory The flash memor y consists of the flash program memor y and the flash data memor y . The flash program memor y is fur ther divide d into the Boot Area and the Code Area. A special protection scheme is applied to the l ower portio n of the flash prog ram memory , called the Boot Area. The Boot Area alwa y[...]

www.national.com 32 CP3BT26 8.2.1 Main Bloc k 0 and 1 Main Block 0 and Main Block 1 hold the 2 56K-byte progr am space, which consists of the Boot Area and Code Area. Each bloc k consists of sixteen 8K-b yte sections. Write ac- cess by the CPU to Main Block 0 and Main Block 1 is con- trolled by the corresponding bits in the FM0WER and FM1WER regist[...]

33 www.national.com CP3BT26 8.3.3 Main Bloc k P age Erase A flash erase operation sets all of the bits in the erased re- gion. P ages of a main block can be individually erased if their wri te enable bits are set. This method can not be used to erase the boot area, if defined. Each page i n Main Block 0 and 1 consists of 1024 bytes (512 words). Eac[...]

www.national.com 34 CP3BT26 8.4 INFORMATION BLOCK W ORDS T wo words in the inf or mation blocks are dedicated to hold settings that affect the operat ion of the system: the Function W ord in Information Block 0 and the Protection Word in In- f or mation Blo ck 1. 8.4.1 Function W ord The Function Word resides in the Information Block 0 at ad- dress[...]

35 www.national.com CP3BT26 RDPRO T The RDPRO T field controls the global read protection mechanism for the on-chip flash program memor y. If a major ity of the three RDPR OT bits are clear , the flash pr ogram memor y is protected against read access from the ser ial debug interface or an e xter nal flash programmer . CPU read access i s not af- f[...]

www.national.com 36 CP3BT26 8.5.1 Flash Memor y Information Bloc k Address Register (FMIB AR/FSMIBAR) The FMIBAR register specifies the 8-bit address for read or write access to an information block. Because only w ord ac- cess to the information blocks is supported, the least signif- icant bit (LSB) of the FMIBAR must be 0 (word-aligned). The hard[...]

37 www.national.com CP3BT26 8.5.5 Flash D ata Memory 0 Write Enable Register (FSM0WER) The FSM0WER register contro ls write protection for the flash data memor y . The data bloc k is divid ed into 16 512- byte sections . Each bit i n the FSM0WER register co ntrols write prote ction for one of these sections. The FSM0WER register is cleared a fter d[...]

www.national.com 38 CP3BT26 8.5.7 Flash Memor y Stat us Re gister (FMST A T/ FSMST A T) This register repor ts the cu rrents status of the on-chip Flash memory . The FLSR regist er is clear after de vice res et. The CPU bus master has read/wr ite access to this register . EERR The Erase Error bit indicates whether an error has occurred dur ing a pa[...]

39 www.national.com CP3BT26 8.5.10 Flash Memory T ran sition Time Reload Register (FMTRAN/FSMTRAN) The FMTRAN/FMSTRAN register is a byte-wide read/write register that controls some progr am/erase tr ansition tim es. Software must not modify this register while program/erase operation is in progr ess (FMBUSY set). At reset, this regis- ter is initia[...]

www.national.com 40 CP3BT26 8.5.16 Flash Memory Recover y Time Reload Register (FMRCV/FSMRCV) The FMRCV/FSMRCV register is a byte-wide read/wr ite register that controls the recov er y delay time between two flash memor y accesses. Software must not modify this reg- ister while a program/erase operation is in progress (FM- BUSY set). At reset, this[...]

41 www.national.com CP3BT26 9.0 DMA Controller The DMA Controller (DMAC) has a register-based program- ming interface , as op posed to an interface based on I/O control bloc ks. After loading the registers with source and destination addresses, as well as bloc k size and type of o p- eration, a DMA C ch annel is ready to respond to DMA trans- f er [...]

www.national.com 42 CP3BT26 Direct mode suppor ts two bus policies: inter mittent and con- tinuous. In intermittent mode, the DMAC giv es bus master- ship back to the CPU after ev er y cycle. In continuous mode , the DMAC remains b us master un til the transfer is complet- ed. The maximum bus throughput in inter mittent mode is one transf er f or e[...]

43 www.national.com CP3BT26 If the DMAST A T .VLD bit is clear : 1. The transfer operation terminate s. 2. The channel sets the DMAST A T .OVR bit. 3. The DMAST A T .CHAC bit is cleared. 4. An interrupt is generated if enabled by the DMA CNTLn.EOVR bit. The DMACNTLn.CHEN bit must be cleared before loading the DMACNTLn register to a v oid prematurel[...]

www.national.com 44 CP3BT26 9.6.1 Device A Address Co unter Register (ADCAn) The Device A Address Counter register is a 32-bit, read/ write register. It holds the current 24-bit ad dress of either the source data item or the destination location, depending on the state of the DIR bit i n the CNTLn register . The ADA bit of DMA CNTLn re gister contr[...]

45 www.national.com CP3BT26 9.6.6 Block Length Register (BL TRn) The Block Length register is a 16-bit, read/write register . It holds the number of DMA transfers to be performed for the next b lock. Writing this regist er automatically sets the DM- AST A T .VLD bit. Note: 0000h is inter preted as 2 16 -1 transf er cycles. 9.6.7 DMA Control Re gist[...]

www.national.com 46 CP3BT26 9.6.8 DMA Status Register (DMAST A T) The DMA status register is a byte-wide, read register that holds the status information for the DMA channel n. This register is cleared at reset. Th e reser ved bits alwa ys retur n zero when read. The VLD , O VR and TC bits are sticky (once set by the occurrence of the specific cond[...]

47 www.national.com CP3BT26 10.0 Interrupts The Interrupt Control Un it (ICU) receives interrupt re quests from inter nal and externa l sources and generates interrupts to the CPU . Interrupts from the timers, U AR Ts, Microwire/ SPI interf ace, and Mult i-Input W ake-Up modu le are all maskable interrupts. The highest-prior ity interr upt is the N[...]

www.national.com 48 CP3BT26 10.3.1 Interrupt V e ct or Register (I VCT) The IVCT register is a byte-wid e read-only register which re- por ts the encoded value of the highest pr ior ity maskable in- terrupt that is both asser ted and enabled. The valid range is from 10h to 3Fh. The register is read by the CPU dur ing an interrupt acknowledge b us c[...]

49 www.national.com CP3BT26 10.3.4 Interrupt Enab le an d Mask Register 0 (IENAM0) The IENAM0 register is a word-wide read/wr ite register which holds bits that i ndividually enable and disable the maskable interrupt sources IRQ1 through IR Q15. The reg- ister is initialized to FFFFh at reset. IENA Each Interrupt Ena ble bit enab les or disables th[...]

www.national.com 50 CP3BT26 10.4 MASKABLE INTERRUPT SOURCES T able 20 shows the interr upts assigne d to various on-chip maskable interrupts. The priority of simultaneous maskable interrupts is linear, with IRQ47 ha ving the highest pr ior ity . Table 20 Maskable Interrupts Assignment All reser ved interrupt vectors should point to default or error[...]

51 www.national.com CP3BT26 11.0 T riple Clock and Reset The T r iple Clock and Reset module generates a 12 MHz Main Clock and a 32.768 kHz Slow Clock from external crystal networ ks or ex ter nal clock sources. It pro vides vari- ous clock signals f or the rest of the chip. It also pro vides the main system reset signal, a pow er-on reset function[...]

www.national.com 52 CP3BT26 11.1 EXTERNAL CRYSTAL N ETWORK An external cr ystal ne twork is connecte d to the X1CKI and X1CK O pins to gen erate the Main Clock, unless an externa l clock signal is driven on the X1CKI pin. A similar externa l cr ystal network may be used at pins X2CKI and X2CKO f or the Slow Clock. If an e xter nal cr ystal network [...]

53 www.national.com CP3BT26 Choose capacitor component values in the tables to obtain the specified load capacitance for the cr ystal when com- bined with the parasitic capacita nce of the trace, sock et, and package (which can v ar y fro m 0 to 8 pF). As a guideline, the load capacitance is: C2 > C1 C1 can be tri mmed to obtain the desired load[...]

www.national.com 54 CP3BT26 11.5 SYSTEM CLOCK The System Clock drives most of the on-chip modules, in- cluding the CPU. T ypically , it is dr iven by the Main Clock, but it can also be dr iven by the PLL. In either case, the clock sig- nal is passed through a p rogrammab le divider (scal e fa ctors from ÷1 to ÷16). 11.6 A UXILIAR Y CLOCKS A uxi l[...]

55 www.national.com CP3BT26 FCLK bit cannot be cleared until the PLL clock has stabilized. After reset this bit is set. 0 – PLL is active . 1 – PLL is powered do wn. A CE1 Wh en the Auxiliary Clock Enable bit is set and a stable Main Cloc k is provided, the Auxiliary Clock 1 prescaler is enabled and generates the first Auxiliary Clock. When the[...]

www.national.com 56 CP3BT26 12.0 P ower Mana g ement The P ower Management Module (PMM) improves the effi- ciency of the CP3BT26 by changing the operating mode (and therefore the power consumption) according to the re- quired lev el of device activity . The device implements f our power modes:  Active  Po w e r S a v e  Idle  Halt T abl[...]

57 www.national.com CP3BT26 12.3 IDLE MODE In Idle mode, the System Clock is disabled and therefore the clock is stopped to most modules of the device . The PLL and the high-frequen cy oscillator may be disabled as con- trolled by register bits. The low-frequency oscillator remains active . The P ower Managem ent Module (PMM) and the Timing and Wat[...]

www.national.com 58 CP3BT26 HAL T Th e Halt Mode bit indicate s whether the de- vice is in Halt mode. Bef ore en tering Halt mode, the WBPSM bit mu st be set. When the HAL T bi t is wr itten wit h 1, the device enters the Halt mode at the ex ecution of the next W AIT instr uction. When in HAL T mode, the PMM stops the System Clock and then turns of[...]

59 www.national.com CP3BT26 12.6.2 P ower Manageme nt Status Register (PMMSR) The Management Status Registe r (PMMR) is a byte-wide , read/wri te register that provi des status signals for the vari- ous clocks . The re set value of PMSR register bits 0 to 2 de- pend on the status of the clock sources monitored by the PMM. The upper 5 bits are clear[...]

www.national.com 60 CP3BT26 12.7.2 Entering Idle Mode Entr y into Idle mode is pe rf or me d by writing a 1 to the PM- MCR.IDLE bit and then ex ecuting a WAIT instruction. The PMMCR.WBPSM bit must be set before the W AIT instruc- tion is ex ecuted. Idle mode can be entere d only from the Ac- tive or P ower Sav e mode. 12.7.3 Disabling the Hi gh-F r[...]

61 www.national.com CP3BT26 13.0 Multi-Input W ake-Up The Multi-Input W ake -Up (MIWU) unit consists of tw o ide n- tical 16-channel mo dules. Each module can asser t a wak e- up signal for e xiting from a low-power mode, and each can asser t an inte rrupt request on any of four Interrupt Control Unit (ICU) channels assigned to that module. The mod[...]

www.national.com 62 CP3BT26 13.1 MULTI-INPUT W AKE-UP REGISTERS T able 28 lists the MIWU registers. Table 27 MIWU Sources MIWU Channel Sour ce WUI0 TWM T0OUT WUI1 ACCESS .bus WUI2 CANRX WUI3 MWCS WUI4 U ART0 CTS WUI5 UA RT0 RXD WUI6 Blue tooth LL C WUI7 AAI SFS WUI8 USB Wa ke-Up WUI9 PJ7 WUI10 PG6 WUI11 PH0 WUI12 PH1 WUI13 PH2 WUI14 PH3 WUI15 PH4 W[...]

63 www.national.com CP3BT26 13.1.1 W ake-Up Edge Detection R egister (WK0EDG) The WK0EDG register is a word-wide read/write re gister that controls the edge sensitivi ty of the MIWU channels. The WK0EDG register is cleared upon re set, which configures all channels to b e triggered on risi ng edges. The register for- mat is show n below . WKED The [...]

www.national.com 64 CP3BT26 13.1.7 W ake-Up Interrupt Contro l Registe r 1 (WK0ICTL1) The WK0ICTL1 register is a word-wide read/wr ite re gister that selects the interr upt request signa l f or the associa ted MIWU channels WUI7:0. At reset, the WK0ICTL1 register is cleared, which selects MIWU Interrup t Request 0 for all eight channels. The regist[...]

65 www.national.com CP3BT26 13.1.11 Wake-Up P endin g Register (WK0PND) The WK0PND registe r is a word -wide read/wr ite register i n which the Multi-Input Wak e-Up module latches any detect- ed tri gger conditi ons. The CPU can only wr ite a 1 to any bit position in this register. If t he CPU attempts to write a 0, it has no effect on that bit. T [...]

www.national.com 66 CP3BT26 13.2 PROGRAMMING PROCEDURES T o set up and use the Multi-I nput W ake-Up function, use th e f oll owing procedure. P erf or ming the steps in the order shown will pre vent f alse trig gering of a wake-up condition. This same procedure should be used following a reset be- cause the wak e-up inpu ts are left floating, resu[...]

67 www.national.com CP3BT26 14.0 Input/Output P ort s Each device has up to 54 software-configurable I/O pins, or- ganized into 8-bit por ts (not all bits are used in some por ts). The por ts a re named Port B, P or t C, P ort E, P or t F , P o r t G, P or t H, and P or t J . In addition to their g eneral-pur pose I/O capability , th e I/O pins of [...]

www.national.com 68 CP3BT26 In the descri ptions of the por ts and por t re gisters, the lower- case letter “x” represents the por t desig nation, either B, C , E, F , G, H, or J . For e xample, “PxDIR register” means any one of the por t direction registers: PBDIR, PCDIR, PEDIR, PFDIR, PGDIR, PHDIR, or PJDIR. Table 29 Port Registers Name A[...]

69 www.national.com CP3BT26 All of the por t registers are byte-wide read/write registers, e xcept for th e por t data input registers , which are read-only registers. Each register bit c ontrols the function of the cor- responding por t pin. F or exam ple, PGDIR.2 (bit 2 of the PGDIR register) controls the direction of por t pin PG2. 14.1.1 P or t[...]

www.national.com 70 CP3BT26 14.1.6 P ort High Drive Stre ngth Register (PxHDR V) The PxHDR V register is a byte- wide, read/write register that controls the slew rate of the corresponding pins. The high drive strength function is enabled when the correspondin g bits of the PxHDR V register are set. In both GPIO and alter- nate function modes, the d[...]

71 www.national.com CP3BT26 14.2 OPEN-DRAIN OPERATION A por t p in can be confi gured to op erate as an invertin g open-drain output buff er . T o do this, the CPU must clear the bit in the data output regist er (PxDOUT) and then u se the por t direction register (PxDIR) to set the value of the por t pin. With the direction re gister bit set (direc[...]

www.national.com 72 CP3BT26 15.0 Bluetooth Controller The integrated hardware Bluetooth Lower Link Controller (LLC) complies to the Bluetooth Specification V e rsion 1.1 and integrates the f ollowing functions:  4.5K-byte dedicated Bluetooth data RAM  1K-byte dedicated Bluetooth Sequencer RAM  Suppor t of all Blueto oth 1.1 pack et types ?[...]

73 www.national.com CP3BT26 transmitter circuit of the radio chip is enabled, correspond- ing to the settings of the p ower control register in the radio chip . The RFSYNC signal is the alter nate fun ction of the general- pur pose I/O pin PG0. At reset, th is pin is in TRI-ST A TE mode. Softw are must ena ble the alternate functi on of the PG0 pin[...]

www.national.com 74 CP3BT26 Write Operation When the R/W bit is clear , the 16 bits of the data field are shifted out of the CP3BT26 on the falling edge of SCLK. Data is sampled by the radio chip on the risin g edge of SCLK. When SLE is high, the 16-bit da ta are copied into the radio chip register on the next rising edge of SCLK. The data is loade[...]

75 www.national.com CP3BT26 Figure 18. 32 -Bit Write Timing Figure 19. 3 2-Bit Read Timing An e xample of a 32-bit write is shown in T able 31. In this e x- ample, the 32-bit value FFFF DC04h is wr itten to register address 0Ah. In cycle 1, the high word (FFFFh) is written. In the first par t of cycle 2, the CP3BT26 drives the header , R/ W bit, an[...]

www.national.com 76 CP3BT26 15.3 LMX5251 P OWER -UP SEQUENCE T o power-up a Bluetooth syst em based on the CP3BT26 and LMX5251 devices , the following sequence must b e per- f or med: 1. Apply VDD to the LMX5251. 2. Apply IO VCC and VCC to the CP3BT26. 3. Drive the RESET# pin of the LMX5251 high a minimum of 2 ms after the LMX5251 and C P3000 suppl[...]

77 www.national.com CP3BT26 Figure 22. LMX5252 Po wer-Up Sequence 15.5 BLUETOOTH SLEEP MODE The Bluetooth controller is cap able of putting itself into a sleep mode for a specified number of Slo w Clock cycles. In this mode, the controller clo cks are stopped inter nally . The only circuitry which remain s active are two counters (counter N and cou[...]

www.national.com 78 CP3BT26 15.8 BLUETOOTH SHARED DATA RA M The shared data RAM is a 4.5K memor y-mapped se ction of RAM that contains the link control data, RF programming look-up table, and the link pa yload. This RAM can be read and written in the same way as the Static RAM space and can also be read by the sequencer in the Bluetooth L LC. Ar- b[...]

79 www.national.com CP3BT26 16.0 12-Bit Analog to Digital Con ver ter The integrated 12-bit ADC prov ides the f ollowing f eatures:  8-input analog multiplex er  8 single-ended channels or 4 differential channels  Exter nal filter ing capability  12-bit resolution with 11-bit accu racy  Sign bit  15-microsecond conversion time [...]

www.national.com 80 CP3BT26 The output of the In put Multiplex er is availab le externally as the MUXOUT0 and MUXOUT1 signals. In single-ended mode, only MUXOUT0 is used. In differential mode, MUXOUT0 is the positive si de and MUXOUT1 is the nega- tive side. The MUXOUT0 and MUXOUT1 outputs and the ADCIN e xter nal anal og input ar e provided so tha[...]

81 www.national.com CP3BT26 16.2 T OUCHSCREEN INTERFACE The ADC provides an interface f or 4-wire resisti ve touch- screens with the resolu tion necessar y for applications such as signature analysis. A typical touchscreen co nfiguration is shown in Figure 25. Figure 25 . T ouchsc reen Interface A touchscreen consists of two resistive plates nor ma[...]

www.national.com 82 CP3BT26 16.2.2 Measuring P en Force Figure 27 shows equivalent circuits f or th e driver modes used to measure the X, Y , an d Z coordinates, in which Z rep- resents pen force . In this di scussion, the ohmic resistance of the drivers is neglected (see Section 16.2.3), and series resistance between the node of interest and the A[...]

83 www.national.com CP3BT26 3. By extension, the ADC negative v olta ge reference can be inter nally connecte d to the TSY - ter minal, to re cov er the full 4096 values. The Global Configuration Regi ster (ADCGCR ) provides the flexibility to implement any of these techniques. 16.3 ADC OPERATION IN PO WER-SAVING MODES T o reduce the lev el of swit[...]

www.national.com 84 CP3BT26 16.5.1 ADC Global Configur ation Register (ADCGCR) The ADCGCR register controls the basic op eration of the in- terface . The CPU bus master has read/wr ite access to the ADCGCR register . After reset th is register is set to 0000h. CLKEN The Clock Enab le bit contro ls whether the ADC module is running . When this bit i[...]

85 www.national.com CP3BT26 PREF_CFG The Positiv e V oltage Reference Configuration field specifies the source of the ADC positive voltage ref erence, according to the following table: NREF_CFG The Negative V oltage Reference Configura- tion field specifies the source of the ADC neg- ative v oltage reference, according to the f ol lowing table: MUX[...]

www.national.com 86 CP3BT26 16.5.3 ADC Con version Contr ol Register (ADCCNTRL) The ADCCNTRL register specifies the tr igger conditio ns fo r an ADC conv ersion. POL The ASYNC P olarity bi t specifie s the polarity of edges which tr igger ADC conversions . 0 – ASYNC input is sensitive to rising edges. 1 – ASYNC input is sensitive to f allin g e[...]

87 www.national.com CP3BT26 16.5.6 ADC Result Register (ADCRESL T) The ADCRESL T register includes the software-visible end of a 4-word FIFO . Conversion results are loaded into the FIFO from the 12-bit ADC and unloaded when software reads the ADCRESL T register . The ADCRESL T register is read-only . With the exceptio n of the PEN_DOW N bit, the f[...]

www.national.com 88 CP3BT26 17.0 Random Number Generator (RNG) The RNG unit i s a hardware “tr ue random” number g enera- tor . When enabled, this unit provides up to 800 random bits per second. The bits are availab le for reading from a 16-bit register . The RNG unit includes two oscillators which operate inde- pendently of the System Clock: ?[...]

89 www.national.com CP3BT26 17.2 RANDOM NUMBER GENERATOR REGISTER SET T able 34 lists the RNG registers . 17.2.1 RNG Contr ol and Status Register (RNGCST) The RNGCST register provides co ntrol and status bi ts for the RNG module. This register is cleared at reset. RNGE The Rand om Number Generator Enable bit enables the operation of the RNG. When t[...]

www.national.com 90 CP3BT26 18.0 USB Controller The CR16 USB node is an integr ated USB node co ntroller that f eatures enhanced DM A suppor t with many automatic data handling features . It is co mpatible with USB specifica- tion versions 1.0 and 1.1. It integrates the required USB transceiver , a Serial Interface Engine (SIE), and USB endpoi nt ([...]

91 www.national.com CP3BT26 18.2 ENDPOINT OP ERATION 18.2.1 Add re ss Detection P ackets are broadcast from the host controller to all nodes on the USB network. Address detection is implemented in hardware to allow selective reception of pack ets and to per- mit optimal use of CPU bandwid th. One function address with sev en different endpoint comb[...]

www.national.com 92 CP3BT26 Bidirectional Control Endpoint FIFO0 Op eration FIFO0 should be used for the b idirectional control endpoint 0. It can be config ured to receive data sent to the de fault ad- dress with the DEF bit in t he EPC0 regi ster . Isochronous transf e rs are not suppor t ed f or the control endpoi nt. The Endpoint 0 FIFO can hol[...]

93 www.national.com CP3BT26 Receive Endpoint FIFO Operation (RXFI FO1, RXFIFO2, RXFIFO3) The Receive FIFOs for endpoints 2, 4, and 6 suppor t b ulk, interrupt, and isochronous USB packet transf ers larger than the actual FIFO size. If the pack et le ngth exceeds the FIFO size, softw are must read t he FIFO contents while the USB pack et is being re[...]

www.national.com 94 CP3BT26 18.3.1 Main Control Regi ster (MCNTRL) The MCNTRL register controls the main functions of the CR16 USB node. The MCNTRL re gister provides read/write access from the CPU bus . Reser ved bits must be written with 0, and they return 0 when read. It is clear after reset. USBEN The USB Enable controls whether the USB module [...]

95 www.national.com CP3BT26 NA T The Node Attached indicates th at this node is ready to be detected as attached to USB. When clear , the transcei ver f orces SE0 on th e USB node controller to prev ent the hub (to which this node is connec ted) from detecting an attach ev ent. After reset or when the USB node is disabled, this bit is cleared to gi[...]

www.national.com 96 CP3BT26 18.3.3 Main Event Register (MAEV) The Main Event Register summarizes and repor ts the main e vents of the USB transactions . This register provides read- only access. The MAEV regist er is clear after reset. W ARN The W a rni ng Event bit indicates whether one of the unmasked bits in the FIFO W ar ning Event (FWEV) regis[...]

97 www.national.com CP3BT26 SD3 The Suspend Detect 3 ms bit is set after 3 ms of IDLE hav e been d etected on the upstream por t, indicating that the device should be sus- pended. The suspend o ccurs under software control by writing the suspen d value to the Node Functional State (NFSR ) register . This bit is cleared when the register is read. 0 [...]

www.national.com 98 CP3BT26 18.3.9 Receive Event Register (RXEV) The RXEV register repor ts the current status of the FIFO , used by the three Receive Endpoints. The RXEV register is clear after reset. It provides read-only access from the CPU bus . RXFIFO The Receive FIFO n are set whene ver either RX_ERR or RX_LAST in the respective Re- ceive Sta[...]

99 www.national.com CP3BT26 18.3.13 FIFO Warning Event Register (FWEV) The FWEV register signals wh ether a receive or transmit FIFO has reached its war ning lim it. It repor ts the status f or all FIFOs, e xcept for the Endpoint 0 FIFO , as no warning limit can be specified for thi s FIFO . The FWEV register pro- vides read-only access from the CP[...]

www.national.com 100 CP3BT26 MF The Missed SOF bit is set when the frame number in a v alid received SOF does not match the e xpected next v alue, or w hen an SOF is not received within 12060 bit times. The MF bit provides read-only access. On re- set, this bit is set. This bit is set by the hard- ware and is cleared by reading the FNH register . 0[...]

101 www.national.com CP3BT26 DTGL The DMA T oggle bit is used to deter mine the initia l state of Automatic DMA (ADMA) opera- tions. Software initially sets this bit if starting with a DA T A1 operation, and cle ars this bit if star ting with a DA T A0 operation. Writes to this bit also update the NTGL bit in the DMAEV register . IGNRXTGL The Ignor[...]

www.national.com 102 CP3BT26 18.3.20 D MA Mask Register (DMAMSK) Any set bit in the DMAMSK register enables automatic set- ting of the DMA bi t in the AL TEV register whe n the respec- tive e v ent in the DM AEV register occurs. Otherwise , setting the DMA bit is disabled. For a description of bits 0 to 3 , see the DMAEV register . The DMAM SK regi[...]

103 www.national.com CP3BT26 receive the ne xt packet. The erroneous pack et is igno red and not transferred via DMA. If this bit is cleared, automatic error handling ceases. 18.3.24 Endpoint Contro l 0 Register (EPC0) The EPC0 register controls th e mandator y En dpoint 0. It is clear after reset. Reser ved bits read undefined data. EP Th e Endpoi[...]

www.national.com 104 CP3BT26 FLUSH W r iting a 1 to the Flush FIFO bit flushes all data from the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read and write pointe r , and then clears itself. If the endpoint is currently using the FIFO0 to transf e r data on USB, flushing is delayed until after the transf er is complet[...]

105 www.national.com CP3BT26 FLUSH Writing 1 to the Flush bit fl ushes all data from the control endpoint FIFOs, resets the end- point to Idle state, clears the FIFO read and write pointer, a nd then clears itself. If the end- point is currently u sing FIFO0 to transfer data on USB, flushing is dela yed until after the transf e r is done. This bit [...]

www.national.com 106 CP3BT26 A CK_ST A T The Ackno wledge Status bit is valid when the TX_DONE bit is set. Th e meaning of th e A CK_ST A T bit di ffers depending on whether ISO or non-ISO operation is used (as selected by t he ISO bit in the EPCn register).  Non-Isochronous mode — This bit indi- cates the ackno wledge status (from th e host) [...]

107 www.national.com CP3BT26 TFWL The T ransmit FIFO W arni ng Limit bits specify how many more b ytes can be transmitte d from the respective FIFO bef ore an underr un con- dition occurs. If the n umber of bytes remaining in the FIFO is equal to or less than the select- ed warning limit, the TXW ARN bit in the FWEV register is set. T o av oid inte[...]

www.national.com 108 CP3BT26 18.3.36 R eceive Command Register n (R XCn) Each of the receive endpoints (2, 4, and 6) has one RXCn register . The registers provid e read /write access from the CPU bus . Reading reser ved bits returns undefined data. Af- ter reset, it is clear . RX_EN The Receive Enab le bit enables receiving pack ets. OUT packet rec[...]

109 www.national.com CP3BT26 19.0 CAN Module The CAN module con tains a Full C AN class, CAN (Control- ler Area Network) ser ial bus interf ace for low/high speed ap- plications. It suppor ts re ception and transmissi on of ex tended frames with a 29-bit identifier, standard frames with an 11-bit identifier, applications that require high speed (up[...]

www.national.com 110 CP3BT26 Figure 34. CAN Block Diagram 19.2 BASIC CAN CONCEPTS This section provides a gener ic ov er view of the basic co n- cepts of the Controller Area Network (CAN). The CAN protocol is a me ssa ge-based protocol that allows a total of 2032 (2 11 - 16) diff eren t messages in the standard f or mat and 5 12 million (2 29 - 16)[...]

111 www.national.com CP3BT26 The CAN protocol allows sev eral transmitting modules to star t a transmission at the same time as soo n as they detect the bus is idle. During the star t of transmission, ev er y nod e monitors the bus line to detect whether its message is ov er- written by a message with a higher pri ority . As soon as a transmitting [...]

www.national.com 112 CP3BT26 Data Length Code (DLC) The DLC fi eld indicates the n umber of b ytes in the data f ield. It consists of f our bits. The dat a field can be of length zero . The admissible number of data bytes f or a data frame rang- es from 0 to 8. Data Field The Data field consists of the data to be transferred within a data frame. It[...]

113 www.national.com CP3BT26 A CAN data frame consists of the following fields:  Star t of F rame (SOF)  Arbitration Field + Extended Arbitration  Control Field  Data Field  Cyclic Redundancy Check Field (CRC)  Ackno wledgmen t Field (ACK)  End of F rame (EOF) Remote Frame Figure 38 shows the structure of a standard remote fram[...]

www.national.com 114 CP3BT26 Error Frame As shown in Figure 40, the Error F rame consists of the error flag and the error delimiter bit field s. The error flag field is built up from the various error flags of the different nodes. Therefore , its l ength may v ar y from a mini mum of six bits up to a maximum of twelv e bi ts depending on when a mod[...]

115 www.national.com CP3BT26 Figure 42. Interfr ame Space 19.2.4 Err or T ypes Bit Error A CAN de vice which is currently transmitting also monitors the bus. If the monitored bit v alu e is di fferent from the trans- mitted bit value, a bit error is detected. Howev er , the recep- tion of a “dominant” bit instead of a “recessive” bit during[...]

www.national.com 116 CP3BT26 Error Active An error active unit can par ticipate in bus communication and may send an activ e (“do minant”) error flag. Error W arning The Error W ar ning state is a sub-state of Error Active to in- dicate a heavily disturbed bus . The CAN module behaves as in Error Active mode. The de vice is reset into th e Erro[...]

117 www.national.com CP3BT26 19.2.6 Bit Time Logic In the Bit Time Logic (BTL), the CAN bus speed and the Synchronization Jump Width can be configured by software . The CAN module divides a nominal bit time into three time segments: synchronization segment, time segment 1 (TSEG1), and time segment 2 (TSEG2). Figure 44 shows the various elements of [...]

www.national.com 118 CP3BT26 Figure 45. Resynchron ization (e > SJW) Figure 46. Resynchronization (e < -SJW) 19.2.7 Cloc k Generator The CAN prescaler (PSC) is shown is Figure 47. It divides the CKI input clock by the v alue defined in the CTIM register . The resulting clock is called time qua nta clock and defines the length of one time quan[...]

119 www.national.com CP3BT26 independent filter ing procedure, which provides the possi- bility to establis h a BASIC-CAN path. F or reception of data frame or remote frames, the CAN module follo ws a “receive on first match” r ule which means that a given message is only received b y one buffer: the first one which matches the received message[...]

www.national.com 120 CP3BT26 buff er status field. With this lock function, software has the capability to sav e sev eral me ssages with the same identifier or same identifier group into more than one buffer . For e x- ample, a b uffer with the second highest pr iori ty will receive a message if the buff er with the highest pr ior ity has already r[...]

121 www.national.com CP3BT26 All contents of the hidden receive b uffer are alwa ys copied into the respective receiv e buff er . This incl udes the received message ID as well as the received Data Length Cod e (DLC); therefore when some mask bits are set to don’t care, the ID field will get the received message ID which could be diff erent from [...]

www.national.com 122 CP3BT26 Figure 54. Buffer R ead Routine (BUFFLOCK Disabled) The first step is only appl icable if polling is used to ge t the status of the receive bu ffer . It can be deleted for an interrupt driven receive routine. 1. Read the status (CNST A T) of the receive buff er . If the status is RX_READ Y , no was the message receiv ed[...]

123 www.national.com CP3BT26 CNST A T status section will be 0101b, as the b uffer w as RX_FULL (0100b) before . After finally reading th e last re- ceived message , the CPU can reset the buffer to RX_READ Y . 19.6 T RANSMIT STRUCTURE T o transmit a CAN messa ge, software must configure the message buff er by changing the buffer status to TX_NO T_A[...]

www.national.com 124 CP3BT26 ity is combined by the 4-bit TXPRI v alue and the 4-b it buff er number (0...14) as shown bel o w . The lowest resulting num- ber results in the highest transmit priority . T able 47 shows the transmit priority configuration if the pri- ority is TXPRI = 0 for all transmit buff ers: T able 48 shows the tr a nsmit prior i[...]

125 www.national.com CP3BT26 19.6.4 TX Buffer States The transmission process can be star ted after software has loaded the buff er registers (da ta, ID , DLC , PRI) and se t the buff er status from TX_NO T_ACTIVE to TX_ONCE, TX_RTR, or TX_ONCE_RTR. When the CPU wr ites TX_ONCE, the buffer will be TX_BUSY as soon as the CAN module has scheduled thi[...]

www.national.com 126 CP3BT26 19.7.1 Highest Priori ty Interrupt Code T o reduce the decoding time for the CIPND register , the buff er interrupt request with the highest pr iori ty is placed as interrupt status code into the IST[3:0] section of the CSTP- ND register . Each of the b uffer interrupts as well as the error interrupt can be individually[...]

127 www.national.com CP3BT26 19.9 MEMOR Y ORGANIZATION The CAN module occupies 144 words in the memo r y ad- dress space. This space is organized as 15 banks of 8 words per bank (plus one reser ved bank) for the message buff ers and 14 words (plus 2 reserved words ) f or control and status . 19.9.1 CPU Access to CAN Registers/Memory All memor y loc[...]

www.national.com 128 CP3BT26 19.10 CAN CONTROLLER REGISTER S T able 51 lists the CAN module registers. 19.10.1 Buffer Status/Control Register (CN ST A T) The buff er status (ST), the buff er prior ity (PRI), and the data length code (DLC) are controlled by manipulating the con- tents of the Bu ffer Stat us/Control Regist er (CNST A T). The CPU and [...]

129 www.national.com CP3BT26 Table 52 Buffer Status Sectio n of the CNSTAT Register ST3 (DIR) ST2 ST1 ST0 (BUSY) Buffer Status 00 0 0 R X _ N O T _ A C T I V E 00 0 1 Reser ved f or RX_BUSY . (This co ndition indicates that soft- ware wrote RX_NO T_A CTIVE to a buff er when the data copy process is still activ e.) 00 1 0 R X _ R E A D Y 00 1 1 RX_B[...]

www.national.com 130 CP3BT26 PRI The T ransmit Pr iority Code fiel d holds the software-defined transmit prio rity code for the message buff er . DLC The Data Length Code field deter mines the number of data bytes within a received/trans- mitted frame. F or transmission, these bits need to be set according to the number of data bytes to be transmit[...]

131 www.national.com CP3BT26 19.10.3 Storage of Messages with Less Than 8 Data Bytes The data bytes that are not used for data transf er are “do n’t cares”. If the object is tran smitte d, the data within these bytes will be ignored. If the obj ect is received, the data with- in these bytes will be o verwritten with invalid data. 19.10.4 Stor[...]

www.national.com 132 CP3BT26 19.10.5 Storage of Remote Messages During remote frame transf er, the b uffer registers D A T A0– D A T A3 are “don’t cares”. If a remote frame is transmitted, the contents of these registers are ignored. If a remote frame is receiv ed, the conten ts of these registers will be ov erwr itten with inva lid data. T[...]

133 www.national.com CP3BT26 19.10.6 CAN Global Config uration Register (CGCR) The CAN Global Co nfiguration Register (CGCR) is a 16-bit wide register used to:  Enable/disab le the CAN mo dule.  Configure the BUFFLOCK func ti on f o r the message buff- er 0..14.  Enable/disab le the time stamp synchronization .  Set the logic lev els of[...]

www.national.com 134 CP3BT26 Figure 61. Data Directio n Bit Clear Setting the DDIR bit will caus e th e direction of th e data stor- age to be rev ersed — the la st by te received is stored at the highest address and the first byte is stored at the lowest ad- dress, as shown in Figure 62. Figure 62. Data Direction Bit Set LO Th e Listen Only bit [...]

135 www.national.com CP3BT26 INTERNAL If the Inter nal function is en abled, the CANTX and CANRX pins of the CAN module are inter- nally connected to each other. This feature can be used in conj unction with the LOOP- BA CK mode. This means that the CAN mo d- ule can receive its o wn sent messages without connecting an external transceiver chip to [...]

www.national.com 136 CP3BT26 TSEG1 Th e Time Segment 1 field configu res the length of the Time Se gment 1 (TSEG1). It is not recommended to configure the ti me seg- ment 1 to be smaller than 2 ti me quanta. (see Ta b l e 5 9 ) . TSEG2 Th e Time Segment 2 field specifies the num- ber of time quanta (tq) f or phase seg ment 2 (see T able 60). 19.10.[...]

137 www.national.com CP3BT26 19.10.9 Basic Mask Regi ster (BMSKB/BMSKX) The BMSKB and BMSKX register s allow masking the b uffer 14, or “don’t care” the incomin g extended/standard identifier bits, R TR/XRTR, and IDE. Throughout this document, the two 16-bit registers BMSKB and BMSKX are referenced to as a 32-bit register BMSK. The follo wing[...]

www.national.com 138 CP3BT26 19.10.12 CAN Interrupt Clear Register (CICLR) The CICLR register bits individually clear CAN inte rrupt pending flags caused by the message buff ers and from the Error Management Logic. Do not m odify this register with in- structions that access the regi ster as a read-modify-wr ite operand, such as the bit manipulatio[...]

139 www.national.com CP3BT26 19.10.15 CAN Error Counter Register (CAN EC) The CANEC register repor ts t he values of the CAN Receive Error Counter and the CAN T ransmit Error Counter . REC The CAN Receive Error Counter field repor ts the value of the receiv e error counter. TEC The CAN T ransmit Error Counter field repor ts the value of the tr ansm[...]

www.national.com 140 CP3BT26 DRIVE Th e Drive bit shows the output v alue on th e CANTX pin at the time of the error . Note that a receiver will not drive the bus e xcept dur ing A CK and dur ing an active error flag. 19.10.17 CAN Timer Register (CTMR) The CTMR regist er repor ts the current val ue of the Time Stamp Counter as described in Section [...]

141 www.national.com CP3BT26 The cr itical path derives from receiving a remote frame, which triggers the transmission o f one or more data frames. There are a minimum of f ou r bit times in-between two con- secutive frames . These bit ti mes star t at the validation point of received fr ame (recepti on of 6th EOF bit) and end at th e earliest poss[...]

www.national.com 142 CP3BT26 19.12 USAGE HINT Under cer tain conditio ns, the CAN module receives a frame sent by itself , ev en th ough the loopback f ea ture is disabled. T wo conditions must be true to cause this ma lfunction:  A transmit buff er and at least one receive buff er are con- figured with the same ide ntifier . Assume this identi [...]

143 www.national.com CP3BT26 20.0 Adv anced A udio In terface The Advanced A udio Interface (AAI) provides a serial syn- chronous, full duplex interf ace to codecs and similar seria l devices . The transmit and re ceive paths ma y operate asyn- chronously with respect to each other . Each path uses a 3- wire interface consisting of a bit cloc k, a [...]

www.national.com 144 CP3BT26 20.2.2 Syn chronous Mo de In synchronous mode, the receive and transmit paths of th e audio interface use the same shift clock and frame sync sig- nal. The bit shift clock and frame sync signal f or both paths are der ived from the same set of clock prescalers. 20.2.3 Normal Mode In nor mal mode, each rising edge on the[...]

145 www.national.com CP3BT26 On the receiver side, only the valid data bits which were re- ceived during the slots assigned to this inte rf ace are copied into the receive FIFO or DMA registers. The assignment of slots to the receiver is specified b y the Receive Slot Assign- ment bits (RXSA) in the A TCR register . It can also be spec- ified whet [...]

www.national.com 146 CP3BT26 Figure 69. Accessing Three Devices in Network Mode 20.3 BIT CLOCK GENERATION An 8-bit prescaler is provided to divide the audio interface input clock do wn to the required bit clock rate . Software can choose between two input clock sources, a pri mar y and a secondar y clock source . On the CP3BT26, the two optional in[...]

147 www.national.com CP3BT26 Figure 70 shows the interru p t structure of the AAI. Figure 70. AAI In terrupt Structure 20.5.3 Normal Mode In nor mal mode, each frame sync signal marks the beg in- ning of a new fr ame an d also the beginning of a new slot, since each frame only consists of one slo t. All 16 receive and transmit FIFO locations hold d[...]

www.national.com 148 CP3BT26 20.5.6 Netw ork Mode In network mode, each frame sync signal ma rks the beg in- ning of new fr ame. Each frame can consist of up to four slots. The audio interface operates in a similar wa y to nor- mal mode, howe ver , in network mode the transmitter and re- ceiver can be assigned to specific slots within each frame as[...]

149 www.national.com CP3BT26 If the corresponding F rame Sync Select (FSS) b it in the Au- dio Control and Status register is set, the receive and/or transmit path generates or recognizes long frame sync puls- es. F or 8-bi t data, the frame sync pulse generated will b e 6 bit shift clock periods long, and f or 16-bit data the frame sync pulse can [...]

www.national.com 150 CP3BT26 20.6.4 IOM-2 Mode The AAI can operate in a special IOM-2 compatible mode to allow to connect to an external ISDN controller d e vice. In this IOM-2 mode, the AAI can only operate a s a slav e, i.e. the bit clock and frame sync signal is provided by the ISDN controller . The AAI only suppor ts the B1 and B2 data o f the [...]

151 www.national.com CP3BT26 20.6.6 Freeze Mode The audio interface provides a FREEZE input, which allows to freeze the status of the audio i nterface while a de velop- ment system e xamines the cont ents of the FIFOs and reg- isters. When the FREEZE input is asser ted, the audio interf ace be- hav es as follows:  The receive FIFO or receive DMA[...]

www.national.com 152 CP3BT26 20.7.1 A udio Receive FI FO Register (ARFR) The Audio Receive FIFO regi ster shows the receiv e FIFO location currently addressed by the Receive FIFO Read P ointer (RRP). The receive FIFO receives 8-bit or 16-bit data from the A udio Recei ve Shift Register (ARSR), when the ARSR is full. In 8-bit mode, only the lower by[...]

153 www.national.com CP3BT26 20.7.5 A udio Global Config uration Register (A GCR) The AGCR register controls the basic operation of the inter- f ace. The CPU bus master has read/write access to the A GCR register. After reset, this regi ster is clear . ASS The Asynchrono us/Synchronous Mode Se- lect bit controls whether the audio interface operates[...]

www.national.com 154 CP3BT26 IOM2 The IOM-2 Mode bit selects the nor mal PCM interf a ce mode or a special IOM-2 mode used to connect to external ISDN controller devic- es. The AAI can only operate as a slave in the IOM-2 mode, i.e . th e bit clock and frame sync signals are provided by the ISDN controller . If the IOM2 bit is cle ar , the AAI oper[...]

155 www.national.com CP3BT26 20.7.7 A udio Receive Status and Control Register (ARSCR) The ARSCR register is used to control the operation of th e receiver path of the audio interface . It also holds bits which repor t the current status of the receive FIFO . The CPU bus master has read/wr ite access to the ASCR regi ster . At re- set, this registe[...]

www.national.com 156 CP3BT26 20.7.8 A udio T ransmit Stat us and Control Register (A TSCR) The ASCR register con trols the basic op eration of the inter- f ace. It also holds bits which repor t the current status of the audio communication. The CPU bus master has read/write access to the ASCR register. At reset, this register is loaded with F003h. [...]

157 www.national.com CP3BT26 20.7.9 A udio Clock Contr ol Register (ACCR) The ACCR register is used to c ontrol the b it timing of the au- dio interface. After reset, this register i s clear . CSS The Clock Source Select bit selects one out of two possible cloc k source s fo r the a udio inter- f ace. After reset, the CSS bit is clear . 0 – The A[...]

www.national.com 158 CP3BT26 21.0 CVSD/PCM Con version Module The CVSD/PCM module performs conversion between CVSD data and PCM data, in which the CVSD encoding is as defined in th e Bluetooth specification and the PCM en- coding may be 8-bit µ-La w , 8-bit A-Law , or 13-bit to 16-bit Linear . The CVSD conv e rsion modul e operates at a fi xed r a[...]

159 www.national.com CP3BT26 If the module is only used for PCM con versions, the CVSD clock can be disabled b y clear ing the CVSD Clock Enable bit (CLKEN) in the control register . 21.3 CVSD CON VERSION The CVSD/PCM conv er ter module transf or ms either 8-bit logarithmic or 13- to 16-bit li near PCM samples at a fixed rate of 8 ksps. The CVSD to[...]

www.national.com 160 CP3BT26 The CVSD/PCM module only su ppor ts indirect DMA trans- f ers. Therefore, transf erring PCM data between the CVSD/ PCM module and another on-chip modul e requires two bus cycles. The trigger for DMA ma y also tr igger an interr upt if the cor- responding enable bits in the CVCTRL register is set. Therefore care m ust be[...]

161 www.national.com CP3BT26 21.9.5 Logarithmic PCM Data Input Register (LOGIN) The LOGIN register is a n 8-bit wide wr ite-only registe r . It is used to receive 8-bit logarithmic PCM data from the perip h- eral bu s and conv er t it into 13-bit linea r PCM data. 21.9.6 Logarithmic PCM Data Output Register (LOGOUT) The LOGOUT register is an 8-bi t[...]

www.national.com 162 CP3BT26 DMAPI The DMA Enable f o r PCM In bit enables hard- ware DMA control fo r wr iting PCM d ata into the PCMIN register . If cleared, DMA suppor t is disabled. After reset, this bit is clear. 0 – PCM input DMA disabled. 1 – PCM input DMA enabled. CVSDCONV The CVSD to PCM Conversion F or mat field specifies the PCM form[...]

163 www.national.com CP3BT26 22.0 U AR T Modules The CP3BT26 provides four U AR T modules. Each UAR T module is a full-duplex Univ ersal Asynchronous Re ceiver/ T ransmitter that suppor ts a wide range of software-pro- grammab le baud rates and d ata formats. It handles auto- matic parity generation and sev eral error detection schemes. All U ART m[...]

www.national.com 164 CP3BT26 Data bits are sensed by taking a majority vote of three sam- ples latched near the midp oint of each baud (bit time). Nor- mally , the position of the samples with in the baud is deter mined automatically , but software can ov erride the au- tomatic selection by setting the USMD bit in the UnMDSL2 register and programmi[...]

165 www.national.com CP3BT26 22.2.2 Syn chronous Mo de The synchronous mode of the UAR T enables the de vice to communicate with other devices using three communication signals: transmit, receiv e, and clock. In this mode, data bits are transf erred synchronously w ith the UAR T clock signal. Data bits are transmitted on the risi ng edges and recei[...]

www.national.com 166 CP3BT26 parity bi t is generated and transmitted follo wing the eight data bits. Figure 80. 8-Bit Da ta Frame Options The format shown in Figure 81 consists of one star t bit, nine data bits, and one or two stop bits. This f or mat also su ppor ts the U ART attention feature. When operating in this f or mat, all eight bits of U[...]

167 www.national.com CP3BT26 Figure 82 shows a diagram of the interr upt sources and as- sociated enable bits. Figure 82. U ART I nterrupts The interr upts can be individ ually enabled or disabled using the Enable T ransmit Interrup t (UETI), Enable Receive Inter- rupt (UERI), and En able Receiv e Erro r Interrupt (UEER) bits in the UnICTRL registe[...]

www.national.com 168 CP3BT26 22.3 U ART REGISTER S Software inter acts with the UA RT modules b y accessing the U ART registers , as listed in T ab l e 70. Table 70 UART Registers Name Address D escription U0RBUF FF F202h UAR T0 Receive Data Buff er U0TBUF FF F200h U ART0 T ransmit Data Buff er U0PSR FF F20Eh U AR T0 Baud Rate Prescaler U0BA UD FF [...]

169 www.national.com CP3BT26 22.3.1 U ART Receive Data Buffer (UnRBUF) The UnRBUF register is a by te-wide, read/write register used to receive each data b yte. 22.3.2 U ART T ransmit Data Buffer (UnTBUF) The UnTBUF register is a by te-wide, read/write register used to transmit each data byte . 22.3.3 U ART Baud Rate Prescaler (UnPSR) The UnPSR reg[...]

www.national.com 170 CP3BT26 UPEN The Parity Enable bit enables or disables par- ity generation and par ity checking. When the U ART is configured to transmit nine da ta bits per frame, there is no parity bit and the Un- PEN bit is ignored. 0 – P ar ity generation and checking disabled. 1 – P ar ity generation and checking enabled. 22.3.6 U ART[...]

171 www.national.com CP3BT26 UBKD The Bre ak Detect bit indicates when a line break condition occurs. This condition is de- tected if RXD remains low f or a t least ten bit times after a missing stop bit has been de tect- ed at the end of a frame. The hardware auto- matically clears the UBKD bit on reading the UnST A T register , but only if the br[...]

www.national.com 172 CP3BT26 22.3.10 UAR T Mode Select Register 2 (UnMDSL2) The UnMDSL2 register is a byte-wide, read/write register that controls the sample mode used to recover asynchro- nous data. At reset, the Un O VR register is cleare d. The reg- ister f or mat is shown below . USMD Th e USMD bit controls the sample mode for asynchronous tran[...]

173 www.national.com CP3BT26 22.4.2 Syn chronous Mo de Synchronous mode is only availab le for the U AR T0 mod ule. When synchronous mode is selected and the UCKS bit is set, the UAR T operates from a clock received on the CKX pin. When the UCKS bit is clear , th e U ART uses the clock from the inter nal baud rate generator which is a lso driven on[...]

www.national.com 174 CP3BT26 Table 72 Baud Rate Pr ogramming Baud Rate SYS_CLK = 8 MHz SYS_CLK = 6 MHz SYS_CLK = 5 MHz SYS_CLK = 4 MHz O N P %err O N P % err O N P %err O N P %err 300 7 401 9.5 0.00 16 1250 1.0 0.00 11 202 7.5 0.01 12 202 5.5 0.01 600 12 1111 1.0 0.01 16 625 1.0 0.00 11 101 7.5 0.01 1 2 101 5.5 0.01 1200 12 101 5.5 0 .01 16 125 2.5[...]

175 www.national.com CP3BT26 23.0 Micro wire/SPI Interface Microwire/Plus is a synchronous seria l communications protocol, or iginally implemente d in National Semiconduc- tor's COP8 ® and HPC families of microcontrollers to mini- mize the number of connections, and theref ore the cost, of communicating with per ipherals. The CP3BT26 has a n[...]

www.national.com 176 CP3BT26 Figure 84. Microwire Bloc k Diagram 23.1.2 Reading The enhanced Microwire interface implements a double buff er on read. As illustrated in Figure 84, the double read buff er consists of the 16-bit shifter and a buff er , called the read buffer . The 16-bit shifter load s the read buff er with new data when the data tran[...]

177 www.national.com CP3BT26 23.2 MASTER MODE In Master mode, the MSK pin is an output for the shift clock, MSK. When data is wr itten to the MWD A T register , eight or sixteen MSK clocks, depending on the mode selected, are generated to shift the 8 or 16 bits of data, an d then MSK goes idle again. The MSK idle state can b e either high or low , [...]

www.national.com 178 CP3BT26 23.3 SLAVE MODE In Slav e mode, the MSK pin is an input for the shift clock MSK. MDIDO is placed in TRI-ST A TE mode when MWCS is inactive. Data tr ansfer is enabled when MWCS is activ e. The slav e star ts driving MDIDO when MWCS is active . The most significant bit (lower byte in 8-bit mode or upper b yte in 16-bit mo[...]

179 www.national.com CP3BT26 23.5 MICRO WIRE INTERFACE REGISTERS Software inter acts with the Microwire interf ace by accessing the Microwire registers. Ther e are three such registers: 23.5.1 Micr owire Data Register (MWD A T) The MWD A T register is a word-wide, read/wri te register used to transmit and receive data through the MDODI an d MDIDO p[...]

www.national.com 180 CP3BT26 MWD A T re gister is transmitted on MDIDO , whether or not the data is valid. 0 – Echo back disabled. 1 – Echo back enabled. EIO The Enable Interrupt on Overrun bit enables or disables the ov err un error interr upt. When set, an interrupt is generated when the Re- ceive Overrun Error bit (MWST A T .O VR) is set. Ot[...]

181 www.national.com CP3BT26 24.0 A CCESS.bus Interface The ACCESS .bus interf ace module (ACB) is a tw o- wire se- rial interface compatible with the A CCESS.b us physical la y- er . It permits easy i nterfacing to a wide range of lo w-cost memories and I/O devices , including: EEPROMs, SRAMs , timers, A/D con verters, D/A conv er ters, clock chip[...]

www.national.com 182 CP3BT26 Ac knowledge Cyc le The Acknowledge Cycle consists of two signals: the ac- knowledge clock pulse the master sends with each byte transf e rred, and the acknowledge signal sent by the receiv- ing de vice (Figure 93 ). Figure 93. A CCESS.bus Data T ransaction The master generates the ackno wledge clock pulse on the ninth [...]

183 www.national.com CP3BT26 24.2 A CB FUNCTIONAL DE SCRIPTION The ACB module provides the ph ysical lay er for an AC- CESS.b us comp liant seria l interface . The module is config- urable as either a master or sla ve de vice. As a slav e, the A CB module may issue a request to become the b us mas- ter . 24.2.1 Master Mode An ACCESS .bus transactio[...]

www.national.com 184 CP3BT26 Master Bus Stall The ACB module can stall the ACCESS.b us between trans- f ers while waiting for the core’ s response. The A CCESS.b us is stalled by holding the SCL sign al low after the acknowl- edge cycle. Note that this is inter preted as the beginni ng of the following b us operation. Software must make sure that[...]

185 www.national.com CP3BT26 P ower Down When this device is in P ower Sav e, Idle, or Halt mode, the A CB module is not act ive b ut re tains its status. If the A CB is enabled (A CBCTL2.EN ABLE = 1) on detection of a Star t Condition, a wake-up signal is issued to the MIWU module. Use this signal to s witch this device to Ac tive mode. The ACB mo[...]

www.national.com 186 CP3BT26 NEGACK The Negative Ackno wledg e bit is set by hard- ware when a transmission is not a ckno wl- edged on the ninth clock. (In this case, the SD AST bit is not set.) Wri ting 1 to NEGACK clears it. It is also cleared whe n the module is disabled. Writing 0 to the NEGACK bit is ig- nored. 0 – No transmission not ackno [...]

187 www.national.com CP3BT26 GCMTCH The Globa l Call Match bit is set in slave mode when the ACBCTL1.GCMEN bit is set and the address byte (the first b yte transferred after a Star t Condi tion) is 00h. It is cl eared by a Star t Condition or repeated Star t and Stop Condi- tion (including ille gal Star t or Stop Condition). 0 – No global call ma[...]

www.national.com 188 CP3BT26 INTEN The Interr upt Enable bit controls generating A CB interr upts. When the INTEN bit is cleared A CB interr upt is disabled. When the INTEN bit is set, interrupts are enabled. 0 – A CB interrupts disab led. 1 – ACB interrupts enabled. An interrupt is generated (the interrupt signals to the ICU is high) on any of[...]

189 www.national.com CP3BT26 24.3.7 A CB Own Address Register 1 (ACB ADDR1) The ACBADDR1 register is a by te-wide, read/write register that holds the module’s first A CCESS.b us addre ss. After re- set, its value is undefined. ADDR The Own Address field holds the first 7-bit AC- CESS.b us address o f this device . When in sla ve mode , the first [...]

www.national.com 190 CP3BT26 24.4.1 A v oiding Bus Error Du ring Writ e T rans action A Bus Error (BER) ma y occur dur ing a write transaction if the data register is wr itten at a very specific time. The mod- ule generates one system-cloc k cycle setup time of SD A to SCL vs. the minimum time of the cloc k divider ratio . The problem can be masked[...]

191 www.national.com CP3BT26 acb->ACBctl1 |= ACBSTOP; /* Send STOP bit */ /* Return success status.... */ return (ACB_NOERR); } /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%% ; NAME: ACBStartX Initiates an ACB bu s transaction by sending the Start bit, followed by the Slave addres[...]

www.national.com 192 CP3BT26 25.0 Timing and W atchdog Module The Timing and W atchdog Module (TWM) generates the clocks and interrupts used for timing periodi c functions in the system; it also pro vides Wa tchdog protection o ver soft- ware e xecution. The TWM is designed to provid e fle xibility in system design by configuring various clock rati[...]

193 www.national.com CP3BT26 25.3 W ATCHD OG OPERATION The W atchdog is an 8-bit down counter that operates on the rising edge of a specified clock source. At reset, t he W atch- dog is disabled; it does not count and no Watchdog signal is generated. A write to either the Watchdog Count (WDCNT) register or the W atchdog Ser v ice Data Match (WDSDM)[...]

www.national.com 194 CP3BT26 25.4.1 Timer and W atchdog Configuration Register (TWCFG) The TWCFG register is a byte-wide, read/write register that selects the W atchd og clock input and serv ice method, and also allows the W atchdog registers to be selectively lock ed. A lock ed register cannot be read or wr itten; a read operation retur ns unpredi[...]

195 www.national.com CP3BT26 25.4.4 TWMT0 Contr ol and St atus Re gister (T0CSR) The T0CSR register i s a byte-wide, read/write registe r that controls Timer T0 and shows its current status. At reset, the non-reser ved bits of the regi ster are cleared. The register f or mat is show n below . RST The Restar t bit is used to reset Timer T0. When thi[...]

www.national.com 196 CP3BT26 26.0 Multi-Function Timer The Multi-Functi on Timer modu le contains a p air of 16-bit timer/counters. Each timer/counter unit offers a choice of clock sources f or operation and can be configured to oper- ate in any of the f ollowing modes:  Processor-Independent Pulse Wi dth Modulation (PWM) mode, which generates p[...]

197 www.national.com CP3BT26 Counter C lock Sour ce Select There are two clock source se lectors that allo w software to independently sel ect the clock source f or each of the two 16-bit counters from a ny one of the follo wing sources:  No clock (which stops the counter)  Prescaled System Clock  Externa l ev ent count based on TB  Pul[...]

www.national.com 198 CP3BT26 26.2.1 Mode 1: Pr ocessor-Independent PWM Mode 1 is the Processor-Independe nt Pulse Width Modula- tion (PWM) mode, which generates pulses of a specifie d width and duty cycle, and whic h also pro vides a separate general-pur pose timer/counter . Figure 100 is a block diagr am of the Multi-Function Timer configured to o[...]

199 www.national.com CP3BT26 26.2.2 Mode 2: Dual Input Capture Mode 2 is the Dual Inp ut Capture mode, which measures the elapsed time between occurrences of exter nal ev ents, and which also provides a separate general-pur pose timer/ counter . Figure 101 is a block diagr am of the Multi-Function Timer configured to operate in Mode 2. The time b a[...]

www.national.com 200 CP3BT26 26.2.3 Mod e 3: Dual Independent Timer/Counter Mode 3 is the Dual Independent Timer mode, which gener- ates system timing signals or counts occurrences of e xter- nal ev ents. Figure 102 is a block diagr am of the Multi-Function Timer configured to operate in Mode 3. The ti mer is configured to operate as a dual indepen[...]

201 www.national.com CP3BT26 26.2.4 Mod e 4: Input Capture Plus Timer Mode 4 is the Single Input Cap ture and Single Timer mode, which provides one external ev ent counter and o ne system timer . Figure 103 is a block diagr am of the Multi-Function Timer configured to operate in Mode 4. This mode offers a combi- nation of Mode 3 and Mode 2 function[...]

www.national.com 202 CP3BT26 26.3 TIMER INTERRUPTS The Multi-Functi on Timer unit has four interrupt sources, designated A, B, C , and D . Interrupt sources A, B, and C are mapped into a single system in terrupt cal led Timer Interr upt 1, while interrupt source D is mapped into a system interrupt called Timer Interrupt 2. Each of the four interrup[...]

203 www.national.com CP3BT26 26.5 TIMER REGI STERS T able 79 lists the CPU-accessible registers used to control the Multi-Functi on Timers. 26.5.1 Cloc k Prescaler Register (TPRSC) The TPRSC register is a byte- wide, read/write registe r that holds the current value of the 5-bit cloc k prescaler (CLKPS). This register is cleared on reset. The regis[...]

www.national.com 204 CP3BT26 26.5.5 Reload/Capture A Register (TCRA) The TCRA register is a word-wide, read/write register that holds the relo ad or capture va lue for Timer/C ounter 1. The register contents are not affected b y a reset and are un- known after po wer-up . 26.5.6 Reload/Capture B Register (TCRB) The TCRB register is a word-wide, rea[...]

205 www.national.com CP3BT26 26.5.8 Timer Interrupt Co ntr ol Register (TICTL) The TICTL register is a byte-w ide, read/write re gister that contains the interr upt enable bits and interrupt pendin g bits f or the four timer interrupt sources, designated A, B, C, and D . The condition that causes each type of interr upt depends on the operating mod[...]

www.national.com 206 CP3BT26 27.0 V ersatile Timer Unit (VTU) The V ersatil e Timer Unit (VTU) contains four fully indepen- dent 16-bit timer subsystems. Each timer subsystem can operate either as dual 8-bit PWM timers, as a si ngle 16-bit PWM timer , or as a 16-bit counter with 2 input capture chan- nels. These timer subsystems of f ers an 8-bit c[...]

207 www.national.com CP3BT26 27.1.1 Dual 8-bit PWM Mode Each timer subsystem ma y be configured to generate two fully independent PWM wav eforms on the resp ective TIOx pins. In this mode, the counter COUNTx is split and oper- ates as two independent 8-bit coun ters. Each counter incre- ments at the rate determined by the clock prescaler . Each of [...]

www.national.com 208 CP3BT26 The two I/O pins associated with a timer subsystem function as independent PWM outputs in the d ual 8-bit PW M mode. If a PWM timer is stopped using its associated MODE.TxR UN bit the follo wing acti ons result:  The associated TIOx pin will retur n to its default v al ue as defined by the IOxCTL.PxPOL bit.  The c[...]

209 www.national.com CP3BT26 Figure 108 illustrates the configuration of a timer sub system while operating in capture mode. The numb ering i n Figure 108 refers to timer subsystem 1 but equally applies to the other thre e timer subsystems. Figure 108. VTU Dual 16-bit Capture Mode 27.1.4 Lo w Power Mode In case a timer subsystem is not used, softwa[...]

www.national.com 210 CP3BT26 27.2 VTU REGISTE RS The VTU contains a total of 19 user acce ssible registers, as listed in T able 81. All registers are word-wide an d are initial- ized to a known v alue upon reset. All software accesses to the VTU registers must be w o rd accesses. 27.2.1 Mode Contro l Register (MODE) The MODE regi ster is a word- wi[...]

211 www.national.com CP3BT26 27.2.2 I/O Contr ol Register 1 (IO1CTL) The I/O Control Register 1 (IO1CTL) is a word-wide read/ write register. The r egister controls the function of the I/O pins TIO1 through TIO4 dependi ng on the selected mode of operation. The register is clear after reset. CxEDG The Capture Edge Control field specifi es the polar[...]

www.national.com 212 CP3BT26 IxCEN The Timer x Interrupt C Enable bit controls in- terrupt requests tr iggered on the correspon d- ing IxCPD bit bei ng set. The associated IxCPD bit will be updated rega rdless of the value of the IxCEN bit. 0 – Disab le system interr upt request f or the IxCPD pending bit. 1 – Enable system interrupt request f [...]

213 www.national.com CP3BT26 27.2.8 Counter Regi ster n (COUNTx) The Counter (COUNTx) regist ers are word-wide read/wr ite registers. There are a total of four registers called COUNT1 through COUNT4, one for each of the four timer sub- systems. Software ma y read the regi sters at any time. Reading the register will retur n the current value of the[...]

www.national.com 214 CP3BT26 28.0 Register Map T able 82 is a detailed memor y map showing the specific memor y address of the me mor y , I/O por ts, and registe rs. The table shows the star ting address, the size, and a br ief description of each memor y block and register . F or detailed inf o rmatio n on using these memor y locations, see the ap[...]

215 www.national.com CP3BT26 WTPTC_1SLO T W ord 0E F1B0 h W rite-Only WTPTC_3SLO T W ord 0E F1B2 h W rite-Only WTPTC_5SLO T W ord 0E F1B4 h W rite-Only SEQ_RESET Byte 0E F1B6h Wr ite-Only SEQ_CONTINUE Byte 0E F1B7h Write-On ly RX_ST A TUS Byte 0E F1B8h Read-Only CHIP_ID Byte 0E F1BAh Read-Only INT_VECT OR Byte 0E F1BCh Read-Only SYSTEM_CLK_EN Byte [...]

www.national.com 216 CP3BT26 DMAEV Byte FF FDAAh Read/Wr ite 00h DMAMSK Byte FF FD ACh Read/Write 00h MIR Byte FF FDAEh Read/Wr ite 1Fh DMA CNT Byte FF FDB0h Read/Wr ite 00h DMAERR B yte FF FDB2h Read/Wr ite 00h EPC0 Byte F F FDC0h R ead/Write 00h TXD0 Byte FF FDC2h Read/Wr ite XXh TXS0 Byte FF FDC4h Read/Write 08h TXC0 Byte FF FDC6h Read/Wr ite 00[...]

217 www.national.com CP3BT26 CAN Module Message Buffers CMB0_CNST A T Word 0E F000h Read/Wr ite XXXXh CMB0_TSTP W ord 0E F002h R ead/Write XXXXh CMB0_D A T A3 W ord 0E F004h R ead/Write XXXXh CMB0_D A T A2 W ord 0E F006h R ead/Write XXXXh CMB0_D A T A1 W ord 0E F008h R ead/Write XXXXh CMB0_D A T A0 W ord 0E F00A h Read/Write XXXXh CMB0_ID0 W ord 0E[...]

www.national.com 218 CP3BT26 CAN Registers CGCR Word 0E F100h Read/Wr ite 0000h CTIM W ord 0E F102h Read/Wr ite 0000h GMSKX W ord 0E F104h R ead/Write 0000h GMSKB W ord 0E F106h R ead/Write 0000h BMSKX W ord 0E F108h Read/Wr ite 0000h BMSKB W ord 0E F10Ah Read/Wr ite 0000h CIEN W ord 0E F10Ch Read/Wr ite 0000h CIPND Word 0E F10Eh Read On ly 0000h C[...]

219 www.national.com CP3BT26 BL TC1 W ord FF F830h Read/Wr ite 0000h BL TR1 W ord FF F834h Read/Wr ite 0000h DMA CNTL1 W ord FF F83Ch Read/Write 0000h DMAST A T 1 B yte FF F83Eh R ead/Write 00h ADCA2 Double Wo r d FF F840h Read/Wr ite 000 0 0000h ADRA2 Double Wo r d FF F844h Read/Wr ite 000 0 0000h ADCB2 Double Wo r d FF F848h Read/Wr ite 000 0 000[...]

www.national.com 220 CP3BT26 System Co nfiguration MCFG Byte FF F910h R ead/Write 00h DBGCFG Byte FF F9 12h R ead/Write 00h MST A T Byte FF F914h Read Only ENV2:0 pins SWRESET Byte FF F918h Wr ite Only N/A Flash Program Me mory Interface FMIBAR W ord FF F940h Read/Wr ite 0000h FMIBDR W ord FF F942h Read/Wr ite 0000h FM0WER W ord FF F944h Read/Wr it[...]

221 www.national.com CP3BT26 FSMTRAN Byte F F F754h Read/Write 30h FSMPROG Byte FF F756h Read/Wr ite 16h FSMPERASE Byte FF F7 58h Read/Wr ite 04h FSMMERASE0 Byte FF F75Ah Read/Wr ite EAh FSMEND Byte FF F75Eh Read/Wr ite 18h FSMMEND Byte FF F760h Read/Write 3Ch FSMRCV Byte FF F7 62h R ead/Write 04h FSMAR0 W ord FF F7 64h Read Only FSMAR1 W ord FF F7[...]

www.national.com 222 CP3BT26 P ower Management PMMCR Byte FF FC60h Read/Write 00h PMMSR Byte FF FC62h Read/Wr ite 0000 0XXXb Multi-Input W ake-Up 0 WK0EDG W ord FF FC80 h Read/Wr ite 00h WK0ENA W ord FF FC82h Read/Write 00h WK0ICTL1 W ord FF FC84h Read/Wr ite 00h WK0ICTL2 W ord FF FC86h Read/Wr ite 00h WK0PND W ord FF FC88h Read/Wr ite 00h Bits ma [...]

223 www.national.com CP3BT26 PCDIR Byte FF FB12h Read Only 00h PCDIN Byte FF FB14h Read/Wr ite XXh PCDOUT Byte FF FB16h Read/Wr ite XXh PCWPU Byte FF FB18h R ead/Write 00h PCHDR V Byte FF FB1Ah Read/Wr ite 00h PCAL TS Byte FF FB1Ch Read/Wr ite 00h PEAL T Byte FF FCC0h Read/Wr ite 00h PEDIR Byte FF FCC2h Read/Wr ite 00h PEDIN Byte FF FCC4h Read Only[...]

www.national.com 224 CP3BT26 PJDIN Byte FF F3 44h Read Only XXh PJDOUT Byte FF F346h Read/Wr ite XXh PJWPU Byte FF F348h R ead/Write 00h PJHDR V Byte FF F34Ah Read/Wr ite 00h PJAL TS Byte FF F34Ch Read/Wr ite 00h Adv anced Audio Interface ARFR Word FF FD40h Read On ly 0000h ARDR0 W ord FF FD42h Read Only 0000h ARDR1 W ord FF FD44h Read Only 0000h A[...]

225 www.national.com CP3BT26 Micro wire /SPI Interface MWD A T Word FF F3A0 h Read/Write XXXXh MWCTL1 W ord FF F3A2h Read/Wr ite 0000h MWST A T Word FF F3A4h Read Only All imple- mented bits are 0 UA R T 0 U0TBUF Byte FF F200h R ead/Write XXh U0RBUF Byte FF F202h Read Only XXh U0ICTRL Byte FF F204h Read/Wr ite 01h Bits 0:1 read only U0ST A T Byte F[...]

www.national.com 226 CP3BT26 UA R T 2 U2TBUF Byte FF F240h R ead/Write XXh U2RBUF Byte FF F242h Read Only XXh U2ICTRL Byte FF F244h Read/Wr ite 01h Bits 0:1 read only U2ST A T Byte FF F246h Read only 00h U2FRS Byte FF F248h Read/Wr ite 00h U2MDSL1 Byte FF F24Ah Read/Wr ite 00h U2BA UD Byte FF F24Ch Read/Wr ite 00h U2PSR Byte FF F24Eh R ead/Write 00[...]

227 www.national.com CP3BT26 A CCESS.bus A CBSDA Byte FF F2A0h Read/Wr ite XXh A CBST Byte FF F2A2h Read/Wr ite 00h A CBCST Byte FF F2A4h Read/Wr ite 00h A CBCTL1 Byte FF F2A6h Read/Wr ite 00h A CBADDR Byte FF F2A8h Read/Wr ite XXh A CBCTL2 Byte FF F2AAh R ead/Write 00h A CBADDR2 Byte FF F2ACh Read/Wr ite XXh A CBCTL3 Byte FF F2AEh R ead/Write 00h [...]

www.national.com 228 CP3BT26 V ersatile Timer Unit MODE W ord FF FF80h Read/Wr ite 0 000h IO1CTL W ord FF FF82h Read/Write 0000h IO2CTL W ord FF FF84h Read/Write 0000h INTCTL W ord FF FF86h Read/Wr ite 0 000h INTPND Word FF FF88h Read/Wr ite 0000h CLK1PS Wo rd FF FF8Ah Read/Wr ite 0000h COUNT1 Word FF FF8 Ch Read/Wr ite 0000h PERCAP1 W ord FF FF8Eh[...]

229 www.national.com CP3BT26 RNG RNGCST W ord F F F280h Read/Wr ite 0000h RNGD Word FF F282h R ead/Wr ite 0 000h RNGDIVH Word FF F284h R ead/Write 0000h RNGDIVL W ord FF F286h Read/Wr ite 0000h Register Name Size Address Access Ty p e V alue After Reset Comments[...]

www.national.com 230 CP3BT26 29.0 Register Bit Fields The follo wing tables show the functions of the bit fields of t he d evice registers. F or more information on using these regis- ters, see the detailed descri ption of the applicable function elsewhere in this data sheet. Bluetooth LLC Regist ers 7654321 0 PLN Reserved P LN[2:0] WHITENING_ CHAN[...]

231 www.national.com CP3BT26 WTPTC_5SLO T[15:8] WTPTC_5SLO T[15:8] SEQ_RESET Reserved SEQ_RESET SEQ_CONTINUE Reser ved SEQ_ CONTINUE RX_ST A TUS Reser ved HEC Error Header Error Correction AM_ ADDR Error P ayload CRC Error P ayload Error Correction P ayload Length Error PA C K E T _ DONE CHIP_ID Reser ved CHIP_ID INT_VECT OR INT_VEC TOR[ 7:0] SYSTE[...]

www.national.com 232 CP3BT26 NAKEV OUT IN NAKMSK OUT IN FWEV RXW ARN[3:1] Reser ved TXW ARN[3:1] Reser ved FWMSK RXW ARN[3:1] Reser ved TXW ARN[3:1] Reser ved FNH MF UL RFC Reser ved FN[10:8] FNL FN[7:0] DMACNTRL D EN IGNRXTGL DTGL ADMA DMOD DSRC DMAEV Reser ved NTGL ARD Y DSIZ DCNT DERR DSHL T DMAMSK Reserved DSIZ DCNT DERR DSHL T MIR ST A T DMACN[...]

233 www.national.com CP3BT26 RXS2 RX_ERR SETUP T OGGLE RX_LAST RCOUNT RXC2 Reser ved RFWL Reser ved FLUSH IGN_ SETUP Reser ved RX_EN EPC5 ST ALL Reserved ISO EP_EN EP TXD3 TXFD TXS3 TX_UR UN ACK_ST A T TX_DONE TCOUNT TXC3 IGN_ ISOMSK TFWL RFF F LUSH T OGGLE LAST TX_ EN EPC6 ST ALL Reserved ISO EP_EN EP RXD3 RXFD RXS3 RX_ERR SETUP T OGGLE RX_LAST RC[...]

www.national.com 234 CP3BT26 CAN Memory Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMBn.ID1 XI28 ID10 XI27 ID9 XI26 ID8 XI25 ID7 XI24 ID6 XI23 ID5 XI22 ID4 XI21 ID3 XI20 ID2 XI19 ID1 XI18 ID0 SRR RTR IDE XI17 XI16 XI15 CMBn.ID0 XI14 XI13 XI12 XI11 XI10 XI9 X I8 XI7 XI6 XI5 XI4 XI3 XI2 XI1 XI0 R TR CMBn.D A T A0 Data 1.7 Data 1.6 Data 1.5 Data [...]

235 www.national.com CP3BT26 System Co nfiguration Registers 7 6 5 43210 MCFG Reser ved MEM_IO_ SPEED MISC_IO_ SPEED USB_ ENABLE SCLK OE MCLK OE PLLCLK OE EXIOE DBGCFG Reserved FREEZE ON MST A T ISPRST WDRST Reser ved DPGM BUSY PGMBUSY OENV2 OENV1 OENV0 BIU Registers 1 5 1 2 1 1 1 0 9876543210 BCFG Reserved EWR IOCFG Reserved IPST Res. BW Reser ved[...]

www.national.com 236 CP3BT26 FMPROG Reserved FTPR OG FMPERASE Reserved FTPER FMMERASE0 Reser ved FTMER FMEND Reser ved FTEND FMMEND Reserved FTMEND FMRCV Reser ved FTRCV FMAR0 Reserved USB_ EN- ABLE FMAR1 WRPR O T RDPRO T ISPE EMPTY BOO T AREA FMAR2 CADR15:0 Flash Program Memory Interface Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Flash Data M[...]

237 www.national.com CP3BT26 FSMAR0 Reser ved USB_ EN- ABLE FSMAR1 WRPRO T RDPRO T ISPE EMPTY BOO T AREA FSMAR2 CADR15:0 Flash Data Memory Interface Regist ers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CVSD/PCM Registers 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 CVSDIN CVSDIN CVSDOUT CVSDOUT PCMIN PCMIN PCMOUT PCMOUT LOGIN Reserved LOGIN LOGOUT Reserve d LOGO[...]

www.national.com 238 CP3BT26 P M M R e g i s t e r 76543210 PMMCR HCCH HCCM DHC DMC WBPSM HAL T IDLE PSM PMMSR Reser ved OHC OMC OLC MIWU16 Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKEDG WKED WKENA WKEN WKICTL1 WKINTR7 WKINTR6 WKINTR5 WKINTR 4 WKINTR3 WKINTR2 WKINTR1 WKINTR0 WKICTL2 WKINTR15 WKINTR14 WKINTR13 WKINT R12 WKINTR11 W KINTR10 WKI[...]

239 www.national.com CP3BT26 A TDR1 A TDH A TDL A TDR2 A TDH A TDL A TDR3 A TDH A TDL AGC R CLK EN AAI EN IOM2 IFS FSL CTF CRF IEBC FSS IEFS SCS LPB DWL ASS AISCR Reserved TX EIC TX IC RX EIC RX IC TX EIP TX IP RX EIP RX IP TX EIE TX IE RX EIE RX IE ARSCR RXFWM RXDSA RXSA RXO RXE RXF RX AF A TSCR TXFWM TXDSA TXSA TXU TXF TXE TXAE ACCR BCPRS FCPRS C[...]

www.national.com 240 CP3BT26 MWSPI16 Registers 1 5 . . . 9 876543210 MWD A T M WD A T MWCTL1 SCD V SCIDL SCM EIW EIR EIO ECHO MOD MNS MWEN MWST A T Reser ved O VR RBF BSY A C B R e g i s t e r s 76543210 AC BSDA D A T A AC BST SL VSTP SDAST BER NEGACK ST ASTR NMA TCH MASTER XMIT ACBCST ARPMA TCH MA TCHAF TGSCL TSD A GMA TCH MA TCH BB BUSY ACBCTL1 S[...]

241 www.national.com CP3BT26 VTU Registers 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 MODE TMOD4 T8 RU N T7 RU N TMOD3 T6 RU N T5 RU N TMOD2 T4 RU N T3 RU N TMOD1 T2 RU N T1 RU N IO1CTL P4 POL C4EDG P3 POL C3EDG P2 POL C2EDG P1 POL C1EDG IO2CTL P7 POL C7EDG P6 POL C6EDG P5 POL C5EDG P5 POL C5EDG INTCTL I4DEN I4CEN I4BEN I 4AEN I3DEN I3CEN I3BEN I3AEN I2DEN[...]

www.national.com 242 CP3BT26 RNG Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RNGCST Reser ved IMSK Reser ved DVA L I D RNGE RNGD RNGD RNGDIVH Res er ved RNGDIV17:16 RNGDIVL RNGDIV15:0[...]

243 www.national.com CP3BT26 30.0 Electrical Characteristics 30.1 ABSOLUTE MAXIMUM RATINGS If Militar y/Aerospace specifie d devices are required, please contact the National Semiconductor Sales Office/Di stribu- tors f or availability and specifications. Note: Absolute maximum ratings indicate limits beyond which damage to the device ma y occur . [...]

www.national.com 244 CP3BT26 I O(Off) Output Leakage Current (I/O pins in i nput mode) 0V ≤ Vo u t ≤ Vcc -2.0 2.0 µA Icca1 Digital Supply Current Active Mode b Vcc = 2.75V , IO Vcc=3.63V 20 mA Iccprog Digital Supply Curren t Active Mode c Vcc = 2.75V , IO Vcc = 3.63V 20 mA Iccps Digital Supply Current P ower Sav e Mode d Vcc = 2.75V , IO Vcc =[...]

245 www.national.com CP3BT26 30.3 USB T RANSCEIVER ELECTRIC AL CHARACTERISTICS (T emperature: -4 0°C ≤ T A ≤ +85°C) 30.4 ADC ELECTRICAL CHARACTERISTICS (T emperature: -40°C ≤ T A ≤ +85°C) Symbol Parameter Conditions Min Max Units V DI Diff erential Input Sensitivity (D+) - (D-) -0.2 0.2 V V CM Diff erential Common Mode Range 0.8 2.5 V V[...]

www.national.com 246 CP3BT26 30.5 FLASH MEMORY ON-C HIP PROGRAMMING Symbol P arameter Conditions Min Max Units t ST ART Prog ram/Erase to NVSTR Setu p Time a (NVSTR = Non-V olatile Storage a. Program/er ase to NVSTR Setup Time is deter mined by the following equation: t ST ART = T cl k × (FTDIV + 1) × (FTST ART + 1), where T clk is the System Clo[...]

247 www.national.com CP3BT26 30.6 OUTP UT SIGNAL LEVELS All output signals are powered by the digital supp ly (VCC). T able 83 summarizes the states of the output signals dur ing the reset state (when VCC power e xists in the reset state) and during the P o wer Sav e mode. The RESET and NMI input pins a re active during the P ower Sav e mode. In or[...]

www.national.com 248 CP3BT26 Figure 110. Clock Timing Figure 111. NMI Signal Timing Figure 112. Non-Po wer-On Reset Figure 113. Po wer-On Reset X1CKI t X1h t X1l t X1p X2CKI t X2h t X2l t X2p DS095 CLK t IW t lH t lS NMI DS096 CLK t RST RESET DS097 VCC 0.9 VCC 0.1 VCC t DS115 R[...]

249 www.national.com CP3BT26 30.8 U ART TIMING Figure 114. U ART Asynchr onous Mode Timing Table 85 UART Signals Symbol Figure Description Referenc e Min (ns) Max (ns) UA R T I n p u t S i g n al s t Is 114 Input setup time RXD (asynchronous mode) Bef ore Rising Edge (RE) on CLK - t Ih 114 Input hold time RXD (asynchronous mode) After RE on CLK - U[...]

www.national.com 250 CP3BT26 30.9 I/O PORT TIMIN G Figure 115. I/O P ort Timing Table 86 I/O Port Signals Symbol Figure Description Referenc e Min (ns) Max (ns) I/O P ort Input Signals t IS 115 I nput Setup Time Bef ore Rising Edge (RE) on System Clock - t IH 115 Inpu t Hold Time After RE on System Cloc k - I/O P ort Output Signals t COv1 115 Outpu[...]

251 www.national.com CP3BT26 30.10 ADVANCED A UDIO INTERFACE (AAI) TIMING Figure 116. Receive Timing, Shor t Frame Sync Table 87 Advanced Audio Interface (AAI) Signals Symbol Figure Description Referenc e Min (ns) Max (ns) AAI Input Signal s t RDS 116, 118 Receive Data Setup Time Bef ore F alli ng Edge (FE) on SRCLK 20 - t RDH 116, 118 Receive Data[...]

www.national.com 252 CP3BT26 Figure 117. T ransmit Ti ming, Shor t Frame Sync Figure 118. Receiv e Timing, Long Frame Sync Figure 119. T ransmit Timing, Long Frame Sync 0 STD SCK SFS DS117 1 01 2 t TD V 0 SRD SRCLK SRFS DS118 1 01 2 t FSVH t FSVL t RDH t RDS N 0 STD SCK SFS DS119 1 01 2 t TD V N[...]

253 www.national.com CP3BT26 30.11 MICROWIRE/SPI TIMING Table 88 Microwir e/SPI Signals Symbol Figure Description Referenc e Min (ns) Max (ns) Micro wire/SPI Input Signals t MSKh 120 Microwire Clock High At 2.0V (both edges) 80 - t MSKl 120 Microwire Clock Low At 0.8V (both ed ges) 80 - t MSKp 120 Microwire Clock P eriod SCIDL bit = 0; Rising Edge [...]

www.national.com 254 CP3BT26 Figure 120. Microwire T ransaction Timi ng, Normal Mode , SCIDL = 0 t MDOv 120 Microwire Data Out V alid Nor mal Mode: After FE on MSK 25 Alter nate Mode: After RE on MSK t MITOp 124 MDODI to M DIDO (slav e only) Propagation Time V a lue is the same in all clocking modes of the Microwire 25 Table 88 Microwir e/SPI Signa[...]

255 www.national.com CP3BT26 Figure 121. Microwire T ransaction Ti ming, Normal Mod e, SCIDL = 1 lsb msb t MSKp t MSKh t MDlh t MDls t MCSs t MCSh t MSKs t MDOf t MDOv t MDOf t MDOh Data In MSK lsb msb MDODO (master) lsb msb MDIDO (slav e) t MSKh MCS (slav e) t MSKhd DS102[...]

www.national.com 256 CP3BT26 Figure 122. Microwire T ransaction Ti ming, Alternate Mode, SCIDL = 0 MSK lsb msb Data In lsb msb MDODO (master) lsb msb MDIDO (slav e) MCS (slav e) t MSKp t MSKh t MDlh t MDls t MCSs t MCSh t MSKs t MDOf t MDOv t MDOf t MDOh t MSKl t MSKhd DS103[...]

257 www.national.com CP3BT26 Figure 123. Microwire T ransaction Ti ming, Alternate Mode, SCIDL = 1 Figure 124. Microwire T ransaction Timing, Data Echoed to Outpu t, Normal Mode, SCIDL = 0, ECHO = 1, Slave Mode lsb msb t MSKp t MSKh t MDlh t MDls t MCSs t SKd t MCSh t MSKs t MDOf t MDOv t MDOff t MDOh Data In MSK lsb msb MDODI (master) lsb msb MDID[...]

www.national.com 258 CP3BT26 30.12 ACCESS.B US TIMING Table 89 ACCESS. bus Signals Symbol Figure Description Referenc e Min (ns) Max (ns) A CCESS.bus In put Signals t BUFi 126 Bus free time between Stop and Sta r t Condition t SCLhigho - t CSTOsi 12 6 SCL setup time Bef ore Stop Condition (8 × t CLK ) - t SCLri - t CSTRhi 126 SCL hold time After S[...]

259 www.national.com CP3BT26 Figure 125 . A CB Signals (SDA and SCL) Timing Figure 126. A CB Star t and Stop Condition Timing Figure 127. A CB Star t Conditio n Timing SCL 0.7VCC Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" f or input signal timing. 0.3VCC t SCLf 0.7VCC 0.3V[...]

www.national.com 260 CP3BT26 Figure 128. ACB Data Timing t SCAv o t SDAh t CSLlo w t SDAsi t SCLhigh SCL SDA Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. unless the parameter already includes the suffix. DS109[...]

261 www.national.com CP3BT26 30.13 USB PORT A C CHARACTERISTICS 30.14 M ULTI-FUNCTION TIMER (MFT) TIMING Figure 129. Mu lti-Function Ti mer Input Timing Table 90 USB Port Signal s Symbol Description Conditions a Min T yp Max Units T R Rise Time C L = 50 pF 4 20 ns T F F all Time C L = 50 pF 4 20 ns T RFM F all/Rise Time Matching (T R /T F )C L = 50[...]

www.national.com 262 CP3BT26 30.15 V ERSATILE TIMI NG UNIT (VTU) TIMING Figure 130. V er satile Timing Unit Input Timin g Table 92 Ver sat ile Timing Unit Input Signals Symbol Figur e Description Referenc e Min (ns) Max (ns) t TIOH 129 TIOx Input High Time Rising Edge (RE) on CLK 1.5 × T CLK + 5ns t TIOL 129 TIOx Input Low Time RE on CLK 1.5 × T [...]

263 www.national.com CP3BT26 30.16 EXTERNA L BUS TIMING Table 93 External Bus Signals Symbol Figure Description Referenc e Min (ns) Max (ns) External Bus Input Signals t 1 131, 133, 134, 135 Input Setup Time D[15:0] Bef ore Rising Edge (RE) on CLK 8 t 2 131, 133, 134, 135 Output Hold Time D[15:0] After RE on CLK 0 External Bus Output Signals t 3 13[...]

www.national.com 264 CP3BT26 Figure 131. Early Write Between Normal Read Cycles (No W ait States) T1 T2 T1 T2 T3 T1 T2 A[21:0] A22 ('13 only) CLK Normal Read Normal Read Early Write SELx D[15:0] In In Out t 4 t 4 , t 12 SELy (y ≠ x) RD WR[1:0] t 5 , t 12 t 5 , t 12 t 5 , t 12 t 8 , t 12 t 3 t 9 t 5 , t 12 t 5 , t 12 t 6 , t 13 t 5 , t 12 t 6[...]

265 www.national.com CP3BT26 Figure 132 . Late Write Betw een Normal Read Cyc les (No W ait States) T1 T2 T1 T2 T1 T2 CLK SELx D[15:0] In In Out (y ≠ x) RD Normal Read Normal Read Late Write t 4 , t 12 t 5 , t 12 t 5 , t 12 t 5 , t 12 t 5 , t 12 t 8 , t 12 t 3 t 11 t 5 , t 12 t 6 , t 13 t 6 , t 13 t 5 , t 12 t 10 t 9 t 4 , t 12 SELy (y ≠ x) WR[[...]

www.national.com 266 CP3BT26 Figure 133. Consecutive Nor mal Read Cycles (Burst, No W ait States) T1 T2 T2B T1 T2 T2B Normal Read Normal Read CLK SELx SELy WR[1:0] D[15:0] In In In In (y ≠ x) (y ≠ x) RD t 5 , t 12 t 5 , t 12 t 4 , t 12 t 4 , t 12 t 4 t 5 , t 12 t 5 , t 12 t 7 t 5 , t 12 t 5 , t 12 t 2 t 1 t 2 t 1 A[21:0] A22 ('13 only) Bus[...]

267 www.national.com CP3BT26 Figure 134. Nor mal Read Cycle (W ai t C ycle Followed b y Hold Cycle) T1 TW T2 TH CLK D[15:0] SELn, SELIO WR[1:0] RD t 4 t 5 , t 12 t 5 , t 12 t 5 , t 12 t 5 , t 12 t 2 t 1 t 4 , t 12 A21:0 A22 ('13 only) Bus State DS127[...]

www.national.com 268 CP3BT26 Figure 135. Early Write Between Fast Read Cycles T idle T1-2 T1 T1 T2 T3 T1-2 F ast Read Early Write CLK SELx SELy WR[1:0] D[15:0] (y ≠ x) (y ≠ x) RD F ast Read t 5 , t 12 t 5 , t 12 t 2 t 1 t 5 , t 12 t 5 , t 12 t 4 , t 12 t 4 A[21:0] A22 ('13 only) Bus State DS128 In In Out[...]

269 www.national.com CP3BT26 31.0 Pin Assignments 31.1 LQFP-128 P ACKAGE F or 128-pi n devices , Figure 13 6 provides a pinout diagram, and T a ble 94 pro vid es the pin assignments. The ph ysical di- mensions are provided in Section 33.0. Figure 136. CP3BT26 in the LQ FP-128 Pac kage (T op View) DS181 CP3BT26 (LQFP-128) 1 PJ1/WUI19 PC7 PC6 IOGND P[...]

www.national.com 270 CP3BT26 AV C C 2 9 P W R ADGND 90 PWR AD VCC 89 PWR UVCC 62 PWR UGND 63 PWR X2CKI 30 I X2CK O 31 O ENV2 SLO WCLK 34 I/O ENV1 CPUCLK 35 I/O ENV0 PLLCLK 36 I/O RESET 100 I TMS 101 I TDI 102 I TCK 103 I TDO 106 O RD Y 108 O RFD A T A 68 I/O D- 61 I/O D+ 60 I/O SCL 81 I/O SD A 82 I/O ADC0 TSX+ 92 I/O/HIZ 20mA+ ADC1 TSY+ 93 I/O/HIZ [...]

271 www.national.com CP3BT26 PC5 D13 5 GPIO PC6 D14 3 GPIO PC7 D15 2 GPIO PE0 RXD0 87 GPIO PE1 TXD0 83 GPIO PE2 R TS 86 GPIO PE3 CTS 88 GPIO PE4 CKX/TB 40 GPIO PE5 SRFS/NMI 120 GPIO PF0 MSK /TIO1 111 GPIO PF1 MDIDO/T IO2 114 GP IO PF2 MDODI/T IO3 116 GP IO PF3 MWCS/ TIO4 109 GPIO PF4 SCK/TIO 5 122 GPI O PF5 SFS/TIO 6 1 23 GPIO PF6 STD/TIO7 125 GPI [...]

www.national.com 272 CP3BT26 31.2 LQFP-144 P ACKAGE F or 144-pi n devices , Figure 13 7 provides a pinout diagram, and T a ble 95 pro vid es the pin assignments. The ph ysical di- mensions are provided in Section 33.0. Figure 137. CP3BT26 in the LQ FP-144 Pac kage (T op View) DS182 1 PC7 PC6 IOGND PC5 PC4 IOVCC PC3 PC2 IOGND PC1 PC0 IOVCC PB7 PB6 P[...]

273 www.national.com CP3BT26 Table 95 Pin Assignments for LQFP-144 Package Pin Name Alternate Functio n(s) Pin Number T ype GND 23, 32, 58, 85, 91, 12 1 PWR VCC 24, 31, 57, 86, 90, 12 2 PWR IOGND 3, 9, 16, 43, 46, 49, 55, 66, 84, 117, 130 PWR IO VCC 6, 12, 20, 41, 44, 51, 63, 80, 126, 140 PWR AGN D 27 P W R AV C C 2 8 P W R ADGND 96 PWR AD VCC 95 P[...]

www.national.com 274 CP3BT26 PB4 D4 17 GPIO PB5 D5 15 GPIO PB6 D6 14 GPIO PB7 D7 13 GPIO PC0 D8 11 GPIO PC1 D9 10 GPIO PC2 D10 8 GPIO PC3 D11 7 GPIO PC4 D12 5 GPIO PC5 D13 4 GPIO PC6 D14 2 GPIO PC7 D15 1 GPIO PE0 RXD0 93 GPIO PE1 TXD0 89 GPIO PE2 R TS 92 GPIO PE3 CTS 94 GPIO PE4 CKX/TB 37 GPIO PE5 SRFS/NMI 134 GPIO PF0 MSK /TIO1 120 GPIO PF1 MDIDO/[...]

275 www.national.com CP3BT26 A22 62 O A21 61 O A20 60 O A19 54 O A18 53 O A17 45 O A16 42 O A15 40 O A14 39 O A13 143 O A12 142 O A11 141 O A10 139 O A9 132 O A8 131 O A7 129 O A6 128 O A5 125 O A4 124 O A3 119 O A2 118 O A1 116 O A0 114 O SEL0 79 O SEL1 81 O SEL2 82 O SELIO 83 O RD 65 O WR0 67 O WR1 68 O Note 1 : The ENV0, E NV1, ENV2, RESET , TCK[...]

www.national.com 276 CP3BT26 32.0 Revision History Table 96 Revision History Date Major Changes From Previous V ersion 4/3/03 Or iginal rele ase. 5/26/03 Fixed maxim um boot area in Secti on 8. Fixed names of cloc k signals in Figures 5 and 6. Fixed addresses of FSMARx registers in Register Map section. Added default v alue for RNGDIV . 6/16/03 C o[...]

277 www.national.com CP3BT26 33.0 Physical Dimensions (millimeters) unless otherwise noted Figure 138. LQFP-128 P ackage Figure 139. LQFP-144 P ackage[...]

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