ST & T UPSD3212CV manual

1/163 December 2004 uPSD 321 2A, uPS D321 2C uPSD 3212C V Flas h Progr amm able Syste m Device s with 80 32 MC U with US B an d P rog ram m ab le Lo gic FEA TUR ES SU MM ARY ■ FA S T 8-BIT 8032 M CU – 40MHz at 5.0V, 24MHz at 3.3V – Core, 1 2-clocks per i nstructi o n ■ DUAL FL A SH MEMO RIES WI TH MEM ORY MANAG EMEN T – Place either memor[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 2/163 Table 1. Device S u mmary Par t N u m be r Max Clo c k (MHz) 1st Flash (bytes) 2nd Flash (bytes) SRAM (bytes) GP IO US B 8032 Bus V CC (V) Pkg . T em p. uPSD321 2C-40T6 40 64K 16K 2K 37 No No 4.5-5.5 TQFP52 –40°C to 85°C uPSD3 212CV -24T6 24 64K 16K 2K 37 No No 3.0-3.6 TQFP52 –40°C to 85°C uPSD321 2C[...]

3/163 uPSD3212A, uPSD 3212C , uPSD3212CV T ABLE O F CO NTENTS FEAT UR ES SU M MARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SU MM ARY DESCRIP TION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 4/163 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 Power -Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 I/O PORTS (M CU Mod[...]

5/163 uPSD3212A, uPSD 3212C , uPSD3212CV In-Sy stem Pr ogrammin g (ISP ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 0 DE VELOPMENT SYST EM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 PSD MODULE REGISTER DESCRIP TION[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 6/163 PSD Chip Sele c t In put ( CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 24 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 4 Input Contro l Signal s[...]

7/163 uPSD3212A, uPSD 3212C , uPSD3212CV S UM MA RY DESCR IPT IO N The uP S D3 21x Series com bi n es a fast 8051- based microcontroller with a flex i ble memory structure, programmable logic, and a rich p eri ph- eral mix including USB, to form an ideal embed ded controller. At i ts core is an i ndustry-sta ndard 8032 MCU ope r a t i ng up t o 40M[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 8/163 Figu re 3. TQ FP52 C on ne ct i on s N ot e: 1. P ul l - up re sis tor re qu ir ed on pi n 5 ( 2 k Ω for 3V dev ices , 7. 5k Ω for 5V dev ices) . 39 P1.5/ADC1 38 P1.4/ADC0 37 P1.3/TXD1 36 P1.2/RXD1 35 P1.1/T2X 34 P1.0/T2 33 V CC 32 XTAL2 31 XTAL1 30 P3.7/SCL1 29 P3.6/SDA1 28 P3.5/T1 27 P3.4/T0 PD1/CLKIN [...]

9/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figu re 4. TQ FP80 C on ne ct i on s N ot e: 1. P ul l - up re sis tor re qu ir ed on pi n 8 ( 2 k Ω for 3V dev ices , 7. 5k Ω for 5V dev ices) . 2. N C = No t Co nn ec te d. 60 P1.5/ADC1 59 P1.4/ADC0 58 P1.3/TXD1 57 A11 56 P1.2/RXD1 55 A10 54 P1.1/TX2 53 A9 52 P1.0/T2 51 A8 50 V CC 49 XTAL2 48 XTAL1 47 [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 10/163 Table 2. 80-Pin Packag e Pin Description Po r t P i n Signal Name Pin N o. In/Out Functio n Basic Alte rnate AD0 36 I/O Exter nal Bus Multiplex ed Address/D ata bus A1/D1 AD1 37 I/O Multip le xed Address/D ata bus A0/D0 AD2 38 I/O Multip le xed Address/D ata bus A2/D2 AD3 39 I/O Multip le xed Address/D ata [...]

11/163 uPSD3212A, uPSD 3212C , uPSD3212CV P4.4 PWM1 25 I/O Gene r al I/O por t pin 8-bit Pulse Width Mo dulation output 1 P4.5 PWM2 23 I/O Gene r al I/O por t pin 8-bit Pulse Width Mo dulation output 2 P4.6 PWM3 19 I/O Gene r al I/O por t pin 8-bit Pulse Width Mo dulation output 3 P4.7 PWM4 18 I/O Gene r al I/O por t pin Programmable 8 -bit Pulse W[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 12/163 52- PIN PACKA GE I /O PO RT The 52-pi n package m embers of the uPS D321x Devices ha v e the same port pins as t hose of the 80-pin package except : – P ort 0 (P 0.0-P0 .7, external address/data b us AD0-AD 7) – P ort 2 (P 2.0-P 2.3, external address bus A8- A11) – Port A (PA0- PA7 ) – P ort D (PD2)[...]

13/163 uPSD3212A, uPSD 3212C , uPSD3212CV ARC HITECT URE OVER VIEW M emor y Or gani zati on The u PSD321x Devices’s stan dard 8032 Core has separate 64KB address s paces for Program mem- ory and Data Mem ory . Program m em ory is where the 8032 execut es instructions from. Data m e mory is used to hold data variabl es . Fl ash memory can be mappe[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 14/163 Registers The 8032 has s everal registers; these are the Pro- gram Counter (PC), Ac cum ul a t or (A), B Register (B), the S t a c k P oi nt er (SP), the Program Status Word (PSW), General purpose regist ers (R0 to R7), and DPTR (Data P ointer register). Accumul ato r. The Ac c u m ul at or is the 8-bit gen[...]

15/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figu re 9. P SW (Pro gram S t at us Wo rd) Regi s te r Progr am Me mory The program memory c onsists of two F lash mem- ory: 64K B yt e Main Flas h and 16KBy t e of Sec ond- ary Flash. The F lash memory can be ma pped to any address s pace as defined by t h e user in the PSDsoft Tool. It can al s o be mappe[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 16/163 SF R The SFRs can only be addressed directly in the address range from 80h t o F F h. Tab le 15., page 28 gives a n overview of t he Special Function Registers. Sixteen address in the SFRs space are bot h-byte and bit-addressabl e. Th e bit- addressable SFRs are those whose addre s s ends in 0h and 8h. Th e[...]

17/163 uPSD3212A, uPSD 3212C , uPSD3212CV (3) Register ad dressing. The regi s t er banks, containing regist ers R0 through R7, can be ac- cessed by c ertain instructions whi ch c a r ry a 3-bi t register specif i cation wi thin the opc ode of the in- struction. Instructions t hat access the reg isters this way are code efficient, since this m ode [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 18/163 Tab le 4 . Ar it hm e t ic In st ru ct io ns Logical Instructio ns Table 5 ., page 19 shows list of uPSD321 x Devic- es logical instructions. The instructions that per- form Boolean o perations (AND, OR, Exclusive OR, NOT ) on bytes perform t he operat i on o n a bit- by-bit basis. T h at is, if the A ccumu[...]

19/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 5. Logical Instruc tions Mnem onic Oper ation Addressing Modes Dir . Ind. Reg. Imm ANL A,<byte> A = A .A ND . <byte> X X X X ANL <byte>,A A = <byte> . AND . A X ANL <byte> ,#data A = <byte> .AN D . #data X ORL A,<byte> A = A .OR . <byte> X X X X ORL <[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 20/163 Data Tran sfers Internal RAM . Tab le 6 shows the m enu of in- structions that are available for m oving data around within the internal memory spaces, and t he addressing modes that can be used with each one. The MOV <dest>, <src> inst r u c tion a ll ows data to be transferred bet ween any two[...]

21/163 uPSD3212A, uPSD 3212C , uPSD3212CV First, pointers R1 and R0 are set up to point to the two byte s containing t he last four BCD digits. Then a loop i s executed whi c h leaves t he last byte, loca- tion 2EH, ho lding the l ast two dig its of t he shifted number. The pointers are decremented, and the loop is repeated f or l ocat i on 2DH . T[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 22/163 Ext e rnal RAM. Tab le 10 shows a l ist of t he Data Transfer instructions that access ex ternal Data Memory. Only i ndirect addressing c a n be used. The choice i s whether t o use a one-byte ad dres s, @Ri, where Ri c a n be either R0 or R1 of the se- lected register bank, or a two-byte address, @DT P R .[...]

23/163 uPSD3212A, uPSD 3212C , uPSD3212CV Boolean Instructions The uPSD32 1x Devices cont ain a comp let e Bool- ean (single-bit) proc ess o r . On e page of the inter- nal RAM conta ins 128 addressable bi t s, and the SFR space can s upport up to 128 ad dressable bits as well. All of the port lines are bit-addressable, and each one can be tre at e[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 24/163 Jump Instr uctions Table 13 s hows the list of unconditional jump in- structions. The table lists a single “JMP add” in- struction, but in fact t here a re three S JMP , LJ M P, and AJMP, which differ in t he format of the desti- nation address. J M P i s a generi c mnem onic which can be used if th e p[...]

25/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 14 sh ows the list of conditional jumps av ail- able to the uP S D321x Devices user. All of these jumps specify the des tination address by the rela- tive offset method, and so are li m i t ed to a jump dis- tance of -128 to +127 bytes from the i ns t ruct i on following the conditional jump i nst ruc[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 26/163 Figure 1 4. State Seq uence i n uPSD3 21x Devices Osc. (XTAL2) Read opcode Read next opcode Read next opcode and discard Read next opcode and discard Read 2nd Byte No Fetch No Fetch No ALE S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 Read opcode Read next opcode S1 S2 S3 S4 S5 S6 Read opcode Read n[...]

27/163 uPSD3212A, uPSD 3212C , uPSD3212CV uPSD 3200 HARDWAR E DESCRIPTI ON The u PSD321x Devices has a m odular architec- ture with two m ain functional m od ules: the MC U Module and t he PSD M o dule. The MCU M odule consists of a st andard 80 32 c ore, peripheral s and other syst em support i ng f u n c tions. The PSD Mod- ule provides configura[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 28/163 MCU MO DULE DISC RIP TIO N This section provides a detail descript i on of the MCU Module system func t i ons and Peripherals, including: ■ Spe cial Function Registers ■ Timers / Cou nt e r ■ Inter rupts ■ PWM ■ Sup ervisory Function (LVD and Watchdog) ■ US AR T ■ Powe r Saving Modes ■ I 2 C[...]

29/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 16. List of all SFR SFR Addr Reg Nam e Bit Re gister Nam e Reset Va l u e Com me nt s 76 5 4 3 2 1 0 80 P0 FF Port 0 81 SP 07 Sta c k P tr 82 DPL 00 Data Ptr Low 83 DPH 00 D ata Ptr High 87 PCO N SM OD SM OD1 L VREN A DSFINT RCLK1 TCLK1 PD ID LE 00 P ower Ct rl 88 TCO N TF 1 TR1 TF0 TR0 IE1 IT1 IE0 IT[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 30/163 A4 PWM2 00 PWM2 Outpu t Duty Cycle A5 PWM3 00 PWM3 Outpu t Duty Cycle A6 WDRST 00 Watch Dog Reset A7 IEA ES2 EI 2 C 00 Interr upt Enable (2nd) A8 IE E A - E T2 ES ET1 EX1 ET0 EX0 00 I nterrupt Enable A9 AA PWM4P 00 PWM 4 Pe r i o d AB PWM4W 00 PWM 4 P ul se Width AE WDKEY 00 Watch Do g Key Register B0 P3 FF[...]

31/163 uPSD3212A, uPSD 3212C , uPSD3212CV D2 S2SET UP 00 I 2 C (S2) Setup D4 D5 D6 D7 D8 D9 DA DB DC S2CON CR 2 EN1 S T A ST O ADD R AA CR1 C R0 00 I 2 C B us Contro l Reg DD S2S T A G C Stop I ntr TX-Md Bbusy Blost ACK_R S L V 00 I 2 C B us Status DE S2DA T 00 Data Hold Register DF S2ADR 00 I 2 C address E0 ACC 00 Accumulator E1 USCL 00 8-bit Pres[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 32/163 Table 17. PSD Module Register Address Offset CSIOP Addr Offset Regi ster N ame Bit R egist er Name Reset Va l u e Com ments 76 5 4 3 2 1 0 00 Dat a In (P ort A) Reads P or t pins as i nput 02 Con trol (P or t A) Co nfigure pin between I/O or Addres s Out Mod e . Bit = 0 selects I/ O 00 04 Data Out (P or t A[...]

33/163 uPSD3212A, uPSD 3212C , uPSD3212CV Note : (Re giste r addres s = c s iop addre ss + add ress offs et; wher e csiop a ddres s is define d by use r i n P SDsof t) * ind icate s bit is not used and need to set to '0. ' 21 Output Macrocell s BC 22 Mask Macr ocells AB 23 Mask Macr ocells BC C0 Prima ry Fl ash Protect ion Sec 3_ Prot S e[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 34/163 INT ERRUPT SY STEM There are i nt errup t req uests from 10 sources as follows (see F igure 16., page 35 ). ■ IN T 0 Ex te rna l In ter rup t ■ 2nd USART Interr upt ■ Timer 0 Int errupt ■ I 2 C Inte rr upt ■ INT1 Exter nal In te rr u pt ( o r ADC Interr upt) ■ Timer 1 Int errupt ■ U SB Interru[...]

35/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figu re 16. I nte rru pt S ys tem AI07427b INT0 USART Timer 0 I2C INT1 Timer 1 2nd USART Timer 2 High Low Interrupt Polling Interrupt Sources IE / IP / IPA Priority Global Enable USB www.BDTIC.com/ST[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 36/163 USA R T In te rru pt – T he USART Interrupt is generated by RI (Receive Inter r upt) O R TI ( Tr ansmi t I nterr up t) . – W hen the USART Interrupt is generated, the correspon ding request flag must be cleared by the sof tware. The interrupt s ervice rout i ne wi ll have to c heck th e vario us USART r[...]

37/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 20. Description of the IE Bits. Table 21. Description of the IEA Bits Table 22. Description of the IP Bits Bit Sym bol Funct ion 7E A Disable all in terrupts : 0: no in terrupt w ith be acknowled ged 1: each interrup t source is indivi dually enabled or disabled by sett ing or clear ing its enable bit[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 38/163 Table 23. Description of the IPA Bits How Interr up ts are Handled The interrupt flags are sam pl e d at S5P2 of every mach ine cycl e . The sa mples ar e pol l ed during fol - lowing machine cycle. If one of the flags was in a set condition at S5P 2 of the preceding cycle, the pol ling cycle w ill f i nd i[...]

39/163 uPSD3212A, uPSD 3212C , uPSD3212CV PO W E R- SA V ING MO DE Two software s el ectab le modes of reduced power consump tion are implemen ted (see Table 25 ). Id le M od e The following Functions are Switched Off. – C PU (Halted) The following F unction Remain Active During Idle Mod e. – E x ternal Interrupts – T im er 0, Timer 1, T i me[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 40/163 Table 27. Description of the PCON Bits N ot e: 1. S ee t he T2 CO N regi ster f o r de ta i l s of th e f l a g de sc ri pti on I/O PO RTS ( MCU MO DUL E) The MCU Modul e has five ports: Port0, Port1, Port2, Port3 and Port 4. (Ref er to the PSD M odule section on I/O po rts A,B,C and D). P ort s P 0 and P2 [...]

41/163 uPSD3212A, uPSD 3212C , uPSD3212CV The followi n g SFR registers (Tables 29 , 30 , and 31 ) are us ed to control the mapping of alternat e functions onto the I/ O port bits. Port 1 alternate functions are c ontrolled using t he P1SFS r e gist er, except for T imer 2 and the 2nd UART whi c h are enabled by their configuration registers. P1.0 [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 42/163 POR T Ty pe and De s cri pt i on Figure 17. PORT Type and Description (Part 1) AI07438 Symbol Circuit Description In / Out RESET I • Schmitt input with internal pull-up CMOS compatible interface NFC : 400ns WR, RD,ALE, PSEN O Output only XTAL1, XTAL2 I O On-chip oscillator On-chip feedback resistor Stop i[...]

43/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figure 18. PORT Type and Description (Part 2) AI07428b Symbol Circuit Function In/ Out PORT1 <3:0>, PORT3, PORT4<7:3,1:0> PORT2 I/O PORT4.2 Bidirectional I/O port with internal pull-ups Schmitt input CMOS compatible interface Bidirectional I/O port with internal pul l-ups Schmitt input. TTL comp[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 44/163 OSC ILLATOR The oscillator circuit of the uPSD321x De vices i s a single stag e in verting am plifier in a Pierce o scilla- tor configuration (see Figure 19 ). The circuitry be- tween XTA L1 and XTAL2 is bas ically an inverter biased to the transf er poi nt. Either a c rys tal or ce- ramic resonator can be [...]

45/163 uPSD3212A, uPSD 3212C , uPSD3212CV SUP ERV ISOR Y There are four way s t o i nvoke a r e s et an d i nitialize the uPS D321x Devices. ■ Via the external RES ET pin ■ V ia th e i n te r n a l L VR B loc k. ■ Via Watch Dog timer ■ Via USB bus reset signal ling Th e R ESET m echanism is illustrated in Figure 20 . Eac h RESET sou rce wil[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 46/163 WA TCH DOG TIMER The hardware Watchd og Ti m er (WDT ) reset s the uPSD321x Devices when it overflows. T he WDT is intended as a recovery method in situat i ons where the CPU may be subje c ted to a software upset. To prevent a system r ese t the time r must be reloa ded in time by the application software.[...]

47/163 uPSD3212A, uPSD 3212C , uPSD3212CV Watchdog r eset pulse w idth dep ends on the clock frequency . The reset peri od is T f OSC x 12 x 2 22 . The RESET p ulse width is Tf OSC x 12 x 2 15 . Figu re 21 . RE SET P ulse Width Table 34. W atchdog T i mer Clear Register (WDR ST: 0A6H) Table 35. D escription of the WDRST Bits Note : Th e Wa tchd og [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 48/163 T IM ER/ COUN TERS (TI ME R 0, TIMER 1 AND TIM ER 2) The uPSD321x Dev ices has three 16-bit Timer/ Counter registers: T imer 0, Timer 1 and T imer 2. All of them can be configured to op erate either as timers or event counters and are compatible with standard 80 32 architecture. In the “Timer” fu nction[...]

49/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 39. Description of the TMOD Bits Bit Sym bol Time r Fu nction 7G a t e Timer 1 Gating co ntrol when set. T imer/Coun ter 1 is ena b led only while INT1 pin is High and TR1 contro l pin is set. When cle ared, Timer 1 is e nabled whenev e r TR1 control bi t i s set 6C / T Time r or Cou nter select or , [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 50/163 Mo de 0. Putting either Timer into Mo de 0 makes it look li ke an 8 048 Timer, wh ich is an 8-bit Counter with a d ivide-by-32 prescaler. Figure 22 sh o ws the Mode 0 operation as it ap pl i es to T imer 1. In this mode, the Timer register is c onfigured as a 13-bit register. A s the count rolls o ver from [...]

51/163 uPSD3212A, uPSD 3212C , uPSD3212CV Mo de 2. Mod e 2 conf igures the T imer register as an 8-bit Count er (TL1) with auto m atic rel oad, as shown in Figure 23 . Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by soft w are. The reload leaves TH1 unchan ged. M ode 2 operation is the same for[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 52/163 Table 41. Timer/C oun ter 2 Oper ating Modes No t e : ↓ = fall i ng ed ge Table 42. D escription of the T2CON Bi ts Note : 1. T he R CLK1 and T C LK1 Bi ts i n th e PCO N Re giste r cont ro l UART 2, and hav e th e same f unct i on as RCLK and TCLK. Mode T2CON T2 MOD DEC N T2CON EXEN P1.1 T2E X Remarks In[...]

53/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figu re 24. Ti m er 2 in Cap t ure M ode Figu re 25 . Tim er 2 in Aut o-R el oa d Mo de AI06625 f OSC TF2 Capture TR2 T2 pin Control TL2 (8 bits) TH2 (8 bits) C/T2 = 0 C/T2 = 1 ÷ 12 EXP2 Control EXEN2 RCAP2L RCAP2H T2EX pin Timer 2 Interrupt Transition Detector AI06626 f OSC TF2 Reload TR2 T2 pin Control T[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 54/163 Mo de 3. Timer 1 in Mode 3 s i m ply holds i t s count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 e s t ablishes TL0 and TH0 a s t wo separate count ers. The logi c for Mode 3 on Timer 0 is shown in Figure 26 . TL 0 uses t h e Timer 0 con- trol Bits: C/T, GAT E, TR0, INT0 , an d TF0. TH0 [...]

55/163 uPSD3212A, uPSD 3212C , uPSD3212CV S TANDAR D SER IAL I NTERFA CE ( UART) The uPSD321x D evices provides two standard 8032 UART s eri al p ort s . The first port is connected to pin P3.0 (RX) and P3.1 (TX). The second port is connected t o pi n P1. 2 (RX) and P1.3(TX). The op- eration of the two serial ports are the same a nd are controlled [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 56/163 S eri al P ort Co nt rol R egi ster The serial port cont rol and status register is the Special Function Register S CON ( SCO N2 for the second port), shown in Figure 27 . This register (see Tables 43 an d 44 ) contains n ot o nly t h e mode selection b it s, bu t also the 9th data bit for transmit and rece[...]

57/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 44. Description of the SCON Bits Bit Sym bol Funct ion 7 SM0 (S M1,SM 0)=(0,0): S hift Regist er . B aud rate = f OSC /12 (SM1,SM 0)=( 1,0): 8-bit UART . Bau d rate = variable (SM1,SM 0)=(0,1): 8 -bit UAR T . Baud rate = f OSC /64 or f OS C /3 2 (SM1,SM 0)=( 1,1): 8-bit UART . Bau d rate = variable 6S[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 58/163 Baud Ra t e s. The baud rate in Mode 0 is fixed: Mode 0 Baud Rat e = f OSC / 12 The baud rat e in Mo de 2 de pends on the value of Bit SMO D = 0 (whi ch is the v al ue on res et ), t he baud rate is 1/64 the oscillator f requ ency. I f SMOD = 1, t h e baud ra te is 1 /32 the oscillator fr eque nc y. Mode 2 [...]

59/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 45. Timer 1-Generated Co m monly Used Baud Rates More A bo ut Mo de 0 . Seria l d at a enters a nd exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received : 8 data bits (LSB f irst) . T he baud rate is f i xed at 1/12 the f OSC . Figure 27 . , page 56 show s a simp l ified func[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 60/163 Figure 28. Seri al Port Mode 0, Wavefo rms More A bo ut Mo de 1 . Ten b its are trans m i t ted (through TxD), or received (through Rx D): a start Bit (0), 8 data bits ( L SB firs t) . an d a St op Bit (1). On receive, the S top Bit goes i nt o RB8 in SCON. In the uPS D321x Devices the baud rate is de t er-[...]

61/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figure 2 9. Seri al Port Mode 1, Block D iagram Figure 30. Seri al Port Mode 1, Wavefo rms AI06826 Zero Detector Internal Bus Tx Control Rx Control Internal Bus SBUF Write to SBUF Read SBUF Load SBUF SBUF Input Shift Register Shift Serial Port Interrupt Rx Clock Start Tx Clock Start Shift Shift Send Load SB[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 62/163 More About Modes 2 and 3. Eleven bits are transmitted (through TxD), or received (t h r o ugh RxD): a Start Bit (0), 8 da ta bits (LSB first), a pro- grammab l e 9th data bit, and a Stop Bit (1). O n transmit, the 9th data bit (TB 8) can be a s sig ned the value of '0' or '1. ' On receiv[...]

63/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figure 3 1. Seri al Port Mode 2, Block D iagram Figure 32. Seri al Port Mode 2, Wavefo rms AI06844 Zero Detector Internal Bus Tx Control Rx Control Internal Bus SBUF Write to SBUF Read SBUF Load SBUF SBUF Input Shift Register Shift Serial Port Interrupt Rx Clock Start Tx Clock Start Shift Shift Send Load SB[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 64/163 Figure 3 3. Seri al Port Mode 3, Block D iagram Figure 34. Seri al Port Mode 3, Wavefo rms AI06846 Zero Detector Internal Bus Tx Control Rx Control Internal Bus SBUF Write to SBUF Read SBUF Load SBUF SBUF Input Shift Register Shift Serial Port Interrupt Rx Clock Start Tx Clock Start Shift Shift Send Load SB[...]

65/163 uPSD3212A, uPSD 3212C , uPSD3212CV ANAL OG- TO -D IG IT A L CO N VER TO R (A DC ) The analo g to digital (A/D) conv erter allows con- version of an analog input t o a corresponding 8-bit digital value. T he A /D mod ule has four analog in- puts, which are multiplexed i nto one sample and hold. The outpu t of t he sam ple and hold is the in- [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 66/163 Table 46. A DC SFR Memory Map Table 47. D escription of th e ACO N Bits Table 48. A DC Clock Inp u t SFR Addr Reg Name Bit R egister Na me Reset Va l u e Com ments 76 5 4 3 2 1 0 95 ASCL 00 8-bit Presca ler f or ADC c lock 9 6 A D AT A D AT 7 A D AT 6 A D AT 5 A D AT 4 A D AT 3 A D AT 2 A D AT 1 A D AT 0 0 [...]

67/163 uPSD3212A, uPSD 3212C , uPSD3212CV PULS E WIDTH MODULA TION ( PWM) The P WM block has the f ol lowing feature s : ■ Four-channe l, 8-bit PW M unit with 16-bit pr es ca ler ■ One-c hanne l, 8-bit unit with programmable freque nc y and pulse width ■ PW M Output with programmable polarity 4-channel PWM Unit (PWM 0-3) The 8-bit counter of [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 68/163 Figu re 3 6. Four- Chann el 8 -bit PWM Block Dia gram AI06647 8-bit PWM0-PWM3 Comparators Registers 8-bit PWM0-PWM3 Comparators 8 8 8-bit Counter x 4 8-bit PWM0-PWM3 Data Registers 8 x 4 Port4.3 Port4.4 Port4.5 Port4.6 Overflow clock load 16-bit Prescaler Register (B2h,B1h) 16 16-bit Prescaler Counter f OSC[...]

69/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 49. PWM SFR Mem ory Map PWMCON Register Bit De f i nition: – PW ML = PW M 0-3 polarity control – PW MP = PW M 4 polarity control – PW ME = PWM enabl e (0 = disabled, 1= enabled ) – C F G3..CFG0 = PWM 0-3 Outp ut (0 = O pen D rain; 1 = Push-Pull) – C F G4 = PWM 4 Output (0 = Open Drain; 1 = P[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 70/163 Prog ramm ab le P e ri od 8- bi t PW M The PW M 4 channel can be programmed to pro- vide a PWM out put with variable pulse width and period. The P WM 4 has a 16-bit Presc al er, an 8- bit Counter, a P ul se Wid th Register, a nd a Period Register. The Pulse Wid t h Regi st er defines t he PWM pulse wid t h [...]

71/163 uPSD3212A, uPSD 3212C , uPSD3212CV PWM 4 Channel Ope ration The 16-bit Prescaler1 d ivi des the input clock (f OS C /2) to the desired freq uency, the result i ng clock runs the 8-bi t Counter of the PWM 4 chan- nel. The input clock frequenc y to the PWM 4 Counter is: f P W M 4 = (f OSC /2)/(Prescaler1 dat a value +1) When the Pres c a l er1[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 72/163 I 2 C IN TER FAC E The serial p ort supports the twin line I 2 C-bus, c on- sisting of a data line (S DA1), and a clock line (SCL1) as shown i n Figure 39 . Depending on the configuration, the SDA 1 a nd S CL 1 l i nes ma y re- quire pull-up resi s tors . These lin es also func t i on as I / O port line s i[...]

73/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 51. Description of the S2CON Bits Table 52. Selection o f the Seri al Clock F req uency SC L in Ma ster Mode Bit Sym bol Funct ion 7C R 2 This bit along with B its CR1and CR0 det ermine s t he serial clock freque ncy when SIO is in the M aster Mode. 6E N I I Enable IIC. When ENI1 = 0, the IIC is d isa[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 74/163 Serial Status Register (S2STA ) S2STA is a “Read-on ly” r e gist e r . Th e contents of this regi s ter may be used as a vector to a service routine. This op t imized the res ponse time o f the software and consequ ently t hat of t he I 2 C bus. T he status cod es for al l possible m odes of the I 2 C b[...]

75/163 uPSD3212A, uPSD 3212C , uPSD3212CV Address Register (S2ADR) This 8-bit register m ay be loaded with t h e 7-bit slave address to which t he controller will respond when programme d as a slave receive/transm itter. The Start/Stop Hold T ime Detection and Sys t em Clock registers (Tables 57 and 58 ) are included in the I 2 C unit to spec i fy [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 76/163 US B HA RDW ARE The charac t eri s tics of US B hardware are as fol- lows : ■ C o mp lies w ith t h e U n iv er s al S erial B us sp ec if ic at i on R e v. 1. 1 ■ Integrat ed SI E (Serial Interface Engine ) , F IFO mem ory and trans ceiver ■ Low s peed (1.5Mbit/s) device capabil i t y ■ Sup ports c[...]

77/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 62. U SB Interrupt E nable Register (UIEN: 0E9h) Table 63. Descri ption of th e UI EN Bits 76543210 SUSPNDI RS TE RST FIE TXD0 IE RXD0IE TXD1 IE EOPIE R ESUMI Bit Sym bol R/W Functi on 7 SUSPNDI R/W En ab le SUS PND Interr upt 6R S T E R / W Enable USB Reset; als o resets th e CPU and PSD Modu les whe[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 78/163 Table 64. U SB Interrupt S tatus Register (UISTA : 0E8h) Table 65. Descri ption of the UISTA Bits 76543210 SUSPND — RST F TXD 0F RXD0F TXD1F EOPF R ESUMF Bit Sym bol R/W Functi on 7S U S P N D R / W USB Su spend Mod e Flag. T o save power, this bit shou ld be set if a 3ms cons tant i dle state is detected[...]

79/163 uPSD3212A, uPSD 3212C , uPSD3212CV Ta bl e 66 . USB Endp oi nt 0 Tra nsmi t Co nt rol Re gist er (U CON0: 0E Ah) Table 67. Descri ption of the UCON0 Bits 76543210 TSEQ0 ST ALL0 TX0 E RX0 E TP0S IZ3 TP0SI Z2 T P0SI Z1 TP0SIZ 0 Bit Sym bol R/W Functi on 7T S E Q 0 R / W Endpoin t0 Da ta Sequen ce Bit. (0=DA T A0, 1=DA T A1) This bit d eterm in[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 80/163 Table 68. USB End point1 (and 2) Transmit Control Register (UCON1: 0EBh) Table 69. Descri ption of the UCON1 Bits 76543210 TSEQ1 EP12SEL TX1 E FRES UM T P1SIZ3 T P1SIZ2 TP1SI Z1 TP1SIZ 0 Bit Sym bol R/W Functi on 7T S E Q 1 R / W Endpoin t 1/ Endpo int 2 T ran smit Data Pack et PID . (0=DA T A0, 1=DA T A 1)[...]

81/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 70. USB Control Reg ister (UCON2: 0ECh) Table 71. Descri ption of the UCON2 Bits Table 72. USB Endpo int0 Status Register (USTA: 0EDh) Table 73. Descri ption of th e US TA Bits Table 74. USB Endpoint0 Data Receive Register (UDR0: 0EFh) Table 75. U SB Endpoin t0 Data Transmit Register (UDT0: 0E7h) Tabl[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 82/163 The USC L 8-bi t P rescaler Register for USB is at E1h. The USCL should be loaded with a value that results in a clock rate of 6 M Hz for the USB using the following f ormula: U SB clock input = (f OSC / 2) / (Prescaler register valu e +1) Where f OS C is the MCU clock input fr equency. Note: US B works ONL[...]

83/163 uPSD3212A, uPSD 3212C , uPSD3212CV Transceiver USB P h ysical Laye r Charac t eristics. The fol- lowing section d escribes the u P SD 321x Devices compliance to t he Chapter 7 Electrical section of the USB S p ecif i c a t io n, Revision 1.1. The section contains al l si g naling, and physical layer spec i f i c a- tions necessary to describ[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 84/163 Table 78. Tran scei ver DC Chara cteristics No t e : 1 . V CC = 5V ± 10 %; V SS = 0 V ; T A = 0 to 70°C. 2. Level gu ara nt ee d for ran ge of V CC = 4.5V to 5.5V . 3. With R PU, e xternal idle r esisto r, 7.5 κ ± 2% , D- to V CC . Table 79. Tran scei ver AC Chara cteristics No t e : 1 . V CC = 5V ± 10[...]

85/163 uPSD3212A, uPSD 3212C , uPSD3212CV Receiver Characteri stics The uP SD321x Device s has a differential input re- ceiver which is able to accept the USB data s i gnal. The receiver features an input se nsit i vity of at l ea s t 200mV when both differential data input s a r e i n the range o f a t leas t 0. 8V to 2.5V with r e s p ect to its [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 86/163 External US B Pull-Up Re sistor The USB system specifies a pull-up resistor on the D- pin fo r low-spee d peripherals. The USB Spec 1. 1 describes a 1.5 k Ω pull-up resistor to a 3.3V supply. An approv ed alternative method is a 7.5k Ω pull-up to the USB V CC s uppl y. This alterna- tive is defined for [...]

87/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figure 44. Differential to EOP T ran sition Skew and EOP Wid th Figure 45. Differential Data Jit te r AI06633 Receiver EOP Width T EOPR1 , T EOPR2 Differential Data Lines Source EOP Width: T EOPT Crossover Point Crossover Point Extended Diff. Data to SE0 Skew N*T PERIOD +T DEOP T PERIOD AI06634 Consecutive [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 88/163 PSD MODU LE ■ The P SD Module provides configurab le Program and Dat a m emories to t h e 8 032 CP U core (MCU). In addition, it has its own s e t of I/ O ports and a PLD with 16 mac rocell s for general logic implemen tation. ■ Ports A ,B,C, and D are general purpose pro grammab le I/O ports that have [...]

89/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figure 46. PSD MODUL E Bloc k Diagram BUS Interface WR_, RD_, PSEN_, ALE, RESET_, A0-A15 D0 – D7 CLKIN (PD1) CLKIN CLKIN PLD INPUT BUS PROG. PORT PORT A PROG. PORT PORT B POWER MANGMT UNIT 512KBIT PRIMARY FLASH MEMORY 8 SECTORS VSTDBY PA0 – PA7 PB0 – PB7 PROG. PORT PORT C PROG. PORT PORT D PC0 – PC7[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 90/163 In-S yst em Progr amming (ISP) Using the JTAG signals on P o rt C, t he entire P SD MODULE dev i ce can be prog ram m ed or erased without the use of the M CU. The primary F lash memory c a n also be programmed i n-s yst em by the MCU executing the program ming algorithms out of t he secondary m emory, or S[...]

91/163 uPSD3212A, uPSD 3212C , uPSD3212CV DEVE LOPMEN T SYSTEM The uPSD3200 is supported by PSDsof t , a Win- dows-based sof t wa re development tool ( W in - dows-95, Wind ows-98, Windows-NT). A PSD MODULE des i gn i s quickly and easily produced in a point and click environment . T he de signer does not need t o ente r Hardware De scri ption Lang[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 92/163 P SD MO DULE RE GISTER D ESCRI PTION AN D ADDRE SS OFFSET Table 81 show s the offset addresses to the P SD MODULE registers rel ative to the CS I OP b ase ad- dress. The CS IOP space is the 256 byt es of ad- dress that is allocate d by the user to the inte r n al PSD MO DULE registers. Table 81 p r o v i de[...]

93/163 uPSD3212A, uPSD 3212C , uPSD3212CV P SD MO DULE DE TAILED OPERATI ON As shown in F i gure 15 . , pa ge 27 , the P SD MOD- ULE consists of five maj or t ypes of functional blo cks: ■ Memo r y Bl ock ■ PLD Bl ocks ■ I/O P o rts ■ Powe r Manage ment Unit (PMU) ■ JTAG Inter f ace The fu nct io ns of each bl o c k are de s crib ed in th[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 94/163 Instructions An instruction con s i s ts of a sequence o f specific operations. E ach received byt e is sequentially de- coded by the P SD MO DULE and not ex ecut ed as a standa r d WRITE operation. T he instru c tion is ex- ecuted when the c orrect number of byte s are prop- erly received and the time betw[...]

95/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 82. Instruction s Note : 1. All bu s cycl es a re WRI TE bus cycle s, ex ce pt the one s with t he “Re ad” l a bel 2. All v al ue s are in hex adec i m al : 3. X = Don’t care. Ad dres se s of the fo rm X X XXh, in t hi s t ab le, mu st be ev en add ress es 4. RA = Ad dre ss of th e memor y loc a[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 96/163 Power -dow n In st ruc tion a nd Pow e r-up Mode P ower- up Mo de. The P SD MODULE i nt e r n al logic is reset upon Po wer-up t o t he RE AD M ode. Sector Select (FS0-FS3 and CSBOOT0- CSBOOT 1) must be h eld Low, and WRITE Strobe (WR , CNTL0) H i gh, during Power-up for maximum security of t h e da ta cont[...]

97/163 uPSD3212A, uPSD 3212C , uPSD3212CV Toggl e Fl ag ( DQ6 ). The Flash m emory offers an- other way for determining when the P r ogram cycle is completed. Du ring the i nternal WRITE operation and when either the FS0-FS3 or CSBOO T 0- CSBOOT 1 is t rue, the Toggle Fla g Bit (DQ6) tog- gles from 0 to 1 and 1 to 0 on subsequent at tempts to read [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 98/163 Progr amming F lash Memor y Flash memory m ust be erased prior to being pro- grammed . A byte of Flash m emory is erased to a ll '1s' (FFh), and is program m ed by s etting s elected bits to '0.' T he MC U may e rase F lash memory a ll at once o r by-sector, but n ot byt e-by-byte. Howev[...]

99/163 uPSD3212A, uPSD 3212C , uPSD3212CV Da t a To gg le . Ch ecking the To ggl e F lag Bit (DQ6) is a method of determinin g whether a P ro- gram or Er ase cy cl e i s in progress or has comple t - ed. F i gure 49 s h ows the Data Toggle alg ori t h m . When th e MCU issue s a Program instruction, the embedded algorithm begins. The MCU t hen read[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 100/163 Erasing Flash Memo ry Flash Bulk Erase. The Flash B ulk E rase instruc- tion uses six WRITE operations followed by a READ operation of t he st atus register, as de- scribed in Table 82. If any byte of the Bulk Erase instruction is wrong, t he Bulk Erase instruction aborts and the d evice is reset to the RE[...]

101/163 uPSD3212A, uPSD 3212C , uPSD3212CV Specific Features Flash M emory Secto r Protect. Each primary and seconda r y F l ash m emory sector can b e sepa- rately protected against Program and E rase c y - cles. Sector P r o t ect i on provi des additional data security because it disables all P r o gram or Erase cycles. This mod e can be activat[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 102/163 SRA M The S RA M is enab l ed when SRAM S el e c t (RS0) from t he DPLD is High. SRAM Select (RS0) can contain up to two prod uct t erms , all ow i ng f l exib l e mem or y ma p ping . The SRAM c a n be backed up usin g an ext e r n al battery. The ex ternal battery shoul d be connect ed to Voltage S t an [...]

103/163 uPSD3212A, uPSD 3212C , uPSD3212CV Mem ory Se l e ct Conf igura tion in Pro gram an d Data Sp aces. The MCU Core has separate ad- dress spaces for Program memory and Data memory. Any of the memories wi t hin t he PSD MODULE c an reside in either sp ace or both spac- es. This is controlled through m an ipul a t io n of the VM Regist er that [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 104/163 Sepa rate S pace Mode . Program space is s epa- rated from Data spac e. For example, Program Se- le ct Enabl e (PSEN ) is u s ed to ac cess the program code from the p r ima r y Flash mem ory, while READ Strobe (RD ) i s used to access d at a from the s ec- ondary Flash memory, SRAM and I/O Port blocks. Th[...]

105/163 uPSD3212A, uPSD 3212C , uPSD3212CV Page R egi st e r The 8-bit Page Register increases the addres sing capability of the MCU Core by a factor of up to 256. The conte nt s o f the registe r can also be rea d by the MCU. T he outputs of the P age Register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in t h e Sector S elect ([...]

uPSD3212A, uPSD 3212C , uPSD3212CV 106/163 PLD S The PLDs bring program mable logic func t i onal i t y to the uPS D. After specifying t h e logic for the PLDs in PSDs oft E xpress, the logic is pro- grammed i nto the device and available upo n Pow- er-up. Tab le 87. D PLD and C P LD I npu ts Note : 1. T hes e input s are no t av ai l a ble in t he[...]

107/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figu re 54. P LD D ia gra m Note : 1. Po rts A is no t availa ble in t he 52 -pin pac kage PLD INPUT BUS 8 INPUT MACROCELL & INPUT PORTS DIRECT MACROCELL INPUT TO MCU DATA BUS CSIOP SELECT SRAM SELECT SECONDARY NON-VOLATILE MEMORY SELECTS DECODE PLD PAGE REGISTER PERIPHERAL SELECTS CPLD PT ALLOC. MACRO[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 108/163 Decode PLD ( DP LD) The DPLD, shown i n Figure 55 , i s u s e d for decod- ing the a ddress for P S D MODULE and external component s . The DPLD can be used to generat e the following decode signals: – 4 Se cto r Se l ect (FS0-F S3 ) si gnals for th e prima ry Flash memory (three product terms eac h) –[...]

109/163 uPSD3212A, uPSD 3212C , uPSD3212CV Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable coun ters and shift reg- isters, system m ail bo x e s , ha ndshaking protocol s , state machines, and random logic. Th e CPLD can also be us ed to generate E xt e rnal Chip Sele c t (ECS1-ECS2), routed to Port D.[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 110/163 Outp ut Ma croce ll (OMC ) Eight of the Output Macrocells (OM C) are con- nected t o Ports A and B pins an d are named as McellAB0 - Mcell A B 7. The ot h er eight m acrocells are connected t o P o r ts B and C pins and are named a s McellBC0-Mcel lBC7. If an M cell AB ou t - put is not assign ed t o a spe[...]

111/163 uPSD3212A, uPSD 3212C , uPSD3212CV Prod uct Term Al lo c at or The CPLD has a Product Term Allocator. PSDsoft uses the P roduct Term A l l ocat or t o borrow and place product terms from one macr ocell to anoth- er. The following list summarizes how product terms are al located: – M c ellAB0-M c ellAB7 all have three native produc t terms[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 112/163 The OMC Mask Register. Th er e is one Ma sk Register for each of t h e two groups of eight Output Macrocells (OMC ) . T he Mask Registers can be used to block the loading of data to individual Ou t - put Macrocell s ( O MC). The default value for the Mask Registers is 00h , which allows loading o f the Out[...]

113/163 uPSD3212A, uPSD 3212C , uPSD3212CV I/ O PO RTS ( PSD MOD ULE ) There are four programm abl e I / O p ort s: P orts A, B , C, and D in the PSD MODULE. Eac h of th e ports is eight bits except Port D, which is 3 bits. Each port pin is i n dividually user configurable, thus al- lowing multiple functions per port . T he ports are configured usi[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 114/163 The Port pin’s tri-state output drive r en abl e i s con- trolled by a two input O R gate whose inputs c ome from the CP L D AND Array ena ble product term and the Direction Re gist e r . I f the ena ble product term of an y of the Array out puts are not d ef ined and that port pin i s no t defined as a [...]

115/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figu re 60 . Pe riphera l I/O Mode Table 89. Port O perating Mo d es N ote: 1. JT AG p ins ( TMS, TC K, TD I, T DO) are ded ica te d pi ns. 2. P or t A is no t av ai l a b l e i n th e 52- pin pac ka ge . 3. On pin s PC2, PC3 , PC4 and P C 7 only. Table 90. Port Operating Mode Settings Note: N/A = N o t Ap[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 116/163 Port C onf i gu ra t i on Re g ist e rs (PCR) Each Port has a set of Port Con f iguration Regis- ters (PCR) used for conf i guration. The contents of the registers can be accessed by the M CU through normal READ/WRITE bus cycles at the addresses given in Tabl e 81., page 92 . The addresses i n Ta- ble 81 a[...]

117/163 uPSD3212A, uPSD 3212C , uPSD3212CV Port Data Re gisters The Port Data Registers, s h own in Table 97 , a re used by the MCU t o write data to or read data from the ports. T abl e 97 shows the regi st er name, the ports having eac h reg ister type, a nd M CU a ccess for each register type. The registers are described below. Data In. Port pin[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 118/163 Ports A and B – F unctionality and Structure Ports A and B have similar funct i onalit y and struc- ture, as s hown i n Figure 61 . The two ports can be configured to perform one or m ore of the following functions: ■ MCU I/O Mode ■ C P LD O ut pu t – Mac rocells Mc el l AB7- Mcell AB0 can be conne[...]

119/163 uPSD3212A, uPSD 3212C , uPSD3212CV Port C – F u nction ality and Stru cture Port C can be co nf igured to perform one or more of the foll owing functi ons (see Figure 62 ): ■ MCU I/O Mode ■ C P LD Outpu t – Mcell B C7-McellBC0 ou tputs can be connected to Port B o r Port C. ■ C PLD Input – via t h e Input Macroc ells (IMC) ■ I[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 120/163 Port D – F u nction ality and Stru cture Port D has tw o I/O pi ns (only o ne pin, PD1 , in t he 52-pin package ) . S ee F ig ure 63 and Figure 64., page 121 . This port does not s upport Address Out Mode, a nd t h eref ore no Cont rol Register is re- quired. Of the ei ght bits in the Port D registers, o[...]

121/163 uPSD3212A, uPSD 3212C , uPSD3212CV External Chip Select The CPLD al so provides tw o External Chip Sele c t (ECS1-ECS2) ou tputs on P ort D pins t hat can be used to select external devices. Eac h External Chip Select (ECS1-E CS2) consists of one produ c t term that can be configured ac t iv e Hi gh or Low. The output enable of the pin is c[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 122/163 POW E R MANA GE MEN T All PSD MODULE offers configurable power sav- ing options. These options may be used individu- ally or i n com bina tions , as foll ows: – T he primary and seconda ry Flash m emory, and SRAM blocks are built with po wer mana gem ent technology. In addition to using spe cial silicon [...]

123/163 uPSD3212A, uPSD 3212C , uPSD3212CV The PSD M ODULE has a Turbo Bit in PM M R0. This bit c an b e set to turn the Tu rbo Mode off (the default is with Turbo Mode turned on). W hil e T urbo Mode is off, the PLDs can achieve standby current when no P LD i np ut s a r e changing (zero DC cur- rent). Even when inputs do change, significant power[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 124/163 PL D Po we r M ana ge m en t The power and spee d of t he P LDs are controlled by the Turbo Bit (Bit 3) i n PMMR 0 (see Table 99 ). By setting the bit to '1,' the Turbo Mode is off and the PLDs consum e t h e s p ecified standby current when the inputs are not switching for an extended time of 70[...]

125/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 100. Power Mana gemen t Mode Regi sters PMM R2 Not e: The bits of t his reg ister a re clear ed to z ero fol lowing Power-u p. Subs e quent R ESET p ulses do not cle ar t he r egist ers. Table 101. APD Counter Oper ation Bit 0 X 0 Not u sed, and s hould be se t to zero . Bit 1 X 0 Not u sed, and s ho[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 126/163 RESE T T IMING AND D EVICE ST ATUS A T RES ET Upon Power-up, the P SD MODULE requi res a Re- s e t (RE SET ) pulse of du ration t NLNH-PO after V CC is steady. During this period, t h e device loads in- ternal configurations, clears some of the reg isters and sets the Flash mem ory into operating mode. Aft[...]

127/163 uPSD3212A, uPSD 3212C , uPSD3212CV P ROGRA MMING IN- CIRCU IT USIN G THE JTA G SER IA L INT ERF ACE The JTAG S eri al Interfa c e pi ns (TM S, TCK, TDI, TDO) are dedicated pins on P ort C (see Tab le 103 ). All memory bl o c ks (pri m ary and secondary Flash memory), PLD logic, and PSD MODULE Configuration Regi st er Bits may be programmed [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 128/163 AC/D C PAR AMET E RS These tables describe the A D an d DC p aram eters of the uPSD32 1x D evices: ➜ DC Electrical Specification ➜ AC Timing S pecification ■ PLD T iming – Com bin at ori al T im ing – Synchronou s Clock Mode – Async hronous Clock Mode – Input M acrocell T iming ■ MCU M odul[...]

129/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 104. PSD MODULE Exam ple, Typ. Power Cal culation at V CC = 5.0V (Turbo Mode Off) Condit ions MCU Clock Frequency = 12 MHz Highes t Com posite PLD input freq uency (F req PL D) = 8MHz MCU A LE frequen cy (Freq ALE) = 2M Hz % Flash m emor y Acc ess = 80 % % SRAM a ccess = 15 % % I/O acce ss = 5% (no a[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 130/163 MAXI MU M RAT IN G Stressing th e de vice above the rating listed in the Absolute M aximum Ra t ings” t abl e may cause per- manent dam age to t h e device. These a re stress ratings only and operation of the device at t hese or any other con ditions ab ove those i ndicated in t he Operating s e c tions [...]

131/163 uPSD3212A, uPSD 3212C , uPSD3212CV E M C C HARAC TERIST ICS Su scep tibilit y tes t ar e perf orm ed o n a sampl e ba - sis during p roduct charac t erization. Func ti ona l EMS (El ec tro magn etic Susceptibility) Based on a sim pl e running appli cat ion on the product (toggling 2 L E Ds t hrough I/O ports), the product is stressed by two[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 132/163 LU. 3 com plement ary s tat ic t ests are req uired on 10 parts to assess th e l at ch-up performance. A supply overvoltage (applied to each pow er supply pin) and a current injection (appl ied to eac h in put, output, and c onfigurable I /O pi n) are performed on each sam ple. This test c onforms t o the [...]

133/163 uPSD3212A, uPSD 3212C , uPSD3212CV DC AN D A C PARAM ETERS This section sum marizes the operating and mea- surement condition s , and the DC a nd AC charac- teri st ics of the de v ice . The parameters in the DC and AC Charact eri stic t abl es t ha t f ol lo w are de- rived from tests performed under the Measure- ment Conditions sum marize[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 134/163 Figure 7 0. Swit ch ing W avefo rms – Key WAVEFORMS INPUTS OUTPUTS STEADY INPUT MAY CHANGE FROM HI TO LO MAY CHANGE FROM LO TO HI DON'T CARE OUTPUTS ONLY STEADY OUTPUT WILL BE CHANGING FROM HI TO LO WILL BE CHANGING LO TO HI CHANGING, STATE UNKNOWN CENTER LINE IS TRI-STATE AI03102 www.BDTIC.com/ST[...]

135/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 113. Major Para m eters Parameters/Co nditions/ Comment s 5V T e st Conditio ns 5.0V V alu e 3.3V T est Condi tions 3.3V Value Un it Operatin g V oltag e – 4.5 to 5.5 – 3.0 to 3 .6 V Operatin g T emperat ure – –40 to 85 – –40 to 85 °C MCU Freq uency 12MHz (m in) for USB; 8MHz (mi n) for [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 136/163 Table 114. DC Characteristics (5V Devices ) Symbol Paramet er T est Condi tion (in additi on to those in Tabl e 109., page 133 ) Min. T yp. Max. Unit V IH Input H igh V oltage (Ports 1, 2, 3, 4[Bit s 7,6, 5,4,3,1,0], XT AL1 , RESET ) 4.5 V < V CC < 5.5V 0.7V CC V CC + 0.5 V V IH1 Input H igh V oltage[...]

137/163 uPSD3212A, uPSD 3212C , uPSD3212CV No t e : 1 . I PD (Power- down Mo de) is meas ured with : 2. XTAL 1=V SS ; XT AL 2=n ot co nne cted ; RESET =V CC ; P ort 0 = V CC ; a ll ot he r pin s ar e di s conne cted. P LD not in Tur bo Mod e. 3. I CC_CPU (act iv e m o de) is m eas ured w i th : 4. XTAL 1 driven w ith t CLCH , t CHCL = 5ns, V IL = V[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 138/163 Table 115. DC Characteristics (3V Devices ) Symbol Parameter T est Co ndition (in addition to those in Tab l e 110., pa ge 1 33 ) Min. Typ. M ax. Unit V IH Input Hig h V oltage (P or ts 1, 2, 3, 4[Bits 7,6,5,4,3,1 ,0], A, B, C, D , XT AL 1, RESET ) 3.0V < V CC < 3.6V 0.7V CC V CC + 0.5 V V IH1 Input [...]

139/163 uPSD3212A, uPSD 3212C , uPSD3212CV No t e : 1 . I PD (Power- down Mo de) is meas ured with : 2. XTAL 1=V SS ; XT AL 2=n ot co nne cted ; RESET =V CC ; P ort 0 = V CC ; a ll ot he r pin s ar e di s conne cted. P LD not in Tur bo mod e. 3. I CC_CPU (act iv e m o de) is m eas ured w i th : 4. XTAL 1 driven w ith t CLCH , t CHCL = 5ns, V IL = V[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 140/163 Figu re 71 . Ext ern al Prog ram Me m ory R EA D Cycle Table 116. External Progr am Memo ry AC Ch arac t e ristics (with t h e 5V MCU Modu le) Note : 1. Con diti ons (in ad dition t o those i n Table 109 ., pa ge 133 , V CC = 4. 5 to 5.5V): V SS = 0V ; C L for Port 0, ALE a nd PSEN outpu t is 1 00pF; C L f[...]

141/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 117. External Progr am Memo ry AC Ch arac t e ristics (with t h e 3V MCU Modu le) Note : 1. Con diti ons (in ad dition t o those i n Table 110 ., pa ge 133 , V CC = 3. 0 to 3.6V): V SS = 0V ; C L for Port 0, ALE a nd PSEN outpu t is 1 00pF, for 5V dev ices, an d 50pF for 3V d ev ices; C L f o r ot he[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 142/163 Figure 7 2. External Data M e mory READ Cycle Table 118. External Clock Drive (with the 5V MCU Module) Note : 1. Con diti ons (in ad dition t o those i n Table 109 ., pa ge 133 , V CC = 4. 5 to 5.5V): V SS = 0V ; C L for Port 0, ALE a nd PSEN outpu t is 1 00pF; C L for othe r outpu ts is 80 pF Table 119. E[...]

143/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figu re 73 . Exte rn al Dat a Me mory WRI TE Cycl e Table 120. External Data Memo ry AC Charac teristics (wit h the 5V MCU Module) Note : 1. Con diti ons (in ad dition t o those i n Table 109 ., pa ge 133 , V CC = 4. 5 to 5.5V): V SS = 0V ; C L for Port 0, ALE a nd PSEN outpu t is 1 00pF; C L for othe r ou[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 144/163 Table 121. External Data Memo ry AC Charac teristics (wit h the 3V MCU Module) Note : 1. Con diti ons (in ad dition t o those i n Table 110 ., pa ge 133 , V CC = 3. 0 to 3.6V): V SS = 0V ; C L for Port 0, ALE a nd PSEN outpu t is 1 00pF, for 5V dev ices, an d 50pF for 3V d ev ices; C L f o r ot he r outp u[...]

145/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figu re 7 4. Inpu t to Outpu t Di sable / Ena ble Table 123. CPLD Combinatorial Timing (5V Devices) Note : 1. F as t Slew Rat e ou tput ava ilable o n PA3-P A0, P B3 -PB0, and PD2-P D 1. Decr emen t t i m es b y given a mount 2. t PD fo r MCU a ddress an d cont rol signa ls refe rs to de lay from pins o n [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 146/163 Figu re 75 . Sy nch ronou s Clo ck Mo de Ti m i ng – P LD Table 125. CPLD Macroce ll Synchronous Cl ock Mod e Timing (5V Devices) Note : 1. F as t Slew Rat e ou tput ava ilable o n PA3-P A0, P B3 -PB0, and PD2-P D 1. Decr emen t t i m es b y given a mount. 2. CL KIN (P D1) t CLCL = t CH + t CL . Symb ol [...]

147/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 126. CPLD Macroce ll Synchronous Cl ock Mod e Timing (3V Devices) Note : 1. F as t Slew Rat e ou tput ava ilable o n PA3-P A0, P B3 -PB0, and PD2-P D 1. Decr emen t t i m es b y given a mount. 2. CL KIN (P D1) t CLCL = t CH + t CL . Fig ur e 76. Asynch ro n ou s RESET / Preset Figu re 7 7. Asy nchr o[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 148/163 Table 127. CPLD Macroce ll Asynchron ous Clock Mo de Timing (5V Devices ) Table 128. CPLD Macroce ll Asynchron ous Clock Mo de Timing (3V Devices ) Symb ol P ara meter Co nditions Min Max PT Alo c Tu r b o Off Slew Rate Unit f M AXA Maximum Frequency Exter nal Feedback 1/(t SA +t COA ) 38.4 MHz Maximum Fre[...]

149/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figu re 7 8. Inpu t Ma crocel l Tim ing ( Produc t Ter m Cl ock ) Table 129. Input Macro cel l Timing (5V Devices ) Note : 1. In puts fro m Po rt A, B, an d C rel at ive to re giste r/ la tch cl oc k from t he P LD. ALE/ AS la tc h t imings refer to t AVLX an d t LX AX . Table 130. Input Macro cel l Timing[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 150/163 Table 131. Program, WRITE and Erase Time s (5V Devices) Note : 1. Pr ogr amme d to all zer o befo re er ase. 2. The po lling s tatus, DQ 7, is vali d t Q7VQV t ime uni ts befor e the data b yte, DQ 0 -DQ7, i s valid f or r e ading . Table 132. Program, WRITE and Erase Time s (3V Devices) Note : 1. Pr ogr a[...]

151/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figu re 7 9. Pe ripher al I/O READ Tim ing Table 133. Port A Peripheral Da ta Mode READ T i ming (5V Devices) N ote: 1. Any in put us ed to s elec t Por t A Dat a Pe ri pher al Mode . 2. Data i s a lread y st able on P ort A. Table 134. Port A Peripheral Da ta Mode READ T i ming (3V Devices) N ote: 1. Any [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 152/163 Figu re 80 . Pe riphera l I/O WRIT E T i ming Table 135. Port A Peripheral Data Mod e WRITE T i ming (5V Devices) Note : 1. Dat a stabl e on Port 0 pi ns to dat a on P or t A. Table 136. Port A Peripheral Data Mod e WRITE T i ming (3V Devices) Note : 1. Dat a stabl e on Port 0 pi ns to dat a on P or t A. S[...]

153/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figure 81. Reset (RESET ) Timing Table 137. Reset (R ESET ) Timi n g (5V Devices) No te : 1. Reset (R ESET ) d oes no t reset Fl as h memo ry Prog ram or Er as e cycl es. Table 138. Reset (R ESET ) Timi n g (3V Devices) No te : 1. Reset (R ESET ) d oes no t reset Fl as h memo ry Prog ram or Er as e cycl es[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 154/163 Figu re 82 . ISC Ti m i ng Table 141. ISC Timing (5V Devices) Note : 1. F or no n-PL D Pro gra mmi ng, Erase or in ISC By -pa ss Mod e. 2. Fo r P rog ram or Eras e PLD o nl y. Symb ol Parame ter C onditions M in Max Unit t ISCCF C lock (TCK, PC 1) F reque ncy (except for PLD) (Note 1) 20 MHz t ISCCH C lock[...]

155/163 uPSD3212A, uPSD 3212C , uPSD3212CV Table 142. ISC Timing (3V Devices) Note : 1. F or no n-PL D Pro gra mmi ng, Erase or in ISC By -pa ss Mod e. 2. Fo r P rog ram or Eras e PLD o nl y. Figure 8 3. MCU Module AC Meas u rement I/O Waveform N ot e: AC inp u ts du r ing t es ti n g ar e dr i ve n at V CC –0.5V f or a log i c '1, ' an[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 156/163 Figure 85. Extern al Clock Cycle Figu re 86. Re co mme nd e d Os cillat or C ir cui t s Note : C1, C2 = 30 pF ± 10pF fo r cryst al s Fo r ce ram ic re sonat ors, co ntac t re sona to r manu fa ct urer Oscillation circuit is designed to be used either wit h a cera mic resonator or crystal o scillat or. Sin[...]

157/163 uPSD3212A, uPSD 3212C , uPSD3212CV P ACK AGE ME CHANI CAL INFO RMAT ION Figure 89. TQFP52 – 52-le ad Plastic Thin, Quad, Flat Package Outline No te : D rawi ng is not to scale. QFP-A Nd E1 CP b e A2 A N L A1 α D1 D 1 E Ne c D2 E2 L1 www.BDTIC.com/ST[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 158/163 Table 144. TQFP52 – 52-lead Plastic Thi n , Quad, Flat Package Mechanical Data Symb mm in ches Ty p M i n M a x Ty p M i n M a x A – –1 . 7 5– – 0 . 0 6 9 A1 – 0.05 0.02 0 – 0. 002 0.008 A2 – 1.25 1.5 5 – 0. 049 0.061 b – 0.02 0.0 4 – 0. 007 0.016 c – 0.07 0.2 3 – 0. 002 0.009 D 1[...]

159/163 uPSD3212A, uPSD 3212C , uPSD3212CV Figure 90. TQFP80 – 80-le ad Plastic Thin, Quad, Flat Package Outline No te : D rawi ng is not to scale. QFP-A Nd E1 CP b e A2 A N L A1 α D1 D 1 E Ne c D2 E2 L1 www.BDTIC.com/ST[...]

uPSD3212A, uPSD 3212C , uPSD3212CV 160/163 Table 145. TQFP80 – 80-lead Plastic Thi n , Quad, Flat Package Mechanical Data Symb mm in ches Ty p M i n M a x Ty p M i n M a x A – –1 . 6 0– – 0 . 0 6 3 A1 – 0.05 0.1 5 – 0. 002 0.006 A2 1.40 1.35 1.4 5 0.0 55 0.053 0.057 b 0.22 0.17 0.2 7 0.0 09 0. 007 0 .011 c – 0.09 0.2 0 – 0. 004 0.[...]

161/163 uPSD3212A, uPSD 3212C , uPSD3212CV P ART N UMBER ING Table 146. Orderi ng Infor mation Sc heme For other options, or for mo re information on any aspe ct of this device, please con tact the ST Sales O f fice nearest you. Example: uPSD 3 2 1 2 C V – 24 U 6 T Device T ype uPSD = M icrocontrolle r PSD Fam i ly 3 = 8032 c ore PLD Size 2 = 16 [...]

uPSD3212A, uPSD 3212C , uPSD3212CV 162/163 REVI SION HIST ORY Table 147. Document Revision History Date Ver sion Revision De tails 18-Dec-20 02 1 .0 First Issu e 04-Mar-0 3 1 .1 Updates : por t informa tion (T a b le 30 ); interf ace in f orma tion (Figur e 30 , T ab le 44 ); r e mo ve programming guide; PS D Module inf ormation (T able 82 ); PLD i[...]

163/163 uPSD3212A, uPSD 3212C , uPSD3212CV Information fur nished is bel ieved to be accurate and reliable. However, S TMicroelectronics assumes no re sponsibility for the co nseq uen c es of u se of such infor mati on no r for any i nfri ngemen t of p atent s or o ther rig hts of thir d par t ie s wh ich m ay result from i ts u se. No lic ense is [...]