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Texas Instruments TMS320C6201 manual

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Índice de manuales de instrucciones

  • Página 1

    TMS320C6201 Digital Signal Processor Silicon Errata SPRZ153 November 2000 Copyright  2000, T exas Instruments Incorporated[...]

  • Página 2

    SPRZ153 TMS320C6201 Silicon Errata 2 Contents 1 Introduction 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Quality and Reliability Conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

  • Página 3

    SPRZ153 TMS320C6201 Silicon Errata 3 Advisory 2.1.19 PMEMC: Branch from External to Internal 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advisory 2.1.21 DMA: DMA Data Block Corrupted After Start Zero T ransfer Count 23 . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Silicon Revision 2.0 Kno[...]

  • Página 4

    SPRZ153 TMS320C6201 Silicon Errata 4 1 Introduction This document describes the silicon updates to the functional specifications for the TMS320C6201 silicon releases 3.1, 3.0, 2.1, and 2.0. 1.1 Quality and Reliability Conditions TMX Definition T exas Instruments (TI) does not warranty either (1) electrical performance to specification, or (2) produ[...]

  • Página 5

    SPRZ153 TMS320C6201 Silicon Errata 5 1.2 Revision Identification The device revision can be determined by the lot trace code marked on the top of the package. The location for the lot trace codes for the GJL package is shown in Figure 1 and the revision numbers are listed in T able 1. Figure 1. Example, Lot T race Code for TMS320C6201 DSP TMS320C62[...]

  • Página 6

    SPRZ153 TMS320C6201 Silicon Errata 6 2 Changes to the TMS320C6201 Data Sheet (literature number SPRS051) T able 2. Timing Requirements for Interrupt Response Cycles NO C6201B UNIT NO. MIN MAX UNIT 4 t d(CKO2L-IACKV) Delay time, CLKOUT2 low to IACK valid – 4 6 ns 5 t d(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid 6 ns 6 t d(CKO2L-INUMIV) De[...]

  • Página 7

    SPRZ153 TMS320C6201 Silicon Errata 7 Figure 3. SBSRAM Write T iming (1/2 Rate SSCLK) (See Note) BE1 BE2 BE3 BE4 A1 A2 A3 A4 Q1 Q2 Q3 Q4 16 15 10 9 14 13 6 5 4 3 2 1 SSCLK BE_ [3:0] EA [21:2] ED [31:0] CE SSADS SSOE SSWE NOTE: The CEx output setup and hold times are specified to be accurate relative to the clock cycle to which they are referenced, s[...]

  • Página 8

    SPRZ153 TMS320C6201 Silicon Errata 8 3 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications Issues When Pausing at a Block Boundary Advisory 3.1.1 Revision(s) Affected : 3.1, 3.0, 2.1, and 2.0 Details : The following problems exist when a DMA channel is paused at a block boundary: • DMA does not flush internal FIFO when a cha[...]

  • Página 9

    SPRZ153 TMS320C6201 Silicon Errata 9 DMA Multiframe Split-mode T ransfers Source Address Indexing Not Functional Advisory 3.1.3 Revision(s) Affected : 3.1, 3.0, 2.1, and 2.0 Details : If a DMA channel is configured to do a multiframe split-mode transfer with SRC_DIR = Index (1 1b), the source address is always modified using the Element Index, even[...]

  • Página 10

    SPRZ153 TMS320C6201 Silicon Errata 10 DMA Paused During Emulation Halt Advisory 3.1.6 Revision(s) Affected : 3.1, 3.0, 2.1, and 2.0 Details : When running an autoinitialized transfer , the DMA write state machine is halted during an emulation halt regardless of the value of EMOD in the DMA Channel Primary Control Register . The read state machine f[...]

  • Página 11

    SPRZ153 TMS320C6201 Silicon Errata 11 Alternative: If a 64M-bit SDRAM is located in CE3, avoid using the last 1K byte in the CE3 memory map (0x03FFFC00). Cache During Emulation With Extremely Slow External Memory Advisory 3.1.9 Revision(s) Affected : 3.1, 3.0, 2.1, and 2.0 Details : If a program requests fetch packet “ A ” followed immediately [...]

  • Página 12

    SPRZ153 TMS320C6201 Silicon Errata 12 4 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz Advisory 3.0.8 Revision(s) Affected : 3.0, 2.1, and 2.0 Details : A speedpath in the device causes SDCLK and SSCLK to start up 180 degrees out-of-phase (effectively inverted) from t[...]

  • Página 13

    SPRZ153 TMS320C6201 Silicon Errata 13 EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz (Continued) 2 . On SBSRAM/SDRAM reads, data will be sampled on the falling edge before the rising edge that would be expected. In this case, the input setup time for data at the C62x t is reduced by 1 CPU cycle. Note that this case can be compounded with Ca[...]

  • Página 14

    SPRZ153 TMS320C6201 Silicon Errata 14 EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz (Continued) Alternate Workaround : The following alternate workarounds can help for certain board and layout configurations. • Using faster (125 MHz or PC100) SDRAMs and/or SBSRAMs will reduce the chances of data corruption and/or increase the frequency a[...]

  • Página 15

    SPRZ153 TMS320C6201 Silicon Errata 15 5 Silicon Revision 2.1 Known Design Exceptions to Functional Specifications EMIF: CE Space Crossing on Continuous Request Not Allowed Advisory 2.1.1 Revision(s) Affected : 2.1 and 2.0 Details : Any continuous request of the EMIF cannot cross CE address space boundaries. This condition can result in bad data rea[...]

  • Página 16

    SPRZ153 TMS320C6201 Silicon Errata 16 EMIF: SDRAM Invalid Access (Continued) Workaround : Avoid use of multiple CE spaces of SDRAM within a single refresh period. DMA: RSYNC Cleared Late for Frame-synchronized T ransfer Advisory 2.1.4 Revision(s) Affected : 2.1 and 2.0 In a frame-synchronized transfer , RSYNC is only cleared after the beginning of [...]

  • Página 17

    SPRZ153 TMS320C6201 Silicon Errata 17 McBSP: DXR to XSR Copy Not Generated (Continued) Example: Configure the DMA as follows: (a) For half-word/byte-size accesses with right justification on receive data: – ch_A: /* for transmit */ src_address = mem_out; dst_address = DXR; Element_size = WORDAddress_inc_mode = indexIndex_reg_value = 2 /* change t[...]

  • Página 18

    SPRZ153 TMS320C6201 Silicon Errata 18 McBSP: DXR to XSR Copy Not Generated (Continued) (c) For byte-size writes with right justification on receive data: – ch_A: /* for transmit */ dst_address = DXR+3; /* 0x018C0007 for McBSP0 or 0x01900007 for McBSP1 */ Element_size = WORDAddress_inc_mode = indexIndex_reg_value = 1 – ch_B : /* for receive */ s[...]

  • Página 19

    SPRZ153 TMS320C6201 Silicon Errata 19 DMA Channel 0 Multiframe Split-Mode Incompletion Advisory 2.1.7 Revision(s) Affected : 2.1 and 2.0 Details : If DMA Channel 0 is configured to perform a multiframe split-mode transfer , it is possible for the last element of the last frame of the Receive Read to not be transferred. After the last element of the[...]

  • Página 20

    SPRZ153 TMS320C6201 Silicon Errata 20 McBSP: Incorrect m Law Companding V alue Advisory 2.1.1 1 Revision(s) Affected : 2.1 and 2.0 Details : T he C6201 McBSP m -Law/A-Law companding hardware produces an incorrectly expanded m -Law value. McBSP receives m -Law value 01 1 1 1 1 1 1, representing a mid-scale analog value. Expanded 16-bit data is 1000 [...]

  • Página 21

    SPRZ153 TMS320C6201 Silicon Errata 21 EMIF: HOLD Request Causes Problems With SDRAM Refresh Advisory 2.1.14 Revision(s) Affected : 2.1 and 2.0 Details : If the HOLD interface is used in a system with SDRAM, there are some situations that are likely to occur . If the NOHOLD bit is not set and an external requester attempts to gain control of the bus[...]

  • Página 22

    SPRZ153 TMS320C6201 Silicon Errata 22 DMA Split-mode Receive T ransfer Incomplete After Pause Advisory 2.1.16 Revision(s) Affected : 2.1 and 2.0 Details : If the DMA is performing a split-mode transfer and the channel is paused after all T ransmit Reads in a frame are completed but before the Receive Reads are completed, then the Receive T ransfer [...]

  • Página 23

    SPRZ153 TMS320C6201 Silicon Errata 23 PMEMC: Branch from External to Internal Advisory 2.1.19 Revision(s) Affected : 2.1 and 2.0 Details : The program flow is corrupted after branching from external memory to internal program memory when the following are true: • CPU is executing from external memory • A CPU stall occurs that holds the CPU unti[...]

  • Página 24

    SPRZ153 TMS320C6201 Silicon Errata 24 6 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications Program Fetch: Cache Modes Not Functional Advisory 2.0.1 Revision(s) Affected : 2.0 Workaround : Use internal program memory in mapped mode. Bootload: Boot from 16-Bit and 32-Bit Asynchronous ROMs Not Functional Advisory 2.0.2 Revision([...]

  • Página 25

    SPRZ153 TMS320C6201 Silicon Errata 25 Data Access: Parallel Accesses to EMIF or Internal Peripheral Bus Location Sequenced Wrong Advisory 2.0.5 Revision(s) Affected : 2.0 Details : Parallel read and write accesses to the same EMIF or internal peripheral bus location are sequenced incorrectly when: • A load and store are in the same execute packet[...]

  • Página 26

    SPRZ153 TMS320C6201 Silicon Errata 26 McBSP New Block Interrupt Does Not Occur for Start of Block 0 Advisory 2.0.9 Revision(s) Affected : 2.0 Details : When end-of-block interrupt is selected ((R/X)INTM=01b), McBSP new block interrupt does not occur at end of frame (i.e., before block 0). (Internal reference number 4357) Workaround : This interrupt[...]

  • Página 27

    SPRZ153 TMS320C6201 Silicon Errata 27 McBSP: XEMPTY Stays Low When DXR Written Late Advisory 2.0.13 Revision(s) Affected : 2.0 Details : XEMPTY goes low and stays low when DXR was written on either the last bit or next-to-last bit of the previous word being transferred to DX. (Internal Reference Number 3383) EMIF: Multiple SDRAM CE Spaces: Invalid [...]

  • Página 28

    SPRZ153 TMS320C6201 Silicon Errata 28 EMIF: Data Setup Times Advisory 2.0.19 Revision(s) Affected : 2.0 Details : The data setup time for the external memory interface is listed in the February 21, 1998 Advanced Information TMSX320C6201 Data Sheet as 2 ns, 3 ns, and 2 ns for full-rate SBSRAM, half-rate SBSRAM, and SDRAM, respectively . In revision [...]

  • Página 29

    IMPORT ANT NOTICE T exas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orde[...]