ELAN Home Systems EM78P459AK manuel d'utilisation

EM78P458/459 OTP ROM EM78P458/459 8-BIT MICRO-CONTROLLER Version 1.3 ELAN MICROELECTRONICS CORP. No. 12, Innovation 1 st RD., Science-Based Industrial Park Hsin Chu City, Taiwan, R.O.C. TEL: (03) 5639977 FAX: (03)5782037(S L) 5630118 (FAE)[...]

EM78P458/459 OTP ROM Specification Revision History Version Content 1.0 Initial version 1.1 Modify ERC frequency 2003/03/06 1.2 Add AD & OP spec 2003/05/07 1.3 Change Power on reset content 2003/07/01 Application Note AN-001 A/D Pre-amplifier AN-002 Calibration Offset on A/D AN-003 Example of Microcomputer Dig ital Thermometer AN-004 Tips on ho[...]

EM78P458/459 OTP ROM 1. GENERAL DESCRIPTION EM78P458 and EM78P459 are 8-bit microproce ssor s designed and developed with low-powe r and high-speed CMOS technology. It is equi pped with a 4K *13-bit Elect rical One Time Programma ble Read Only Memory (OTP-ROM). With its OTP-ROM feature, it is able to offer a convenient way of developing and verifyi[...]

EM78P458/459 OTP ROM 2. FEATURES • Operating voltage range: 2.3V~5.5V • Operating temperature range: 0 ° C~70 ° C • Operating frequency range (base on 2 clocks): * Crystal mode: DC ~ 20MHz/2clks,5V; DC ~ 8MHz /2clks,3V * RC mode: DC ~ 4MHz/2 clks,5V; DC ~ 4MHz/2cl ks,3V • Low power consumption: * Less than 1.5 mA at 5V/4MHz * Typically 15[...]

EM78P458/459 OTP ROM • Package types: * 20 pin DIP 300mil : EM78P458AP * 20 pin SOP 300mil : EM78P458AM * 24 pin skinny DIP 300mil : EM78P459AK * 24 pin SOP 300mil : EM78P459AM • Power on voltage detector available (2.0V ± 0.15V) This specification is subject to cha nge without prior notice. 07.01.2003 (V1.3) 5[...]

EM78P458/459 OTP ROM 3. PIN ASSIGNMENT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 EM78P459 EM78P458 VSS P60/ADC1 P61/ADC2 P62/ADC3 P63/ADC4 P64/ADC5 P65/ADC6 P66/ADC7 P56/CIN+ P57/CO VDD OSCI OSCO P53/VREF P52/PWM2 P51/PWM1 P50/INT P67/ADC8 P54/TCC P55/CIN- P60/ADC1 P61/ADC2 P62[...]

EM78P458/459 OTP ROM PWM2 * Defined by PWMCON (IOC51)<6, 7> VREF 15 I * External reference voltage for ADC * Defined by AD-CMPCON (IOCA0)<7>. CIN-, CIN+, CO 20, 1,2 I O * “-“ -> the input pin of Vin- of the comparator. * “+”-> the input pin of Vin+ of the comparator. * Pin CO is the output of the comparator. * Defined by A[...]

EM78P458/459 OTP ROM 4. FUNCTION DESCRIPTION DATA & CONTROL BUS IOC5 R5 P 5 0 P 5 1 P 5 2 P 5 3 P 5 4 P 5 5 P 5 6 P 5 7 Comparators 8 ADC 2 PWMs IOC6 R6 P 6 0 P 6 1 P 6 2 P 6 3 P 6 4 P 6 5 P 6 6 P 6 7 ACC R3 STACK 0 STACK 1 STACK 2 STACK 3 STACK 4 P C ROM Instruction Register Instruction Decoder ALU Interrupt Control /INT R4 RAM WDT Timer Presc[...]

EM78P458/459 OTP ROM • The contents of R2 are set to all "0"s upon a RESET condition. • "JMP" instruction allows the direct loading of t he lower 10 prog ram counter bits. Thus, "JMP" allows PC to jump to any location within a page. • "CALL" instruction loads the lower 10 b its of the PC, and then PC+1 [...]

EM78P458/459 OTP ROM 4. R3 (Status Register) 7 6 5 4 3 2 1 0 CMPOUT PS1 PS0 T P Z DC C • Bit 7 (CMPOUT) the result of the comparator outp ut. • Bit 6 (PS1) ~ 5 (PS0) Page select bits. PS0~PS1 are used to select a program memory page . When executing a "JMP", "CALL", or other in structions which cause the program co unter to [...]

EM78P458/459 OTP ROM R0 R1 (TCC) R2 (PC) R3 (Status) R4 (RSR) R5 (Port 5) R6 (Port 6) R7 R9 (ADCON) RA (ADDATA) RB (TMR1L) RC (TMR1H) RD (TMR2L) RE (TMR2H) RF 16x8 Common Register 00 01 02 03 04 05 07 06 08 0A 09 0B 0C 0D 0E 0F 11 10 1E 1F 3F 20 21 STACK 4 STACK 3 STACK 2 STACK 1 STACK 0 R8 00 32x8 Bank Register (Bank 0) 01 32x8 Bank Register (Bank[...]

EM78P458/459 OTP ROM 8. R9 (ADCON: Analog to Digital Control) 7 6 5 4 3 2 1 0 - - IOCS ADRUN ADPD ADIS2 ADIS1 ADIS0 • Bit 7:Bit 6 Unemployed, read a s ‘0’; • Bit 5(IOCS): Select the Segme nt of IO control register. 1 = Segment 1 ( IOC51~IO CF1 ) selected; 0 = Segment 0 ( IOC50~IO CF0 ) selected; • Bit 4 (ADRUN) : ADC starts to RUN. 1 = an[...]

EM78P458/459 OTP ROM An 8-bit general-purpose register. 13. RE A 2-bit, Bit 0 and Bit 1 register. 14. RF (Interrupt Status Register) 7 6 5 4 3 2 1 0 - CMPIF PWM2IF PWM1IF ADIF EXIF ICIF TCIF “1” means interrupt re quest, and “0” means no interrupt occurs. • Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by softwar[...]

EM78P458/459 OTP ROM 2. CONT (Control Register) 7 6 5 4 3 2 1 0 INTE INT TS TE PAB PSR2 PSR1 PSR0 • Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits. PSR2 PSR1 PSR0 TCC Rate WDT Rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 • Bit 3 (PAB) Prescaler assignment bi[...]

EM78P458/459 OTP ROM 4. IOC90 (GCON: I/O Confi guration & Control of ADC ) 7 6 5 4 3 2 1 0 OP2E OP1E G22 G21 G20 G12 G11 G10 • Bit 7 ( OP2E ) Enable the gain amplifier which input is c onne cted to P64 and output is connected to the 8-1 analog switch. 0 = OP2 is off ( default valu e ), and by passes the input signal to the ADC; 1 = OP2 is on.[...]

EM78P458/459 OTP ROM 1 = The Vref of the ADC is connected to P53/VREF. • Bit 6 (CE): Comparator enable bit 0 = Comparat or is off (default value); 1 = Comparat or is on. • Bit 5 ( COE ): Set P57 as the output of the comparator 0 = the comparato r acts as an OP if CE=1. 1 = act as a comparator if CE=1. • Bit4:Bit2 (IMS2:IMS0) : Input Mode Sele[...]

EM78P458/459 OTP ROM • Bit 4 (/PD4) Control bit is used to enable the pull-down of the P64 pin. • Bit 5 (/PD5) Control bit is used to enable the pull-down of the P65 pin. • Bit 6 (/PD6) Control bit is used to enable the pull-down of the P66 pin. • Bit 7 (/PD7) Control bit is used to enable the pull-down of the P67 pin. • IOCB0 register is[...]

EM78P458/459 OTP ROM 9. IOCE0 (WDT Control Register) 7 6 5 4 3 2 1 0 WDTE EIS - - - - - - • Bit 7 (WDTE) Control bit is used to enable Watch dog Timer. 0: Disable WDT; 1: Enable WDT. WDTE is both readable an d writable • Bit 6 (EIS) Control bit is used to define the function of the P50 (/INT) pin. 0: P50, input pin only; 1: /INT, external inter[...]

EM78P458/459 OTP ROM • Bit 5 (PWM2IE) PWM2IF interrupt enable bit. 0: disable PWM2 interrupt 1: enable PWM2 interrupt • Bit 6 (CMPIE) CMPIF interrupt enable bit. 0: disable CMPIF interrupt 1: enable CMPIF interrupt • Bit 7 : Unimplemented, read as ‘0’. Individual interrupt is enabled by setting its as sociated control bit in the IOCF0 to [...]

EM78P458/459 OTP ROM • Bit 1 : Bit 0 ( T1P1:T1P0 ): TM R1 clock prescale option bits. T1P1 T1P0 Prescale 0 0 1:2(Default) 0 1 1:8 1 0 1:32 1 1 1:64 12. IOC61 ( DT1L: the Least Significant Byte ( Bit 7 ~ Bit 0) of Duty Cycle of PWM1 ) A specified value keeps the output of PWM1 to stay at high until the value matches with TM R1. 13. IOC71 ( DT1H: t[...]

EM78P458/459 OTP ROM 0 = Calibratio n disable; 1 = Calibration enabl e. • Bit 6 (SIGN2): Polarity bit of offset voltage 0 = Negative voltage; 1 = Positive voltage. • Bit 5:Bit 3 (VOF2[2]:VOF2[0]): Offset voltage bits • Bit 1:Bit 0 (PWM2[9] :PWM2[8 ]) : The Most Significant Byte of PWM1 Duty Cycle A specified value keeps the PWM2 output to sta[...]

EM78P458/459 OTP ROM 4.3 TCC/WDT & Prescaler An 8-bit counter is available as prescale r for the TC C or WDT. The prescale r is available fo r either the TCC or WDT only at any given time, and the PAB bit of CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits determi ne t he prescale ratio. The prescaler is cleare d [...]

EM78P458/459 OTP ROM 8-bit Counter 8-to-1 MUX MUX M U X WDT TCC Pin M U X M U X SYNC 2 cycles TCC (R1) PAB PAB PAB TS TE 0 0 1 1 1 0 WDTE (in IOCE) WDT timeout PSR0 ~ PSR2 0 1 DATA BUS CLK (Fosc/2 or Fosc/4) TCC overflow interrupt Fig. 5 Block Diagram of TCC and WDT 4.4 I/O Ports Port 5, Port 6, and the I/O registers are bi-directi o nal tri-state [...]

EM78P458/459 OTP ROM M U X PORT PCWR PDWR IOD PDRD 0 1 PCRD D D Q Q Q Q _ _ C L C L P R CLK CLK NOTE: Pull-down is not shown in the figure. Fig. 6 The Ccircuit of I/O Port and I/O Control Register for Port 5 PCRD M U X IOD 0 1 INT PDRD P50, /INT Bit 6 of IOCE0 PCWR D Q Q _ CLK P R C L PDWR D Q Q _ CLK P R C L P R C L CLK DQ Q _ P R C L CLK DQ Q _ P[...]

EM78P458/459 OTP ROM PCRD M U X IOD 0 1 PDRD P60 ~ P67 PCWR D Q Q _ CLK P R C L PDWR D Q Q _ CLK P R C L P R C L CLK DQ Q _ TI n PORT NOTE: Pull-high (down) and Open-drain are not shown in the figure. Fig. 8 The Circuit of I/O Port and I/O Control Register for P60~ P67 /SLEP T17 T10 T11 IOCE.1 Interrupt ENI Instruction DISI Instruction Interrupt (W[...]

EM78P458/459 OTP ROM Table 4 Usage of Port 6 Input Change d Wake-up/Interrupt Fun ction Usage of Port 6 Input Status Changed Wake-u p/Interrupt (I) Wake-up from Port 6 Input Status Cha nge (II) Port 6 Input Status Change Interrupt (a) Before SLEEP 1. Read I/O Port 6 (MOV R6,R6) 1. Disable WDT 2. Execute "ENI" 2. Read I/O Port 6 (MOV R6,R6[...]

EM78P458/459 OTP ROM (1) External reset input on /RESET pin. (2) WDT time-out (if enabled). (3) Port 6 input status change (if enable d). (4) Comparator high. The first two cases will cause the EM78P458/459 to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). Ca se 3 is considered the continuation of program[...]

EM78P458/459 OTP ROM IOW RF ENI (or DISI) ; Enable (or disable) global i nterrupt SLEP ; Sleep NOP Similarly, if the Comparator High Interrupt is used to wake up the EM78P458/459 (as in Case [c] above), the following instruction s must be executed before SLEP: MOV A, @0Bxx000110 ; Sele ct internal TCC clock CONTW CLR R1 ; Clear TCC and prescaler MO[...]

EM78P458/459 OTP ROM Table 5 The Values of RST, T, and P after RESET Reset Type T P Power-on 1 1 /RESET during Operating mode *P *P /RESET wake-up during SLEEP mode 1 0 WDT during Operating mode 0 *P WDT wake-up during SLE EP mode 0 0 Wake-up on pin change during SLEEP mode 1 0 *P: Previous status before reset Table 6 The Status of RST, T and P bei[...]

EM78P458/459 OTP ROM 4.6 Interrupt The EM78P458/459 has six interrupt s as listed below: (1) TCC overflow inte rrupt (2) Port 6 Input Status Change Interrupt (3) External interrupt [(P50, /INT) pin]. (4) Analog to Digital conversion completed. (5) When TMR1/TMR2 matches with PRD1/PRD2 respectively in PWM. (6) When the compar ators output chang e. B[...]

EM78P458/459 OTP ROM Fig. 1 1 Interrupt Input Circuit 4.7 Analog-To-Digital Converter (ADC) The analog-to-digital circuitry consi sts of an 8-bit analog multiplexer , three control registers (ADCON/R9, AD-CMP-CON/IOCA0, GCON/IOC90) , one data regi ster (ADDA T A/RA) and an ADC with 8-bit resolution. The functional block di agr am of the ADC is show[...]

EM78P458/459 OTP ROM 1. ADC Control Register (ADCON/ R9, AD-CMP-CON/IOCA0, GCON/IOC90) 1.1 ADCON/R9 The ADCON register cont rols the operation of t he A/D conversio n and decides which pi n should be currently active. BIT 7 6 5 4 3 2 1 0 SYMBOL - - IOCS ADRUN AD PD ADIS2 ADIS1 ADIS0 *Init_Value 0 0 0 0 0 0 0 0 *Init_Value: Initial value at power on[...]

EM78P458/459 OTP ROM 0 = The Vref of the ADC is connected to Vdd (default value), and the P53/VREF pin ca rries out the function of P53; 1 = The Vref of the ADC is connected to P53/VREF. • CE (Bit 6): Control bit used to enable comparator. 0 = Disable comparato r 1 = Enable comparator • COE (Bit 5): Set P57 as the output of the comparator 0 = t[...]

EM78P458/459 OTP ROM When the A/D conversion is comple te, the result is loaded to t he ADDATA. The START/END bit is clear, and the ADIF is set. 3. A/D Sampling Time The accuracy, linearity, and sp eed of the successive approximation A/D converter a re dependent on the properties of the ADC and the co mparator. Th e source imp edance and the intern[...]

EM78P458/459 OTP ROM (1) Write to the three bits (IMS2:IMS0) on the AD -CMP-CON1 regi ster to define the characteristics of R6: Digital I/O, analog channels, and voltage refere nce pin; (2) Write to the ADCON regist er to configure AD module: (a) Select A/D input channel ( ADAS2:ADAS0 ); (b) Select the proper gains by writi ng to the GCON register [...]

EM78P458/459 OTP ROM ;ADC Control Registers ADDATA == 0xA ; The contents are the results of ADC ADCON R== 0x9 ; 7 6 5 4 3 2 1 0 ; - - IOCS ADRUN ADP D ADIS2 ADIS1 ADIS0 ADCONC== 0xA ; 7 6 5 4 3 2 1 0 ; VREFS X X IMS2 IMS1 IMS0 CKR1 CKR0 GCON == 0x9 ; 7 6 5 4 3 2 1 0 ; OPE2 OPE1 G22 G21 G20 G12 G11 G10 ;To define bits ;In ADCONR ADRUN == 0x4 ; ADC i[...]

EM78P458/459 OTP ROM CONTW MOV A, @0B00000000 ; To employ Vdd as the refere nce voltage, to define P60 as IOW ADCONC ; an analog input and set clock rate at fosc/4 En_ADC: MOV A, @0BXXXXXXX1 ; To define P60 as an i nput pin, and the ot hers are de pendent IOW PORT6 ; on applications MOV A, @0B01000101 ; To enable the OP1, and set the gain as 32 IOW[...]

EM78P458/459 OTP ROM Dat a Bus Dat a Bus PRD1 Com parator Com parator TM R1H + TM R1L S RQ MUX Dut y Cy cl e Ma t ch Peri od Ma t ch P WM1 T1P0 T1P1 T1 EN IOC 51 PRD2 Com parator Com parator S RQ MUX Dut y Cy cl e Ma t ch Peri od Ma t ch P WM2 T2P0 T2P1 T2 EN IOC 51 To PWM 1IF To PWM 2IF reset reset latc h latc h 1:2 1:8 1:32 Fos c 1:64 1:2 1:8 1:3[...]

EM78P458/459 OTP ROM 3. PWM Period ( PRDX : PRD1 or PRD2 ) The PWM period is defined by writing to the PRDX register. When TMRX is equal to PRDX, the following events occur on the next incre ment cycle: • TMRX is cleared. • The PWMX pin is set to 1. • The PWM duty cycle is latched from DT1/DT2 to DTL1/DTL2. < Note > The PWM output will [...]

EM78P458/459 OTP ROM 4.9 Timer 1. Overview Timer1 (TMR1) and Timer2 (TM R 2) (TMRX) are 10 -bit clock counters with programmable prescalers, respectively. They are designed for the PWM module as baud rate clock gen erators. TMRX can be read, written, and cleared at any reset co nditions. 2. Function description Fig. 15 shows TMRX block diagram. E a[...]

EM78P458/459 OTP ROM ComparatorX ( Compara t or 1 and Comparator 2 ): To re set TMRX while a match occurs and the TMRXIF flag is set at the same time. 3. Programming the Related Registers When defining TMRX, refer to the related registers of its operation as shown in Table 9.It must be noted that the PWMX bits must be disa bled if thei r related TM[...]

EM78P458/459 OTP ROM This specification is subject to cha nge without prior notice. 07.01.2003 (V1.3) 42 • The compared result is stored in the CMPOUT of R3. • The comparator outputs is output to P57 by pr ogramming bit5<COE> of the AD-CMPCON register to 1. • P57 must be defined as an output if implemented as the comparator output. • [...]

EM78P458/459 OTP ROM • If enabled, the comparator remains a ctive and t he interrupt remain s functional, even under SLEEP mode. • If a mismatch occurs, the interrupt will wake up the device from SLEEP mode. • The power consumption should be taken into cons ideration for the benefit of energy conse rvation. • If the function is unemployed d[...]

EM78P458/459 OTP ROM Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 0 Bit 2 Bit 1 Wake-up from Pin Changed P P P P P P P P Bit Name CALI1 SIGN 1 VOF1[2] VOF1[1] VOF1[0] X Bit1 Bit0 Power-on 0 1 1 0 0 0 0 0 /RESET and WDT 0 1 1 0 0 0 0 0 N/A IOC71 (DT1H) Wake-up from Pin Changed P P P P P 0 P P Bit Name - - - - - - - - Power-on 0 0 0 0 0 [...]

EM78P458/459 OTP ROM Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Wake-up from Pin Changed P P P P P P P P Bit Name P57 P56 P55 P54 P53 P52 P51 P50 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 0x05 P5 Wake-up from Pin Changed P P P P P P P P Bit Name P67 P66 P65 P64 P63 P62 P61 P60 Power-on 1 1 1 1 1 1 1 1 /RES[...]

EM78P458/459 OTP ROM MASK Option. The up-limited operation frequency of cr ystal/resonator on the different VDDs is listed in Table 11 Table 12 The Summary of Maximum Operating Speeds Conditions VDD Fxt max.(MHz) 2.3 4 3.0 8 Two clocks 5.0 20 2. Crystal Oscillator/ Cera mic Resonators (XTAL) EM78P458/459 can be driv en by an external clock si gnal [...]

EM78P458/459 OTP ROM Table 13 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators Oscillator Type Frequency M ode Frequen cy C1(pF) C2(pF) 455 kHz 100~150 100~150 2.0 MHz 20~40 20~40 Ceramic Resonators HXT 4.0 MHz 10~30 10~30 32.768kHz 25 15 100KHz 25 25 LXT 200KHz 25 25 455KHz 20~40 20~150 1.0MHz 15~30 15~30 2.0MHz 15 15 Crystal[...]

EM78P458/459 OTP ROM 3. External RC Oscillator Mode For some applications that do not require precise ti ming calculation, the RC oscillator (Fig. 22) could offer users with an effective cost savings. Neve rt heless, it should be noted th at the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (R ext), [...]

EM78P458/459 OTP ROM 3.3k 1.43 MHz 1.35 MHz 5.1k 980 KHz 877 KHz 10k 520 KHz 465 KHz 100 pF 100k 57 KHz 54 KHz 3.3k 510 KHz 470 KHz 5.1k 340 KHz 320 KHz 10k 175 KHz 170 KHz 300 pF 100k 19 KHz 19 KHz <Note> 1. Measured on DIP packages. 2. Design reference only 4. RC Oscillator Mode wi th Internal Capacitor If both precision and cost are taken [...]

EM78P458/459 OTP ROM 4.13 Power-on Considerations Any microcontroller is not wa rranted to start proper operation befo re the powe r supply st abilizes in steady state. EM78P458/459 POR voltage rang e is 1.2V~1.8V. Un der customer application, when power is OFF, Vdd must drop to below 1.2V and remai n s OFF fo r 10us before p ower can be switche d [...]

EM78P458/459 OTP ROM EM78P458 EM78P459 /RESET VDD 100K Q1 1N4684 10K 33K VDD Fig. 25 Circuit 1 for the Residue V oltage Protection EM78P458 EM78P459 /RESET VDD Q1 VDD R3 R2 R1 Fig. 26 Circuit 2 for the Residue V oltage Protection 4.14 CODE OPTION EM78P458/459 has one CODE option word and one Customer ID word that are n ot a part of the normal progr[...]

EM78P458/459 OTP ROM 1: XTAL type • Bit 11 (/ENWTD) : Watchdog timer e nable bit. 0: Enable 1: Disable • Bit 10 (CLKS): Clocks of each instru ction cycle. 0: Two clocks 1: Four clocks Refer to the section of Instruction Set. • Bit 9 (/PTB): Protect bit. 0: Enable 1: Disable • Bit 8 (HLF) : XTAL frequency sel ection. 0: Low frequency 1: High[...]

EM78P458/459 OTP ROM 4.15 Instruction Set Each instruction in the inst ruction set is a 13- bit word divided into an OP code and one o r more operands. Normally, all instru ctions are executed wi thin one single instruction cycle (one instruction consists of 2 oscillator pe riods), unless the program counte r is ch anged by instruction "MOV R2[...]

EM78P458/459 OTP ROM INSTRUCTION BINARY HEX MNEMONIC OPERATION ST ATUS AFFECTED 0 0011 10rr rrrr 03rr ADD A,R A + R → A Z,C,DC 0 0011 11rr rrrr 03rr ADD R,A A + R → R Z,C,DC 0 0100 00rr rrrr 04rr MOV A,R R → A Z 0 0100 01rr rrrr 04rr MOV R,R R → R Z 0 0100 10rr rrrr 04rr COMA R /R → A Z 0 0100 11rr rrrr 04rr COM R /R → R Z 0 0101 00rr r[...]

EM78P458/459 OTP ROM 4.16 Timing Diagrams RESET T i m i ng ( CLK=" 0" ) CLK / R ESET NOP Inst ruct ion 1 Executed Tdr h TCC I nput T i m ing ( C LKS ="0" ) CLK TCC Tt cc Ti ns AC Test ing : I nput i s dri ven at 2. 4V for logi c "1" , and 0. 4V f or l ogi c "0" . T i m ing m easurem ents are m ad e at 2. 0V f[...]

EM78P458/459 OTP ROM 5. ABSOLUTE MAXIMUM RATINGS Items Rating Temperature under bias 0 ° C to 70 ° C Storage temperature -65 ° C to 150 ° C Input voltage -0.3V to +6.0V Output voltage -0.3V to +6.0V This specification is subject to cha nge without prior notice. 07.01.2003 (V1.3) 56[...]

EM78P458/459 OTP ROM 6. ELECTRICAL CHARACTERISTICS 6.1 DC Electrical Characteristic (Ta=0 ° C ~ 70 ° C, VDD=5.0V ± 5%, VSS=0V) Symb ol Parameter Condition Min Typ Max Unit XTAL: VDD to 3V DC 8 MHz XTAL: VDD to 5V Two cycle with two clocks DC 20 MHz Fxt RC: VDD to 5V R: 5.1K Ω , C: 100pF F ± 30 % 760 F ± 30 % KHz IIL Input Leakage Current for[...]

EM78P458/459 OTP ROM 6.2 AC Electrical Characteristic (Ta=0 ° C ~ 70 ° C, VDD=5V ± 5%, VSS=0V) Symb ol Parameter Conditions Min Typ Max Unit Dclk Input CLK duty cycle 45 50 55 % Tins Instruction c ycle time (CLKS="0") Crystal type RC type 100 500 DC DC ns ns Ttcc TCC input period (Tins+20)/N* ns Tdrh Device re set hold time Ta = 25 ° [...]

EM78P458/459 OTP ROM IVR Input voltage range Vdd =5.0V, V SS =0.0V 0 5 V 0 0.2 0.3 OVS Output voltage s wing Vd =5.0V, V SS =0.0V,RL=10K Ω 4.7 4.8 5 V Iop Supply current of OP 250 350 500 uA PSRR Power-supply Rejection Ration for OP Vdd= 5.0V, V SS =0.0V 50 60 70 dB Vos Offset voltage Vdd= 5.0V, V SS =0.0V ±10 ±20 mV Vs Operating range 2.5 5.5 [...]

EM78P458/459 OTP ROM APPENDIX Package Types: OTP MCU Package Type Pin Count Package Size EM78P458AP DIP 20 pin 300mil EM78P458AM SOP 20 pin 300mil EM78P459AK Skinny DIP 24 pin 300mil EM78P459AM SOP 24 pin 300mil This specification is subject to cha nge without prior notice. 07.01.2003 (V1.3) 60[...]