Silicon Laboratories SI4421 manuel d'utilisation

Si4421 PIN ASSIGNMENT This document refers to Si4421-IC rev A1. See www.silabs.com/i ntegration for any applicable e rrata. See ba ck page for orde ring i nforma tion. Si4421 Universal ISM Band FSK Transceiver DESCRIPTION Silicon Labs’ Si4421 is a single ch ip, low power, multi-channel FSK t ransceiver designed for use i n applications requ iring[...]

Si4421 2 DETAILED FEATURE-LEVEL DESCRIPTION The Si4421 FSK transceiver is d esi gned to cover the unlicensed frequency bands at 433, 868 and 915 MHz. The device facilitates complian ce with FCC and ETSI requ irements. The receiver block employs t he Zero-IF approach with I/Q demodulation, allowin g the use of a minimal number of external components[...]

Si4421 3 Data Validity Blocks RSSI A digital RSSI ou tput is provided t o monitor the input s ignal level. It goes high if the r eceived signal strength e xceeds a given preprogrammed level. An analog RSSI s ignal is also availab le. The RSSI settlin g time depends on the externa l filter capacitor. Pin 15 is used as analog RSSI output. Th e digita[...]

Si4421 PACKAGE PIN DEFINITIONS Pin type key: D=digital, A= analog, S=su pply, I=input, O=output, IO=input/output Pin Name Typ e Function 1 SDI DI Data input of the serial control interface 2 SCK DI Clock input of the serial control interface 3 nSEL DI Chip select input of the serial control interface (active low) 4 SDO DO Serial data output with bu[...]

Si4421 5 Internal Pin Connections Pin Name Internal connection 1 SDI 2 SCK 3 nSEL PAD 1.5k VSS VDD 4 SDO 5 nIRQ FSK DATA 6 nFFS DLCK CFIL 7 FFIT 8 CLK PAD 10 VSS VDD XTL 9 REF Pin Name Internal connection 10 nRES 11 VSS 12 RF2 13 RF1 14 VDD 15 ARSSI nINT 16 VDI[...]

Si4421 PIN6 Logic Diagram (FSK / DATA / nFFS) PIN10 Logic Diagram (nRES I/O) * Note: These pins can be left floating. 6[...]

Si4421 7 Typical Application Typical application with FIFO usage C3 C2 10n X1 10MHz C1 2.2u Si4421 1 3 4 2 5 7 6 8 9 10 11 12 13 14 15 16 VDD SCK SDO nIRQ P4 P3 P1 P2 SDI CLKin nSEL nFFS FFIT nRES PCB Antenna P5 P6 P7 nRESin C4 2.2n P0 CLK (optional)* TP (optional) (optional)* (optional) (opt.) (optional) VDI Note: * Connect ions needed only in tim[...]

Si4421 GENERAL DEVICE SPECIFICATIONS All voltages are referenced to V ss , the potential on the ground reference pin VSS. Absolute Maximum Ratings (non-operating) Symbo l Parameter Min Max Units V dd Positive supply voltage -0.5 6 V V in Voltage on any pin (except RF1 and RF2 ) -0.5 V dd +0.5 V V oc Voltage on open collector outputs (RF1, RF2) -0.5[...]

Si4421 ELECTRICAL SPECIFICATION Test Conditions: T op = 27 o C; V dd = V oc = 3.3 V DC Characteristics Symbo l Parameter Conditions/Notes Min Ty p Max Units 433 MHz band 15 868 MHz band 16 I dd_TX_0 Supply current (TX mode, P out = 0 dBm) 915 MHz band 17 mA 433 MHz band 22 26 868 MHz band 23 27 I dd_TX_PMAX Suppl y current (TX mode, P out = P max )[...]

Si4421 AC Characteristics (PLL parameters) Symbo l Parameter Conditions/Notes Min Ty p Max Units f ref PLL reference frequency (Note 2) 9 10 11 MHz 433 MHz band, 2.5 kHz resolution 430.24 439.75 868 MHz band, 5.0 kHz resolution 860.48 879.51 f o Receiver LO/Transmitter carrier frequency 915 MHz band, 7.5 kHz resolution 900.72 929.27 MHz t lock PLL [...]

Si4421 AC Characteristics (Transmitter) Symbo l Parameter Conditions/Notes Min Ty p Max Units I OUT Open collector output DC current Programmable 0.5 6 mA In 433 MHz band 7 P max_50 Max. output power delivered to 50 Ohm load over a suitable matching network (Note 4) In 868 MHz / 915 MHz bands 5 dBm In 433 MHz band with monopole antenna with matchin[...]

Si4421 Note 1: Measured with disa bled clock output buffer Note 2: Not using a 10 MHz crystal is allowed but not recommended because all crystal refe rred timing and frequency paramete rs will change accordingly Note 3: See the BER diagrams in the measurement results section (page 37 ) for detailed information Note 4: See reference design with 50 O[...]

Si4421 CONTROL INTERFACE Commands to the transmitter are sent serially. Data bits on pin SD I are shifted into the device upon the rising edge of the clo ck on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. A ll comman ds consist of a command code, followed by a varying number of[...]

Si4421 Control Commands Control Command Relate d Parameters/Functions Related control bits 1 Configuration Setting Command Frequency band, crystal oscillator load capacitance, RX FIFO and TX register enable el , ef , b1 to b0 , x3 to x0 2 Power Management Command Receiver/Transmitter mode change, synthesizer, crystal oscillator, PA, wake-up timer, [...]

Si4421 15 Description of the Control Commands 1. Configuration Setting Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 0 0 0 0 0 0 0 el ef b1 b0 x3 x2 x1 x0 8008h Bit el enables the internal data register. Bit ef enables the FIFO mode. If ef = 0 then DATA (pin 6) a nd DCLK (pin 7) are used for da ta and data clock output. b1 b0 Freq y Ba ue[...]

Si4421 Logic connections between power control bits: Edge detector et er es ebb ex enable crys tal oscillator enable baseba nd circuits enable RF front end enable RF synthesize r start TX clear TX latch enable power am plifier VCO and PLL Crystal oscillator Digital signal processing TX latch enable baseban d circuits enable RF front end enable powe[...]

Si4421 3. Frequency Setting Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 0 1 0 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 A680h The 12-bit parameter F (bits f11 to f0 ) should be in the range of 96 and 3903. When F value sent is out of range, the previou s value is kep t. The synthe sizer center frequency f 0 can be calculated as: f 0 = 10 ·[...]

Si4421 Bits 9-8 (d1 to d0) : V DI (valid data indica tor) signal response time setti ng: d1 d0 Response 0 0 Fast 0 1 Medium 1 0 Slow 1 1 Alway s on VDI Logic Diagram: d0 R/S FF LOGIC HIGH d1 CR_LOCK DRSSI DQD IN0 IN1 IN2 IN3 SEL1 SEL0 Y Q DQD CR_LOCK DQD DRSSI SET CLR VDI MUX FAST MEDIUM SLOW er * CLR Note: * For details see the Power Management Co[...]

Si4421 Bits 4-3 (g1 to g0) : LNA gain se lect: g1 g0 Gain relati ve to maximum [dB] 0 0 0 0 1 -6 1 0 -14 1 1 -20 Bits 2-0 (r2 to r0) : RSSI detector threshold: r2 r1 r0 RSSI setth 0 0 0 -103 0 0 1 -97 0 1 0 -91 0 1 1 -85 1 0 0 -79 1 0 1 -73 1 1 0 Reserved 1 1 1 Reserved The RSSI threshold depends on the LNA gain, the r eal RSSI threshold can be ca [...]

Si4421 Bits 2-0 ( f2 to f0 ): DQD threshold parameter. The Data Quality Detector is a digital pr ocessing part of the radi o, connected to the demodulator - it is a n indicator reporting the reception of an FSK modulated RF signal. It will work every time the receiver is on. Setting this parameter defines how clean incoming data stream wo ul d be s[...]

Si4421 Bit 1 ( ff ): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared. Bit 0 ( dr ): Disables the highly sensitive RESET mode. dr Reset mode Reset triggered when 0 Sensitive reset V dd belo w 1.6V, V dd glitch greater than 600mV 1 Non-sensitive reset V dd below 250mV Note: To restart the synch[...]

Si4421 Bit 5-4 ( rl1 to rl0 ): Range limit. Limits the value of the freq uency offset register to the next values: rl1 rl0 Max deviation 0 0 No restriction 0 1 +15 f res to -16 f res 1 0 +7 f res to -8 f res 1 1 +3 f res to -4 f res f res : 433 MHz bands: 2.5 kHz 868 MHz band: 5 kHz 915 MHz band: 7.5 kHz Bit 3 ( st ): Strobe edge, when st goes to h[...]

Si4421 23 There are four operation modes: 1. ( a1 =0, a0 =0) Automatic operation of the AFC is off. Strobe bit can be controlled by the microcontrolle r. 2. ( a1 =0, a0 =1) The circuit measures the fre quency offset only once af ter power up. This way, extended TX-RX distance can b e achieved. In the final application, when the user inserts the bat[...]

Si4421 12. PLL Setting Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 1 0 0 1 1 0 0 0 ob1 ob0 1 dly ddit 1 bw0 CC77h Bits 6-5 ( ob1-ob0 ): Microcontroller output clock buffe r rise and fall time control. The ob1-ob0 bits are changing the output drive current of the CLK pin. Higher current provides fa ster rise and fall times but can cause [...]

Si4421 14. Wake-Up Timer Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 1 1 r4 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 E196h The wake-up time period can be ca lculated by ( m7 to m0 ) and ( r4 to r0 ): T wake-up = 1.03 · M · 2 R + 0.5 [ms] Note:  For continual operation, the ew bit should be cleared and se t at the end of e very cycle. ?[...]

Si4421 Application Proposal for LPDM (Low Power Duty-Cycle Mode) Receivers: 16. Low Battery Det ector and Microc ontroller Clock Divider Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 1 0 0 0 0 0 0 d2 d1 d0 0 v3 v2 v1 v0 C000h The 4-bit parameter (v3 to v0) represents the value V, which defines the threshold voltage V lb of the detector: V[...]

Si4421 17. Status Read Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h The read command starts with a zero, wherea s all other control co mmands start with a one. If a read co mmand is identified, the status bits will be clocked out on the SDO pin as follows : Status Register Read Sequence with FIFO Read [...]

Si4421 INTERRUPT HANDLING In order to achieve low power consumption th ere is an advanced event handling circui t implemented. The device has a very low power consumption mode, so called sleep mode . I n t h i s m o d e o n l y a f e w p a r t s o f t h e c i r c u i t a r e w o r k i n g . I n c a s e o f a n e v e n t , t h e d e v i c e w a k e [...]

Si4421 The best practice in interrupt handling is t o s t a r t w i t h a s t a t u s r e a d w h e n i n t e r r u p t o c c u r s , a n d t h e n m a k e a d e c i si o n b a s e d o n the status byte. It is very importa nt to mention that any interrupt can “wake-up” the EZradio chip from sleep mode. This means that the crystal oscillator sta[...]

Si4421 Typical TX register usage et bit (enable transmitter) TX data SPI commands (nSEL, SCK, SDI) enable Synthesizer / PA PA Synt. nIRQ SDO** et = 1 Power Man 0xAA TX latch wr TX byte1 TX byte1 0xAA Notes: *T tx_ XTA L_ON is the start-up time of the PL L + PA with running crystal oscillator ** SDO is tri-state if nSE L is logic high. et = 0 Power [...]

Si4421 RX FIFO BUFFERED DATA READ In this operating mode, incoming data are clocked into a 16-b it FI FO buffer. The receiver starts to fill up the FIFO when the V alid Data Indicator (VDI) bit and the synchron patter n recognition circu it indicates potentially re al incoming data. Thi s prevents the FI FO from being filled with noise and overload[...]

Si4421 CRYSTAL SELEC TION GUIDELINES The crystal oscillator of the Si4421 requires a 10 MHz parallel mode c rystal. Th e circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps. With appropriate PCB layout, the to tal lo[...]

Si4421 RX-TX ALIGNMENT PROCEDURES RX-TX frequency offset can be caused only by the differences in the actual reference freq uency. To minimize these errors it is suggested to use the same crystal type and the same PC B layout for the crystal placement on the RX and TX PCBs. T o v e r i f y t h e p o s s i b l e R X - T X o f f s e t i t i s s u g g[...]

Si4421 RESET MODES The chip will enter into reset mode if an y of the following conditions are met:  Power-on reset: During a power up sequence un til the V dd has reached the correct level and stabilized  Power glitch reset: Transients present on the V dd line  Software reset: Special control command recei ved by the chip Power-on reset A[...]

Si4421 Sensitive Reset Enabled, Ripple on V dd : time V dd Reset threshold voltage (600mV ) nRes output H L 1.6V Reset ramp line (100mV/ms ) Sensitive reset disabled: time V dd Reset th reshold voltage (600mV) nRes output H L 250mV Reset ramp line (100mV/ms ) Software reset Software reset can be issued by sending the appropr iate control command (d[...]

Si4421 TYPICAL PERFORMANCE CHARACTERISTICS Channel Selectivity and Blocking: 0 10 20 30 40 50 60 70 80 90 01 234 567 89 1 0 1 1 1 2 CW interferer offset from carrier [MHz] 434 MHz 868 MHz ETSI Note:  LNA gain maximum, fil ter bandwidth 67 kHz, data r ate 9.6 kbps, AFC switched off, FSK deviation ± 45 kHz, V dd = 2.7 V  Measured according to [...]

Si4421 BER Curves in 433 MHz Band: 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 1 1.2k 2.4k 4.8k 9.6k 19.2k 38.4k 57.6k 115.2k -120 -115 -110 -105 -100 -95 -90 BER Curves in 868 MHz Band: 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 1 1.2k 2.4k 4.8k 9.6k 19.2k 38.4k 57.6k 115.2k -115 -110 -105 -100 -95 -90 -85 The table below shows the optimal receiver baseband band[...]

Si4421 Receiver Sensitivity over Ambient Temperat ure (433 MHz, 2.4 kbps,  f FSK : 45 kHz, BW: 67 kHz): 434 M Hz -115 -112 -109 -106 -103 -100 - 5 0 - 2 5 0 2 55 07 5 1 0 0 Ce ls ius dB m 2. 2V 2. 7V 3. 3V 3. 8V Receiver Sensitivity over Ambient Temperat ure (868 MHz, 2.4 kbps,  f FSK : 45 kHz, BW: 67 kHz): 868 M Hz -11 5 -11 2 -10 9 -10 6 -1[...]

Si4421 REFERENCE DESIGNS Evaluation Board with 50 Ohm Matching Network Schematics CLK_OUT ARSSI C8 C10 C9 C11 L1 L4 L2 L3 AN T ** * * * * * * * See values in the table * optional C3 C2 C4 C1 SDI 1 SCK 2 NSEL 3 SDO 4 NIRQ 5 FSK/DATA/NFFS 6 DCLK/ CFIL/FFI T 7 NINT/ VDI 16 XTL/REF 9 CLK 8 VSS 11 RF2 12 RF1 13 VDD 14 ARSSI 15 NRES 10 IC1 TP61 CN62 1 2 [...]

Si4421 Notes: 1. SRF, DCR and Q should be similar if co mponents from other manufacturer used 2. The SRF should be twice as much as the operation frequency 3. The dielectric type should be C0G and the resonant frequency should be similar if components from alternative v endor used. 4. The values are valid for 1.5mm thick FR4 PCB. If thinner board u[...]

Si4421 Evaluation Board with Resonant PCB Antenna (BIFA) Schematics * * * See v alue s in the t able L1 12 34 56 78 91 0 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CS1 C6 C3 C2 Q1 ARSSI C4 TP1 C1 FFS/DATA SEL SCK SDI SDO IRQ FFE VDI 1 2 3 JP1 TP3 SDI 1 SCK 2 NSEL 3 SDO 4 NIRQ 5 FSK/D ATA/NFF S 6 DCLK/C[...]

Si4421 PCB Layout (Antenna designed for 868/915 MHz band) Top View Bottom View 42[...]

Si4421 43 PACKAGE INFORMATION 16-pin TSSOP De ta i l “ A” ” Ga ug e Plane 0. 2 5 Se ction B- B Se e Det ai l “ A ” Mi n. N om. M ax. M in. N om. M ax. 7 4 0 , 0 0 2 , 1 A 6 0 0 , 0 2 0 0 , 0 5 1 , 0 5 0 , 0 1 A A2 0 ,80 0 ,90 1,05 0 ,031 0,035 0, 041 2 1 0 , 0 7 0 0 , 0 0 3 , 0 9 1 , 0 b b1 0,19 0 ,22 0, 25 0,007 0,009 0, 010 8 0 0 , 0 4 [...]

Si4421 RELATED PRODUCTS AND DOCUMENTS Si4421 Universal ISM Band FSK Transceiver DESCRIPTION ORDERI NG NUMBER Si4421 16-pin TSSOP Si4421-IC CC16 Revision # A1 Demo Boards and Development Kits DESCRIPTION ORDERING NUMBER Development Kit IA ISM – DK ISM Repeater Demo IA ISM – DARP Related Resources DESCRIPTION ORDERING NUMBER Antenna Selection Gui[...]

Si4421 45[...]