Kane Industries C6713CPU manuale d’uso

H ARDWARE R EFERENCE G UIDE Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 1 Orsys Orth System GmbH, Am Stadtgraben 25, 88677 Markdorf , Germany http://www.orsys.de Hardware Reference Guide micro-line  C6713CPU High performance DSP / FPGA board[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 2 Contents 1 PREFACE ...................................................................................................................... 6 1.1 Document Organization ..........................................................[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 3 3.3 Internal fast SRAM ............................................................................................................... 21 3.4 DSP Peripherals ..................................................................[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 4 7.2.3 Configuring for HPI or McASP1 Usage ............................................................................... 47 7.2.4 Configuring micro-line ® Pin D30 Termination ...............................................[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 5 List of Tables Table 1: Memory map of the processor ........................................................................................... 20 Table 2: Memory map of the C6713CPU .........................................[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 6 1 Preface This document describes the hardware of the C6713CPU board. It is intended to get an overview of the board and its features. Detailed information about programming, usage of the FPGA and the DSP is described in oth[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 7 Configuration parameters, function names, path names and file names are written in italic typeface. Example: dev_id Source code examples are given in a small, fixed-width typeface. Example: int a = 10; Menus and commands fro[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 8 1.5 Revision History Revision Changes 0.1 ORSYS internal preliminary version / April 2005 0.5 First public preliminary version / May 2005 0.9 Completely revised. Block diagram completed. 1.0 Flash File System: short descript[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 9 2 Hardware Overview The micro-line ® C6713CPU is a high performance DSP board that combines several key technologies for high speed data processing:  a TMS320C6713 DSP with 256 KB internal fa st SRAM and 225MHz or 300MHz[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 10 2.1 Block Diagram of the C6713CPU Figure 1: Block diagram of the C6713 CPU[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 11 C9 green LED ( PLD) red LED (PLD) yellow LE D (FPGA ) JT AG conne c tor DSP SDRA M temp eratur e senso r fl ash m e m ory FPG A PLD micro-lin e connect ors Figure 2: Top side of the C6713CP U micr o-lin e connec tors R1 SDR[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 12 2.2 Connectors 2.2.1 micro-line ® Connectors The micro-line ® connectors are the main I/O connectors of the C6713CPU. They provide access to all signals that are needed for a wide range of I/O connectivity. The signals on[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 13 interfacing over for the majority of the micro-line ® connector pins. The user is no longer restricted to a fixed I/O logic. The FPGA has access to the following signal groups:  DSP EMIF (data bus, address bus, control [...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 14 can be software reconfigured by PLL settings. It can also be generated by the FPGA, allowing any clock frequency up to 100 MHz. Compared to the internal fast SRAM of the DSP chip, the on-board SDRAM is significantly slower.[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 15 DSP-internal temperature is roughly 15 degrees Celsius above the temperature measured by the sensor. Software drivers for the temperature sensor are included in the development kits, see [20] for details. Further informatio[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 16 2.4.1 User Prog rammable LED's (PLD) These LED's are controlled by PLD registers (see chapter 3. 10). They can be switched on and off by application software to display certain events or states. Examples for softw[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 17  CE0 is used for on-board SDRAM  CE1 is used for on-board flash memory , PLD and FPGA registers.  CE2 and CE3 are used for the FPGA Please refer to chapter 3 for further descriptions of the CE spaces and th eir add[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 18 2.5.6 Timers The TMS320C6713 DSP provides two independent 32-bit general purpose timers. The timers support two signaling modes and can be clo cked by an internal or an external source. Each timer has a separate input pin a[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 19 2.5.9 DMA The TMS320C6713 DSP provides an enhanced DMA (EDMA) controller with 16 channels and 16 possible synchronization events. It can be used t o transfer data between two locations anywhere in the address range of the C[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 20 3 Memory Maps and Description of the PLD Registers 3.1 TMS320C6713 M emory Map The memory map of the TMS320C6713 is divided into several sections:  internal memory  DSP peripherals  EMIF CE spaces CE0 .. CE3 The ex[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 21 3.2 C6713CPU Address Map The table below shows how the C6713CPU uses the four CE address spaces of the processor: address range (hex) CE space size (bytes) Description 8000 0000 - 83FF FFFF 128MB external RAM (SDRAM) 8400 0[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 22 3.7 Endianness When data is transferred between the C6713CPU board and external hardware over the micro- line ® connector it is important to know how data is stored in memory. The C6713CPU is configured for little endian o[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 23 3.8 EMIF Configuration All accesses to off-DSP-chip peripherals, such as on-board SDRAM, the UART or the FPGA are performed by the DSP's external memory inte rface (EMIF). The timings and interface type for these acces[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 24 base address 2 register name register mnemonic 9010 0000h Hardware configuration register HWCFG 9011 0000h FPGA control register FCR 9012 0000h LED control register LED 9013 0000h Module control register MCR 9014 0000h I 2 [...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 25 CPUSPEED: This bit can be used by application software to determine the DSP speed version and to program the DSP's PLL accordingly. CPUSPEED CPU clock frequency 0 225 MHz 1 300 MHz FLASH_A19: This bit represents the hi[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 26 7 6 5 4 3 0 RED_LED GREEN_LED RESERVED r, w, 00 r, w, 11 RED_LED: RED_LED Encoding 00 2 off 01 2 on others reserved GREEN_LED: RED_LED Encoding 00 2 off 01 2 on 10 2 on when CE1 active, that is when Flash, PLD or FPG regist[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 27 7 6 5 4 3 0 SDA_STAT SDA_CTL SCL_S TAT SCL_CTL RESERVED r, 1 r, w, 1 r, 1 r, w, 1 SDA_STAT: retrieves the current state of the SDA line. If this bit is read as 1, the SDA line is in a logic h igh state and no device pulls t[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 28 WDG_RST: The WD_RST pin of the PLD is connected to the watch dog input of the reset generator. If the watchdog is enabled the WD_RST pin must be set to 1 at least once per second. This must be done by writing a 1 to the WDR[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 29 4 Boot Process and Default Setup of the C6713CPU After reset or power up the C6713CPU boots the Flash File System from flash memory. The Flash File System first checks, if a command from a ho st PC on the RS-232 interface i[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 30 5 Using the Flash File System The Flash File System of the C6713CPU consists of three parts:  A target-resident boot loader which initializes the C67 13CPU at startup, looks for commands on the RS-232 interface and then [...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 31 6 Description of the micro-line ® Board Connectors 6.1 Location of the Connectors For the micro-line ® connectors, Pin 1 is marked by a black sq uare in Figure 6. C9 JT AG conne c tor con necto r A con necto r B con necto[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 32 6.2 Connector Overview Table 10 gives an overview about usage of the micro-line ® connectors, including the ' classic' usage as peripheral interface as used with previous CPU boards. The cla ssic peripheral inter[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 33 shared with Default signal name Interface signal micro-line ® connector CLKX0 ACLKX0 E23 FSX0 AFSX0 E25 DX0 AXR0[1] E21 CLKR0 ACLKR0 E22 FSR0 AFSR0 E24 DR0 AXR0[0] E20 CLKS0 McASP0 AHCLKR0 E19 CLKX1 McASP0 AMUTE0 E13 FSX1 [...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 34 shared with Signal interface signal micro-line ® connector AXR0[7] FSR1 E14 AXR0[6] CLKR1 E12 AXR0[5] McBSP DX1 E11 AXR0[4] TOUT1 E29 AXR0[3] TINP0 E18 AXR0[2] Timer TOUT0 E28 AXR0[1] DX0 E21 AXR0[0] DR0 E20 ACLKR0 CLKR0 E[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 35 6.4 Pinout of the JTAG Connector Pin Signal pin signal used for A1 FPGA_TMS B1 GND A2 FPGA_TDI B2 GND A3 FPGA_TDO B3 GND A4 FPGA_TCK B4 GND A5 +3.3 V B5 GND FPGA A6 not connected B6 not connected unused A7 CPU_EMU0 B7 CPU_E[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 36 6.5 Function of the micro-line ® Connector Pins 6.5.1 Connector A Pins A1 through A32: These signals are routed to the FPGA. Usage of these signals requires either an ORSYS board support package or a custom FPGA design. Th[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 37 package or a custom FPGA design. Optionally, SDA0 can additionally be connected to the DSP's I 2 C interface #0, see chapter 7.2.5 for details. When connecte d, SDA0 has a 10K  pull-up resistor. If the board is conf[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 38 TXD : This pin is the transmit data output of the RS-232 interface. Output voltage is either -5.5 V (typical) or +5.5 V (typical). This output can be disabled by putting the RS-232 line driver in shut down mode, see chapter[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 39 DX1 / AXR0[5]: This pin has a dual function:  If configured for McBSP usage, this pin is th e data transmit output of McBSP1. All outgoing data to devices, connected to the McBSP1 is communicated via this output pin. If [...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 40 CLKS1 / SCL1: This pin has a dual function:  If configured for McBSP usage, this pin is the external input of the internal sample rate generator used for McBSP1. If the transmitter and the receiver port function is not n[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 41 DR0 / AXR0[0]: This pin has a dual function:  If configured for McBSP usage, this pin is th e data receive input of McBSP0. All incoming data from devices connected to the McBSP is communicated via this input pin. If the[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 42 FSR0 / AFSR0: This pin has a dual function:  If configured for McBSP usage, this pin is the receiver frame sync input or output of McBSP0. If frame synchronization is provided by an external device, FSR0 is an input. If [...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 43 Pins E30 and E31: These signals are routed to the FPGA. Usage of these signals requires either an ORSYS board support package or a custom FPGA design. These signals are pulled-up by the FPGA as long as the FPGA is not loade[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 44 7 Environment 7.1 Minimum Connections This chapter shows how to set up the C6713CPU for use without a micro-line ® Power Supply carrier board. Please refer to chapter 7.4 for the supply voltage limits. C9 D + - 3.3 V - V o[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 45 C9 D st andard PC RS-232 co nnector Sub-D 9 p in so cket; f its d irect l y int o a P C fr ont v iew 5 6 9 1 TxD (connect to PC 's RxD) RTS (connect to PC 's CTS) CTS (connect to PC 's RTS) RxD (connect to PC[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 46 7.2 Changing the Bo ard Configuration This chapter shows the different hardware board configurations. The factory defaults are listed below. Some configuration settings may be changed by the user and are described in the su[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 47 R1 R7 2 R7 3 R6 4 R6 6 Figure 11: Location of configuration elements (bottom side) 7.2.2 Configurin g DSP Clock Speed R81 controls the setting of the CPUSPEED bit in the PLD's HWCFG register. The Flash File System take[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 48 7.2.6 Configurin g CLKS1 / SCL1 Termination By default, a 10k  pull-down resistor (R65) is installed for CLKS1 operation. This configuration is suitable for McBSP #1 operation. For usage of I 2 C interface #1, R65 must b[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 49 7.4 Supply Voltage The C6713CPU must be supplied with a voltage of nominal +3.3 V. The integrated switching voltage regulators generate all necessary on-board voltages. CAUTION: The C6713CPU is not protected against reverse[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 50 7.9 Dimensions of the Board Figure 12 shows the dimensions of the C6713CPU. When the C6713CPU is stacked with other modules, board spacing is 14mm. C9 78.74 90.17 97.54 58.42 60.96 67.06 2.54 2.54 1, 5 1,5 6,0 5,0 3,5 maxim[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 51 2.5 4 5.71 1.2 7 5.7 1 15, 24 17. 78 5.7 1 5.7 1 17. 78 2.5 4 5.0 8 7.6 2  2.5 1.2 7 B AA A BB XP E C D EE 1394-2 1394-1 EGN D 16 10 1 1 32 1 5 1 32 1,2 7 66, 04 78, 74 Figure 13: Complete micro-line ® footprint[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 52 7.10 Spare micro-line ® Connectors The C6713CPU uses square connectors with 0.1 inch (2.54 mm) spa cing. In cont rast to previous micro-line ® CPU boards, the C6713CPU does not allow stacking other boards on top of it. Ho[...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 53 8 List of abbreviations used in this document BSP b oard s upport p ackage: a combination of software and FPGA design that provides further functionality to the C6713CPU CCS C ode C omposer S tudio –TI's development [...]

H ARDWARE R EFERENCE G UIDE MICRO - LINE  C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 54 9 Literature references Further information that is not covered in this u ser's guide can be found in the documents liste d below. References to this list are given in square brackets throughout this document. The docu[...]