Yamaha OPL3-SA3 manuale d’uso

           YMF715E OPL3-SA3 OPL3 Single-chip Audio System 3 YAMAHA CORPORAT ION May 21, 1997 Preliminary ■ ■ ■ ■ OUTLINE YMF715E-S (OPL3-SA 3) is a sin gle au dio chip that i ntegrates OPL 3 and its DAC, 16bit S igma- delta CODEC, MPU401 MIDI interf ace, joystick port, an d a 3D enhanced con troller including all th e an[...]

YMF715E                              May 21, 1997 -2- ■ ■ ■ ■ PIN CONFIGURATION YMF715E-S      100 pin SQ FP Top View 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 [...]

YMF715E                              May 21, 1997 -3- ■ PIN DESCRIPTION ISA bus interface: 36 p ins name p ins I/O t yp e Size function D7-0 8 I/O TTL 24mA Data Bus A11- 0 12 I TTL - Address Bu s AEN 1 I T T L - Address Bus Enable /IOW 1 I Sc hmitt - W rite Enab le /IOR 1 I Sc hmitt - Read E[...]

YMF715E                              May 21, 1997 -4- Multi- p ur p ose p ins : 13 p ins name p ins I/O t yp e size function SEL2-0 3 I+ CMOS - Refer to “Multi-purpose pins” sectio n MP9-0 10 I+/O TTL 2mA Ref er to “multi-purpose pins” section Others : 27 p ins name p ins I/O t yp e si[...]

YMF715E                              May 21, 1997 -5- ■ ■ ■ ■ BLOCK DIAGRAM[...]

YMF715E                              May 21, 1997 -6- ■ ■ ■ ■ FUNCTION OVERVIEW 1. Multi -purpose pin         1-1. Multi -purpose function OPL3-S A3 can su pport the variou s fun ctions lis ted below by program min g SEL2- 0 pins. A. 16- bit address decode B. EEPROM interface C[...]

YMF715E                              May 21, 1997 -7-         1-2. Pin descri ption SEL=0 SEL=1 SEL=2 SEL=3 SEL=4 SEL=5 SEL=6 SEL=7 MP0 - /MCS /MCS /EXTEN /EXTEN /MCS - /EXTEN MP1 - MIRQ MIRQ /SYNCS /SYNCS MIRQ - /SYNCS MP2 - ROM CLK ROM CLK ROM CLK BCLK_ZV A12 - A12 MP3 - ROMCS ROMCS [...]

YMF715E                              May 21, 1997 -8-         1-3. System Block D iagram                (1) SEL=1 ( Sound Card and Co mbo Card Add-in)   1. Extern al PAL(16V8 etc.) (i) connect the sign al AEN* generated by decoding SA 15-12 and AEN t o the AEN of OPL3[...]

YMF715E                              May 21, 1997 -9-   2. Master Clock Both 33.8688MHz and 24.576MHz are used or 14.31818MHz and clock m odule (ex.MK1420 by Micro Clock) are u sed.   3. O PL4 -ML/M L2 The external DAC (YAC516) is necess ary for w avetable upgrade.         (2) SEL=[...]

YMF715E                              May 21, 1997 -10-   (3) SEL=3 ( Sound Card fo r Add- in)   1. 16bit Address Decode The sig nal AEN* gen erated by decoding SA 15-12 and A EN needs to be connected to th e AEN of OPL 3-SA3. AEN RESET DRV YMF715E-S (OPL3-SA3) EEPROM 138 OPL4- ML /ML2 / IO[...]

YMF715E                              May 21, 1997 -11-   (4) SEL=4 ( for No teboo k PC)   1. 16bit Addres s Decode The sig nal AEN* gen erated by decoding SA 15-12 and A EN needs to be connected to th e AEN of OPL 3-SA3.   2. ZV Port an d OPL4-ML /ML2 I/F ZV port is supporte d by u sing [...]

YMF715E                              May 21, 1997 -12-   (5) SEL=5 ( for No teboo k PC)   1. Internal DA C The internal OPL3 and the ZV Port shares the internal DAC, w hich is very similar to the case mentioned the previous sectio n. (i) either internal OPL3 or ZV port is active at a time [...]

YMF715E                              May 21, 1997 -13- (6) SEL=7 ( for No teboo k PC, Desktop PC) AEN RESET DRV YMF715E-S (OPL3-SA3) / IOW , / IO R RESET MP6 MP7 MP8 /IOW,/IOR A11- 0 MP5-2 SA11- 0 D7-0 SD7-0 AEN SA15- 12 BCLK _ML L RCK_ML SI N_ML D7-0 /IOW /IOR A2- 0 DBDIR /IOW,/IOR SA2-0 SD7-[...]

YMF715E                              May 21, 1997 -14-         2. ISA Interface OPL3-S A3 su pports ISA Plu g and Pl ay (PnP) th at frees th e users f rom con figuri ng the I/ O address, IRQ and DMA channel. Those sy stem resources are set autom atically by the sy stem. How ever even w[...]

YMF715E                              May 21, 1997 -15-         2-2. PnP ISA Configur ation Register OPL3 -SA3 has the following Register s define d in the P nP I SA software. LDN=3, CDROM LDN=1, Jo y Stick LDN=0, SA3 Sound S y stem Card Control 0x75 0x30 0x22 0x00 LDN=2, MODEM Listed b[...]

YMF715E                              May 21, 1997 -16- Logical Device Num ber = 0 : SA3 Sound System 30h R/W Activate 60h R/W I/O port base address[15..8], Descriptor 0 (SB base) 61h R/W I/O port base address[7..0], Descriptor 0 (SB base) 62h R/W I/O port base address[15..8], Descriptor 1 (WSS[...]

YMF715E                              May 21, 1997 -17- Logical Device Num ber = 3 : CD-RO M (Optional) 30h R/W Activate 60h R/W I/O port base address [15..8], Descriptor 0 (/CDCS0) 61h R/W I/O port base address [7..0], Descriptor 0 (/CDCS0) 62h R/W I/O port base address [15..8], Descriptor 1 ([...]

YMF715E                              May 21, 1997 -18- IRQ-A : high-active, edg e-sense Index Best Acceptable1 Acceptable2 Acceptable3 IRQ 10 7,9,10,11 5,7,9,10,11 <- IRQ-B: high -active, edge-sen se Index Best Acceptable1 Acceptable2 Acceptable3 IRQ 5 5,7 5,7,9,10,11 <- DMA-A : 8bit, co[...]

YMF715E                              May 21, 1997 -19-         (4) LDN=3:CD-ROM I/O (/CDC S0): 16bit address decode Index Best Acceptable1 Acceptable2 Acceptable3 I/O 1E8h 100-1F8h <- <- Length 8 8 <- <- Alignment - 8 <- <- I/O (/CDC S1): 16bit address decode Index Be[...]

YMF715E                              May 21, 1997 -20- 3. Download Resour ce data When OPL3-SA 3 is in the Configuration state, the host can download th e resources data to EEP R OM and internal SRAM via 2 0h: Resource Data W rite. T o switch OPL3-SA3 into configuration mode, there are tw o me[...]

YMF715E                              May 21, 1997 -21- 6. DAC interface OPL3-SA 3 supports two ty pes of DAC in terface format. On e is the conventional DA C interface form at (very comm on for the cons umer audio produ ct) for OPL4-ML/ML 2. Another is th e I 2 S format for Zoom ed Video port.[...]

YMF715E                              May 21, 1997 -22-   8. Power Managem ent Following 4 functionalities are provided for APM(Advanced Po wer Management) com pliance. (1) Partial Power Dow n Mode (2) Power S ave Mode (3) Global Power Dow n Mode (4) Suspen d/Resum e Mode F ig.8-1 P ower M a [...]

YMF715E                              May 21, 1997 -23-         8-1. Partia l Power Down Mo de Functional blo cks co mprising OPL3-SA3 which are shown in Fig.8-1, are designed so they can be disabled independent of each other. SA3 control register, index 12h and 13h, implem ents these c[...]

YMF715E                              May 21, 1997 -24- 8-4. Suspend/Resume M ode There is no “read only ” or “h idden state” registers in OPL3-SA 3. This means y ou can alway s read and sav e these values bef ore power of f and can set those v alues back in reg isters after reset or po[...]

YMF715E                              May 21, 1997 -25-    9. Register descr iption         9-1. SA Sound System   9-1-1. OPL3 Listed below are the OPL3-L register for AdLib com patib ility. AdL ib base (R) Status Register port AdL ib base (W) Address port for Regi ster Array 0 Ad[...]

YMF715E                              May 21, 1997 -26- OPL3 Data Register Array 1 (R/W) Index D7 D 6 D5 D4 D3 D2 D1 D0 00 - 01h LSI TEST 04h - - CONNECTION SEL 05h - - - - - NEW3 * NEW 20 - 35h AM VIB EGT KSR MULT 40 - 55h KSL TL 60 - 75h AR DR 80 - 95h SL RR A0 - A8h F-NUM (L) B0 - B8h - - KO[...]

YMF715E                              May 21, 1997 -27-   9-1-2-1. DSP Command List ed below are the su pported comm ands of DSP defin ed Sound Blaster Pro com patibility. CMD Support Function 10h o 8bit direct mode digitized sound I/O output 14h o 8bit single-cycle DMA mode digitized sound o[...]

YMF715E                              May 21, 1997 -28-   9-1-2-2. Sound Blas ter Pro c ompatibility Mixer The table belo w is the register map of m ixer of Sound B laster Pro co mpatibility. Index D7 D 6 D5 D4 D3 D2 D1 D0 00h Reset Mixer 04h Voice Vol. Lch - Voice Vol. Rch 0 A h ----- M IC V[...]

YMF715E                              May 21, 1997 -29- MIDI Vol. ( 26h ) 0123456 7 0 mut e mute mu te mute mut e mute mu te mute 1 mut e -24.0dB -18.0dB -12. 0dB -6.0dB -3.0dB +1.5dB +4.5dB 2 mut e -18.0dB -12.0dB -6.0dB -3.0dB +1.5dB +4.5dB +4.5dB 3 mut e -12.0dB -6.0dB -3.0dB +1.5dB +4.5dB +[...]

YMF715E                              May 21, 1997 -30-   9-1-3. WSS com patible 16-bit CODEC The followings are the I/Os for Window Sound System compatibility. WSS base (R) WSS Configuratio n Register p ort WSS base + 3 h (R) WSS Status Register p o rt WSS base + 4h (R/W) WSS CODEC Index add[...]

YMF715E                              May 21, 1997 -31- WSS CODEC Indirect Reg isters (R/W) : Index D7 D 6 D5 D4 D3 D2 D1 D0 00h LSS1 LSS0 LMGE - LIG3 LIG2 LIG1 LIG0 01h RSS1 RSS0 RM GE - RIG3 RIG2 RIG 1 RIG0 02h LX1M - - LX1G4 LX1G3 LX1G2 LX1G1 LX1G0 03h RX1M - - RX1G4 RX1G3 RX1G2 RX1G1 RX1G0 [...]

YMF715E                              May 21, 1997 -32- Mixer d efault: 02h:A UX1L = 88h (m ute) 03h:A UX1R = 88h (m ute) 04h:A UX2L = 05h (+4.5dB) 05h:A UX2R = 05h (+4.5dB) 06h:DA CL = 80h (m ute) 07h:DA CR = 80h (m ute) 12h:L ineL = 88h (m ute) 13h:L ineR = 88h (m ute) 1Ah:Mono In = C0 h (mut[...]

YMF715E                              May 21, 1997 -33- Notice) 1) Set D7, D6, D4 and D3 bits to “0”. 2) In the p ow er save modes 1 , 2, the OUT L /R pins w ill keep the VREF voltage. In the power down mode, VREF voltage slow ly decays to ground on transition into this m ode, and quickly r[...]

YMF715E                              May 21, 1997 -34- Interrupt Channel configuration (R/W): Index D7 D 6 D5 D4 D3 D2 D1 D0 IRQ-B IRQ-A OPL3 MPU SB WSS OPL3 MPU SB WSS There are four dev ices (WSS (Windows Sou nd System CODEC), SB (Sound Blaster compatible portion), OP L3, MPU (MPU4 01)) that[...]

YMF715E                              May 21, 1997 -35- Interrupt (IRQ-B) sta tus (RO): Index D7 D 6 D5 D4 D3 D2 D1 D0 05h - MV OPL3 MPU SB TI CI PI This register is the status register that indicates w hich is the interrupt source o f IRQB. When an in terrupt occurs, the corresponding bit beco[...]

YMF715E                              May 21, 1997 -36- Master Volume Lch (R/W): Index D7 D 6 D5 D4 D3 D2 D1 D0 07h MVLM - - - MVL3 MVL2 M VL1 MVL0 This register specifies the m aster volum e of left channel. MVLM... Setting to “1” to this bit makes Master Volum e Left Channel muted. MVL3-0[...]

YMF715E                              May 21, 1997 -37- Miscellaneous: Index D7 D 6 D5 D4 D3 D2 D1 D0 0Ah VEN - - MCSW MODE VER2 VER1 VER0 VEN... T his bit enables the hardware volume control. Default is VEN=“1”. MCSW... This bit determ ines w heth er Rch of Mic in put or loopback of monaur[...]

YMF715E                              May 21, 1997 -38- Sound Blaster compatibility Internal State Scan out/in (R/W): Index D7 D 6 D5 D4 D3 D2 D1 D0 10h SBPDA - - - SS SM SE SBPDR SBP DA... Sound Blaste r P ower Down Acknowled gment: “1” in SBP DA ackno wledges that OPL3-SA 3 is ready for s[...]

YMF715E                              May 21, 1997 -39- i) Scan Out SBPDA=0 SBPDR=1 SBPDA=1 SM=1 SS=1 SE=1 → 0 : not r eady for scanning internal state data : inhibit fur ther D MA, internal state shutdown : ready for scan n in g internal state data : inter nal state re ad out : re ading inte[...]

YMF715E                              May 21, 1997 -40- Digital Block Partial Power Down (R/W): Index D7 D 6 D5 D4 D3 D2 D1 D0 12h JOY MPU MCLKO FM WSS_R WSS_P SB PnP This register specifies the partial power m anagement of the digital portion. T his function is to spare power dissipation in un[...]

YMF715E                              May 21, 1997 -41- Notice) In the partial power down mode, master volume is not m uted, so all analog input sources and enabled digital sources (i.e. FM, SB, WSS etc.) can be heard. Note that AUX2 inpu ts are exceptions in this regard since setting FMDAC bit[...]

YMF715E                              May 21, 1997 -42- Hardware Volume Interr upt Channel Configuration (R/W): Index D7 D 6 D5 D4 D3 D2 D1 D0 17h - - IR Q-B MV IRQ-A MV -* * * The Hardware Volume can source interrupt. This register indicates which interrupt channel will be used. If IRQ-A MV=?[...]

YMF715E                              May 21, 1997 -43-   9-4. CD-ROM The follow ing pins are f or IDE CD-ROM interface w ith PnP supported. /CDCS0... chip select for CD-ROM /CDCS1... chip select for CD-ROM CDIRQ... interrupt sig nal Other signals needed for CD-ROM mu st b e generated b y the[...]

YMF715E                              May 21, 1997 -44- ■ ■ ■ ■ Electrical Characteristics         Absolute Maximum Ratin g s   Note : V DD =DV DD =AV DD , V SS =DV SS =A V SS =0[V]   Recommended Oper ating Conditions   Note : DV SS =AV SS =0[V]   DC Characteristics 1 (D[...]

YMF715E                              May 21, 1997 -45-   Note : DV SS =AV SS =0[V], T OP =0~70 ℃ , AV DD =5.0[V] *1 : A pp licab le to s chmitt input pins w ithout /VOLUP, /VOLDW. *2 : Applicable to /VOLUP and /VOLDW pins. *3 : W he n V OL1 =max. 0.5V, th e value into the brack ets is spec[...]

YMF715E                              May 21, 1997 -46- AC Character istics CPU Interface & DMA BUS Cycle :Fig.1,2,3,4,5,6,7,8   Note : DV SS =AV SS =0[V], T OP =0~70 ℃ , DV DD =5.0 ± 0.25[V] or 3.3 ± 0.30[V], AV DD =5.0[V] *... The valu e into the brackets is s pecified at DV DD =3.3[...]

YMF715E                              May 21, 1997 -47- Miscellaneous Note : DV SS =AV SS =0[V], T OP =0~70 ℃ Duty Search Point is 1/2 DV DD . *... DV DD = 5.0 ± 0.25[V] or 3.3V ± 0.30[V], AV DD = 5.0 ± 0.25[V] Pow er Save1 : S A3 Control Regist er, index 01h , PSV=PDX=1 Pow er Save2 : S A[...]

YMF715E                              May 21, 1997 -48- F ig.2 I/ O Re ad Cy c l e Valid Valid D7-0 /DACK3,1,0 (A15-12) A11-0 /I OR t AKH t AKS t RDH t ACC t RW t AH t AS F ig.1 I / O W r it e C ycle Valid D7-0 /DACK3,1,0 (A15-12) A11-0 /I OW t AKH t AKS t WDH t WDS t WW t AH t AS[...]

YMF715E                              May 21, 1997 -49- F ig.4 Valid 8b it M on o & ADP C M DM A R ea d C ycle D7-0 DRQ3,1,0 /DACK3,1,0 /I OR t DGH t RDH t ACC t RW t HR t SF F ig.3 8b it M on o & ADP C M DM A W r it e C ycle D7-0 DRQ3,1,0 /DACK3,1,0 /I OW t DGH t WDH t WDS t WW t HR t [...]

YMF715E                              May 21, 1997 -50- F ig.6 16b i t S t er eo DM A C ycle DRQ3,1,0 Righ t/ Low Byte L eft/Hig h Byte D7-0 /I OW,/IOR /DACK3,1,0 t NX L eft/L ow Byte Right/Hig h Byte 8b it St er eo or 16b it M on o DM A C ycle DRQ3,1,0 Right/Hig h Byte L eft/L ow Byte D7-0 /I [...]

YMF715E                              May 21, 1997 -51- S e ri a l A u d i o I n t e rf a c e L RCK SI N BCLK t LRH t DH t DS 1/f BCK F ig.9 F ig.8 t RST Re s e t Pul s e Wi dth RESET F ig.7 E xt er n a l I n t er fa ce (E xt er n a l Syn t h esizer , C D R O M , M od em ) Valid (A15-12) A11-0 [...]

YMF715E                              May 21, 1997 -52- Analog Character istics Analog Input Characteristics Note : DV SS =AV SS =0[V], T OP =25 ℃ , DV DD =AV DD =5.0[V], fs =44.1kHz Analog Output Characteristics Note : DV SS =AV SS =0[V], T OP =25 ℃ , DV DD =AV DD =5.0[V], fs =44.1kHz Item[...]

YMF715E                              May 21, 1997 -53- ■ ■ ■ ■ External Di mensions Note : The LSIs for surface m ount need especial consideration on storage and soldering conditions. For detailed inform ation, please contact y our nearest agent of y amah a.[...]

YMF715E                              May 21, 1997 -54- IMPORTANT NOTICE 1. Yamaha reserv es the r ight to make changes to its Produc ts and to this document without notice. The information contained in this doc ument has been car efully chec k ed and is believ ed to be reliable. However, Yamah[...]