Arm Enterprises GP4020 manual

GP40 20 GP S Ba se band Pr oces sor D esi g n Man ual Publication Nu mber: DM 5280 Issue: 3 Re visi on : 002 Issued: Janu ary 2002 Zarlink Se miconductor , Chene y Manor Swindon, Wiltshire, U nited K ingdom, SN2 2 QW[...]

ii Manu al Revision History Vers ion Re visio n Da te Up date Su mmary 1 001 Fe brua ry 20 00 Fi rst Ver sion 2 00 1 Aug ust 20 00 GN D a n d VD D p ins mar ked as t yp e “PW R” in t abl es 2 .2 and 20 .1. Modif i ed T EST MOD E ( pin 74 ) def in iti on. R emoval of extr a " TM " an d " ® " tr ade- mark in gs thr oug hout. [...]

GP4020 GPS Baseband Processor Design Manual iii Contents Page Co nte nts ....................................................................................................................... ..................iii Re late d P rodu cts and Doc ume nts................................................................................................. .[...]

iv GP4020 GPS Baseband Processor Design Manual 8.3 DM AC Tri gg e ring ................................................................................................................ 99 8.4 Cautionary No tes .............................................................................................................. 10 1 9 GENE RA L PU RP OSE INP[...]

GP4020 GPS Baseband Processor Design Manual v 19.2 GP4020 F ir e fly MF1 A ddress M ap ..................................................................................... 183 20 INPU T / OU TPU T PIN CH AR A CTERIS TICS ................................................................. 185 20 .1 Pin T ype s ........................................[...]

vi GP4020 GPS Baseband Processor Design Manual Docum ent Refer ences Re fer e nces to t he following d ocumen ts are made w ithin the GP4020 GPS Ba seband P roce ssor De si gn Manua l: 1) "ARM7TDM I Technical Re f e r e nce M anual " ARM DDI 0029F , Rev 4 Copyrigh t  ARM Limited 20 01. Ar m Lt d. Do cum ent at io n w ebs it e ( ht t p:[...]

1: Int r oduc tion GP4020 GPS Baseband Processor Design Manual 1 1 INTRODUCTION 1.1 GP4020 GPS Baseband Pr ocessor Ov erv iew This de si gn manua l describe s the GP4020 GPS Base band Processor , which is base d on the Zarlink Se mi condu ct o r Fire f ly M F1 M i c rocontroller Co re ( r e f. Firefly MF 1 Core Design Manua l (DM5003 ) ), and a c u[...]

1: Int r oduc tion 2 GP4020 G PS Ba seband P rocessor Des ign M anual 1.3 Fun ctional Descripti on 12 CHANNEL GPS CORRELATOR RAM (2k x 32) MPC UIM ARM7TDMI MICRO JTAG UART1 DMAC TIC SSM INTC Firefly MF1 Core SYSTEM CLOCK GENERATOR UART2 BSIO GPIO PLL BOOT ROM (512 x 16) GPIO[7:0] BSIO U1RXD U1TXD GPIO[7:0] U2TXD U2RXD SIGN0 MAG0 SAMPCLK CLK_T CLK_I[...]

1: Int r oduc tion GP4020 GPS Baseband Processor Design Manual 3 1.3. 1 A RM  P rocesso r (A RM7T DMI ) The ARM7TDM I is a 32 -bit RISC microp rocesso r core de signed b y Advance d RI SC Machine s (ARM ) . I t use s a series 7 micropro cessor C ore, wi th the fo llowing fun ctional e xte nsions: • Th um b (16 - bit ) i ns tr u cti o n s et ?[...]

1: Int r oduc tion 4 GP4020 G PS Ba seband P rocessor Des ign M anual De tai ls ca n be found in s ection 6 "B µ ILD SER IAL INPU T OUTPUT ( BSI O) INTER FACE" on page 33. 1.3. 5 12 Chan nel Correlato r (CORR) This m odu le contains 1 2 channe ls of P RN code correlators for spre ad-spectrum correlation of 12 s imultaneous signals. E ach[...]

1: Int r oduc tion GP4020 GPS Baseband Processor Design Manual 5 1.3. 9 Gen eral Purpose Inpu t Output (GPIO) This m odu l e prov i de s e ight I/O pins, w hi c h may be b i t or byte addresse d and configured i n a l atche d or t r ans parent mode. W he n in byt e mode , buffer full/e m pty f lags are a vailable whi ch can be use d to ge nerate an[...]

1: Int r oduc tion 6 GP4020 G PS Ba seband P rocessor Des ign M anual Since the in t e rnal SRAM i s hi gh-spe ed, it can be a ccesse d with Zero wait-state s through the M e m ory Pe ripheral Cont roll e r . Refer t o section 11 "ME MORY PERI PHERAL C O NTR OLLER (M PC)" on p age 1 09, for more i nfor mati on. 1.3. 14 Real T ime Clock (R[...]

1: Int r oduc tion GP4020 GPS Baseband Processor Design Manual 7 Further de tail s of the function and p rogramming S yste m Se rvices Modu le can be found in Sec tions 2 and 8 o f the "Firefl y M F1 Core D esign Manual" DM5003, avai lable from Za rlink S emi conductor . 1.3. 17 System Ti mer/Count ers (SYS T IC) Two dua l indepe ndent 32[...]

1: Int r oduc tion 8 GP4020 G PS Ba seband P rocessor Des ign M anual 1.4 T y pical A pplication ANTENNA 470 470 1k SAMPCLK SIGN0 MAG0 (58) (59) (61) (62) (63) (64) (56) GP4020 (84) BuILD _CLK M_CLK POWER_GOOD RF _PLL_LOCK SAMPCLK SIGN0 MAG0 CLK _I CLK _T BOOT R OM SRAM (2K X 32) FIRE FLY MF1 MICROCO NTROLLER UART 1 ARM7 TDMI FLASH EPROM (16-BIT ) [...]

1: Int r oduc tion GP4020 GPS Baseband Processor Design Manual 9 Figure 1.2 above shows a typ i ca l GPS re ceive r e m ploying a GP 2015 RF front–end, and a GP4020 correla tor. The RF sect i on, GP2015, performs d own conve rsion of the L1 (1575.42MHz ) signal f o r digita l baseband p r oce ssing. The re sult a nt signa l is the n correlated in[...]

1: Int r oduc tion 10 GP4020 GPS Baseband Processor Design Manual Thi s page intentional ly left bl ank.[...]

2: G P4020 Package and El ectrical Conn ections GP4020 GPS Baseband Processor Design Manual 11 2 GP40 20 PACK AGE A ND ELEC TRIC AL CONNE CTIONS 2.1 GP4020 100 -pin Packa ge Dimen sions The GP4020 GPS B aseband P rocessor is available from Zarlink Se m i c onductor in a 1 00-pin gull-w i ng Thin Quad Flat Package (TQFP ). Order i ng information for[...]

2: G P4020 Package and El ectrical Conn ections 12 GP4020 GPS Baseband Processor Design Manual Figure 2.2 GP4020 100-pin p ackage ou tline draw i ng[...]

2: G P4020 Package and El ectrical Conn ections GP4020 GPS Baseband Processor Design Manual 13 Symbol Dimens ions i n millim etres MI N N om in a l MA X A 1.4 0 1.60 A1 0.0 5 0.15 A2 1.3 5 1.45 D 15. 80 16.20 D1 13. 80 14.20 D3 12. 00 E 15. 80 16.20 E1 13. 80 14.20 E3 12. 00 L 0.4 5 0.75 e 0.5 0 b 0.1 7 0.27 c 0.0 9 0.20 Table 2.1 GP4020 100-pin pa[...]

2: G P4020 Package and El ectrical Conn ections 14 GP4020 GPS Baseband Processor Design Manual Pi n No . Signal N ame T ype Circui t Bl oc k De scr ip tion N o t es 24 SDATA[7] I/O MPC System Dat a bi t 7 1 25 NS OE I/O MP C S y s t em O utput En ab le - Ac ti ve Low 1 26 NSW E[1] I/O MPC S y st em W rite En abl e bi t 1 - Ac ti ve L ow 1 27 NSW E[[...]

2: G P4020 Package and El ectrical Conn ections GP4020 GPS Baseband Processor Design Manual 15 Pi n No . Signal N ame T ype Circui t Bl oc k De scr ip tion N o t es 61 SIG N0 I COR R S ampl ed Si g n (p olari t y ) d ata f r om RF Fr ont- en d 62 MAG 0 I COR R S ampl ed Mag ( am pl itud e) d at a fr om R F F ront -en d 63 SAMP CLK O CO RR S ampl e [...]

2: G P4020 Package and El ectrical Conn ections 16 GP4020 GPS Baseband Processor Design Manual Pi n No . Signal N ame T ype Circui t Bl oc k De scr ip tion N o t es 88 TDO / bdiag[2] / XBurs t I/O JTAG / SSM JT AG Te st Da ta Out / S SM D i a gn ost ic broadcast ou tput b di a g[2] / S yste m Te st con trol input XBu r s t 6 89 TMS / bdiag[3] / XCo[...]

2: G P4020 Package and El ectrical Conn ections GP4020 GPS Baseband Processor Design Manual 17 TEST (pin 67) T ESTM OD E (pin 7 4) TEST FUNCTI ON GND (0) GND (0) N o rm al Operation VDD (1) GND (0) Fire f ly Macrocell t e s t mode GND (0) VDD (1) Fire f ly System t e st mode VDD (1) VDD (1) UIM Logic test mode De tai ls of ALL test modes are cove r[...]

2: G P4020 Package and El ectrical Conn ections 18 GP4020 GPS Baseband Processor Design Manual iii) NIC E = Hig h an d NT RS T = Lo w: Fir e fly MF 1 Syste m Te st Co ntrol input signal s are connected t o pins 8 6, 87 , 88, and 89 as fol l ows : Pin 86 = Xreq Pin 87 = X W rite Pin 88 = Xburst Pin 89 = XCon Syste m test i nputs are used in Fi refly[...]

3: ARM7T DMI TM Microp r o cessor GP4020 GPS Baseband Processor Design Manual 19 3 A RM7TDMI MICROPROCESSOR Th e ARM 7T DM I is a m e m b er of t he A dv an c ed R I SC Ma chi n es ( AR M) f am il y o f g ener a l - pur po s e 32 - bit microproce ssors, which o ff e r hi g h per formance for very low powe r cons umption and pri ce . The ARM ar chit[...]

3: ARM7T DMI TM M i croprocesso r 20 GP4020 GPS Baseband Processor Design Manual If a 16-b it arch itecture on ly has 16 -bit inst ructions, a nd a 32 -bit arch itecture only h as 32-bit instruction s, then ove rall the 16-b it archi t e ctur e will have be t ter code de nsity. A lso 16 - bit will ha ve better than one half the pe r forman ce of t [...]

3: ARM7T DMI TM Microp r o cessor GP4020 GPS Baseband Processor Design Manual 21 M nemonic Instr ucti on Actio n AD C Ad d w ith c a rry Rd := Rn + Op2 + Car ry ADD Add Rd := Rn + Op2 AND AND Rd := Rn AND O p2 B Br anch R15 := ad dr e s s BIC Bit C lear Rd := Rn AND NOT Op2 BL Br anch wi th Li nk R14 := R 15, R 15 := ad dress BX Branc h and E xch a[...]

3: ARM7T DMI TM M i croprocesso r 22 GP4020 GPS Baseband Processor Design Manual M nemonic Instr ucti on Actio n Lo/Hi regi ster oper ands Condi tion co des se t AD C Ad d w i th Ca rry Rd := Rd + Rs + C Lo Y e s ADD Add Rd := Rn + Rs Lo/ H i Ye s* AND AND Rd := Rd AND Rs Lo Yes ASR Arithmetic Shif t Right Rd := Rd ASR Rs L o Yes B Unc ondi ti onal[...]

3: ARM7T DMI TM Microp r o cessor GP4020 GPS Baseband Processor Design Manual 23 • Syste m (sys) A privilege d user mode for the operating syste m • Unde fi ned (un d) Entere d whe n an unde fi ne d instruction is ex ecute d Mode change s m ay be m ade unde r so ft wa re con tr o l, or ma y be b rought about b y ex t e rnal i n terrupts or ex c[...]

3: ARM7T DMI TM M i croprocesso r 24 GP4020 GPS Baseband Processor Design Manual System & Use r FIQ Superv isor Abor t IRQ Undef ined R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 SP SP_fiq * SP_s v c* SP_ ab t * SP_ir q * SP_ und * LR LR _f iq * L[...]

3: ARM7T DMI TM Microp r o cessor GP4020 GPS Baseband Processor Design Manual 25 An int errupt impul se to t he ARM 7TDMI will cause it to e xit SLEEP m ode. I n cert a i n cir cumstances, t his m ay cause th e ARM7TDMI to e nt er an UNDEF ( Undefi ned Instr uction) t rap ( to a d dr ess 0x04). I n order to r etur n t o n orm al progra m co ntrol, [...]

3: ARM7T DMI TM M i croprocesso r 26 GP4020 GPS Baseband Processor Design Manual Thi s page intentional ly left bl ank.[...]

4: Boot ROM GP4020 GPS Baseband Processor Design Manual 27 4 BOOT ROM 4.1 Fun ctional Descripti on The GP4020 Boot R OM is an internal part of t he IC. Th e code i n t he Boot ROM will a ll ow t he GP4020 base d GPS r ecei ver t o u p-l oa d a sof t w ar e ro uti ne i nt o RA M f rom a n ext er n al d at a so u rc e ( e. g . a P C), a nd r u n t h [...]

4: Boot ROM 28 GP4020 GPS Baseband Processor Design Manual 0000, and the ROM space from 0x6000 000 0. The ARM7TDM I will then be gi n exe cut ion of code downloade d to the I nternal RAM , s t a rting a t ad dress 0x 6000 0000 . Th e E XT _N CS0 bi t i n t he I O _R EV r eg i st er ( wi t hi n t he P CL) c an t h en b e s et s o t h at Fir ef l y N[...]

4: Boot ROM GP4020 GPS Baseband Processor Design Manual 29 HEADER BYTE 1 (MSB) HEADER BYTE 2 HEADER BYTE 3 (LSB) DATA BYTE 1 Header Bytes 1, 2, 3 produce 24-bit number indicating total number of Data Bytes (N) to be received. Byte 1 = Most Significant. DATA BYTE 2 DATA BYTE N-1 DATA BYTE N DATA BYTES TIME Fi gure 4.1 Boo t R OM UART Down load Data [...]

4: Boot ROM 30 GP4020 GPS Baseband Processor Design Manual Thi s Page intenti onall y l ef t bl ank.[...]

5: T h e B µ ILD BUS GP4020 GPS Baseband Processor Design Manual 31 5 The B µ ILD BUS The GP4020 Base band Pro cessor CPU subsys tem is i nt e rnally b ased ar ound the B µ IL D bu s. T he AR M7 TD MI processor i s conne cted to pe ripherals through i ts B us for µ Controll er I nt eg r ati o n i n L ow - Powe r D esigns (B µ ILD ). Although t[...]

5: T h e B µ ILD BUS 32 GP4020 GPS Baseband Processor Design Manual Exa m ple sl a v e dev i c es ar e: • UART • Mem ory / Periph eral Contr oller • Ge ne ral Pu rpose Inpu t Ou tpu t 5.3 Bus Signals The B µ ILD bus, inte rnal to t he GP4020 has ful l 32-bit u n-multiplexe d address a nd d at a busse s, b_ad dr<31:0> and b_data<31:[...]

6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 33 6 B µ ILD SERI AL INPU T OUTPUT (BSIO ) INTERFACE 6.1 Overv iew A 3- w ir e se rial input/output is include d i n the GP4020 to al l ow se rial dat a co nnection to any device wi t h a thre e-pin s eri al i nt er f ac e. Th e BS IO pi ns ar e m ult i pl exed wi t h t h e G en er al P[...]

6: BSIO Interface 34 GP4020 GPS Baseband Processor Design Manual 6.1. 3 A rch itect ure BSIO_SS[0] BSIO_SS[1] BSIO_DATA BSIO_CLK GP4020 BSIO SERIAL INTERFACE CS CS CLK CLK DATA DATA IN EEPROM LCD DATA OUT Figur e 6.1 Using B µ I LD Serial Input Outpu t ( BSIO) with EEPROM and LCD pe ripher a l s 6.2 Operational Descr iption A co nt r ol/ s ta t us[...]

6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 35 • After all data ha s bee n sent, s ince there is no read da ta, a re ad data interrupt is gene r ated imme di a tely. If reading dat a, a re ad inter r upt w ould be ge nerated afte r each f our by tes o f data a re read and a f ter the l as t byte of data is read. Th e B SI O c on[...]

6: BSIO Interface 36 GP4020 GPS Baseband Processor Design Manual READ BU FFER WRITE BU FFER FREQ UENCY DIV IDER SLAVE SELECT LOGIC INT ERRUPT CONT ROL SEQ UENCER status status BSIOCLK BSIODATA BSIOSS[0] INT EXTERNAL INTERFACE B_CLK Status Register Config & Transfer Registers Status Slave Select Read Buffer Control Write Buffer Control SCLK EN S[...]

6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 37 N SCLK SLAVE DATA IN SLAVE DATA OUT SS0 - SS1 High Z 1 2 3 4 N TSERCDC TSERDOD (N-5)SCLK TSERCEC 1 2 3 4 (X-5)SCLK X TSERSU TSERHD Note: Last SCLK cycle shown for reference only - not actually generated in BSIO Figure 6.3 BSIO R ead Operation Timing Diagram N SCLK SLAVE DATA IN SLAVE [...]

6: BSIO Interface 38 GP4020 GPS Baseband Processor Design Manual SCLK SDIO DATA OUT SDIO DATA IN SCLK SDIO DATA OUT SDIO DATA IN SCLK SDIO DATA OUT SDIO DATA IN WRPOL = 1, RDPOL = 0, CYCDELAY = 0 SCLK SDIO DATA OUT SDIO DATA IN WRPOL = 1, RDPOL = 0, CYCDELAY = 1 WRPOL = 0, RDPOL = 0, CYCDELAY = 1 WRPOL = 0, RDPOL = 0, CYCDELAY = 0 SCLK SDIO DATA OU[...]

6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 39 Standard and P age Mode s, w it h the width of t he Cont rol W ord be ing con figurable be t we en 2-bits and 32 -bits via t he CW ORD bit s . In Standa r d Mode , the star t of an Operation is de f ine d as whe n the first wo rd is wr itt e n to the Re ad/Write Buffer. In Page Mode, [...]

6: BSIO Interface 40 GP4020 GPS Baseband Processor Design Manual SSEL OPERATION SS0 - SS1 SCLK_INT 01H 00H 02H 03H 03H 00H Note: ENPOL = 0000 Enable Slave Enable Slave Enable Slave Enable Slave Figur e 6.7 B SIO SCLK P olarity Timing SCLKON in the Configuration R egiste r all ow s SCLK_ INT to be stoppe d during a n Ope rati on . 6.4 BSI O Slave S [...]

6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 41 6. 5 BSIO Int errup t Co nt rol Th e Ac t iv e H i gh I N T out p ut i s pr o vi d ed t o al l ow t h e BS IO t o o p er at e i n an i nt er r u pt d ri v en en v ir o nm ent . T h e f i v e int e rrupt so urces a re the W RREA DY, RD READY, W R I TER R an d REA DERR bits in the Statu[...]

6: BSIO Interface 42 GP4020 GPS Baseband Processor Design Manual W h en t he S equ en cer a s ser t s CW O RD_ EN, t he C ont r ol W or d is sh if t ed out a t SDO p ri or t o any d at a t o be wri tt en fr om the FIFO. C W ORD_WR will be set when a Contr ol W or d i s writt e n to t he Control W ord Re gi ster, a nd will be cl eared at the end of [...]

6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 43 SHIFT CLOCKS rx_clk tx_clk shift_rx shift_tx sclkx2 RWPOL SSEL WRITE COUNTERS TXWORD WRSIZE shift_tx end_of_tx OPERATION sclk_int wfifo_wr OPERATION end_read tri_state_en SCLK And Ext Select sclk_en ext_sel SSLEAD SSLAG OPERATION sclkx2 end_write SELBYTE cword_en CWORD CWORDSEL end_wr[...]

6: BSIO Interface 44 GP4020 GPS Baseband Processor Design Manual The S eque nc e r enables SCLK and the Slave Se l e ct Logic by means of SCLK_EN and ex t_sel r e spective l y. T he bits SS LEAD in the Con fi gu ration Re gi s ter sele ct a de lay be twee n the ex ternal se lect be ing ac ti ve an d SCLK be ing enable d of betwe en 1 to 4 SCLK cycl[...]

6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 45 Bit Mnemoni c Descr iption Reset Value R/W 10: 7 SCLKFR E Q SCLK Fr equenc y. Selec t th e fr equ enc y of SC LK , bet ween B_ CLK/ 512 to B_CL K/2 i n nine incre men ts. SCLKFR EQ = 0 000 s elects B _CLK/2 , SCLKFR EQ = 0 001 s elects B _CLK/4 , SCLKFR EQ = 0 010 s elects B _CLK/8 Un[...]

6: BSIO Interface 46 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c Des cript ion R eset Value R/W 9:0 RDSIZ E R ead S iz e. W he n writ t en c onfig ur es t he n umb er o f bytes / words to b e read in t he c urr ent op e r at ion. W ith R DSIZE = 0000 00 0000 f or b yt e s /w ords = 0 t o RD SI ZE = 1111 11 1111 f or b ytes /w or[...]

6: BSIO Interface GP4020 GPS Baseband Processor Design Manual 47 6.9. 5 BSIO Status Regis ter - B S IO_S T A T - Memory Offse t - 0x0030 Bit No . M nemoni c Des crip ti on Res et Value R/W 31: 8 Reserved All = 0 R 7O P C O M P Op erati on C om pl ete: S et onc e c urr ent op e r ati on h as comp l eted. Cl ear ed by R ead of S tat us R eg. 0R 6 OPE[...]

6: BSIO Interface 48 GP4020 GPS Baseband Processor Design Manual 6.9. 7 BSIO Read /Writ e B uf fer Register - RWBUF - Memory O ff se t - 0x0038 Bit No . M nemoni c Descri pt ion Res et Value R/W 31: 0 R W BUF F 32-bit R ead / W rite b uf fer, f o r wor d t o b e s ent and r ec eived . D a t a Tr ansf er c an b e eith er byt e ori ent ed, or b ased [...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 49 7 12 -C HANNEL CORRE LATOR (CORR) 7.1 I nt r od u ction The 12-Channe l Cor relator fo rms the GPS-spe c ific module of the GP4020 GPS Baseband Proce ssor. It comprise s 12 para ll el Spread-spe ctr u m signal tr a cking modules, includ i ng Car ri er offse t mixe r s , C/A c[...]

7: 12-Ch annel Correl ator 50 GP4020 GPS Baseband Processor Design Manual TIMEBASE GENERATOR MEAS_I NT ACCUM_INT CLOCK GENERATOR SAMPLE L ATCH SIGN 0 / MAG0 SIGN 1 / MAG1 SAMPCLK M_CLK (from SC G) TRACKING MODULE 0 TRACKING MODULE 1 TRACKING MODULE 2 TRACKING MODULE 3 TRACKING MODULE 11 TIC MU LTI -PH ASE CLO CKS MU LTI -PH ASE CLO CKS MU LTI -PH A[...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 51 7.1. 3 Raw-T imemark Gen erato r The R aw Tim e mark ge nerator ge nerates two esse nti a l s ignals: 1) CK100kHz . This 100kHz clock is de rived f ro m M_CLK. This cl ock is only a s accu rat e as the re ceiver TCXO att a ched to the RF front-e nd, and he nce cannot be re-sy[...]

7: 12-Ch annel Correl ator 52 GP4020 GPS Baseband Processor Design Manual operations to the code and carrier DC O’s are 32-bit data transfe rs, in w hich the High 1 6- b it word mu st be wr i tte n imm e diate l y before t he low 16-bit wo rd. Note that the write cycle to write cycle delay of 300ns re f e rr e d to in the Microproce ssor I n terf[...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 53 The ind ividual sub–b locks i n the tr a cking mod ul e s are : 7.2. 1 Carrier DCO Th e Car r i er DCO , whi c h i s cl ock ed at th e SA MPC LK fr eq uen c y, i s us ed t o s y nt hes i s e th e di gi t al Lo cal Os ci ll at o r signal re quired to b ri n g the i n put sig[...]

7: 12-Ch annel Correl ator 54 GP4020 GPS Baseband Processor Design Manual output is 2.046 MHz , t o give a ch i p rate of 1.023 MHz and is se t by l oad i ng the 25 -bit registe r CHx_CODE_DCO _I NCR . It i s p rogrammed w ith a re solution o f 8 5·14949 m Hz whe n used w i th a GP2015 /GP2010 f ront end. The very fine resolution is aga in nee ded[...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 55 7.2. 5 Carrier Mixers The C arrier Mixe rs multiply the digital i nput signal by the Carrie r DC O digi t al loca l osc i lla t o r t o ge nerate a signa l at baseband. B oth the I and Q Ca rrier DC O phase s are directed to the appro priate m ixe rs. The mixing of the Carrie[...]

7: 12-Ch annel Correl ator 56 GP4020 GPS Baseband Processor Design Manual 2) Pro ce ss p se udo -ran ge s to g ive the na vig atio n so lu tio n an d fo rm at i t in a fo rm su ita b le fo r th e u se r. In orde r for a Naviga t ion S olut i on to be achieve d, all o f the pse udo-range s mus t h ave e x act ly the same clock error. This c l ock er[...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 57 the re ceived sig nals the refore, a local l y gene rated code must be chose n to pre cise l y match the spre adi n g co de type , ra te, a nd pha se . Th i s p at t er n is t h en m ul ti p li ed bi t- b y- bi t wi t h t he i n c omi n g d at a str eam an d t h e res u lt s [...]

7: 12-Ch annel Correl ator 58 GP4020 GPS Baseband Processor Design Manual CHX_CODE_I NCR_L O / _H I r e gi ste r s t o st ee r t he Code DCO and gradu all y br i ng the gold code phase t o the r ight value. 7.3. 2 Sign al Tracki ng The inco ming GPS signal will ex hibit a Dopp l e r shift that varie s with time due to the non-uniform mot ion of t h[...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 59 milliseconds, an im p roved first gue ss for l ocal time could include an allowance f o r t h i s de lay t o reduce the i tera tion time late r. By using t he data t o tim e -tag the TIC , along w it h the va l ue s of the Epoch co unter , the Code gene rator phase, and the C[...]

7: 12-Ch annel Correl ator 60 GP4020 GPS Baseband Processor Design Manual iv. Release the re l e vant CHx _RSTB bits of the RESET_CONTROL register t o make the channe l acti ve . W h en t he c od e cl oc k i s i nhi b it ed (t o sl ew t he co d e p has e) , t h e I nt eg r at e a nd Dum p m od ul e i s hel d at r eset . I t wi ll start to accu mula[...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 61 For t he poll ed m e th od, t he ACCUM_STATUS_ A regist e r is always read fo llowin g every ACCUM_INT. I n addition, th e ACCUM_STATUS_B register i s r e ad on each ACCUM_INT to e ns ure no Accumulated Dat a ha s been m iss ed and to check the TIC bit (along with se ve r al [...]

7: 12-Ch annel Correl ator 62 GP4020 GPS Baseband Processor Design Manual The A nal ogue delay t hrough the RF Front - e nd of the GPS re ceiver is se t by such param e ters as g roup delay in filt e r s. For the bandw i dths u sed for C/A code will be i n th e region of 1 to 2 µ s. T hi s will nor mally swamp the d i gita l delay, but this c an b[...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 63 1. reading at TIC 0 : CHx_CARR_DCO _PHASE 0 = PH 0 2. re ading a t T IC 1 : CHx_CARR_DCO _PHASE 1 = PH 1 CHx_CARR_CYCLE 1 = K 1 + 1 3. re ading a t T IC 2 : CHx_CARR_DCO _PHASE 2 = PH 2 CHx_CARR_CYCLE 2 = K 2 + 1       × = + + = + + × = ∆ + − 2 ) ( 2 )[...]

7: 12-Ch annel Correl ator 64 GP4020 GPS Baseband Processor Design Manual 7.5. 1 Write Cycl e T o Read Cycle Timin gs As de scribed pre viously, the inte rnal write cycle of the Corre lat o r take s 300ns . O n l y on ce the write cycle is co m plete will t he correlator addre ss decode rs swi t ch to de coding the current addre ss. The correlator [...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 65 Addr ess Offs et Regist er D ir ect ion Functi on 0x1C 0 t o 0 x1D C ALL C ontr ol (s ee Tabl e 7.3 ) (s ee Tabl e 7.3 ) 0x1E C TI MEMARK _C ONT ROL W ri te C onfi gur e R aw T im emar k out pu t 0x1F 0 TE ST_C ONT RO L W r ite Set- up c or r elat or t est mod es 0x1F4 M ULTI[...]

7: 12-Ch annel Correl ator 66 GP4020 GPS Baseband Processor Design Manual 7.6. 2 T racking Chann el Data A ccumu lat io n Registers Each T racking cha nnel ha s the Data Ac cumulat ion registe rs as shown in Tabl e 7. 4 on pa ge 67 . Each addre ss has an inde pende nt r e ad and w rit e function. Comp l e te address o ffset for e ach Cha nnel Contr[...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 67 Addr ess Offs et Regi ster Dir ect ion Fun ctio n CHx_ Accu mula te + 0x0 0 I_T RAC K READ Int egr ate and Du mp V al ues f o r I tr ac ki ng arm in corr el at or c han nel X. CODE_SLE W _COUNTER WRI TE S e ts num ber o f c o de ha lf-ch ips to slew t he C/A code ge nerato r [...]

7: 12-Ch annel Correl ator 68 GP4020 GPS Baseband Processor Design Manual The registers are list e d in alphabe t ica l o rder and no t in add ress o rder to allow e asy refe rence t o e ach sect ion. Un l es s ot h er wi s e st at ed t h e L SB is bi t 0 a n d t h e MS B is bi t 1 5 or as f ar u p t h e r egi st er a s t h er e i s dat a . N ot e [...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 69 Bit No M nemoni c Des cript ion R eset Value R/W 14 DIS CIP 1 T he DISC IP 1 b it i n dic ates t he l ev el on th e DI SCI P i np ut pin at t h e ti me this r ead occ urs . I t m ay b e us ed t o i nter f a c e a har dw ar e c ondi ti on ( suc h as a r ead y fl ag f r om a U [...]

7: 12-Ch annel Correl ator 70 GP4020 GPS Baseband Processor Design Manual 7.6. 5 A CCUM_S T A T US_C Regi ster - Read Address offset 0x200 ACCUM_STATUS_ C i s a regi ster c on taini ng the state of twelv e st atus bit s sampled and latch ed on the active edge of e v e r y ACCUM_I NT (as f o r ACCUM_STATUS_A). T hey can also be sampled and l atch e [...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 71 7.6. 7 CHx_CARRIER_CY CLE_CO UN T ER Reg ister - Offset <CHx_Con trol> + 0x 08 MULTI _CA RRI ER_CYCLE _COUNT ER Reg ister - Offse t (0x180 + 0x08) ALL _CARRIER_CYCL E_COUNT ER Register - Offset ( 0x1C0 + 0 x08) Bit No. Mnemonic Description Reset Valu e R/W 15: 0 Not us [...]

7: 12-Ch annel Correl ator 72 GP4020 GPS Baseband Processor Design Manual 7.6. 10 CHx_CARRIER_DCO _INCR_HI GH Register - Offset <CHx _Control> + 0x0C MULTI _CA RRI ER_DCO_I NCR_HIGH Regi ster - Offset 0x180 + 0x0C ALL_CARRIER_DCO _INCR_HIG H Regi ster - O ffset 0x1C0 + 0x0C The _CARRI ER_DCO _INCR_HIG H Re gi st er contain s the 10 Mos t S i [...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 73 Bit No . M nemoni c Des cript ion R eset Value R/W 15: 10 Not us ed '0' when r ead 0 R 9:0 C H x _C ARRI ER _DCO _PH ASE [ 9:0] Bit s 9 :0 o f the 10- bit C arr ier DCO P h ase C ou nt. 0 x000 R Tabl e 7.15 C O RR CHx_CARRI ER_DCO_PHASE Regist e r 7.6. 13 CHx_CODE_D[...]

7: 12-Ch annel Correl ator 74 GP4020 GPS Baseband Processor Design Manual 7.6. 14 CHx_CODE_DCO _INCR_L OW Re g ister - Offset <CH x_Contro l > + 0x18 MULTI _CODE_DCO _ I NCR_LOW Regist er - Of f set 0x180 + 0x18 ALL_CO DE_DCO_I NCR_LOW Register - Offset 0x1C0 + 0x18 This registe r contains the 16 least s ignificant b i ts for the CHx _CARR I [...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 75 7.6. 17 CHx_CODE_P HA SE Reg ister - Read Of fset <CHx_Con trol> + 0x0 4 CHx_ CODE_PHA SE_COUN T ER R egister - Write Offset <CHx_Con trol> + 0x04 MULTI _CODE_P HA SE_CO UN T E R Register - W rit e Offset 0x 180 + 0x 04 ALL_CODE _PHASE_COUNT ER Register - Write Of[...]

7: 12-Ch annel Correl ator 76 GP4020 GPS Baseband Processor Design Manual If a channel is inactive, a non-z ero sle w value shoul d be w ritt e n in t o CH x_CODE_S LE W be fore t he channel is r el eas ed . Th is wr it e w il l be a ct ed o n im m edi at el y th e r es et i s rel ea s ed. If a TIC occurs du ri n g or soon after a slew, the channe [...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 77 Bit No . M nemoni c Des cript ion R eset Value R/W 15: 14 Not us ed '0' when r ead. - R 13: 8 CH x _ 20MS _EPOC H [5: 0] Ins t ant aneous val u e of the CH x_2 0M S_E POCH . Va lid range = 0 to 49 0x 00 R 7:5 Not used '0' when r ead. - R 4:0 CH x_1 MS_EP O[...]

7: 12-Ch annel Correl ator 78 GP4020 GPS Baseband Processor Design Manual Tabl e 7.26 C ORR CHx _EP O CH_COUNT_LOAD Re g i ster 7.6. 22 CHx_I_T RACK Regi ster - Read Addr es s Offse t <CH x_Accu mulate> + 0x00 CHx_Q_T RACK Regi ster - Read Address O ff se t <CHx_Accu mulate> + 0x04 CHx_I_PRO MPT Regist er - Rea d Add r ess Offset <C [...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 79 t he r egi st er st at e f or th e ti m e of t h e s eco nd c o de c hi p. Tabl e 7. 28 on page 79 show s the va lues re quired to select one of the 37 GPS, 19 WAAS or t he 8 INM ARSAT–GIC possib l e PRN (P seudo Rando m Noi se) patterns . In UPDATE mode , the C/A code ge n[...]

7: 12-Ch annel Correl ator 80 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c Descr ipt ion Res et Value R/W 15 GP S_ NGL ON S e le c t mode o f C/A c o de ge nera tor. '0 ' = Ru n C/A c o de gene rator in GLO NAS S mode , to ge nera te the fix ed 511 -bit sequ enc e us ed b y all G LO NAS S S at ell it e s . Af ter a r e [...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 81 Bit No . M nemoni c Des cript ion R eset Value R/W 11 CH11_MISSE D_ MEAS_DAT A '1' = on e or more s ets o f m eas ur ement dat a h a ve b een m iss e d sinc e t he l a s t r ead f r om t his r egis t e r . I t i s s et Hi gh b y a r ead f r o m the C od e Ph a s e C[...]

7: 12-Ch annel Correl ator 82 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c Descri pt ion Res et Value R/W 15: 12 Not Use d -W 11 CH11 _SE LECT '1' = enab les t he Mu lti-c hann el wri te op er ati ons on C h annel 11. '0' = dis ables Mult i-c han n el writ e op er ati ons on C hann el 1 1. 0W 10 CH10 _SE LECT [...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 83 7.6. 27 PROG _TIC_HIGH Regi ster - Wr ite Address Offset 0x 1B4 The PROG_TI C_H IGH a nd PR OG_TIC_L OW r e gister l ocat ions opera te in co njunction to set the pe riod of T IC. TIC is gene rat e d by a 21 -bit b i nary dow n counter when i t reache s ze ro. It then loads t[...]

7: 12-Ch annel Correl ator 84 GP4020 GPS Baseband Processor Design Manual Cycle, Co de S l e w or the Epoch counte rs. At the e nd of the rese t , the channe l enable re sets the code gene rator to a previously progra mm e d start phase. This i s a l l require d fo r the para l lel search a lgorithm o f one satellite s i gna l using many cha nnels [...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 85 7.6. 30 STAT US Register - Write Addr ess O ff s et 0x200 Thi s register allo ws the b it s on t he Accumulation Status r e gi sters ACCUM_ST ATUS_A, ACCUM_STATUS_B, and ACCUM_STATUS_C t o be l atched for readin g . This could be useful if the Accumulati on d a t a is obtaine[...]

7: 12-Ch annel Correl ator 86 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c Descri pt ion Res et Value R/W 0 CARRIER _MIX _DIS ABLE '1' = Dis a bl e Ca rr ier m i xe rs (N ote 1). '0' = E nabl e C arr ier m ixer s. 0W Table 7.37 C ORR SYSTEM_SETUP Register Note 1: Disab l e car ri er mi x ers by driving a fixe [...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 87 Bit No . M nemoni c Des cript ion R eset Value R/W 3 TM_TEST En abl e s Tr acki ng Modu l e T e s t mod e. Th is perm its writ es t o the r egis ter s whic h ar e n or mall y in hi bit ed fr om writ e op er ati ons, nam ely CH x_CAR RIER _C YCLE _CO UNT ER and CH x_COD E_PH A[...]

7: 12-Ch annel Correl ator 88 GP4020 GPS Baseband Processor Design Manual To get the SI G N and MAG cou nt co rr e ctly i n to the accumu lat o rs, bot h the carrier and code mixe rs m u st be m a de transparent . Th e c ar r i er m i xin g m ay be di s ab l ed b y ei th er : (1) Setti ng CARRIER_ M IX_ DISABLE (bit 0 in SYSTEM_SETUP) to H igh t o [...]

7: 12-Ch annel Correl ator GP4020 GPS Baseband Processor Design Manual 89 7.6. 33 TI MEMA RK_CO NT R O L Reg i ster - Write A ddress O ffset 0x1EC This register i s used to se t- up the cor relator par t of the 1PP S T im e mar k Gene rator (i.e. the R aw_Ti m e mark Ge ne rato r). Th e R A W T I M EM AR K Ge ne rato r o pe rate s in on e of two wa[...]

7: 12-Ch annel Correl ator 90 GP4020 GPS Baseband Processor Design Manual Thi s Page intenti onall y l ef t bl ank.[...]

8: D MA Cont ro ller GP4020 GPS Baseband Processor Design Manual 91 8 DMA CONTROLLER (DMAC) The GP4020 co nt a ins a D MA con troller, wh ich ass ists the p rocessor to move la r ge blocks of da t a around a sys tem. Da t a t r an sf er b et ween m emo r y bl o cks , o r b et ween m e m or y a nd a p er i pher a l c a n be ext r em el y cy cl e- in[...]

8: D MA Cont ro ller 92 GP4020 GPS Baseband Processor Design Manual 1. 1 . 4 ) C l ear to “0 ” t he R ecei v e I n t er ru pt E n abl e b it (bi t 4) t o di s abl e i nt er r upt s gen er a t ed wh en t h e U AR T rece ive re gi ste r is ful l . 1.1. 5) Clear t o “0” the Mode m Int e rrupt Enab l e bit ( bit 7) and the E rror Inte rr up t E[...]

8: D MA Cont ro ller GP4020 GPS Baseband Processor Design Manual 93 3. 1.1 ) Set t o ”1” t he DMAC Ha r dware Request Stat us bit (bit 1), t o allow Hardwar e requests ( dr e q and dack ) f rom t he U AR T t o co nt ro l t he D MAC f u nct i on. 3. 1 . 2 ) Cl ea r t o “ 0 ” t he D MA C S of t war e Req u est b it ( bi t 2 ), t o di s a bl e[...]

8: D MA Cont ro ller 94 GP4020 GPS Baseband Processor Design Manual 3.4) Se t t he DMAC B ase T ransfer Coun t Register (BTR ) , to indicate to the DMAC how many transfers are required in the DM A opera tion be ing progra mm e d. In the case o f the Packe t trans fer be i ng de fined here, this nu m be r is the (numbe r of da ta by t e s - 1), of P[...]

8: D MA Cont ro ller GP4020 GPS Baseband Processor Design Manual 95 8.1. 2 Set up exampl e of DMAC for a F l y-by t ra nsf er from UAR T RX to memory The follow ing ex am p l e shows t he se quence of e vents required to progra m and enable t he GP4 020 DMA C to provide a F ly-by da ta trans fer from a U ART Rece iver input to an a rea of m e m ory[...]

8: D MA Cont ro ller 96 GP4020 GPS Baseband Processor Design Manual 3.1. 2) Clear t o “ 0” the DMA C Softwa re Re quest bit ( b it 2), to d i sable the So ft wa re DM A transfe r trigge ri ng . Note that w hen a s oftware t rigge r is require d after the DMAC i s progra mm e d, a w rite of a "1" t o this register bi t will initiate a [...]

8: D MA Cont ro ller GP4020 GPS Baseband Processor Design Manual 97 this nu m be r is the (numbe r of da ta by t e s - 1), of Packe t siz e "1" which are r e quired to be transferred fro m me mor y to the U ART 1 o r 2 tra ns mit po rt. So i f th e tra ns fe r is to be for 10 ,000 8-b it b yte s, the set ti ng for this register shou ld be[...]

8: D MA Cont ro ller 98 GP4020 GPS Baseband Processor Design Manual 1.3) DMA C Channe l 2 can on l y re ceive D MAC har dware tri gge rs fro m UART 2, and no o t he r source. Conse quently, the tri gge r op ti ons liste d i n Table 8.1 do no t e xist for UA RT 2 D MAC F ly-by or dua l- addresse d transfe rs. 2) Put DM AC i n to “Progra m Mode ”[...]

8: D MA Cont ro ller GP4020 GPS Baseband Processor Design Manual 99 2.1. 12) Clear to "0" t he Periphera l Location bit (bit 18 ), to indicate that the data buffer for a dual-addresse d tran sfe r is inte rna l to the DM AC . 2.2 ) Se t DM AC P ack et S iz e (b its [7:0 ]) o f the Pa cke t Siz e R e giste r (P SR) to z ero (i .e . 0x 00 )[...]

8: D MA Cont ro ller 100 GP4020 GPS Baseband Processor Design Manual 8.3. 2 Sof t w are T riggering Software Tr iggering of a DMAC channel i s the no rmal mode used in Dual-Addre ssed (Buffered) da ta transfe rs. A Software Trigge r is e nabled and disabled de pendent on the leve l of b it [ 2] of the DMAC Channe l Control and Status Regis t e r (C[...]

8: D MA Cont ro ller GP4020 GPS Baseband Processor Design Manual 101 8.4 Caution ary Notes 8.4. 1 Packet T ransfers in pl ace of Block T ra nsf ers For Both Single-addre ssed and Dual-add resse d transfers u si n g the G P 4020 D MA, it is N OT reco mm e nded to use DMA Block-transfe rs, but t o use Packe t transfers inste ad. Packe t transfe rs a [...]

8: D MA Cont ro ller 102 GP4020 GPS Baseband Processor Design Manual Thi s Page intenti onall y l ef t bl ank.[...]

9: GP IO I nter fac e GP4020 GPS Baseband Processor Design Manual 103 9 GENER AL PU RPOS E INPU T OUTPUT ( GPIO) IN TERFACE 9.1 I nt r od u ction A se t o f 8 ge neral purpose static inpu t output log i c lines are include d in the GP4020 to allow mu lti p le st a tic data to be prov ided to e xte rnal fe atur e s, or a llow mu l tip l e input data[...]

9: GP IO I nter fac e 104 GP4020 GPS Baseband Processor Design Manual 1N F D T IO Figur e 9.2 G PIO Pad Cell C onfigur a tion The GPI O modu le m ust be read o r w ritten in 32 - b i t acce sse s, although o nly t he lower eight b i ts o f the B µ ILD data bus ( b_da t a [7: 0 ]) a re used. Da ta i s w ritten t o r e gi s ters on t he f a lli ng e[...]

9: GP IO I nter fac e GP4020 GPS Baseband Processor Design Manual 105 B_SI Z E[1: 0] D ata size B_E RR OR 00 8 - b i t Er r or, b us er r or as s er t ed 01 16- bit Err or, bus e rr or a s s ert ed 10 32- bit V alid, bus e rr or neg at ed 1 1 Re se rv e d Er ro r, bu s e rro r a sse rte d Table 9.1 GPIO B_ERROR s ignal 9.2 I nitialisation On powe r[...]

9: GP IO I nter fac e 106 GP4020 GPS Baseband Processor Design Manual 9.3. 2 GPIO I nput Register – GPIO _INPUT - M emo ry Offset 0x004 Re adabl e only, a w rite to t his addre ss wi l l p roduce a b_erro r . The ins t antane ous voltage condi ti on on the e xternal pin is latched on each r ising e dge of i p_ rd, wh i ch is synch ronous w ith b_[...]

10: I nterrupt C o ntroller GP4020 GPS Baseband Processor Design Manual 107 10 INT ERRUP T CO NTROLLER (INTC) The Interr upt Con tr o ller can manage up to 32 Interrupt source s. In the G P40 20, 18 interrupt source s a re pr e sent: 16 int e rnal sou r ce s, and 2 ex ternal sou rces. The Inte rr up t contro l ler pro cesse s these r aw in terrupt [...]

10: I nterrupt C o ntroller 108 GP4020 GPS Baseband Processor Design Manual In the GP4020, the interrupt channe ls are a ll o cat e d as s hown i n Table 10.2 bel ow . I n each ca se t he appl ication soft ware for the GPS receiver will nee d t o configure t he i n t e rr up t channels a s shown. The GP4020 Interr upt Con t ro ller has a Base Addre[...]

11: Memo ry Periph eral Co n troll er GP4020 GPS Baseband Processor Design Manual 109 11 M EMORY PERI PHER AL CON T R OLL ER (MPC) 11.1 I nt r od u ction Th e Mem or y P er ip her a l C ont r ol l er ( MPC) i s t he i nter f a c e b et ween t h e B µ ILD bus and the e xte rnal bus sy ste m. The MPC i s a B µ I L D b us sl ave, whi c h p er f orm [...]

11: Memo ry Periph eral Co n troll er 110 GP4020 GPS Baseband Processor Design Manual The de f ault hard-w ired con fi gura tion at R ese t of MPC M e m ory A rea 1 (registe r addre ss 0xE000 8000) is 0xFF00 0035: Acce ss W a its bi ts [31: 28] = ‘0y 111 1’ = 15 wa it sta te s Sto p W a its bit s [27:24 ] = ‘0y1 111’ = 15 wai t st a te s Re[...]

11: Memo ry Periph eral Co n troll er GP4020 GPS Baseband Processor Design Manual 111 11.4 GP4020 M emory A rea 3 Con figuration GP4020 M e m ory A rea 3 is a special case whe re a nu mber of internal co mponents share resource s w ith a n Ex t e rnal ch ip se l e ct line – N SCS [2A]. The 12-channe l corre l a tor wh i ch resides in Me mory Area[...]

11: Memo ry Periph eral Co n troll er 112 GP4020 GPS Baseband Processor Design Manual Esse nti al ly, this e quat e s to setting add ress 0x E000 8008 to a value of 0x 3303 306E. The M PC m ust be con fi g ured to address a 32-b it bus wh en ac cessing t he Are a 3 in ternal pe ripherals. By us i ng “Sub- m e mory a ccess” , writes to the 12-ch[...]

12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 113 12 P ERIPHERAL C ONTROL LOGIC (PCL ) 12.1 I nt r od u ction The Peripheral Contro l Logic (PCL) i s used t o contro l GP4020 c hip-wide functions. The PC L can be cons idered to have the follow i ng discrete f u nctions: 1) Chip Re set logi c 2) PLL Enab l e logic 3) M [...]

12: Peri pheral Con trol Logi c 114 GP4020 GPS Baseband Processor Design Manual PLL DT1 UART_CLK BuIL D_CLK RF _PLL_LO CK RTC_CLK NSRESET POWER_GOOD EN_PO W_RST F_SL EEP SFT_RESET UART_CLK NRESET (TO FIREFLY, CORR) NPOR_ RESET (TO 1PPS, R TC, SCG) POW_CNTL REGIST ER UIM ADDRESS & D ATA BUS UIM BUS IO_ REV REGIST ER IP_READ REGIST ER PER_ST AT [[...]

12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 115 • WATCH_TM (or Watchdog Time - ou t) signal. Th is is a n in t e rnall y gene rat e d Re set signal co m es fro m the on- chip W atc hdog m o dul e . Th i s will occur if the W a t chdog has int e rrupte d t he Firef l y MF 1, but an int e rrupt se r v ic e - routine [...]

12: Peri pheral Con trol Logi c 116 GP4020 GPS Baseband Processor Design Manual RF_PLL_LOCK NRESET UART_CLK 3 CYCLES Any Freq Figure 12.3 RF_PLL _LOCK Ha rdware Rese t Genera t ion POWER_GOOD NRESET UART_CLK 3 CYCLES Any Freq Fi gure 12.4 POWER_GOOD Har dware Reset Generati on when POWG_EN = '0', and UART _CLK N OT deri v ed fr o m an RF [...]

12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 117 NSRESET NPOR_RESET NRESET RTC_CLK UART_CLK 3 CYCLES - 150ns 20MHz Any Freq RTC_CLK period = 30517ns. Rising edge only shown. Figur e 12.6 NSRESET Hardwa re Re set Generation WATCH_TM NPOR_RESET NRESET RTC_CLK UART_CLK 3 CYCLES - 150ns 20MHz Any Freq RTC_CLK period = 305[...]

12: Peri pheral Con trol Logi c 118 GP4020 GPS Baseband Processor Design Manual either WATCH_ TM or NSRESET signa l s. The refor e , a co mpl e t e GP4020 r e set can o nl y occur if an NSRESET or a W ATCH _TM e ve nt is introduce d. The se are synch ronise d to the 32kHz c lock de veloped by the Re al Tim e Clock, and t he resulting ou tput is ac [...]

12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 119 PLL_PD / PLL_SLEEP PLL_IN_SEL value change NRESET PLL_ENABLE RTC_CLK 6 RTC_CLK cycles = 183us <30.5us ....................... OR ........................ ....................... OR ........................ Fig ure 12.9 PLL _ENABLE Timi ng The se l ection of an e xte [...]

12: Peri pheral Con trol Logi c 120 GP4020 GPS Baseband Processor Design Manual MULTI_FNIO DISCIO CLK100KHz DISCOP_MUX BSIO_MUX[1:0] MFNIO_CFG[2:0] MULTI_FNIO_READ UART_CLK '0' '1' RF_PD DISCIO_CFG[2:0] DISCIO_READ TIC '0' '1' GPIO[0:7] BSIO DISCOP DISCIP1 GPIO[0:7] RF_SLEEP PLLDT1 UIM_TEST 0 1 2 3 4 5 6 7 0 [...]

12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 121 GPIO output lin e number Altern ative sign al mult ipl ex Condi tion 0 BSIOC LK BS IO_ MUX[ 1: 0] = ' 1 0', '0 1', '11 ' SIGN 1 Not av aila b le in s tan dar d oper at ion UIM_TEST = '1' (i. e. TEST = Hi gh TEST MODE = Hig h) 1 BS[...]

12: Peri pheral Con trol Logi c 122 GP4020 GPS Baseband Processor Design Manual A single Inte r rup t line, PER_ INT, is p roduce d from 3 Peripheral Control L ogic Inter rupt signals from the Real Time Clock (RTC_CM P_INT) , the 1PPS Tim e mark Gene r ator (TIC_INT ), and t he PO W ER_G O OD i npu t ( Pin 64 (100 -pi n package)) . The PE R_INT int[...]

12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 123 Note: t he W ATCH _EN bit i n only e f fects W atchdog behavio ur due t o Firef l y rese t. ( If WATCH_EN is set t o '1', the Watchdog starts imm e di a t e ly. I f W ATCH _EN is '0', W atchdog w ill on l y start after the RES TART KEY value is wr it[...]

12: Peri pheral Con trol Logi c 124 GP4020 GPS Baseband Processor Design Manual 12.6. 2 RF In put and RF Front- e nd Pow er-Down A Powe r-down of an RF Front-e nd IC, alon g with d isabling the 40MHz Low Le vel Diff e rential Input cell i n the Syste m Clock Gene rat o r, can be m ade to oc cur if: a) RF_PD bi t (PO W _CNTL[0] ) set to '1&apos[...]

12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 125 Ad dr e ss Off set Regi ster Dir ect ion Functi on Fun ctio n Bl oc k 0x00 0 RTC_P R E Rea d Rea l T ime C loc k Pr e-s ca ler v alu e RT C 0x00 2 RTC_S EC _B R ead 16 LSBs of R eal T im e Cloc k sec ond cou nt er RTC 0x00 4 COM P_RT CP R ead /W r ite Compa r i s on v a[...]

12: Peri pheral Con trol Logi c 126 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c Des cript ion R eset Value R/W 10 RF_S LEEP ' 1' = Disa ble 40 MH z lo w- lev el di ffe r e nt ial inp ut in Sy stem Clo ck Ge nera to r, and app l y an a c t ive H igh p ower - down si gn al t o th e RF Fr ont -end ( vi a DISCIO ( pin 55 ([...]

12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 127 Note : For each change of va lue of PLL_ IN_SEL[1:0] or a t PLL wake-up, t he PLL will be disabled f or a wait period of approx. 18 3 µ s (6 * 32 kHz clock cycle s, de t e rmined by the Re al Time Clock bl ock). This allows the CLK INB to st ab ilis e . 12.7. 2 PCL Inp[...]

12: Peri pheral Con trol Logi c 128 GP4020 GPS Baseband Processor Design Manual 12.7. 3 PCL Inp ut Read regist er - I P_READ - Memory Of fset 0x00E This Re ad-only re gi s t e r allows t he mos t rece nt stat e of a number o f GP4020 input s ignals t o be read. Bit No . M nemoni c D escr ipt ion Res et Value R/W 15 PER_I NT PE R_ INT in terr upt l [...]

12: Peri pheral Con trol Logi c GP4020 GPS Baseband Processor Design Manual 129 Bit No . M nemoni c D escr ipt ion Res et Value R/W 13 PO W _INT_EN En abl e PE R_INT I nt err upt s i gn al t o I nt erru pt C on tr oll er i n F ir efl y MF1, du e t o PO W _G D_IN T ( POW ER _GOO D (pin 64) g oing L ow.) '1' = En ab l e Interr upt due t o P[...]

12: Peri pheral Con trol Logi c 130 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c D escr ipt ion Res et Value R/W 2 POW _RESET (See No te 2) '1' = Res e t du e t o PO W ER_ GOOD = Low, ha s occurr ed si nc e l a st CLR_RST or NSRESET cl ea r- event. ‘0’ = N o r e s et event du e t o POW ER_G OOD h as o c cur red 0R 1[...]

13: Real Ti me Clock GP4020 GPS Baseband Processor Design Manual 131 13 REAL TIME CL OCK (RTC) 13.1 I nt r od u ction Th e Rea l T im e Cl oc k ( RT C) i s u sed to pr o vi de a n i nc rem en t al ti m e i n di c at or. I t i s b a sed on a 3 2 768 Hz wa t c h- crystal osc ill a tor, w ith a 15-b it divide r to produ ce a 1Hz cloc k, and a 24- b it[...]

13: Real Ti me Clock 132 GP4020 GPS Baseband Processor Design Manual crystal ne ed to be se t to e nsure that the t otal loop gain of t he oscillato r is h i gh e nough t o guar ant e e continuous oscillation unde r all conditions. Nor mall y t h is w i ll m e an tha t a loop gain of greater than 1 is ne eded. A se t of equa ti o ns for calculating[...]

13: Real Ti me Clock GP4020 GPS Baseband Processor Design Manual 133 Bit No . M nemoni c D escr ipt ion Res et Value R/W 15: 1 RT C_PRE [15: 1] Number o f RTC cl o c k c y cl e s a t s ampl e time, w i thin 1 s econd sinc e las t div ide r rese t/rol love r. (One clo ck cy c le = 1/ 32768 = 30. 5 µ s). Most Si gnif icant Bit = Bit 15. Note: Thi s [...]

13: Real Ti me Clock 134 GP4020 GPS Baseband Processor Design Manual Bit No . M nemoni c D escr ipt ion Res et Value R/W 15: 8 RT C_SE C_T[ 7: 0] 8 MSBs of acc um ulat ed RT C s e c onds si nc e l ast 24- bit c ount er r e s et. Most Si gnif icant Bit = Bit 15 Note: Thi s data ONLY re set by writi ng ‘0’ to bit 0 of RTC_ PRE. NOT re set tab le [...]

14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 135 14 SYSTEM CLOCK GENER AT OR (SCG ) 14.1 I nt r od u ction The S yste m Clo ck Gene r ator (SCG) is used to ge nerate two c lock si gnals fo r the GP4020: • The U ART_CLK w hich runs U ART2 continuously and produce s the B µ ILD C lock. The B µ I LD C l oc k runs a ll t[...]

14: Syst em Clock Gen erator 136 GP4020 GPS Baseband Processor Design Manual 14.2 40MH z Low Level Di fferential I nput The 40M Hz l ow- l e vel diffe rential input can proce ss the 40MHz signal f r o m a RF Front -end chip. The signa l should have a DC bias o f less than ap pr ox . 1.7V w i th re spect to GND, and the 4 0MHz signal shou ld have am[...]

14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 137 14.3 Pr ocesso r Cry stal Oscillator Th e Proce ssor Cry sta l Osc illa tor may ne ed to be us ed wi th an ex tern al cry sta l, to ge ne rate the c lock so ur ce fo r the UART_C LK signa l . The two instances w here t his may be ne cessary a re: 1) If the RF Front-e nd is[...]

14: Syst em Clock Gen erator 138 GP4020 GPS Baseband Processor Design Manual Z o = Output I mpedance of oscil l ator at PRX_ OUT G m = T ran s co nd uct a n ce of os c il l at or R f = Fe edback Re sistor (on -chip) ESR = Equiva lent Series R esi st a nce of crys t a l F = Funda m en tal Crys tal freque ncy Equations 1 and 2 above can be use d t o [...]

14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 139 TCXO 10uF Vcc To RF Front-end PLL Ref input Vcc GND 10.0MHz GP4020 PRX_IN PRX_OUT Vdd (NOT Vcc) 1M IC1 100nF 1nF 47nF 100 1V p-p IC1 = ANY 3.3V High-speed CMOS Inverter. 3.3V p-p 47nF ~0.5V p-p 33 ~1k 100nF Figure 14.4 Connect i ons of a TCXO fr equ ency reference t o the [...]

14: Syst em Clock Gen erator 140 GP4020 GPS Baseband Processor Design Manual Fig ure 14 .5 GP4 02 0 S y ste m C lock Ge ne rato r PL L Con figu ra tion The P LL can p rovide accu rate phase a li g nment be twee n a ge nerated clock a nd a refe rence clock withou t i ncu rri ng del a y s n orm al l y as s oci at ed wi t h bu ff er i n g. T he P LL w[...]

14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 141 PI N DE S C RI PT I O N VC OD [1:0 ] PLL VCO O utput Fr equ enc y R ang e s elec ti on pin. Th is inp ut d e t er mines whic h o f t h e 4 f requ enc y r ang es ar e sele ct e d. '00 ' op erat es th e VCO b etwe en 80 MHz an d 25 0MHz; '01 ' op erat es [...]

14: Syst em Clock Gen erator 142 GP4020 GPS Baseband Processor Design Manual If you i ntend t o change the fre quency of the P LL on the fly during tim e -critical co de-e xecution, care should be use d to e nsu re tha t the PLL is a llow e d to s tab ilis e be fo re al low ing th e c ode ex ec ution to con tin ue . It is re co mmen de d th a t t h[...]

14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 143 UART _CLK O/ P Freq. (M Hz) I/P Freq. MH z PLL Mu l t Fact Prog. Div i d er sett ing DI V [4:0] Charge Pump sett ing CHP [4:0] PLL SYNC MO D E SYN CEN PLL O/ P VCO Freq. MH z VCO Freq. Range VCOD [1:0] BY - PASS PLL PLL_ BY P PLL O/ P Div i d e Factor B_ CLK _SEL [1:0] Ts [...]

14: Syst em Clock Gen erator 144 GP4020 GPS Baseband Processor Design Manual UART_CLK O/ P F r eq. (M Hz) POW_C NTL regi ster v alu e PLL_C NTL regi ster v alu e Comments 10. 0 0 x80 3C 0 x19 7F PLL byp a s s ed an d dis abl ed PLL _CNT L val ue = r e s et valu e 11. 25 0 x80D 8 0 x018E 12. 5 0 x8098 0 x09C 6 13. 75 0 x80D 8 0 x01D2 15. 0 0 x8058 0[...]

14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 145 PLL Mu l t Factor Desir ed PLL outp ut fr eq ue ncy Prog. Div i d er Control DIV [4: 0] PLL SYNC MO D E SYNCE N Charge Pump sett ing CH P [4 :0 ] VCO Freq. Range VC OD [1:0 ] Wo rs t case sett lin g ti me . ( µ s) 8 40- 125 MHz 00 110 0 01 011 01 38 9 40- 125 MHz 00 111 0[...]

14: Syst em Clock Gen erator 146 GP4020 GPS Baseband Processor Design Manual 5) Output fr e quency o f PLL; t he highe r the ou tput freque ncy, the m ore cur rent consu m e d: i. 240MHz = 6.2 m A; ii . 125MHz = 4.5 m A; iii. 60 MH z = 3. 4 mA ; i v. 30MHz = 2.9mA As a ge neral r ule of thumb , t he l owe r the PLL i npu t fre quency, the lower the[...]

14: Syst em Clock Gen erator GP4020 GPS Baseband Processor Design Manual 147 Bit No . M nemoni c Des cript ion R eset Value R/W 7:6 B_C LK_S EL[ 1: 0] U ART _CLK di vid er b l ock s e l ect or . All ows s el e c ti on of di ff er ent outp ut di vis i on rat ios f or th e UART _C LK s ign al , t o all ow s m all r es olut i on ch an ges in UART _CL [...]

14: Syst em Clock Gen erator 148 GP4020 GPS Baseband Processor Design Manual 14.6. 2 SCG PL L Co n trol Regist er - PLL _CN T L - M emo ry Offset 0x00A A write to this re gister sto res logic va l ue s which se t or rese t input control l i ne s to the PLL w ithin the Sys tem Clock Gene rat or. A read of this register shows t he status of the se fu[...]

15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 149 15 1PPS TI MEM A R K GENERATO R 15.1 I nt r od u ction The One Pulse Pe r Second (1PPS) T im e m ark G e nerator is nomina l ly u sed to p rovide a 1 ms pu ls e , once eve ry se cond, wh ich is phase-a li g ned to Unive rsal Time Co -ordinate d (UTC) , in con junction wi[...]

15: 1PPS T imema rk Ge nerator 150 GP4020 GPS Baseband Processor Design Manual TIC GENE RATOR (C ount down to Zero) Clock div ide by 7 LOAD ZE RO 1ms delay TIC ARM_TI MEMARK Modulo 7 Add TIC_ CORR[2 :0 ] Phase_offset Overf low TIME MARK / TIC Over flow contr ol TI C_INT Ti memark Dela y STORE PHASE OFF SET TIC_I NT[1: 0] 22 Bit Dow n Counter TIM_D [...]

15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 151 TIC ARM_TIMEMARK RAW TIMEMARK 0.0999999s 10 TIC Periods = 0.999999s Figure 15.2 Time mar k output using A RM_T IM EMARK si gn al, triggered f ro m software. The TIC pe riod can only be adj u sted i n steps of 175ns ( 7 / 40MHz = 175ns). The refore, the close st t ha t TI[...]

15: 1PPS T imema rk Ge nerator 152 GP4020 GPS Baseband Processor Design Manual TIMEMARK 1ms 1ms 1us delay 2us delay UTC 012 10 TIC Periods = 0.999999s TIC ARM_TIMEMARK RAW_TIMEMARK TIMEMARK DELAY SECONDS Figure 15.3 Typical timing rela t ionship between UTC , TIC and Tim e mar k , for s mall Ti m ema r k De lay va l ues The GP4020 e m ploys two sep[...]

15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 153 i v ) T h e va l u e of t he T I C per i od is a t a gi v en TI C. T h is c an b e c a l cul at ed pr eci s el y wit h r es pec t t o U TC i f th e Rec eiv er Cl oc k Of fs et i s kn o wn. v) The value of UTC at a give n TI C , and hence the de lay requi red to be added [...]

15: 1PPS T imema rk Ge nerator 154 GP4020 GPS Baseband Processor Design Manual TOT AL ma x. o sc il lato r dr ift e rro r = (a) + (b ). In pract ice, the drift is much l e ss than t h is unde r typical con ditions ≈ 10 to 20n s 5. Computation induc ed error: It is a ssumed t h at e nough signi f icant bits a re reta i ne d such that th is e rror [...]

15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 155 15.4 Fine-r esolution Timemar k setting, usin g TIC perio d slewin g 15.4. 1 Funct ional descrip tion The GP4020 i nc l ude s so m e logic w ithin the 1PPS T im e m ark Gene rator wh ic h allows t he TI C pe r iod to be specifi e d t o a r eso l ut i o n of 1 M_ CL K cy [...]

15: 1PPS T imema rk Ge nerator 156 GP4020 GPS Baseband Processor Design Manual TIC _INT _EN [1 :0] = ' 01' . In d i cates t hat the T I C per iod will a ut omatica lly be correct ed ind e pendent ly of G PS software e ach tim e the phase _counte r r e aches 7 , by m e ans o f the R ELOAD_T I C signal. E ach TIC eve nt triggers a new phase[...]

15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 157 TIC Event TIC _ CORR [2:0] Phase Off set Off set delay (ns) Ov er flow Next T IC Period ( µ s) Cumulated Ov erf l o w Ov erf l o w delay (ns) Tot a l Dela y (ns) 0 100 0 0 0 999 99. 9 0 0 0 1 100 4 1 00 0 999 99 .9 0 0 100 2 100 1 25 1 1000 00. 0 75 1 17 5 20 0 3 100 5 [...]

15: 1PPS T imema rk Ge nerator 158 GP4020 GPS Baseband Processor Design Manual 15.4. 5 Ti memark setti ng example 3 - T IC period Slewi ng with +2. 5 pp m Receiver Clo ck Of fset For TIC period e rrors whi ch are la rger than +0.75ppm due to an offse t i n the Re ceiver cl o ck, it w ill be ne cessary for the rece i ver to ad just the TIC pe riod t[...]

15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 159 TIC Event TIC _ CORR [2:0] Phase Off set Off set delay (ns) Ov er flow Next T IC Period ( µ s) Cumulated Ov erf l o w Ov erf l o w de lay ( ns) Tot a l Dela y (ns) 5 001 5 1 25 0 999 99. 975 0 0 125 6 001 6 1 50 0 999 99. 975 0 0 150 7 001 0 0 1 100 000 . 15 0 1 175 175[...]

15: 1PPS T imema rk Ge nerator 160 GP4020 GPS Baseband Processor Design Manual 6) The Tim e mar k delay cou nter w ill continue counting down to 0, at which poin t the T I ME MARK output register will be cleared and the counte r will stop. 7) At the ne xt Tim e m ark e vent, the sa m e de lay va lue w ill be use d in the Tim e m a rk delay counter,[...]

15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 161 15.5. 3 Ti memark setti ng example 6 - T imemark Delay Cou nter with +0.5pp m Receiver Clock Of fset In pract i ce , the TIC period c ould be up to ± 2.5 p pm i n er r or d u e to t h e R ecei v er Cl oc k O ff s et ( d rif t i n t h e r ec ei v er TCXO), w hich equates[...]

15: 1PPS T imema rk Ge nerator 162 GP4020 GPS Baseband Processor Design Manual Tim ema rk Event ( s) TIC Event TIC Tim e (s ) R eq uir ed delay ( µ s) TI M _ D EL val ue TI M _ D EL _L O TI M _ D EL_ HI 0 0 0 0 40 000 0 x9C4 0 0 x40 1 10 0 .99 99965 3. 5 4 0140 0x 9 CCC 0x4 0 2 20 1.9 9999 3 7 40 280 0 x9D5 8 0 x40 3 30 2 .99 99895 10 .5 404 20 0x[...]

15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 163 Tim ema rk Event ( s) TIC Eve nt TIC Ti m e (s ) Re qui re d delay ( µ s) TI M _ D EL val ue TI M _ D EL _L O TI M _ D EL _H I 0 0 0 0 40 000 0 x9C4 0 0 x40 (TIC ADD) 1 9 0. 9000 0135 999 98 .65 4 0399 46 0x A50A 0x7 D 2 19 1. 9000 028 5 999 97. 15 403 9886 0x A 4 CE 0x[...]

15: 1PPS T imema rk Ge nerator 164 GP4020 GPS Baseband Processor Design Manual 15 .7 1 PPS T imema rk G enera to r Reg isters The Tim e mar k Gene rat or use s four registers. These re gisters a r e addre ssabl e in t he same part of the m e m ory map as the Pe ripheral Con trol Log ic Block - Root address 0x 4010 1000. Ad dr e ss Off set Regi ster[...]

15: 1PPS T imema rk Ge nerator GP4020 GPS Baseband Processor Design Manual 165 15.7.2 1PPS Timemar k Generat or TIC Re tention Re g ister - TIC_RE T - Me mory O ffset 0x01 2 This register combines con tr o l and m o nito r line s for the 1PPS Tim e mark Generator TIC period slewing logic, with an 8-bit data re tention registe r. Note : Th e Dat a R[...]

15: 1PPS T imema rk Ge nerator 166 GP4020 GPS Baseband Processor Design Manual 15.7.4 1PPS Timemar k Generat or Delay C ounter Reg ister (MSB) - TIM_DE L _HI - Me mory Offse t 0x016 This register sets t he six m o st sign i fican t bits f or the 22 -bit T i me m ark D elay C ount e r down -count in iti a lised va lue, TIM_DEL, i n conjunc ti o n wi[...]

16: Up -Integ ration Modul e GP4020 GPS Baseband Processor Design Manual 167 16 UP-INTE GRA TION MOD ULE (UIM ) The GP4020 conta ins the Firefly MF1 core , wi t h in whic h i s a Me m ory Pe ri phe ral Con troller (MPC) which contain s a module ca ll e d the Up In tegration M odule (UIM ). W ith i n the GP4020 , the UIM is use d to interface the Fi[...]

16: Up -Integ ration Modul e 168 GP4020 GPS Baseband Processor Design Manual Thi s Page intenti onall y l ef t bl ank.[...]

17: UART s GP4020 GPS Baseband Processor Design Manual 169 17 UNIVERSAL A S YNCHRONOUS RECEIVER TRANSMITTER (UART) 17.1 I nt r od u ction The GP4020 uses two U niversal Asy nchronous Rece i ver Trans mitt e r (UART) module s, which a re co mponents that provide indus tr y -standard l eve l s o f support for ful l -dup lex asynchronous serial co mmu[...]

17: UART s 170 GP4020 GPS Baseband Processor Design Manual W hi l st t h ese a r e th e sam e f r eq uen c y, t he B µ I LD_CLK can be d i sabled by us i ng the F_SLEEP facilit y (refer to Section 12. 5 "Interru pt and Wake-up l ogi c" on page 121 , for mo re in for ma tion ). In both UARTs , the c lock pre -scaler, 16 b its lon g, is co[...]

17: UART s GP4020 GPS Baseband Processor Design Manual 171 Baud Rate Require d Div i s io n Sel ect Value Reference Clock (MHz) Baud Rate Ratio Prog. BRR Value Progra mme d Baud Rate Baud Rate Error ( % ) 1200 8 2.6 56 25 13 7.346 3 5 137 12 03. 01 2 -0. 25 1 2400 4 5.312 5 13 7.3 46 35 137 24 06. 02 4 -0.2 51 4800 2 10.62 5 13 7.3 46 35 137 48 12.[...]

17: UART s 172 GP4020 GPS Baseband Processor Design Manual Baud Rate Require d Div i s io n Sel ect Value Reference Clock (MHz) Baud Rate Ratio Prog. BRR Value Progra mme d Baud Rate Baud Rate Error ( % ) 1200 8 3.1 25 16 1.7 604 2 16 2 1198. 23 6 0.1 47 2400 4 6. 25 16 1.7 604 2 16 2 23 96. 472 0. 147 4800 2 12. 5 16 1.7 604 2 16 2 47 92. 945 0. 1[...]

17: UART s GP4020 GPS Baseband Processor Design Manual 173 Baud Rate Require d Div i s io n Sel ect Value Reference Clock (MHz) Baud Rate Ratio Prog. BRR Value Progra mme d Baud Rate Baud Rate Error ( % ) 1200 8 3.5 93 75 186. 174 48 18 6 1201. 12 - 0.09 3 2400 4 7.187 5 18 6.1 744 8 18 6 24 02.23 9 - 0.09 3 4800 2 14.37 5 18 6.1 744 8 18 6 48 04.4[...]

17: UART s 174 GP4020 GPS Baseband Processor Design Manual Baud Rate Require d Div i s io n Sel ect Value Reference Clock (MHz) Baud Rate Ratio Prog. BRR Value Progra mme d Baud Rate Baud Rate Error ( % ) 1200 8 4.3 75 22 6.8 645 8 22 7 1199. 28 7 0.0 59 2400 4 8. 75 22 6.8 645 8 22 7 23 98. 575 0. 059 4800 2 17. 5 22 6.8 645 8 22 7 47 97. 149 0. 0[...]

17: UART s GP4020 GPS Baseband Processor Design Manual 175 Thi s Page intenti onally l ef t Bl ank[...]

18 : Wa tchdo g Timer 176 GP4020 GPS Baseband Processor Design Manual 18 WATCHD OG TIMER (WD OG) The func tion of the W atchdog Ti m er block [ W DOG] i s to dete ct hardware or run - ti m e sof t wa re errors. It pe rforms this function by r e quiring the proce ssor to wr ite to one of it s re gi sters periodically . S hou l d this not oc cur, the[...]

18 : Wa tchdo g Timer GP4020 GPS Baseband Processor Design Manual 177 UART_CLK PRIMARY DOWN-COUNTER 32BIT SECONDARY DOWN-COUNTER 8BIT DIV 16 = WATCH_INT RELOAD READ CONSTAT =0 =0 CLR START WATCH_EN START [7:0 ] BUILD BUS INTERFACE BUILD BUS CLR RESTART KEY 0XECD9F7BD WATCH_TM TEST [11: 0] Figure 18.1 Watchdog Block D iagr a m 18.2 Operational Descr[...]

18 : Wa tchdo g Timer 178 GP4020 GPS Baseband Processor Design Manual To resta rt the w atchdog coun ter, a speci f ic 32 -bit va lue (=0x ECD9F7B D; the R ESTART key) m us t be prog ramm e d into the watchdog restart register . Th is 32 -bit “key” ac tivate s the restart me chanism, w hich pe rforms the following actions: 1) Loads t he wa tc h[...]

18 : Wa tchdo g Timer GP4020 GPS Baseband Processor Design Manual 179 All W atchdog Re gist e rs are 32-bits w i de . 18.3. 1 Wa tchdo g C ontr ol / St atus R e giste r - CON S T A T - M e mory Offset 0x000 The control register is 32-b i ts w ide, with un use d bits de f ine d as ze r o. At te m pts to access the register as a byte or a half-word w[...]

18 : Wa tchdo g Timer 180 GP4020 GPS Baseband Processor Design Manual 18.3. 4 Watch dog Restart Register - REST A RT - Memory Offset 0x00C Bit No . M nemoni c D escri pt ion Reset Val ue R/W 31: 0 RESTAR T _ KEY Re sta rt Ke y . A w ri te to thi s re g is ter w ith the cor re ct ke y va lue , 0xEC D9F 7BD , r est arts t h e W DOG prim ary c ounter [...]

19: Syst em A dd ress Map GP4020 GPS Baseband Processor Design Manual 181 19 A DDRESS M A PS 19.1 GP4020 S ystem A d dress M ap The GP4020 has the Addre ss Map a s show n in Tabl e 19.1 below . ADDRESS R AN G E FUNCTION M PC A r ea NOTES 0x00 00 000 0 - 0x0 00 F FFFF I nter nal B oot RO M or E xt ernal B oot ROM vi a NS CS[ 0] 1 1 0x 001 0 0000 - 0[...]

19: Syst em A dd ress Map 182 GP4020 GPS Baseband Processor Design Manual a) G a te N SCS[2A] ex ternally w ith S ADD[19] t o p roduce a smal l e r ex ternal add ress s pace for NSCS[2A ], but without the r e f lect i on of t he internal l og ic once eve ry 0x2000. The truth-tab l e shown i n Tabl e 19.2 bel ow : NS C S[2A] SADD[19] EXTERNAL CHIP S[...]

19: Syst em A dd ress Map GP4020 GPS Baseband Processor Design Manual 183 19.2 GP4020 Firefly MF1 A d dress M ap The Firef l y MF 1 B µ ILD bus modules have the address map as shown in Tabl e 19.6 bel ow , in the range 0x E000 0000 to 0xE007 FFFF. ADDRESS R AN G E FUNCTION 0xE 000 2000 - 0 x E 000 2F FF S yst em C onfi gur at i on (i ncl udi ng S [...]

19: Syst em A dd ress Map 184 GP4020 GPS Baseband Processor Design Manual Thi s page intentional ly left bl ank.[...]

20: I nput / Output pin Charact eristi cs GP4020 GPS Baseband Processor Design Manual 185 20 INPUT / OU TPUT PIN CH A R ACTERISTICS The GP4020 E l e ctric a l Chara ct e ristics, whi ch are specific to the GP4020 devi ce are shown in the “ GP 4020 GPS Base band Proce ssor Data shee t” , DS51 34, ava ilable f rom Zarlink S e mi cond uctor. In th[...]

20: I nput / Output pin Charact eristi cs 186 GP4020 GPS Baseband Processor Design Manual Pi n No . Pi n Na m e Pi n Typ e IP / O P Ce ll Typ e 5V Tol.? Ho ld Cell? Pull- up/ - down Tri - stat e No te s 34 SDAT A[12] IP/OP CLAIO1HD0 3N No Yes None Yes 35 SDAT A[13] IP/OP CLAIO1HD0 3N No Yes None Yes 36 SDAT A[14] IP/OP CLAIO1HD0 3N No Yes None Yes [...]

20: I nput / Output pin Charact eristi cs GP4020 GPS Baseband Processor Design Manual 187 Pi n No . Pi n Na m e Pi n Typ e IP / O P Ce ll Typ e 5V Tol.? Ho ld Cell? Pull- up/ - down Tri - stat e No te s 7 7 U2 RX D IP SC JIP 1N R Ye s No No ne - 78 U1T XD OP CLAO P03 L1 - - - N o 7 9 U1 RX D IP SC JIP 1N R Ye s No No ne - 80 PLLGN D PW R CLP LLV M [...]

20: I nput / Output pin Charact eristi cs 188 GP4020 GPS Baseband Processor Design Manual Input edge 0.1ns Inpu t e dge 1.5n s Switch ing De lay (n s) Load (fF) Load (fF) 50 100 25 0 50 0 10 00 50 10 0 25 0 500 1000 IP → D ↑ 0.29 0. 34 0.4 9 0.7 4 1.2 3 0.4 0 0.4 5 0.6 0 0.8 4 1.3 4 IP → D ↓ 0.29 0. 31 0.3 9 0.5 1 0.7 6 0.6 2 0.6 4 0.7 2 0.[...]

20: I nput / Output pin Charact eristi cs GP4020 GPS Baseband Processor Design Manual 189 20.3. 1.2 Norm a l N ou tput s (3.3V ou tputs): CLA IO1HD01N, CL AIO1NR01N , CLAOP01N . Input edge 0.1ns Inpu t e dge 1.5n s Sw itc hin g De lay (ns) Load (pF) Load (pF) 10 20 40 80 150 10 20 40 80 150 D → OP ↑ 5. 82 6.99 8. 89 11.75 15.76 5.55 6. 72 8.62 [...]

20: I nput / Output pin Charact eristi cs 190 GP4020 GPS Baseband Processor Design Manual 20.3. 2.2 Norm a l N ou tput s : CLAI O 1HD03N , CLA OP03N . Input edge 0.1ns Inpu t e dge 1.5n s Switch ing De lay (n s) Load (pF) Load (pF) 10 20 40 80 150 10 20 40 80 15 0 D → OP ↑ 5.8 2 6.99 8.8 9 11.75 15.76 5. 55 6. 72 8.62 11. 48 15. 49 D → OP ↓[...]

20: I nput / Output pin Charact eristi cs GP4020 GPS Baseband Processor Design Manual 191 Para mete r Cell Type Mi n Typ Max Unit Conditi ons Input Leakage All IP -1 +1 µ A N o P ull Up /D own, VDD = 3. 6V Outp ut ( Tr ist at e) L eak ag e All OP 1 µ A N o Pull Up /D own, VD D = 3.6V Inp ut C apac it anc e All I P 5 pF N ot incl ud ing P ac kag e[...]

20: I nput / Output pin Charact eristi cs 192 GP4020 GPS Baseband Processor Design Manual Thi s Page intenti onall y l ef t bl ank.[...]

21: T i m ing Characteri stics GP4020 GPS Baseband Processor Design Manual 193 2 1 T IM IN G CHA RA CTE R IS TI CS Th e t im i ng p a r am eter s i n thi s sec ti o n a ssum e a l o gi c s wi t chi n g p oi nt of 5 0% of VDD: All inpu ts assu m e rise and f all tim e s of nomina lly 2ns. Minimum (min) and max im um (max) figures are refe rence d at[...]

21: T i m ing Characteri stics 194 GP4020 GPS Baseband Processor Design Manual SDATA NSOE NSWE NSCS SADDR BuILD_CLK Taddrh Tncs Tnoe Taddr Tncsh Tdih Tnoeh Tdisu Figu re 2 1.2 MPC T imin g D iagra m - E xt erna l Me mory Re ad Cy cle Note : Th ese M PC W r i t e an d Rea d tr a nsa c ti o ns ar e t h e sam e wh et her t h e ARM 7T DM I co r e or t [...]

21: T i m ing Characteri stics GP4020 GPS Baseband Processor Design Manual 195 21.2 Mem ory Per ipheral C ontroller (M PC) E xternal R ead & Write tim ing pa rame te rs wi th SWa it Cont rol Me m ory a ccesse s with S W a i t co ntrol ha ve default of one wait-sta te access , in addition to addi tional wa it-state s triggered by an ex ternal S [...]

21: T i m ing Characteri stics 196 GP4020 GPS Baseband Processor Design Manual For this ex am ple an edge trigge r e d packet t ra nsf e r (size = 2) i s shown . NOT E : W h en p er f orm i n g a DM A tr a ns f er , m e m o ry s i g nal s ar e a s p er th e MPC ti mi ng inf o rm at i on . Para me ter M in M ax Unit Descr ipt ion and n ot es Td re q[...]

21: T i m ing Characteri stics GP4020 GPS Baseband Processor Design Manual 197 21.6 Sy stem Se rvices Modu le (SSM ) Broadcast Dia gnostic Tim ing Diagram s The S BDIAG l ines referred to here are the Xdiag[3:0] lines whi ch can be conf i gu red with i n the SSM to be mu ltip le xe d w ith t he JTA G inte rfac e , to allo w ac ce ss to an y SA DD o[...]

21: T i m ing Characteri stics 198 GP4020 GPS Baseband Processor Design Manual Parame ter M in M ax unit s Des cript ion an d note s T bsc l 15. 6 - ns T CK l ow p e r i od T bsc h 15. 6 - ns T CK hig h peri od Tbsis 5.0 - ns TDI,T MS s e t up t o [TCr] Tbsih 5.0 - ns T DI,TMS hold f r o m [TCr] Tbsoh 2.4 - ns T DO hold time Tb sod - 2 5 ns TCr to [...]

GP4020 GPS Baseband Processor Design Manual Index - I INDEXES[...]

Index - I I GP4020 GPS Baseband Processor Design Manual Thi s page intentional ly left bl ank[...]

GP4020 GPS Baseband Processor Design Manual Index - I II Table of Figu re s Page Fig ure 1.1 GP 40 20 B loc k D iag ra m ............................................................................................... ....................... 2 Figure 1.2 Bloc k Diag r a m of typ i c al GP4020 based GPS r e ceiver ....................................[...]

Index - IV GP4020 GPS Baseband Processor Design Manual Figure 12.10 Pe ri phe ral Cont r ol Log ic - Multiplex Logic .................................................................................... 120 Fig ure 12.1 1 Pe riphe ral C o nt rol L og ic - P e rip he ral In terru pt a nd W a ke -up con tro l log ic ...................................[...]

GP4020 GPS Baseband Processor Design Manual Index - V Thi s page intentional ly left bl ank[...]

Index - VI GP4020 GPS Baseband Processor Design Manual Table of D ata Tabl es Page Table 2 .1 GP4020 100-p in package dimens i on s ........................................................................ 1 3 Table 2 .2 G P4020 100-p in package Signa l Descript i ons ............................................................ 1 6 Table 3 .1 Standa[...]

GP4020 GPS Baseband Processor Design Manual Index - VI I Ta ble 7 .18 C OR R C Hx _C ODE _DC O_P HA SE Re giste r .............................................................74 Tabl e 7 .1 9 CORR CHx_CODE_DCO_PRESET_ PHASE Regis ter ..............................................74 Ta ble 7 .20 C OR R C Hx _C ODE _PH AS E Re giste r ...............[...]

Index - VI II GP4020 GPS Baseband Processor Design Manual Ta ble 12 .8 PC L PE R_ STA T R e gis te r ...................................................................................... 130 Ta ble 13 .1 Re al T ime Clo ck Re giste r M ap ............................................................................... 13 2 Ta ble 13 .2 RT C_ PR E R[...]

GP4020 GPS Baseband Processor Design Manual I ndex - IX Table 18 .1 W atchdog R egister M ap ......................................................................................... 178 Table 18 . 2 W atchdog C O NSTAT R egister ............................................................................... 179 Table 18 .3 W atchdog REL OAD Re gi [...]

Index - X GP4020 GPS Baseband Processor Design Manual Thi s page intentional ly left bl ank[...]

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