Lantronix DSTni DSTni-EX manual

Part Number 900-335 Revision A 3/04 DSTni-EX User Guide Section Five[...]

[...]

i Copyright & Trademark © 2003 Lantronix, Inc. All rights reserved. Lantronix and the Lantronix logo, and combinati ons thereof are registered trademarks of Lantronix, Inc. DSTni is a registered trademark of Lantronix, Inc. Ethernet is a registered trademark of Xerox Corporation. All other product names, company names, logos or other designati[...]

ii Warranty Lantronix warrants each Lantronix product to be free from defects in material and workmanship for a period specified on the product warranty r egistration card after the date of shipment. During this period, if a customer is unable to resolve a product problem with Lantronix Technical Support, a Return Material Authorization (RMA ) will[...]

iii Contents Copyright & Trademark ________________________________________________________ i Warranty ___________________________________________________________________ ii Contents ___________________________________________________________________ iii List of Tables _______________________________________________________________ iv List of F[...]

iv Host Mode Op eration ________________________________________________________ 50 Sample Host M ode Operations ________________________________________________ 51 USB Pull-up/Pull-do wn Resistors_______________________________________________ 53 USB Interface Signals _______________________________________________________ 54 5: CAN Controllers __[...]

v Table 3-17. Clock C ontrol Regi ster ........................................................................................... 28 Table 3-18. Clock Control Register Defi nition s.......................................................................... 28 Table 3-19. Extended Slav e Address R egister ............................................[...]

vi Table 5-34. Tx/Rx Mess age Level R egister .............................................................................. 71 Table 5-35. Tx/Rx Message Le vel Register Definiti ons ............................................................. 71 Table 5-36. In terrupt Flags .........................................................................[...]

1 1 1 : : A A b b o o u u t t T T h h i i s s U U s s e e r r G G u u i i d d e e This User Guide describes the technical feat ures and programming interfaces of the Lantronix DSTni-EX chip (hereafter referred to as “DSTni”). DSTni is an Application Specific Integrated Circui t (ASIC)-based single-chip solution (SCS) that integrates the leading[...]

2 Intended Audience This User Guide is intended for use by hardware and software engineers, programmers, and designers who understand the basic operating princi ples of microprocessors and their systems and are considering designing sy stems that utilize DSTni. Conventions This User Guide uses the following conventions to alert you to information o[...]

3 Organization This User Guide contains information essential for system architects and design engineers. The information in this User Guide is organized into the following chapters and appendixes.  Section 1: Introduction Describes the DSTni architecture, design benefits, theory of operations, ball assignments, packaging, and electrical specifi[...]

4 2 2 : : S S P P I I C C o o n n t t r r o o l l l l e e r r This chapter describes the DSTni Serial Peripheral Interface (SPI) controller. Topics include:  Theory of Operation on page 4  SPI Controller Register Summary on page 5  SPI Controller Register Definitions on page 6 Theory of Operation SPI Background SPI is a high-speed synchron[...]

5 When operating as a slave, the SPI clock signal (SCLK) must be slower than 1/8th of the CPU clock (1/16th is recommended). Note: The SPI is fully synchronous to the CLK si gnal. As a result, SCLK is sampled and then operated on. This results in a delay of 3 to 4 cl ocks, which may violate t he SPI specification if SCLK is faster than 1/8th of the[...]

6 SPI Controller Register Definitions SPI_DATA Register SPI_DATA is the SPI Controller Data register. Table 2-2. SPI_DATA Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B800 FIELD /// DATA[7:0] RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW R W RW RW RW RW RW RW RW RW RW RW RW RW RW Table 2-3. SPI_DATA Register Definitions Bits Field Nam[...]

7 CTL Register CTL is the SPI Controller Control register. Table 2-4. CTL Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B802 FIELD /// IRQENB AUTODRV INVCS PHASE CKPOL WOR MSTN ALT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW R W RW RW RW RW RW RW RW RW RW RW RW Table 2-5. CTL Register Definitions Bits Field Name Description 15:[...]

8 SPI_STAT Register To clear a bit in the SPI_STAT register, write a 1 to that bit. Table 2-6. SPI_STAT Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B804 FIELD /// IRQ OVERRUN COL /// TXRUN SLVSEL RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R Table 2-7. SPI_STAT Register Definitions Bits Field N[...]

9 SPI_SSEL Register SPI_SSEL is the Slave Select Bit Count register. Table 2-8. SPI_SSEL Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B806 FIELD /// BCNT[2:0] /// SELECTO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 2-9. SPI_SSEL Register Definitions Bits Field Name Description 15:8 ///[...]

10 DVD_CNTR_LO Register DVD_CNTR_LO is the DVD Counter Low Byte register. Table 2-11. DVD_CNTR_LO Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET B808 FIELD /// DVDCNT[7:0] RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 2-12. DVD_CNTR_LO Register Definitions Bits Field Name Description 15:8 [...]

11 3 3 : : I I 2 2 C C C C o o n n t t r r o o l l l l e e r r This chapter describes the DSTni I 2 C controller. Topics include:  Features on page 11  Block Diagram on page 12  Theory of Operation on page 12  Programmer’s Reference on page 22  I 2 C Controller Register Summary on page 22  I 2 C Controller Register Definitions o[...]

12 Block Diagram Figure 3-1 shows a block diagram of the DSTni I 2 C controller. Figure 3-1. DSTni I 2 C Controller Block Diagram Theory of Operation I 2 C Background The I 2 C bus is a popular serial, two-wire interfac e used in many systems because of its low overhead. Capable of 100 KHz operation, each device connected to the bus is software add[...]

13 I 2 C Controller The I 2 C controller base address is D000h and shares INT2 with the SPI controller. The I 2 C bus interface requires two bi-directional buffers with open collector (or open drain) outputs and Schmitt inputs. Operating Modes The following sections describe the possible I 2 C operating modes:  Master Transmit Mode, page 13  [...]

14 Table 3-1. Master Transmit Status Codes Code I 2 C State Microprocessor Response Next I 2 C Action 18h Addr + W transmitted, ACK received 7-bit address: Write byte to DATA, clear IFLG OR Set STA, clear IFLG OR Set STP, clear IFLG OR Set STA & STP, clear IFLG 10-bit address: Write extended address byte to DATA, clear IFLG Transmit data byte, [...]

15 Servicing the Interrupt After servicing this interrupt, and transmitting the second part of the address, the Status register contains one of the codes in Table 3-2. Note: If a repeated START condition transmits, the status code is 10h instead of 08h. Table 3-2. Codes After Servicing Interrupts (Master Transmit) Code I 2 C State Microprocessor Re[...]

16 Transmitting Each Data Byte After each data byte transmits, the IFLG is set, and one of the three status codes in Table 3-3 is in the Status register. Table 3-3. Status Codes After Each Data Byte Transmits Code I 2 C State Microprocessor Response Next I 2 C Action 28h Data byte transmitted, ACK received Write byte to DAT, clear IFLG OR Set STA, [...]

17 Table 3-4. Master Receive Status Codes Code I 2 C State Microprocessor Response Next I 2 C Action 40h Addr + W transmitted, ACK received 7-bit address: Clear IFLG, AAK=0 OR Clear IFLG, AAK=1 10-bit address: Write extended address byte to DATA, clear IFLG Transmit data byte, receive not ACK Receive data byte, transmit ACK Transmit extended addres[...]

18 Servicing the Interrupt After servicing this interrupt and transmitting the second part of the address, the Status register contains one of the codes in Table 3-5. Table 3-5. Codes After Servicing Interrupt (Master Receive) Code I 2 C State Microprocessor Response Next I 2 C Action 38h Arbitration lost Clear IFLG OR Set STA, clear IFLG Return to[...]

19 Receiving Each Data By te After receiving each data byte, the IFLG is set and one of three status codes in Table 3-6 is in the Status register. When all bytes are received, set the STP bit by writing a 1 to it in the Control register. The I 2 C controller:  Transmits a STOP condition  Clears the STP bit  Returns to the idle state Table [...]

20 − The IFLG is set and the Status register contains B8h. − After the last transmission byte loads in the Data register, clear AAK when IFLG clears. − After the last byte is transmitted, the IFLG is set and the Status register contains C8h. − The I 2 C controller returns to the idle state and the AAK bit must be set to 1 before slave mode [...]

21 Bus Clock Considerations Bus Clock Speed The I 2 C bus can be defined for bus clock speeds up to 100 Kb/s and up to 400 Kb/s in fast mode. To detect START and STOP conditions on the bus, the M I 2 C must sample the I 2 C bus at least 10 times faster than the fastest master bus clock on the bus. The sampling frequency must be at least 1 MHz (4 MH[...]

22 Resetting the I 2 C Controller There are two ways to reset the I 2 C controller.  Using the RSTIN# pin  Writing to the Software Reset register Using the RSTIN# pin reset method:  Clears the Address, Extended Slave Address, Data, and Control registers to 00h.  Sets the Status register to F8h.  Sets the Clock Control register to 00h[...]

23 I 2 C Controller Register Definitions Slave Address Register Table 3-8. Slave Address Register BIT 7 6 5 4 3 2 1 0 OFFSET D000 EXTENDED ADDRESS 1 1 1 1 0 SLAX9 SLAX8 General Call Address Enable FIELD SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 GCE RESET 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW Table 3-9. Address Register Definitions Bits Field Name Des[...]

24 Data Register The Data register contains the transmission data/slave address or the receipt data byte.  In transmit mode, the byte is s ent most-significant bits first.  In receive mode, the first bit received is plac ed in the register’s most-significant bits. After each byte transmits, the Data register contains the byte pr esent on th[...]

25 Control Register Table 3-12. Control Register BIT 7 6 5 4 3 2 1 0 OFFSET D004 FIELD IEN ENAB STA STP IFLG AAK /// /// RESET 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW Table 3-13. Control Register Definitions Bits Field Name Description 7 IEN Extended Slave A ddress l = interrupt line (INTR) goes HIGH when the IFLG bit is set. 0 = interrupt line [...]

26 Bits Field Name Description 2 AAK A cknowledge 1 = send Acknowledge (LOW level on SDA) during acknow ledge clock pulse on the I 2 C bus if: − The entire 7-bit slave address or the fi rst or second bytes of a 10-bit slave address are received. − The general call address is received and t he GCE bit in the ADDR register is set to one. − A da[...]

27 Table 3-15. Status Register Definitions Bits Field Name Description 7:3 STATUS CODE Status Code Five-bit status code. See Table 3-16. 2:0 /// Reserved Table 3-16. Status Codes Code Description 00h Bus error 08h START condition sent 10h Repeated START condition sent 18h Address + w rite bit sent, ACK received 20h Address + w rite bit sent ACK not[...]

28 Clock Control Register The Clock Control register is a Write Only regist er that contains seven least-significant bits. These least-significant bi ts control the frequency:  At which the I 2 C bus is sampled.  Of the I 2 C clock line (SCL) when the I 2 C controller is in master mode. The CPU clock frequency (of CLK) is first divided by a f[...]

29 Extended Slave Address Register Table 3-19. Extended Slave Address Register BIT 7 6 5 4 3 2 1 0 OFFSET D008 FIELD SLAX7 SLAX6 SLAX5 SLAX4 SLAX3 SLAX2 SLAX 1 SLAX0 RESET 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW Table 3-20. Extended Slave Address Register Definitions Bits Field Name Description 7 SLAX7 Extended slave address. 6 SLAX6 Extended sl[...]

30 4 4 : : U U S S B B C C o o n n t t r r o o l l l l e e r r This chapter describes the DSTni Universal Serial Bus (USB) controller. Topics include:  Features on page 30  Theory of Operation on page 31  USB Register Summary on page 38  USB Register Definitions on page 39  Host Mode Operation on page 50  Sample Host Mode Operatio[...]

31 Theory of Operation USB Background USB is a serial bus operating at 12 Mb/s . USB provides an expandable, hot-pluggable Plug- and-Play serial interface that ensures a standard, low-cost socket for adding external peripheral devices. USB allows the connection of up to 127 devices. Devices suitable for USB range from simple input devices such as k[...]

32 Microprocessor Interface The USB microprocessor interface is made up of a slave interface and a master interface.  The slave interface consists of a number of USB control and configuration registers. USB internal registers can be accessed usi ng a simple microprocessor interface.  The master interface is the integrated DMA controller that [...]

33 Figure 4-1. Buffer Descriptor Table The microprocessor manages buffers intelligent ly for the USB by updating the BDT as necessary. This allows the USB to handle data transmission and reception efficiently while the microprocessor performs communication-ov erhead processing and other function-dependent applications. Because the microprocessor an[...]

34 Table 4-1. USB Data Direction Rx Tx Device OUT or SETUP IN Host IN OUT or SETUP Addressing BDT Entries Before describing how to access endpoint data via t he USB or microprocessor, it is important to understand the BDT addressing mechanism. The BD T occupies up to 256 bytes of system memory. Sixteen bidirectional endpoints can be s upported with[...]

35 Table 4-4. BDT Data Used by USB Controller and Microprocessor USB Controller Determines… Microprocessor Determines… Who owns the buffer in sy stem memory Who ow ns the buffer in system memory Data0 or Data1 PID Data0 or Data1 PID Release Own upon packet completion No address increment (FIFO Mode) Data Toggle Synchronization enable Amount of [...]

36 Table 4-6. USB Buffer Descriptor Format Definitions Bits Field Name Description 7 OWN BD Ow ner Specifies which unit has exclusive access to the BD. 0 = microprocessor has exclusive and entir e BD access; USB ignores all other fields in the BD 1 = USB has exclusive BD access SIE writes a 0 to this bit w hen it completes a token, except when KEEP[...]

37 USB Transaction When the USB transmits or receives data: 1. The USB uses the address generation in Table 4-5 to compute the BDT address. 2. After reading the BDT, if the OWN bit equals 1, the SIE DMAs the data to or from the buffer indicated by the BD’s ADDR field. 3. When the TOKEN is complete, the USB updat es the BDT and changes the OWN bit[...]

38 USB Register Summary Table 4-7. USB Register Summary Hex Offset Mnemonic Register Description Page 00 INT_STAT Bits for each interrupt source in the USB. 39 02 ERR_STAT Bits for each error source in the USB. 41 04 STAT Transaction status in the USB. 43 06 ADDR USB address that the USB decodes in peripheral mode. 45 08 FRM_NUM Contains the 11-bit[...]

39 USB Register Definitions The following sections provide the USB r egister definitions. In these sections:  The register mnemonic is provided for reference purposes.  The register address shown is the address location of the register in the CRB.  The initialization value shown is the r egister’s initialization value at reset. Interrupt[...]

40 Bits Field Name Description 8 USB_RST Enable/Disable USB_RST Interrupt 1 = enable the USB_RST interrupt. 0 = disable the USB_RST interrupt ( default ). 7 STALL Stall Used in target and host modes. • In target mode, it asserts w hen the SIE sends a stall handshake. • In host mode, it is set if the USB detects a stall acknow ledge during the h[...]

41 Error Register The Error register contains bits for each of the error sources in the USB. Each of these bits is qualified with its respective error enable bits. The result is OR’ed together and sent to the ERROR bit of the Interrupt Status register. Once an interrupt bit has been set it may only be cleared by writing a one to the respective in[...]

42 Bits Field Name Description 5 DMAERR 1 = USB requests a DMA access to r ead a new BDT, but is not given the bus before USB needs to receive or transmit data. • If processing a TX transfer, this c auses a transmit data underflow condition. • If processing an Rx transfer, this caus es a receive data overflow condition. This interrupt is useful[...]

43 Status Register The Status register reports t he transaction status within the USB. When the microprocessor has received a TOK_DNE interrupt, the Status register should be read to determine the status of the previous endpoint communication. The data in the status register is valid when the TOK_DNE interrupt bit is asserted. The Status register i[...]

44 Bits Field Name Description 12 RESET USB Reset Signal 1 = enables the USB to generate USB reset signaling. This allows the USB to reset USB peripherals. This control si gnal is only valid in host mode, (i.e., HOST_MDOE_EN=1). Software must set R ESET to 1 for the required amount of time and then clear it to 0 to end reset signaling. For more inf[...]

45 Address Register The Address register contains the unique U SB address that the USB decodes in peripheral mode (HOST_MODE_EN=0). In host mode (HOS T_MODE_EN=1), the U SB transmits this address with a TOKEN packet. This enables t he USB to uniquely address any USB peripheral. In either mode the USB_EN bit in the Control r egister must be set. The[...]

46 Frame Number Registers The Frame Number registers contain the 11-bi t frame number. The current frame number is updated in these registers when a SOF_TOKEN is received. Table 4-16. Frame Number Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 08h FIELD /// FRM[10:0] RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R [...]

47 Token Register The Token register performs USB transacti ons when in host mode (HOST_MODE_EN=1). When the host microprocessor wants to execute a USB transaction to a peri pheral, it writes the TOKEN type and endpoint to this register. After th is register is written, the USB begins the specified USB transaction to the address contained in the Ad[...]

48 Table 4-18. Token Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0Ah SOF Threshold Register Token Register FIELD CNT[7:0] TOKEN_PID TOKEN_ENDPT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W Table 4-19. Token Register Definitions Bits Field Name Description 15:8[...]

49 Endpoint Control Registers The Endpoint Control registers contain the endpoint control bits for the 16 endpoints available on USB for a decoded address. These four bits define all the control necessary for any one endpoint. Endpoint 0 (ENDPT0) is associated with control pipe 0, which is required by USB for all functions. Therefore, after receivi[...]

50 Table 4-23. Endpoint Control Register Definitions EP_CTL_DIS EP_RX_EN EP_TX_EN Endpoint Enable / Direction Control /// 0 0 Disable endpoint. /// 0 1 Enable endpoint for TX transfer only. /// 1 0 Enable endpoint for RX transfer only. 1 1 1 Enable endpoint for RX and TX transfers. 0 1 1 Enable endpoint for RX and TX and control (SETUP) transfers. [...]

51 Sample Host Mode Operations Figure 3. Enable Host Mode and Configure a Target Device[...]

52 Figure 4. Full-Speed Bulk Data Transfers to a Target Device[...]

53 USB Pull-up/Pull-down Resistors USB uses pull-up or pull-down resistors to deter mine when an attach or detach event occurs on the bus. Host mode complicates the resistors, since it requires devices to operate as either a USB target device or a USB host. Figure 4-5 shows the two resistor combinations required for USB targets and hosts. Normally,[...]

54 USB Interface Signals Clock (CLK) The clock input is required to be connec ted to a 12 MHz signal that is derived from the USB signals. USP Speed (SPEED) The USB speed indicator is used by ex ternal USB transceiver logic to determine which speed interface the USB is implementing. 1 = USB is operating at full speed. 0 = USB is a low-speed device.[...]

55 5 5 : : C C A A N N C C o o n n t t r r o o l l l l e e r r s s This chapter describes the DSTni CAN controller. Topics include:  CANBUS Background on page 56  Features on page 57  Theory of Operation on page 58  CAN Register Summaries on page 58  CAN Register Definitions on page 63  CAN Bus Interface on page 84 This chapter as[...]

56 CANBUS Background CAN is a fast and highly reliable, multicast/mul timaster, prioritized serial communications protocol that is designed to provide reliable and cost-effective links. CAN uses a twisted-pair cable to communicate at speeds of up to 1 MB/s with up to 127 nodes. It was originally developed to simplify wiring in automobiles. Today, i[...]

57 CANBUS Speed and Length Table 7-1 shows the relationship bet ween the bit rate and cable length. Table 5-1. Bit Rates for Different Cable Lengths Bit Rate Cable Length 10 KB/s 6.7 km 20 KB/s 3.3 km 50 KB/s 1.3 km 125 KB/s 530 m 250 KB/s 270 m 500 KB/s 130 m 1 MB/s 40 m Features  Three programmable acceptance filters − Message filter covers:[...]

58 Theory of Operation The CAN controller appears to the microprocesso r as an I/O device. Each peripheral has 256 bytes of I/O address space allocated to it. CAN0 and CAN1 share Interrupt 6. Table 5-2. CAN I/O Address CAN Controller Base Address CAN0 A800h CAN1 A900h CAN Register Summaries DSTni contains two independent CAN channels. Operation and[...]

59 Hex Offset Register 30 RxMessage: ID, ID28-13 32 ID12-00 34 RxMessage: Data, D55-48, D63-56 36 D39-32, D47-40 38 D23-16, D31-24 3A D07-00, D15-08 3C RxMessage: RTR, IDE, DLC_3-0,AFI_2-0 3E RxMessage: Control Flags, Fifo_Lvl_2-0, MsgAval 40 Transmitter and Receive Error Counter 42 Error Status 44 Message Level Threshold 46 Interrupts Flags 48 Int[...]

60 Detailed CAN Register Map Table 5-4. Detailed CAN Register Map Hex Offset Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 TX Msg 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 0x02 /// ID12 ID11 ID10 ID09 ID08 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 /// /// /// 0x04 /// D55 D54 D53 D52 D51 D50 D49 D48 D63 D[...]

61 Hex Offset Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30 RX Msg ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 0x32 /// ID12 ID11 ID10 ID09 ID08 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 /// /// /// 0x34 /// D55 D54 D53 D52 D51 D50 D49 D48 D63 D62 D61 D60 D59 D58 D57 D56 0x36 /// D39 D38 D37 D36 D35 D34 D33 D[...]

62 Hex Offset Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x52 Acceptance Mask Register 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 0x54 /// ID12 ID11 ID10 ID09 ID08 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 IDE RTR /// 0x56 /// D55 D54 D53 D52 D51 D50 D49 D48 D63 D62 D61 D60 D59 D58 D57 D56 0x58 Acceptance Co[...]

63 CAN Register Definitions TX Message Registers To avoid priority inversion issues in the transmi t path, three transmit buffers are available with a built-in priority arbiter. When a message is trans mitted, the priority arbiter evaluates all pending messages and selects the one with the highest prio rity. The message priority is re-evaluated aft[...]

64 Tx Message Registers Table 5-5 shows TxMessage_0 registers. The registers for TxMessage_1 and TxMessage_2 are identical except for the offsets. Table 5-5. TxMessage_0:ID28 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 00h FIELD ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 Table 5-6. TxMessage_0:ID12 BIT 15 1[...]

65 Table 5-12. TxMessage_0:Ctrl Flags BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0E FIELD /// /// /// /// /// /// /// /// /// /// /// /// /// /// Tx Abort TRX Table 5-13. TxMessage_0 Register Definitions Field Name Description ID_28:ID_0 Message Identifier for Both Standard and Extended Messages Standard messages use ID_28 .. ID_18 D_63:D_0 M[...]

66 RX Message Registers A 4-message-deep FIFO stores the incoming me ssages. Status flags indicate how many messages are stored. Additional flags determine from which acceptance filter the actual message is coming from. Figure 5-2. RX Message Routing RxMessage 1 MESSA G E FI LTERS CAN Modul e uP Bus CAN BUS RxMessage 0 RxMessage 3 RxMessage 2 To re[...]

67 Rx Message Registers The following table shows RxMessage registers. See the complete register table at the start of this section. Table 5-14. RxMessage:ID28 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 30h FIELD ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R[...]

68 Table 5-20. Rx Message: Data 39 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 36h FIELD D39 D38 D37 D36 D35 D34 D33 D32 D47 D46 D45 D44 D43 D42 D41 D40 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-21. Rx Message: Data 39 Register Definitions Bits Field Name Description 15:0 [...]

69 Table 5-26. RxMessage: RTR BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 3C FIELD /// AFI_2 AFI_1 AFI_0 /// RTR IDE DLC_3 DLC_2 DLC_1 DLC_0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-27. Rx Message: RTR Register Definitions Bits Field Name Description 15:11 /// Reserved 10[...]

70 Error Count and Status Registers Table 5-30. Tx/Rx Error Count BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 40h FIELD RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 TE7 TE6 TE5 TE4 TE3 TE2 TE1 TE0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-31. TxRx Error Count Register Definitions Bits[...]

71 Table 5-34. Tx/Rx Message Level Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 44h FIELD /// RL1 RL0 TL1 TL0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-35. Tx/Rx Message Level Register Definitions Bits Field Name Description 15:4 /// Reserved 3:1 RL[1:0] rx_level[1[...]

72 Interrupt Flags The following flags are set on internal events (they activate an interrupt line when enabled). They are cleared by writing a ‘ 1’ to the appropr iate flag. Acknowledging the tx_msg interrupt also acknowledges all tx_xmit interrupt source s. Acknowledging one of the tx_xmit interrupt sources also acknowledges the tx_msg interr[...]

73 Interrupt Enable Registers All interrupt sources are grouped into three groups (traffic, error and diagnostics interrupts). To enable a particular interrupt, set its enable flag to ‘ 1’ . Table 5-38. Interrupt Enable Registers BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 48h FIELD RX_MSG TX_MSG TX_XMIT2 TX_XMIT1 TX_XMIT0 BUS_OFF CRC_ERR [...]

74 Bits Field Name Description 3 OVR_LOAD Ov erload Condition − int3n group (diagnostic interrupts) 1 = enable flag set. 0 = enable flag not set. 2 ARB_LOSS A rbitration Loss − int3n group (diagnostic inte rrupts) 1 = enable flag set. 0 = enable flag not set. 1 /// Reserved 0 INT_ENB General Interrupt Enable 1 = enable flag set. 0 = enable flag[...]

75 Figure 5-3. CAN Operating Mode CAN Module 1 CAN Module 2 a c b d CAN Port 1 CAN Port 2 DSTni Note: The Loopback Mode register in CAN module 2 is not functional. For proper operation in loopback mode, the configuration of both CAN modules must be the same. CAN Configuration Registers The following registers set bit rate and other configuration pa[...]

76 Table 5-44. Configuration Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 4Eh FIELD OVR_MSG TS2_2 TS2_1 TS2_0 TS1_3 TS1_2 TS1_1 TS1_0 /// AUTO_RES CFG_SJW1 SAMP_MOD EDGE_MOD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-45. Configuration Register Definitions Bits Field[...]

77 The following relations exist for bit time, time quanta, time segments ½, and the data sampling point. Figure 5-4. Bit Time, Time Quanta, and Sample Point Relationships Bit Time 1 tse g1 + 1 tseg2 + 1 time quanta (TQ) Sampl e Po int Bittime = (1+ ( tseg1 + 1) + (tseg2 + 1)) x timequanta timequanta = (bitrate +1) / f clk e.g., for 1Mbps with f c[...]

78 Acceptance Filter and Acceptance Code Mask Three programmable Acceptance Mask and Acceptanc e Code register (AMR/ACR) pairs filter incoming messages. The acceptance mask register (AMR) defines whether the incoming bit is checked against the acceptance code register (ACR). Table 5-46. Acceptance Filter Enable Register BIT 15 14 13 12 11 10 9 8 7 [...]

79 Table 5-50. Acceptance Mask Register: ID 12 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 54h FIELD ID12 ID11 ID10 ID09 ID08 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 IDE RTR /// RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-51. Acceptance Mask Register: ID12 Definitions Bits F[...]

80 Table 5-54. Acceptance Code Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 58h FIELD ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-55. Acceptance Code Register Definitions Bits Field Name [...]

81 CANbus Analysis Three additional registers are provided for advanc ed analysis of a CAN system. These registers include arbitration lost and error capture regist ers, as well as a CANbus frame reference register that contains information about the CANbus state and the physical Rx and TX pins. Arbitration Lost Capture Register The Arbitration Los[...]

82 Error Capture Register The Error Capture register captures the most recent error event with the frame reference pointer, rx- and tx-mode and t he associated error code. Table 5-62. Error Capture Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 78h FIELD ERR2 ERR1 ERR0 FR4 FR3 FR2 FR1 FR0 TX_MOD RX_MOD FRB5 FRB4 FRB3 FRB2 FRB1 FRB0 RESET[...]

83 Frame Reference Register The Frame Reference register contains informat ion of the current bit of the CAN message. A frame reference pointer indicates the current bit position. This enables message tracing on bit level. Note: The reset value of this register’s bits is indeterm inate. Table 5-64. Frame Reference Register BIT 15 14 13 12 11 10 9[...]

84 Bits Field Name Description 5:0 FRB[5:0] frame_ref_bit_nr A 6-bit vector that counts t he bit numbers in one field. Example: if field = “data” = “01010”, “bit_nr” = “000000”, and “tx_mode” = ‘1’, it indicates that the first data bit is being transmitted. CAN Bus Interface DSTni contains two complete CAN controllers, CAN0 [...]

85 You can also provide local isolated power for t he transceiver circuits, as required when using CANopen. If you are using both DeviceNet and CANopen, use the jumpers to select between bus power (+5_BUS) or isolated power (ISO_P WR). The jumpers P_C05V and P_C0G will then provide +5_CAN and GND_CAN to the transceiver circuits. Note: Diagrams are [...]

86 Figure 5-8. CAN Transceiver and Isolation Circuits +5_CAN 1 U6 HCPL-O601 VCC GND 8 5 C67 0. 01uf R191 680 7 +3.3 v 2 R193 270 CAN_TX 3 4 +5_CAN 47 0 6 RXD 4 TXD U18 PCA82C2 51 CANL CANH 6 CAN- 7 CAN+ C10 0. 01uf GND_ CAN 3 V+ 82 GND_CA N GND RS 1 GND_CA N C9 0. 01uf 1 VCC GND 8 5 C12 0. 01uf R190 680 7 +5v( F) 2 R189 CAN_RX 3 4 6 U19 HCPL-0601 C[...]

87[...]