Epson S1D13708 Bedienungsanleitung

S1D13708 Embedded Memor y LCD Controller S1D13708 TECHNICAL MANU AL Docu ment Numb er: X39 A-Q -001 -01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev aluating Seik o Epson/EP[...]

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Epson Research and Development Page 3 Vancouver Des ign Center TECHNICAL MANUAL S1D13708 Issue Date: 01/10/09 X39A-Q-001-01 COMPREHENSIV E SUPPOR T T OOLS EPSON provi des the desig ner and manufacturer a comp lete set of resour ces and tool s for the dev elopment of LCD Graphi cs Syste ms. Docume ntation • T ec h nic al ma nuals • Ev alua tion/[...]

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X39A-C -001-01 1 GRAP HIC S S1D13708 ENERG Y SA VING EPSON S1D13708 Embed d ed Memory LC D Control ler July 20 0 1 The S1D13708 is a color/monochrome LCD graphics contr ol ler with an embedded memory / displ ay buffer. Targeted at PDA and Cell Phone a pplicati ons, the S1D137 08 ‘di rectly’ i nterfaces to numer ous TFT panels and incor porates [...]

X39A-C -001-01 2 GRAP HIC S S1D13708 ■ DESCRIPTION Memor y Interface • Embedde d 80K byte SRAM dis play buffer. CPU Interface • ‘Fixed’ low -lat ency C PU acces s times . • Direct suppo rt for: Hitachi SH-4 / SH-3. Motoro la M6 8x xx (DragonBall, ColdFire,REDCAP2) . MPU bus in terface with pro grammabl e READY. • InDirect Inte rface p[...]

S1D13708 Embedded Memor y LCD Controller Har dware Functional Specification Docume nt Number: X 39A- A -0 01-02 Copyright © 2001, 2002 Epson Research and De velopment, Inc. All Rights Reser ved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev aluating S[...]

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Epson Research and Development Page 3 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 T able of Contents 1 Introducti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 Overvie[...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.2.6 Motorola MC68K #2 Int erface Timin g (e.g. MC68030) . . . . . . . . . . . . . . . 54 6.2.7 Motorola REDCAP2 Interf ace Timing . . . . . . . . . . . . . . . . . . . . . . . . 56 6.2.8 Motorola Dra gonBal[...]

Epson Research and Development Page 5 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 8.3.1 Read-Only Confi guratio n Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 1 21 8.3.2 Clock Confi guratio n Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.3.3 Look-[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 16 Embedded Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.1 Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 17 Big- End ian B us Inte rfa[...]

Epson Research and Development Page 7 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 List of T ables Table 4-1: PFBGA 120-pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 4-2: S1D13708 Pad La yout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 Table 6-25: TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 6-26: 160x160 Sh arp ‘Dire ct’ HR-TFT Horizonta l Timing . . . . . . . . . . . . . . . . . [...]

Epson Research and Development Page 9 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Table 8-19: PWMOUT Duty Cycle Select Opti ons . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 8-20: Exten ded Panel Typ e Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1[...]

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Epson Research and Development Page 11 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 List of Figures Figure 3-1 Typical Syste m Diagram (Generic #1 Bus) . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 3-2 Typical Syste m Diagram (Generic #2 Bus) . . . . . . . . . . . . . . . . . . [...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 Figure 6 -27 Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2 Figure 6 -28 Single Color 16-Bit Panel A.C. Timi ng. . . . . . . . . . . . . . . . . . . . . . . . .[...]

Epson Research and Development Page 13 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Figure 14-1 Memory Mapping fo r Ink Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 87 Figure 14-2 Transparent Co lor Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1[...]

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Epson Research and Development Page 15 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1 Introduction 1.1 Scope This is th e Hardware Functiona l Specifica tion for the S1D13708 Embedded Memory LCD Controlle r. Includ ed in this document ar e timing di agrams , AC and DC charac terist ics, reg[...]

Page 16 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 2 Features 2.1 I ntegrated Fr ame Buff er • Embedded 80K byt e SRAM display b uffer. 2.2 CPU Interface • Direct su pport o f the fol lowing interfa ces: Generic MPU bus i nterf ace using WAIT# signa l. H[...]

Epson Research and Development Page 17 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 2.4 Displa y Modes • 1/2/4/8/16 bit-per -pixe l (bpp) co lor de pths. • Up to 64 gray shade s on monoc hrome passi ve LCD panels or 26214 4 colors on color passive LCD panels using Fra me Rate Modul atio[...]

Page 18 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 2.7 O perating V oltage • CORE V DD 1.62 to 1.98 volts. •I O V DD 3.0 to 3.6 volts . 2.8 Miscella neous • Hardware/So ftware Video I nvert. • Software Po wer Save mode. • General Pur pose Input /Ou[...]

Epson Research and Development Page 19 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 3 T ypical System Implementation Diagra ms . Figure 3-1 Typi cal Syste m Diagram ( Generic #1 Bus) . Figure 3-2 Typi cal Syste m Diagram ( Generic #2 Bus) S1D13708 FPLI NE FPF RAME FPS HIFT DRD Y FPDA T[15:0[...]

Page 20 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 . Figure 3- 3 Typical System Diagr am (Hitachi SH-4 Bus) S1D13708 FPLI NE FPFRAME FPSHIFT DRD Y FPD A T[9:0 ] FPLINE FPFRAME FPSHIFT DRD Y D[9:0] 12-bit SH-4 BUS RESET# WE0# D[15:0] BS# RD/WR# RD# RD Y# A[16[...]

Epson Research and Development Page 21 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 . Figure 3-4 Typical System Dia gram (Hit achi SH -3 Bus) S1D13708 FPLI NE FPF RAME FPS HIFT DRD Y FPDA T[17:0 ] FPLI NE FPF RAM E FPS HIFT DRD Y D[17:0] 18-bit SH-3 BUS RESET# WE0# D[15:0] BS# RD/WR# RD# WA[...]

Page 22 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 . Figure 3-5 Typi cal Syste m Diagram (M C68K # 1, Motor ola 16-Bit 68000) S1D13708 FPLINE FPFR AME FPSHIFT FPDA T[ 17: 0] LP SPS CLK D[17:0 ] 18-bi t MC68K #1 BUS RESET# LDS# D[15:0] AS# R/W# DT A CK# A[16:[...]

Epson Research and Development Page 23 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 . Figure 3-6 Typical Sy stem Dia gram (MC68K #2, Motorol a 32-Bit 68 030) S1D13708 FPSHIFT FPF RAME DRD Y GPIO 0 FPD A T[1 7:0] XSCL DY GCP XINH D[17:0] 18-bit MC68K #2 BUS RESET# SIZ0 D[31:16] AS# R/W# SIZ1[...]

Page 24 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 . Figure 3- 7 Typical System Di agram (Motor ola REDCAP2 Bus ) S1D137 08 FPFR AME FPSHIFT FPLI NE DRD Y FPD A T[7: 4] FPFRAM E FPSHIFT FPLI NE MOD D[3:0] 4- bit REDCAP2 BUS RESET_OUT EB1 D[15:0] R/W OE A[16:[...]

Epson Research and Development Page 25 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 . Figure 3- 8 Typical System Di agram (Motor ola MC68EZ328 /MC68VZ328 “Dr agonBall” Bus ) Figure 3-9 Typical System Dia gram (I ndirect I nterface , Mode 68) S1D13708 FPFRAME FPSHIFT FPLI NE DRD Y FPDA T[...]

Page 26 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 Figure 3- 10 Typical Syste m Diagram ( Indirect Inte rface, Mo de 80) S1D13708 RESET# D[15:0] A0 BUSC LK DB[15:0] WE1# BS# M/R# CS# CLKI RESET# A[23:17] Decoder WE0# WRL# WRU# RD# RD/WR# RDL# RDU# IO V DD FP[...]

Epson Research and Development Page 27 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 4 Pins 4.1 Pinout Diagram - PFBGA - 120pin Figure 4- 1 Pinout Diag ram - PFBGA 120- pin Table 4-1: PFBGA 120-pi n Mapping L COREVDD IOVDD AB6 AB2 DB7 DB4 DB0 WAIT# FPLINE GPIO5 IOVDD K AB7 AB5 AB4 AB3 COREVD[...]

Page 28 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 4.2 Pinout Diagram - Die Form Table 4-2: S1D13708 Pad Lay out VSS IOVDD CNF3 CNF4 CNF5 CNF6 CNF7 TESTEN GPO0 GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 VSS CLKI2 IOVDD FPSHIFT VSS COREVDD CVOUT PWMOUT GPO0 GPIO0 GPI[...]

Epson Research and Development Page 29 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 4.3 Pin Descriptions Key: 4.3.1 Host Interface I = Input O= O u t p u t IO = Bi-Directio nal (In put/Outpu t) P= P o w e r p i n PCLKI1 = CMOS/LVTTL sc hmitt in put cl ock b uffer PIC = CMOS/LVTTL in put buf[...]

Page 30 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 DB[15:0] IO C3,D1, D2,D3, D4,E1, E2,E3, H5,H6, J5,J6 , K6,L5, L6,L7 PBCC8 IOVDD Hi-Z Input data from the s ystem da ta bus . • For Generic #1 , these pi ns are connecte d to D[15 :0]. • For Generic #2 , [...]

Epson Research and Development Page 31 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 WE1# I B2 PIC IOVDD 1 This in put pin has mul tiple f unctio ns. • For Generic # 1, this pin inpu ts the write enab le signal f or th e upper d ata byt e ( WE1 #). • For Generic # 2, this pin inpu ts the[...]

Page 32 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 RD/WR# I B3 PIC IOVDD 1 This inpu t pin h as multi ple fu nction s. • For Ge neric # 1, thi s p in in pu ts th e rea d comm an d f or the upper data b yte ( RD1#). • For G eneric #2 , this pin must b e t[...]

Epson Research and Development Page 33 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 WAIT# O L8 PBCC8 C IOVDD Hi-Z During a d ata tran sfer, th is output pin is drive n active to force th e system to insert wait st ates. I t is drive n inactiv e to i ndicate th e comple tion of a d ata tran [...]

Page 34 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 4.3.2 LCD Interface Table 4-4: LCD Inte rface Pin Descri ptions Pin Name T ype PFBGA Pin # Cell IO Vo l t a g e RESET# State Description FPDAT[17:0] O A4,A5, A6,A7, A8,B4, B6,B7, B8,C4, C5,C6, C8,C9, D5,D6, [...]

Epson Research and Development Page 35 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 GPIO0 IO H10 PBCC8 IOVDD 0 This pi n has multi ple fun ctions. • PS for Sha rp HR-TFT • XINH for Epson D-TFD • VCLK for TF T T ype 2 • CPV for T ype 3 • General p urpose IO pin 0 (G PIO0) • Hardw[...]

Page 36 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 GPIO5 IO L10 PBCC8 IOVDD 0 This pin has m ultip le functio ns. • DD_P1 for Epson D-TFD • XOEV for T ype 3 • General purpose IO pin 5 (GPIO5) See Table 4-10: “L CD Interfac e Pin Map ping,” on p age[...]

Epson Research and Development Page 37 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 4.3.3 Clock Input 4.3.4 Miscellaneous 4.3.5 P ower And Gr ound Table 4-5: Clock Inpu t Pin De scriptio ns Pin N ame T y pe PFBGA Pin # Cell IO Vo l t a g e RESET# State Descri ption CLKI I F 2 PCLK1 IOVDD ?[...]

Page 38 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 4.4 Summary of Configuration Options Table 4-8: Summary of Powe r-On/Reset Options S1D137 08 Configuration Input P ow er- On/Rese t State 10 CNF4,CNF[2 :0] Select hos t bus interface as follows : CNF4 CNF2 C[...]

Epson Research and Development Page 39 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 4.5 Hos t Bus Interface Pin Mapping Not e 1 A0 f or the se b usses is no t use d in te rna lly by th e S1 D 1370 8. 2 If th e target MC68K bus is 32-bi t, then th ese si gnals should be c onnecte d to D[31:1[...]

Page 40 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 4.6 LCD Interface Pin Mapping Not e 1 GPIO pins mus t be confi gured as ou tputs (CNF3 = 0 at RESET#) whe n TFT-Type 2, TFT-Type 3, HR- TFT or D-TFD pane ls are selecte d. 2 These pin map pings u se signal n[...]

Epson Research and Development Page 41 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 5 D .C. Characteristics Not e When applyi ng Supply Vol tages to t he S1D137 08, Core V DD must be applie d to th e chip bef ore, or simultane ously with IO V DD , or damage to the ch ip may resul t. Table 5[...]

Page 42 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6 A.C. Characteristics Conditio ns: CORE V DD = 1.8V ± 1 0% IO V DD = 3.3V ± 10% T A = TBD ° C t r and t f for al l inputs mus t be < 5 nsec ( 10% ~ 90%) C L = 50pF (Bus /MPU I nterf ace ) C L = 0pF (L[...]

Epson Research and Development Page 43 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Not e Maximum inter nal requi rements f or clocks derived f rom CLKI must be consid ered when dete rminin g the fr equenc y of CLKI. Se e Sect ion 6. 1.2, “Inte rnal Clocks” on page 43 for inte rnal cloc[...]

Page 44 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.2 CPU Interface Timing The foll owing sec tion inc ludes CPU inter face AC Ti ming. Thes e timings are based on I O V DD = 3.3V and Co re V DD = 1.8V. 6.2.1 Generic #1 Inter face Ti ming Figure 6- 2 Generi[...]

Epson Research and Development Page 45 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. t11 is the de lay from when da ta is pla ced on the bus unti l the da ta is lat ched into the write buffer. Table 6-5: Generic #1 Int erface Timing Symbol P arameter Min Max Unit f CLK Bus Clock frequen c[...]

Page 46 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.2.2 Generic #2 Inter face Ti ming Figure 6- 3 Generi c #2 Inte rface Timing T CLK t3 t5 t8 t9 BUSCLK A[16:1], M/R# , BHE# CS# RD#, WE# WAIT # D[15:0] (write) D[15:0] (re ad) t13 t7 t11 t14 t15 t10 t6 t4[...]

Epson Research and Development Page 47 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. t11 is the de lay from when da ta is pla ced on the bus unti l the da ta is lat ched into the write buffer. Table 6-6: Generic #2 Interfac e Timin g Symbol P arameter Min Max Unit f BUSCLK Bus Cloc k freq[...]

Page 48 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.2.3 Hitachi SH-4 Interface Ti ming Figure 6 -4 Hita chi SH-4 In terfa ce Timing T CKIO t3 t5 t6 t4 t11 t14 t13 t18 t17 t10 t15 t16 t8 t9 t7 CLKI A[16:1], RD/WR#, M/R# BS# CSn# WEn#, RD# RDY D[15:0] (write [...]

Epson Research and Development Page 49 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. t15 is the de lay from when da ta is pla ced on the bus unti l the da ta is lat ched into the write buffer. Not e Minim um o n e so ftw ar e W AIT s tate is req uire d . Table 6- 7: Hita chi SH- 4 Inte rf[...]

Page 50 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.2.4 Hitachi SH-3 Interface Ti ming Figure 6 -5 Hita chi SH-3 In terfa ce Timing T CKIO t3 t5 t6 t8 t12 t11 t17 t16 t10 t14 t15 t4 t9 t7 t13 CKIO A[16:1], RD/WR#, M/R# BS# CSn# WEn#, RD# WAIT# D[15:0] (writ[...]

Epson Research and Development Page 51 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. t14 is the de lay from when da ta is pla ced on the bus unti l the da ta is lat ched into the write buffer. Not e Minim um o n e so ftw ar e W AIT s tate is req uire d . Table 6- 8: Hita chi SH- 3 Inte rf[...]

Page 52 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.2.5 Motor ola MC68 K #1 Interf ace Timing ( e.g. MC68000) Figure 6- 6 Motorola MC68K # 1 Interf ace Timing T CLK t3 t5 t8 t10 CLK A[16:1], R/W #, M/R# CS# AS# UDS#, LDS# , (A0) DTACK# D[15:0] (write) D[15:[...]

Epson Research and Development Page 53 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. t17 is the de lay from when da ta is pla ced on the bus unti l the da ta is lat ched into the write buffer. Table 6-9 : Motorola MC68 K #1 Int erface Ti ming Symbol P arameter Min Max Unit f CLK Bus C loc[...]

Page 54 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.2.6 Motor ola MC68 K #2 Interf ace Timing ( e.g. MC68030) Figure 6- 7 Motorola MC68K # 2 Interf ace Timing T CLK t3 t5 t8 t10 CLK A[16:1], R/W#, M/R# , SIZ[1:0 ] CS# AS# UDS#, LDS#, (A0) DSACK1# D[31:16] ([...]

Epson Research and Development Page 55 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. t17 is the de lay from when da ta is pla ced on the bus unti l the da ta is lat ched into the write buffer. Table 6-10: Moto r ola MC68K #2 Interfa ce Timing Symbol P arameter Min Max Unit f CLK Bus C loc[...]

Page 56 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.2.7 Motor ola RED CAP2 In terfac e Timi ng Figure 6- 8 Motoro la REDCAP2 In terfa ce Timing T CLK t3 t6 t10 t12 t13 t8 t9 t14 t11 t7 t5 t4 Note: CSn# may be any of CS0# - CS4#. CLK A[16:1], R/W#, M/R#, CS#[...]

Epson Research and Development Page 57 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. t8 is the delay from when data i s placed on the bus until the data is l atched i nto the wri te buffer. Table 6- 11: Moto r ola REDCAP2 Interface Timing Symbol P arameter Min M ax Units f CLK Bus Clock f[...]

Page 58 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.2.8 Motorola Dra gonB all Interface Timi ng with DT A C K (e.g. MC68EZ328/MC 68 VZ3 28) Figure 6- 9 Motorola Dra gonBall Interfa ce with DTACK Timing T CLK O t3 t6 t8 t10 t14 t16 t12 t7 CLKO A[16:1] CSX# U[...]

Epson Research and Development Page 59 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. t12 is the de lay from when da ta is pla ced on the bus unti l the da ta is lat ched into the write buffer. Table 6-1 2: Motor ola Dr a gonBall Int erface wi th DTACK Timi n g Symbol P arameter MC68EZ32 8[...]

Page 60 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.2.9 Motorola Dra gonB all Interface Timi ng w/o DT A CK (e .g. MC 68EZ 328/M C68 VZ 328) Figure 6- 10 Motorola DragonBal l Interf ace withou t DTACK# Timi ng T CLK O t3 t6 t8 t10 t14 t12 t7 CLKO A[16:1] CS[...]

Epson Research and Development Page 61 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. t12 is the de lay from when da ta is pla ced on the bus unti l the da ta is lat ched into the write buffer. Table 6-13: Motor ola Dra gonBall I nterface without DTACK Ti ming Symbol P arameter MC68EZ 328 [...]

Page 62 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.2.10 Indirect Int e rface Timing (Mode 68) Figure 6-1 1 Indir ect Inte rface Timing (M ode 68) BUSCLK A0, R/W# CS# EBU, EBL D[15:0] (wri te) D[15:0] (rea d) t2 t9 t8 t1 t5 t6 t7 t3 t4 T BUSCLK[...]

Epson Research and Development Page 63 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Not e Max freque ncy (f BUSCLK ) when us ing cr ystal osc illator is 12MHz. Table 6-14: In dir ect Interface Ti ming (Mode 68) Symbol Paramete r Min Max Units f BUS CLK Bus Clock frequen cy 50 MHz T BUSCLK B[...]

Page 64 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.2.11 Indirect Int e rface Timing (Mode 80) Figure 6-1 2 Indir ect Inte rface Timing (M ode 80) BUSCLK A[16:1], M /R# CS# | WRn#, CS# | RDn# D[15:0] (write) D[15:0] (re ad) T BUSCLK t3 t10 t9 t8 t7 t6 t5 t4[...]

Epson Research and Development Page 65 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Not e Max freque ncy (f BUSCLK ) when us ing cr ystal osc illator is 12MHz. Table 6-15: In dir ect Interfac e Timing (Mode 80) Symbol Paramete r Min Max Units f BUS CLK Bus Clock frequen cy 50 MHz T BUSCLK B[...]

Page 66 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.3 LCD P o wer Sequenci ng 6.3.1 P assive/TFT P ower - On Sequence Figure 6-1 3 Passiv e/TFT Power-On Sequenc e Timing 1. t1 is control led by software and mus t be determin ed from the bias pow er supply d[...]

Epson Research and Development Page 67 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 6.3.2 P as si ve/ TFT P ow er -Off Sequence Figure 6-1 4 Passiv e/TFT Power- Off Sequ ence Timing 1. t1 is c ontroll ed by s oftware an d mus t be de termined from th e bias p ower sup ply del ay requ iremen[...]

Page 68 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4 Di spla y Inter face The timin g parameter s requ ired to d rive a fl at pan el displa y are s hown below. Ti ming detail s for each suppor ted pa nel ty pe are pro vided i n the r emainder of this secti[...]

Epson Research and Development Page 69 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. For passive p anels , the HDP mu st be a minimum of 32 pix els a nd must be increa sed by multipl es of 16. For TFT panels, the HDP must be a minimum of 8 pixel s and must be increased by multiples o f 8.[...]

Page 70 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4.1 Generic STN P anel Timing Figure 6-1 6 Generi c STN Panel Ti ming FPFR AME VT (= 1 Frame ) MOD 1 (DRDY) FPLI NE MOD 2 (DRDY) FPLINE VDP VPW HT (= 1 Line) HDPS HDP FPDAT[17:0] FPDAT[17:0] 1PCLK FPS HIF [...]

Epson Research and Development Page 71 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 VT = V ertica l Total = [( REG[19h] b its 1-0 , REG[18h] bits 7- 0) + 1] l ines VPS = FPF RAME P ulse St art Positi on = 0 line s, bec ause [( REG[27h] b its 1-0 , REG[26h] bits 7-0)] = 0 VPW = F PFRA ME Pu [...]

Page 72 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4.2 Single Monochr ome 4-Bit P anel Timing Figure 6- 17 Single Mon ochrome 4 -Bit Panel Timing VDP = Vertical D ispla y Peri od = (REG[1 Dh] bits 1 :0, REG[1Ch ] bits 7:0 ) + 1 Li nes VN DP = Ver ti cal No[...]

Epson Research and Development Page 73 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Figure 6- 18 Single Mono ch r ome 4-Bit P anel A.C. Timing 1. Ts = pixe l clock p eriod 2. t1 mi n = HPS + t4 min 3. t2 mi n = t3 min - ( HPS + t4 min ) 4. t3 mi n = HT 5. t4 mi n = HPW 6. t5 mi n = HPS - 1 [...]

Page 74 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4.3 Single Monochr ome 8-Bit P anel Timing Figure 6- 19 Single Mon ochrome 8 -Bit Panel Timing VDP = Vertical D ispla y Peri od = (REG[1 Dh] bits 1 :0, REG[1Ch ] bits 7:0 ) + 1 Li nes VN DP = Ver ti cal No[...]

Epson Research and Development Page 75 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Figure 6- 20 Single Mono ch r ome 8-Bit P anel A.C. Timing 1. Ts = pixe l clock p eriod 2. t1 mi n = HPS + t4 min 3. t2 mi n = t3 min - ( HPS + t4 min ) 4. t3 mi n = HT 5. t4 mi n = HPW 6. t5 mi n = HPS - 1 [...]

Page 76 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4.4 Single Color 4-Bit P anel Timing Figure 6-2 1 Singl e Color 4-Bi t Panel Timing VDP = Vertical D ispla y Peri od = (REG[1 Dh] bits 1 :0, REG[1Ch ] bits 7:0 ) + 1 Li nes VN DP = Ver ti cal No n-Di sp la[...]

Epson Research and Development Page 77 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Figure 6 -22 Single Color 4-Bi t P anel A.C. Timin g 1. Ts = pixe l clock p eriod 2. t1 mi n = HPS + t4 min 3. t2 mi n = t3 min - ( HPS + t4 min ) 4. t3 mi n = HT 5. t4 mi n = HPW 6. t5 mi n = HPS - 1 7. t6 [...]

Page 78 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4.5 Single Color 8-Bit P anel Timing (Format 1) Figure 6- 23 Single Color 8-Bit Panel Timing (Forma t 1) VDP = Vertical D ispla y Peri od = (REG[1 Dh] bits 1 :0, REG[1Ch ] bits 7:0 ) + 1 Li nes VN DP = Ver[...]

Epson Research and Development Page 79 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Figure 6- 24 Single Co lor 8- Bit P anel A.C. Timing (For mat 1) 1. Ts = pixe l clock p eriod 2. t1 mi n = HPS + t4 min 3. t2 mi n = t3 min - ( HPS + t4 min ) 4. t3 mi n = HT 5. t4 mi n = HPW 6. t6a min = HP[...]

Page 80 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4.6 Single Color 8-Bit P anel Timing (Format 2) Figure 6- 25 Single Color 8-Bit Panel Timing (Forma t 2) VDP = Vertical D ispla y Peri od = (REG[1 Dh] bits 1 :0, REG[1Ch ] bits 7:0 ) + 1 Li nes VN DP = Ver[...]

Epson Research and Development Page 81 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Figure 6- 26 Single Co lor 8- Bit P anel A.C. Timing (For mat 2) 1. Ts = pixe l clock p eriod 2. t1 mi n = HPS + t4 min 3. t2 mi n = t3 min - ( HPS + t4 min ) 4. t3 mi n = HT 5. t4 mi n = HPW 6. t5 mi n = HP[...]

Page 82 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4.7 Single Color 16-Bit P anel Timing Figure 6-27 Si ngle Color 1 6-Bit Panel Timing VDP = Vertical D ispla y Peri od = (REG[1 Dh] bits 1 :0, REG[1Ch ] bits 7:0 ) + 1 Li nes VN DP = Ver ti cal No n-Di sp l[...]

Epson Research and Development Page 83 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Figure 6- 28 Single Col or 16-Bit Panel A .C. Timing 1. Ts = pixe l clock p eriod 2. t1 mi n = HPS + t4 min 3. t2 mi n = t3 min - ( HPS + t4 min ) 4. t3 mi n = HT 5. t4 mi n = HPW 6. t5 mi n = HPS - 1 7. t6 [...]

Page 84 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4.8 Generic TFT P anel Timing Figure 6-2 9 Generi c TFT Panel Ti ming VT = Ver tical Tota l = [(REG[ 19h] bits 1-0, REG [18h] bits 7-0) + 1] lines VPS = FP FRAM E Pulse Start Po sitio n = ( REG[27h] bits 1[...]

Epson Research and Development Page 85 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 6.4.9 9/12/18-Bit TFT P anel Timing Figure 6- 30 18-Bit TFT Panel Timing VDP = Vert ical Disp lay P eriod = VDP Lines VNDP = Vertical Non-Display Period = VNDP1 + VNDP 2 = VT - VDP Li nes VNDP1 = Vertica l N[...]

Page 86 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 Figure 6 -31 TFT A.C. Timing t3 t5 FPLINE t1 t4 FPFR AM E DRD Y FPSHIFT 320 t2 FPLINE 2 13 1 9 t13 t10 t11 t14 t15 t16 t7 t8 t9 t12 FPD A T[17:0] Note: DRD Y is used to indicat e the first pix el t6 invalid [...]

Epson Research and Development Page 87 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. Ts = pixel cl ock pe riod 2. t6m in = HDPS - HPS if negati ve add HT 3. t8m in = HPS - (HDP + HDPS) if neg ati ve add HT Table 6-25: TFT A.C. Timing Symbol Param eter Min T yp Max Units t1 FPFRAME cycle t[...]

Page 88 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4.10 160x160 Sharp ‘Direct’ HR-TFT P ane l Timing (e .g. LQ031B1DDxx) Figure 6-3 2 160x160 Sharp ‘Dire ct’ HR-TFT Pan el Horizon tal Ti ming FPLINE t2 FPDAT[17: 0] t3 t4 t12 t11 GPIO 3 GPIO2 t10 t9[...]

Epson Research and Development Page 89 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. Ts = pixel cl ock pe riod 2. t1typ = ( REG[23 h] bits 1-0, REG[2 2h] bits 7-0 ) + 1 3. t2typ = ((REG[12h] bits 6-0) + 1) x 8 4. t3typ = (REG[20h] bits 6- 0) + 1 5. t7typ = ((REG[17h] bits 1-0, REG [16h] b[...]

Page 90 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 Figure 6- 33 160x16 0 Sharp ‘D irect’ HR- TFT Panel Ver tical Ti ming t1 FPDAT[17:0] GPIO1 t4 FPFRAME GPIO0 t2 t3 LINE1 LINE2 LINE160 t5 t6 t7 t8 t10 t11 t12 GPIO1 GPIO0 t9 t13 t14 FPLINE FPSHIFT (SPS) ([...]

Epson Research and Development Page 91 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. Ts = pixel cl ock pe riod Table 6-2 7: 160x1 60 Sharp ‘Direct’ HR-TFT Pane l Vertica l Timin g Symbol Param eter Min T yp Max Units t1 Vertical to tal period 203 264 Lines t2 Vertical d ispla y start [...]

Page 92 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4.11 320x240 Sharp ‘Direct’ HR-TFT P ane l Timing (e .g. LQ039Q2DS01) Figure 6-3 4 320x240 Sharp ‘Dire ct’ HR-TFT Pan el Horizon tal Ti ming FPLINE t2 FPDA T[1 7:0 ] t3 t4 t12 t11 GPIO3 GPIO2 t10 t[...]

Epson Research and Development Page 93 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. Ts = pixel cl ock pe riod 2. t1typ = ( REG[23 h] bits 1-0, REG [2 2h] bits 7-0) + 1 3. t2typ = ((REG[12h] bits 6-0) + 1) x 8 4. t3typ = (REG[20h] bits 6- 0) + 1 5. t7typ = ((REG[17h] bits 1-0, REG [16h] b[...]

Page 94 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4.12 160x 240 Epson D-TFD P a nel Timing (e.g. LF26SCR) Figure 6-36 160x 240 Epson D-TFD Panel Hori zonta l Timing FPLINE t8 FPDAT[17: 0] t1 t2 t10 t13 t9 t14 GPIO4 t10 t16 FPSHIFT GPIO1 GPIO0 GPIO6 GPIO2 [...]

Epson Research and Development Page 95 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. Ts = pixel cl ock pe riod Table 6-30 : 160x24 0 Epson D-TFD Pane l Horizont al Timi ng Symbol Param eter Min T yp Max Units t1 FPLINE pul se widt h 9 Ts (note 1) t2 FPLINE fallin g edge to FPSHIFT start p[...]

Page 96 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 Figure 6-37 160x 240 Epson D-TFD Pa nel GCP Hori zontal Ti ming 1. Ts = pi xel cl ock p eriod Table 6- 31: 160x240 E pson D-TFD Pa nel GCP Horizon tal Timing Symb ol Pa rameter Min T yp Max Un its t1 Half of[...]

Epson Research and Development Page 97 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Figure 6- 38 160x2 40 Epson D-TFD Pane l Vert ical Timi ng 1. Ts = pixel cl ock pe riod Table 6-32 : 160x2 40 Epson D-TFD Pane l Vert ical Timi ng Symbol Param eter Min T yp Max Units t1 FPFRAME puls e width[...]

Page 98 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4.13 320x 240 Epson D-TFD P a nel Timing (e.g. LF37SQR) Figure 6-39 320x 240 Epson D-TFD Panel Hori zonta l Timing FPLI NE t8 FPDAT[17:0] t1 t2 t10 t13 t9 t14 GPIO4 t10 t16 FPSHIFT GPIO1 GPIO0 GPIO6 GPIO2 [...]

Epson Research and Development Page 99 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. Ts = pixel cl ock pe riod Table 6-33 : 320x24 0 Epson D-TFD Pane l Horizont al Timi ng Symbol Param eter Min T yp Max Units t1 FPLINE pul se widt h 9 Ts (note 1) t2 FPLINE fallin g edge to FPSHIFT start p[...]

Page 100 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 Figure 6-40 320x 240 Epson D-TFD Pa nel GCP Hori zontal Ti ming 1. Ts = pi xel cl ock p eriod Table 6- 34: 320x240 E pson D-TFD Pa nel GCP Horizon tal Timing Symb ol Pa rameter Min T yp Max Un its t1 Half o[...]

Epson Research and Development Page 101 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Figure 6- 41 320x2 40 Epson D-TFD Pane l Vert ical Timi ng 1. Ts = pixel cl ock pe riod Table 6-35 : 320x2 40 Epson D-TFD Pane l Vert ical Timi ng Symbol Param eter Min T yp Max Units t1 FPFRAME puls e widt[...]

Page 102 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6.4.14 TFT T ype 2 P anel Timing Figure 6- 42 TFT Type 2 Horizont al Timing FPLINE GPIO0 GPIO3 GPIO2 D[17:0] GPIO1 t1 t2 t3 t4 t5 t6 t7 t10 t11 t12 DRD Y (INV) 2 1 t8 t9 Last FPSHIFT (STB) (VCLK) (STH) (CLK[...]

Epson Research and Development Page 103 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. Ts = pixel cl ock pe riod 2. t1typ = (REG[12h] bits 6- 0) +1) x 8 3. t3typ = Selected from 7, 9, 12 or 16 Ts i n REG[D0h ] bits 1-0 4. t4typ = Selected from 7, 9, 12 or 16 Ts i n REG[D0h ] bits 4-3 5. t5[...]

Page 104 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 Figure 6- 43 TFT Type 2 Vert ical T iming 1. Ts = pi xel cl ock p eriod 2. t1typ = (REG[1 9h] bits 1 -0, REG [18h] bits 7-0) +1 3. t4typ = (REG[1 Fh] bits 1-0, REG[1Eh ] bits 7- 0) 4. t5typ = (REG[1 Dh] bit[...]

Epson Research and Development Page 105 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 6.4.15 TFT T ype 3 P anel Timing Figure 6-4 4 TFT Type 3 Horizontal Ti ming FPLINE GPIO3 GPI O1 GPIO 2 D[17:0] GPI O4 2 1 t1 t2 t3 t5 t4 t6 t7 t8 t11 t12 DRD Y (INV) FPSHIFT GPIO0 t14 t9 t10 t13 Last (LP) ([...]

Page 106 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 1. Ts = pi xel cl ock p eriod 2. t1typ = ((REG [12h] bits 6-0) + 1 ) x 8 3. t2typ = (RE G[20h] bi ts 6-0) + 1 4. t3typ = (RE G[17h] bits 1- 0, REG[16h] bits 7-0) + 3 5. t8typ = (REG[1 4h] bits 6-0) x 8 6. t[...]

Epson Research and Development Page 107 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Figure 6-4 5 TFT Type 3 Vertical Ti ming FPFRAME GPIO0 GPI O1 D[17:0] Lin e2 Line1 t1 t2 t3 t4 t6 Last GPI O5 GPIO2 t3 t7 FPLI NE t5 (Odd F rame) (Eve n F rame) (Odd F rame) (Even Frame) t5 (STV) (CPV) (LP)[...]

Page 108 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 1. Ts = pi xel cl ock p eriod 2. t4typ = (REG[1 Fh] bits 1-0, REG[1Eh ] bits 7- 0) 3. t5typ = (RE G[1Dh] bits 1 -0, REG[ 1Ch] bit s 7-0 ) + 1 4. t6typ = ((REG [DAh] bits 7-0) x 2 5. t7typ = ((REG [DBh] bits[...]

Epson Research and Development Page 109 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 6.4.16 TFT T ype 4 P anel Timing Figure 6- 46 TFT Type 4 Pan el Timi ng VDP = Vert ical Disp lay P eriod = VDP Lines VNDP = Vertical Non-Display Period = VNDP1 + VNDP 2 = VT - VDP Li nes VNDP1 = Vertica l N[...]

Page 110 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 Figure 6- 47 TFT Type 4 A.C. Timing t3 t5 FPLINE t1 t4 FPFR AM E DRD Y FPSHIFT 640 t2 FPLINE 2 16 3 9 t14 t11 t12 t15 t16 t17 t8 t9 t10 t13 FPDA T[1 7:0 ] Note: DRD Y is used to indicat e the first pix el t[...]

Epson Research and Development Page 111 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 1. Ts = pixel cl ock pe riod 2. t1typ = (REG[19 h] bits 1-0, REG[1 8h] bits 7-0) +1 3. t2typ = (REG [24h] bits 2-0) + 1 4. t3typ = (REG[23 h] bits 1-0, REG[2 2h] bits 7-0) + 1 5. t4typ = ((RE G[12h] bi ts 6[...]

Page 112 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 7 Cloc ks 7.1 Cloc k Descriptions 7.1. 1 BCLK BCLK is an inte rna l cl ock deri ved fr om CLKI o r XTAL. CLKI i s t ypi ca ll y prov ided f r om the host CPU bus clock. T he sour ce cl ock options for BCLK [...]

Epson Research and Development Page 113 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 7.1.3 PCLK PCLK is the i ntern al clo ck used to contro l the LCD panel. PCLK s hould be c hosen t o match the opti mum frame r ate of t he LCD panel. See Sect ion 9, “ Frame Rat e Calcula tion” on page[...]

Page 114 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 XTAL REG[CAh] bit 1 = 1 , REG[05 h] = 03 h XTAL ÷ 2 REG[C Ah] bit 1 = 1 , REG[05 h] = 13h XTAL ÷ 3 REG[C Ah] bit 1 = 1 , REG[05 h] = 23h XTAL ÷ 4 REG[C Ah] bit 1 = 1 , REG[05 h] = 33h XTAL ÷ 8 REG[C Ah][...]

Epson Research and Development Page 115 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 There is a relati onship between the frequ ency of MCLK a nd PCLK that mus t be maintai ned. 7.1.4 PWMCLK PWMCLK is the int ernal cl ock used by the Pulse Widt h Modulat or for o utput t o th e panel. The s[...]

Page 116 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 7.2 Cloc k Selectio n The foll owing di agram provi des a l ogical r epresent ation of the S1D137 08 inte rnal clocks. Figure 7-1 Clock Se lect ion Not e 1 CNF[7:6] mus t be set a t RESET#. CLKI CLKI2 ÷ 2 [...]

Epson Research and Development Page 117 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 7.3 Clocks ver sus Functions Table 7-6: “S1D1 3708 Int ernal Clock Req uiremen ts”, lis ts the inter nal cl ocks r equir ed for the foll owing S1D13 708 func tions. Not e 1 PWMCLK is an option al clo ck[...]

Page 118 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 8 Registers This sec tion disc usses how and where t o access the S1D137 08 regist ers. I t also pr ovides detail ed inf ormation a bout th e layout a nd usage of each r egister . 8.1 Regi ster Mapping The [...]

Epson Research and Development Page 119 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 8.2 Register Set The S1D1370 8 registe r set is as fol lows. Table 8-1: S1D13708 Regist er Set Register Pg Regist er Pg Read-On ly Co nfigurat ion Regis ters REG[00h] Revision C ode Register 121 REG[01h] Di[...]

Page 120 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 General Purpose IO Pins Register s REG[A8h] General Purpose IO Pins Configuration Register 0 145 REG [A9h] General Purpos e IO Pins Conf iguration Register 1 146 REG[ACh] General Purpose IO Pins Status/Cont[...]

Epson Research and Development Page 121 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 8.3 Register Descriptions Unless spe cifie d otherwis e, all regist er bit s are set to 0 du ring power -on. 8.3.1 Read-Only Configuration R egisters Not e The S1D13708 r eturns a value o f 34h. bits 7-2 Pr[...]

Page 122 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 8.3.2 Cloc k Configuration Register s bits 5 -4 MC LK D ivide Sel ect Bi ts [1 :0 ] These bits de termine the di vid e used to generate th e Memory Clock (MCLK) from the Bus Clock (BCL K). bits 6- 4 PCLK Di[...]

Epson Research and Development Page 123 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 1-0 P C LK S our ce Sel ect B its [1: 0] Thes e bi ts dete rmin e th e sour ce o f th e Pixel C loc k (PCL K). Not e Selecti ng XTAL as t he PCLK source is con trolled by t he BCLK Sour ce Sele ct bit [...]

Page 124 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bits 7- 2 LUT Red Write Data Bits [5 :0] This re gister conta ins the da ta to be writte n to the r ed compone nt of the Look-Up T able. The data is sto red in this regi ste r un til a wr ite t o th e L UT [...]

Epson Research and Development Page 125 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 7-2 LU T Gre en Re ad Da ta Bi ts [5 :0] This re gister conta ins t he dat a from t he gre en component of t he Look-Up T able. The LUT entr y rea d is c o ntro lle d by the L UT R ead Add res s Regist[...]

Page 126 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 8.3. 4 P anel Conf i guration Registers bit 7 Panel Da ta For m at Se lect When this bi t = 0, 8 -bit sin gle color passi ve LCD panel data for mat 1 is se lecte d. For A C timing see Section 6 .4.5, “Sin[...]

Epson Research and Development Page 127 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 1- 0 Panel T ype S ele ct B its [1:0] Thes e bi ts sele ct the pan el typ e. bits 5-0 M O D Ra te Bi ts [5 :0] These bit s are f or passi ve LCD pa nels only . When the se bits a re all 0 , the M OD ou[...]

Page 128 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bits 6- 0 Horizontal Di splay Peri od Bit s [6:0] These bits speci fy the LCD pan el Hori zontal Di splay per iod, in 8 pixe l resolu tion. Th e Horizonta l Displ ay per iod s hould b e less than the Hor iz[...]

Epson Research and Development Page 129 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 9- 0 V ertica l T ota l B its [9:0 ] Thes e bi ts spe cify th e L C D pan el V er tica l T otal p e riod , in 1 line reso luti on. T he V ert ica l T o tal is th e s um o f the V erti ca l D ispl a y P[...]

Page 130 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bits 9- 0 V ertical Di splay Pe riod Star t Positi on Bits [9:0] The se bit s spe c ify t he V ert ical Disp lay Pe rio d S tar t P os iti on f o r HR- TFT a nd D -TFD panels in 1 line resolut ion. Not e Fo[...]

Epson Research and Development Page 131 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 9-0 FPLINE Pulse Sta rt Position Bits [9: 0] These bit s spec ify the s tart pos itio n of the horizont al syn c signal, in 1 pi xe l resolut ion. FPLINE Pulse St art Po sition i n pixels = [(REG[2 3h][...]

Page 132 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bits 9- 0 FPFRAME Pulse Start P ositi on Bits [9 :0] The se b it s spe cif y t he s tart posit ion of th e vertic al sy n c sig n al, in 1 li ne re s olu tion. Not e For panel AC t iming and t iming para me[...]

Epson Research and Development Page 133 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 8.3.5 Displa y Mode Re giste rs bit 7 Disp lay B la nk When t his bi t = 0, t he L C D dis pla y p ipe lin e i s en ab led . When this b it = 1, the LCD displ ay pip eline is disabled and al l LCD data out [...]

Page 134 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bit 5 Hardw are V ideo I n vert Enab le This bit a llo ws th e V ideo In ver t featur e to b e control led using the Gene ral Pu rpose IO pin GPIO0. This opti on is no t availabl e if configu red for a H R-[...]

Epson Research and Development Page 135 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 2- 0 Bit-p er-pixel Sele ct Bits [2:0 ] These bit s sel ect the c olor d epth (b it-p er -pix el) for the di splay ed dat a for b oth the main windo w and the PIP + windo w (if a cti v e). 1, 2, 4 and [...]

Page 136 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bit 6 Displ ay Da ta By te S wap The display pi pe fetches 32-bi ts of data from the displ ay buf fer . This bi t enables byt e 0 and byte 1 to be s wappe d, and b yte 2 a nd b yte 3 to be swap ped, before [...]

Epson Research and Development Page 137 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 16-0 Main W indo w Displa y Start Add ress Bi ts [16:0 ] These bit s form the 17-bi t addr ess for t he start ing doub le-w ord of th e LCD image i n the displ ay buffer fo r th e m ain w ind ow . Note[...]

Page 138 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 8.3.6 Picture-in-Pict ure Plus Re gister s bits 16- 0 PIP + W indo w Display Start Add ress Bits [16:0 ] These bits form t he 17-b it addres s for the star ting d ouble-wo rd of t he PIP + windo w . Note th[...]

Epson Research and Development Page 139 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 9-0 PIP + W indow X Start Positi on Bits [ 9:0] Thes e bi ts dete rmin e th e X sta rt po sit ion of the PIP + windo w in rel atio n to th e or igin of the panel. Due to the S1D13708 Swi velV ie w f ea[...]

Page 140 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bits 9 -0 PIP + W indow Y Sta rt P o siti on Bi ts [9 :0] These bit s determ ine the Y start positio n of the PIP + windo w in relati on to the orig in of the panel. Due to th e S1D13708 Swi v elV ie w feat[...]

Epson Research and Development Page 141 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 9-0 PIP + W i ndow X En d Po siti on Bi ts [9 :0] These bit s dete rmin e the X end p osi tion of the PIP + windo w in relati on to th e orig in of the panel. Due to the S1D13708 Swi velV ie w feat ure[...]

Page 142 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bits 9 -0 PIP + W indo w Y End Position Bi ts [9 :0] These bits deter mine the Y en d pos ition of the PI P + wind ow in rela tio n to th e orig in of the panel. Du e t o t he S1 D13708 Swi v elV iew f ea t[...]

Epson Research and Development Page 143 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 8.3.7 Miscellaneous R egis ter s bit 7 V erti cal N on- D isp la y Pe riod S tat us This is a read- only sta tus bit. When thi s bit = 0 , the LCD pa nel output is i n a V ert ical Dis play Per iod. When th[...]

Page 144 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bit 7 Reser ved. This bit mus t be set to 0. bit 0 Reser ved. This bit mus t be set to 0. bit 7 Reser ved. This bit mus t be set to 0. bits 15- 0 Scratch P ad Bits [1 5:0] This re gister conta ins gener al [...]

Epson Research and Development Page 145 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 8.3.8 General IO Pins Register s Not e If CNF3 = 0 at RESET#, then all GPIO pin s are conf igu re d as out put s onl y and thi s re g- ister has no effect . This cas e allows t he GPIO pi ns to be use d by [...]

Page 146 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bit 7 GPIO Pin I nput Enable This bit i s used to enable the input functio n of the GPIO pins. I t must be cha nged to a 1 after po wer-on r eset to enable the input funct ion of the GPIO pins (defa ult i s[...]

Epson Research and Development Page 147 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bit 4 GPIO4 Pin IO S tatus When GPIO4 is not used as a LCD signal an d GPIO4 is conf igured as an outp ut, writin g a 1 to thi s bit dri ves GPIO4 h igh and writing a 0 to this bit dr i ve s GPIO4 lo w . Wh[...]

Page 148 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bit 1 GPIO 1 Pi n IO S ta tus When GPIO1 is not use d as a LCD signal and GPIO1 is c onf igur ed as an out put, writi ng a 1 to this bit dri ves GPIO1 hi gh and wr iting a 0 to thi s bit dri ves GPIO1 l ow [...]

Epson Research and Development Page 149 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bit 7 GPO0 Control This bit contr ols the Ge neral Purp ose Outp ut 0 pi n. Writin g a 0 to thi s b it dr iv es GP O 0 to low . Writing a 1 to this bit dri ves GPO0 to high . This bit has no ef fect when HR[...]

Page 150 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 8.3.9 Pulse Width Modulat io n (PWM) Clock and Contrast V oltag e (CV) Pulse Configuration Registers Figure 8- 2 PWM Clock/ CV Pulse Block Diagram Not e For furth er infor mation on PWMCLK, see Sect ion 7.1[...]

Epson Research and Development Page 151 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bit 3 and b it 0 CV Pulse Fo rce Hig h (bit 3) and CV Puls e Enabl e (bit 0) Thes e bi ts con tr ol th e CVOUT pin a nd CV Puls e ci rcuitr y as foll ows. When CV OUT is forced lo w or forced hig h it can b[...]

Page 152 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bits 7- 4 PW M Clock Di vide Select Bits [3:0] The value of thes e bits repre sents the powe r of 2 by which the sele cted PWM clock source is divide d. Not e This divi ded clock i s further d ivided by 256[...]

Epson Research and Development Page 153 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bit 0 PWMCLK Source Sele ct When thi s bit = 0 , the cloc k sourc e for PWMCLK is the BCLK sou rce. When this b it = 1, th e cloc k source f or PWMCLK is CLKI2 or XT AL (see BCLK Source Select Regi ster on [...]

Page 154 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 8.3.10 Exte nded Regist er s bits 16- 0 M emory Access Point er Bits [ 16:0] These r egist ers contr ol memory accesses f or the I ndir ect Int erfac e only (CNF [2:0] = 111). These bits c ontain a p ointe [...]

Epson Research and Development Page 155 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 1-0 Extended P anel T ype Bits [1:0] These bit s over ride the sett ing in RE G[10h] bit s 1-0 an d allow sel ecti on of the a lternat e TFT panel types. bit 0 Memory Access Select Bi t This register o[...]

Page 156 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 Ink Layer Transpa rent Color Register 0 REG[C7h] Read/Write Ink Laye r Transp arent Color Bits 7-0 76543210 Ink Layer Transpa rent Color Register 1 REG[C8h] Rea d/Write Ink Layer Trans parent Color Bit s 15[...]

Epson Research and Development Page 157 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 15-0 Ink Layer T ransparent Col or Bits [1 5:0] The Ink Lay er req uires a transp arent color to be s elected. Th is tr anspar ent color is co m- pared wit h the v alues i n the f ore ground imag e dur[...]

Page 158 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bit 0 BCLK Source S elect This bit se lec ts t he BCLK s our ce betwee n CLKI and XT AL (XT AL is re commend ed only when conf ig ured for the Indi rect In terfa ce, see CNF[ 2:0]). W hen this bit is used t[...]

Epson Research and Development Page 159 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 4-3 VCLK Hold Bits [1:0] These bit s control the TFT T ype 2 A C ti ming paramet er from the rising e dge of STB to t he falling edg e of V CLK . The p ara m ete r is sel ecte d as fo llows. For all o [...]

Page 160 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bit 7 POL T ype This bit s elects h o w often t he POL sig nal is t oggled. The POL signal is used f or the TFT T yp e 2 Int erfac e. F or all other pa nel in terfa ces th is bi t has no ef fect. When this [...]

Epson Research and Development Page 161 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 Not e The GPO pins are us ed by t he TFT Type 3 i nte rf ace when REG[C5h] bi ts 1- 0 = 10. For pin mappin g for TFT Type 3, se e Table 4- 10: “LCD Inte rface Pin Mapping,” on page 40. bit 7 PDME Contro[...]

Page 162 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bit 1 PCLK1 Contro l If the TFT T ype 3 interf ace is sele cted (REG[ C5h] bits 1-0 = 10), this bit enable s the LCD signal PCLK1. When this bi t = 1, PCLK1 = 1. When this bi t = 0, PCLK1 = 0. bits 7- 0 O E[...]

Epson Research and Development Page 163 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 7-0 C P V Pul se Width Bi ts [7 :0] Thes e bi ts spe cify th e pu lse w idt h of t h e CPV sig n al in 2 pixel r eso lutio n. Th is regi ste r is used for the TFT T ype 3 Inte rface and has no ef fec t[...]

Page 164 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bit 5- 4 PCLK 2 Divide R a te Bits [1: 0] These bits specify the di vide rate for PCLK2. This re gister is used for the TFT T ype 3 Inte rface and ha s no effect f or all o ther p ane l inte rface s. bits 3[...]

Epson Research and Development Page 165 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bit 4 Par tial Mode Display En able This bit enabl es/disab les the P artial Mode Displ ay for th e TFT T ype 3 and has no ef fect for all other panel inte rface s. When thi s bit = 1 , Pa rtia l Mode Dis p[...]

Page 166 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bits 5 -0 Parti a l Are a 0 X St art P osi ti on Bi ts [5 :0] These bit s s pecif y t h e X Sta rt Pos itio n of P art ia l Area 0 i n 8 pix el r es olu tion. This re gi st er is used f or the TFT T ype 3 I[...]

Epson Research and Development Page 167 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 5-0 Par tial Area 1 X Star t Posi tion Bits [5:0] Thes e bit s sp ecify the X Star t Pos itio n of Partia l Area 1 in 8 pixel r esolu tio n. Th is regis ter is used for th e TFT T ype 3 Interf ace and [...]

Page 168 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bits 5 -0 Parti a l Are a 2 X St art P osi ti on Bi ts [5 :0] These bit s s pecif y t h e X Sta rt Pos itio n of P art ia l Area 2 i n 8 pix el r es olu tion. This re gi st er is used f or the TFT T ype 3 I[...]

Epson Research and Development Page 169 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 bits 11-0 Command 0 Store Bits [11: 0] These bi ts stor e command 0 f or the TFT T ype 3 Inter face. This re gister h as no ef fect f or all other pa nel i nterf aces. bits 11-0 Command 1 Store Bits [11: 0][...]

Page 170 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 bits 1 -0 Sou rce Driver IC Num ber B its [1 :0] These bits conta in the numbe r of Sou rce Dri ver ICs. TFT Type 3 Source Driver IC Num ber Register REG[F5h] Read/Write n/a Source Driver IC Numbe r Bits 1-[...]

Epson Research and Development Page 171 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 9 Frame Rate Calculation The foll o wing form ula i s used to c alcul ate t he dis pla y fram e rat e. Where: f PCLK = PClk frequen cy (Hz) HT = Horizontal Total = ((REG[ 12h] bits 6-0) + 1) x 8 Pixel s VT [...]

Page 172 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 10 Displa y Data Forma ts The following diagrams show th e display m ode data formats for a little-endian system . Figure 10-1 4/ 8/16 Bit -Per-Pix el Dis play Data Memor y Organi zation Not e 1. The Host-t[...]

Epson Research and Development Page 173 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 11 Look-Up T ab le Ar chitecture The followi ng figure s are int ended to s how the d isplay da ta out put path on ly. Not e When Video Dat a Inve rt is ena bled t he video da ta is inverted after t he Look[...]

Page 174 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 4 Bit-per -pix el Monochr ome Mode Figure 11-3 4 Bi t-per-pi xel Monochr ome Mode Dat a Output Pat h 8 Bit-per -pix el Monochr ome Mode Figure 11-4 8 Bi t-per-pi xel Monochr ome Mode Dat a Output Pat h Gree[...]

Epson Research and Development Page 175 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 16 Bit-P er-Pixel Monochr ome Mode The LUT is bypa ssed an d the gree n data is dir ectly mapp ed for this col or depth– Se e “Display Da ta Forma ts” on page 172.. 11.2 Color Modes 1 Bit-P er-Pix el [...]

Page 176 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 2 Bi t-Per-Pixel C olo r Figur e 11 -6 2 B it-P er -P ixe l Colo r Mo de D a ta O u tpu t P ath 2 bit-per-pix el data from Image Buffer 6-bit Blue Data 00 01 10 11 Blue Look-Up T able 256x6 00 01 02 03 FC F[...]

Epson Research and Development Page 177 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 4 Bit-P er-Pix el Col or Figure 11- 7 4 Bit-Pe r-Pixe l Color Mode Da ta Outpu t Path 0000 0001 4 bit-per-pix el data 6-bit Red Data from Image Buffer 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 [...]

Page 178 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 8 Bit-per -pix el Color Mode Figu re 11- 8 8 B it-p e r-p ixel C olor Mode Data Outp ut Pa th 16 Bit-P er -Pix el Color Mode The L UT is bypa sse d and th e co lor da ta is dire c tly m app ed for this colo[...]

Epson Research and Development Page 179 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 12 SwivelVie w™ 12.1 Concept Most comput er displ ays are r efres hed in lan dscape orien tation – f rom lef t to ri ght and top to botto m. Computer images are st ored in t he sa me manner. Swi velVie [...]

Page 180 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 12.2.1 Register Programmi ng Enable 90 ° Sw ivel Vie w™ M ode Set Swivel View™ Mode Select bi ts to 01. Display Start Address The disp lay refresh c ircuitry sta rts at pixel “B”, the refore the Di[...]

Epson Research and Development Page 181 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 12.3 180° SwivelV ie w™ The followin g figure shows how the pro grammer see s a 480x320 lands cape image and how the image i s bein g displaye d. The ap plicati on image is writt en to the S 1D13708 in t[...]

Page 182 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 P anning Panning i s achieve d by chan ging t he Display S tart Addre ss re gister: • Increment /decrement the Displ ay Star t Address regis ter pans t he dis play window right/l eft by 32 b its, e. g. 4 [...]

Epson Research and Development Page 183 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 12.4.1 R egist er Pr ogram ming Enabl e 270 ° Swivel View™ Mode Set S wive lV ie w™ Mode Sele ct bi ts to 1 1. Display Star t Address The display ref resh ci rcuitry starts at pixel “C”, ther efore[...]

Page 184 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 13 Picture-in-Picture Plus (PIP + ) 13.1 Concept Picture -in-Pic ture Pl us enable s a sec ondary wind ow (or PI P + window) within the main display windo w. Th e PIP + win dow may be po siti oned anywhe re[...]

Epson Research and Development Page 185 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 13.2 With SwivelVi e w Enabled 13.2.1 S wivelVi ew 9 0° Figure 13 -2 Pict ure-in- Pictur e Plus wit h SwivelVi ew 90° ena bled 13.2.2 S wivelVi e w 180° Figure 13 -3 Picture -in- Picture Pl us with Swi v[...]

Page 186 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 13.2.3 Swivel Vie w 270 ° Figure 13- 4 Pictu re-in-Pi cture Plus with S wivelVi ew 270° enabl ed PIP + wi ndow main- window PIP + wind ow y s tar t posi t ion panel’ s origin PIP + window y en d po siti[...]

Epson Research and Development Page 187 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 14 Ink La y er The S1D1370 8 Ink Layer design provid es suppo rt for a foregr ound ima ge that ca n be overlaid on the backgro und (or main ) image . The Ink Layer s upports al l col or depths and auto mati[...]

Page 188 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 The Ink Layer is enabled/di sabled using REG[ C9h] bit 0. When the Ink Layer Enable bit is set to 1 , th e display buffe r is auto matical ly con figured f or a f oreground and back ground image as shown in[...]

Epson Research and Development Page 189 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 15 Indirect Interface The Indire ct Int erface is an async hronous int erfa ce with 2 modes o f opera tion, mode 68 and mode 80. The addr ess a nd dat a are multiple xed onto the da ta bus , thus provi ding[...]

Page 190 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 15.1 Mode 68 The foll owing sh ows an exa mple of a “r egist er write ” with Mod e 68. Figure 1 5-1 Sample timi ng of “regi ster writ e” with Mode 68 1. write regis ter addre ss (c ommand write) . 2[...]

Epson Research and Development Page 191 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 The follo wing shows an example o f a “r egister read” with Mode 68. Figure 15- 2 Sample t iming of “ register read” with Mode 68 1. write regi ster addr ess ( command write ). 2. read re gister da [...]

Page 192 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 The foll owing sh ows an exam ple of a “me mory write” with Mode 68, Big Endian . Figure 15-3 Sampl e timing o f “memory writ e” wit h Mode 68, Big End ian 1. write regis ter addre ss of Memory Acce[...]

Epson Research and Development Page 193 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 6. write Memor y data (data wri te) The S1D13708 i ndire ct inter face impl ements a n auto inc rement functi on to all ow burst m emory ac cesses. Fo r byte access es, th e Memory Addr ess Poi nter reg ist[...]

Page 194 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 The foll owing sh ows an exam ple of a “me mory rea d” with Mod e 68, Big Endi an. Figure 1 5-4 Sample timi ng of “memory r ead” with Mode 68, Big En dian 1. write regis ter addre ss of Memory Acces[...]

Epson Research and Development Page 195 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 6. read Memory data ( data read ) The S1D13708 i ndire ct inter face impl ements a n auto inc rement functi on to all ow burst m emory ac cesses. Fo r byte access es, th e Memory Addr ess Poi nter reg ister[...]

Page 196 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 The foll owing sh ows an exam ple of a “me mory writ e” for Mode 68 when th e Memory Access Sel ect bit is enabl ed (REG[C6h] bi t 0 = 1 ). Figure 15- 5 Sample timing of “regis ter write ” for Mode [...]

Epson Research and Development Page 197 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 The S1D13708 i ndire ct inter face impl ements a n auto inc rement functi on to all ow burst m emory ac cesses. Fo r byte access es, th e Memory Addr ess Poi nter reg ister s (REG [ C0 h], R EG[C 1h ] , RE [...]

Page 198 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 The foll owing sh ows an exa mple of a “me mory rea d” for Mod e 68 when the Memory Access Sel ect bit is enabl ed (REG[C6h] bi t 0 = 1 ). Figure 15-6 Sampl e timing o f “regist er read” f or Mode 6[...]

Epson Research and Development Page 199 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 burst m emory ac cesses. Fo r byte access es, th e Memory Addr ess Poi nter reg ister s (REG [ C0 h], R EG[C 1h ] , RE G[C 2h ]) a re a uto mati call y in crem ent ed “+ 1” . F or word accesse s, the Me[...]

Page 200 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 15.2 Mode 80 Mode 80 supp orts byte an d word acce ss for bo th regist er and memory access. It also all ows both bi g and l ittle endian modes . The f ollowing shows an example of a “r egister write ” [...]

Epson Research and Development Page 201 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 6. write regi ster dat a (dat a write) . Word acc esses (16-bit) use the l ower byt e for the low- er regi ster number and t he higher b yte fo r the h igher reg iste r number.[...]

Page 202 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 The foll owing sh ows an example of a “ register read ” with Mode 80. Figure 15 -8 Sample timing of “registe r read” with Mode 80 1. write regis ter addre ss (comma nd write) . Command write i s alw[...]

Epson Research and Development Page 203 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 The followi ng shows an e xample of a “memory wri te” with Mode 80, li ttle end ian. Figure 15- 9 Sample ti ming of “ memory wri te” with mode 80, li ttle end ian 1. write regi ster number of M emor[...]

Page 204 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6. writ e Mem ory data (d ata writ e ) The S1D1370 8 indirec t interf ace i mplements an auto i ncrement functio n to allo w burst memory access es. For byte acce sses, t he Memory Addres s Point er regi st[...]

Epson Research and Development Page 205 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 The following s hows an e xample of a “memory re ad” with Mode 80, Littl e endian. Figure 15- 10 Sample timi ng of “memory r ead” with mode 80, Lit tle endian 1. write regi ster number of M emory Ac[...]

Page 206 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 6. read Memory data (da ta re ad) The S1D1370 8 indirec t interf ace i mplements an auto i ncrement functio n to allo w burst memory access es. For byte acce sses, t he Memory Addres s Point er regi sters ([...]

Epson Research and Development Page 207 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 The following s hows an e xample of a “memory write ” for Mod e 80 when the Memory Access Sel ect bi t is enabl ed (REG[C6h] bit 0 = 1). Figure 15 -11 Sample timi ng of “memory wr ite” for Mode 80 w[...]

Page 208 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 upper and l ower byt es). The bi t/Li ttle endi an set ting is used to determine the da ta ar- rangement f or word accesses only. The S1D1370 8 indirec t interf ace i mplements an auto i ncrement functio n [...]

Epson Research and Development Page 209 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 The followi ng shows an e xample of a “memory re ad” for Mode 80 when t he Memory Access Sel ect bi t is enabl ed (REG[C6h] bit 0 = 1). Figure 15- 12 Sample t iming of “memor y read” for Mode 80 whe[...]

Page 210 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 arrangemen t for word acc ess es onl y. The S1D1370 8 indirec t interf ace i mplements an auto i ncrement functio n to allo w burst memory access es. For byte acce sses, t he Memory Addres s Point er regi s[...]

Epson Research and Development Page 211 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 16 Embed ded Crystal Oscillator The S1D1370 8 includes an embedd ed crysta l osci llator which i s availab le when t he Indirect Inte rface is sele cted. 16.1 Oscillator Cir cuit When a cry stal is used in [...]

Page 212 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 17 Big-Endian Bus Interface 17.1 Byte Swapping Bus Data The displa y buff er and reg is ter arc hit ec ture of the S1D137 08 is inher en tly litt le- en dian. If configur ed as big-endia n (CNF4 = 1 at rese[...]

Epson Research and Development Page 213 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 17.1.1 1 6 Bpp Color Depth For 16 bpp color depth, the Disp lay Data By te Swap bit (REG[71h] b it 6) must be set to 1. Figure 1 7-1 Byte-s wapping for 16 Bpp For 16 bpp co lor dep th, the MSB of the 16- bi[...]

Page 214 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 17.1.2 1/2/4/8 Bpp Color Depth For 1/2/4 /8 bpp col or de pth , byt e swapp ing must be per for med on t he bus dat a but not t he display data. For 1/2/ 4/8 bpp color depth, the Di splay Data Byt e Swap bi[...]

Epson Research and Development Page 215 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 18 P ower Sa ve Mode A software initiate d Power Save Mod e is incorp orated into the S1D13708 to accommodate the need for power reduction in the hand- held device s market. Thi s mode is ena bled via t he [...]

Page 216 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 19 Mech anical Dat a Figure 19- 1 Mechanical Data PFBGA 120-p in Pack age All dimens io ns in mm 8 0.8max TO P V IEW L K J H G F E D C B A 123456789 1 0 11 0.65 0.7 5 0.30 BOTTOM VI EW 0.08 M SIDE VIEW 0.75[...]

Epson Research and Development Page 217 Vancouver Des ign Center Hardware Functional Spe cification S1D13708 Issue Date: 02/03/07 X39A-A-001-02 20 Refere nces The followi ng is a partial list of documents whi ch contain addi tional infor mation rel ated to the S1D13708. Do cument nu mbers ar e listed i n paren thesis af ter the document name. All d[...]

Page 218 Epson Research and Development Vancouver Des ign Center S1D13708 Hardware Functional Specification X39A-A-001-02 Issue Date: 02/03/ 07 21 T echnical Suppor t Japan Seiko Epson Corporation Electronic Device s Marketing D ivision 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www. epson.co.jp/ Hong K o[...]

ADVANCE D IN F ORMAT ION Subje ct to C ha nge S1D13708 Embedded Memor y LCD Controller Pr ogramming Notes and Examples Docu ment Numb er: X39 A-G -003 -01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but on[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge T able of Contents 1 Introducti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Identifyi ng the S1D13708 . . . . . . . . . . [...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 8.3.3 SwivelView 180° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.3.4 SwivelView 270° . . . . . . . . . . . . . . . . . . . . . . .[...]

Epson Research and Development Page 5 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge List of T ables Table 5-1: Look-Up Tabl e Configurat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5- 2: Suggested LUT Values for 1 Bpp [...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 7 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge List of Figures Figure 4- 1: Pixel S torage fo r 1 Bpp in One By te of Disp lay Buff er . . . . . . . . . . . . . . . . . . 13 Figure 4- 2: Pixel S torage fo r 2 Bp[...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 9 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 1 Introduction This guide discusse s progr amming issue s and pr ovides exa mples f or the main featu res of the S1D13708, s uch as Swi velView and Pi cture-i n-Pic[...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 2 Identifying the S1D13708 The S1D13708 c an be i dentifi ed by readi ng the value cont ained in t he Revi sion Code Registe r (REG[00h]) . To iden tify the S1D137[...]

Epson Research and Development Page 11 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 3 Init iali zat ion This sect ion des cribe s ho w to ini tial ize th e S1D13708. Sample co de f or per forming init ial- ization of the S1D13708 is pr ovided in t[...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 4 Memory Models The S1D13708 contai ns a disp lay buf fer of 80K by tes an d s upports color dept hs of 1 , 2, 4, 8, and 16 bit-per -pix el. For each co lor depth,[...]

Epson Research and Development Page 13 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Two bit pixels provi de 4 gra y sha des /co lor poss ibi l it ie s. For monoc hr ome pane ls t he gra y shades ar e gener ated by in dexing i nto the f irst 4 e le[...]

Page 14 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 4.5 Memory Organizat ion f or 16 Bpp (65536 Colors /64 Gra y Shades) Figure 4- 5: Pixel S torage for 16 B pp in Two Byte s of Displ ay Buff er At a col or depth of[...]

Epson Research and Development Page 15 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 5 Look-Up T a ble (LUT) This sect ion discus ses pr ogramming th e S1D13708 Lo ok-Up Tab le (LUT). In cluded is a summary of th e LUT regist ers, r ecommendat ions[...]

Page 16 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Not e The LUT entry is upda ted only whe n the LUT Wri te Addres s Register (REG[0Bh]) i s writ ten to . bits 7- 2 LUT Red Write Data Bits [5 :0] This re gister co[...]

Epson Research and Development Page 17 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge bits 7-2 LU T Gre en Re ad Da ta Bi ts [5 :0] This re gister conta ins t he dat a from t he gre en component of t he Look-Up T able. The LUT entr y rea d is c o nt[...]

Page 18 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 5.2 Look-Up T a ble Or ganization • The Look-Up Tab le treat s the val ue of a pixel as an inde x into an a rray. Fo r example, a pixe l va lue of zero wou ld p [...]

Epson Research and Development Page 19 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 5.2.1 Gray Shade M odes Gray shade (monoc hrome) mod es are def ined by th e Color /Mono Panel Se lect bit (REG[10h] bi t 6). When this bit is se t to 0 , the va l[...]

Page 20 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 4 bpp gra y shade The 4 bpp gr ay shad e mode uses t he green c omponent o f the fi rst 16 LUT ent ries. The remainin g indices of the LUT are unuse d. Table 5-4: [...]

Epson Research and Development Page 21 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 8 bpp gra y s hade When conf igu red fo r 8 bpp gra y s hade mode , t he g reen c ompone nt of all 25 6 LUT e nt ries may be used. Howe ver, th e gree n component [...]

Page 22 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 16 bpp gr ay shade The Look-Up Table is bypassed at t his color dept h, therefor e programming th e LUT is not requi red. As w ith 8 b pp the re a re lim itat ion [...]

Epson Research and Development Page 23 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 5.2.2 Color Modes In color displa y modes, the number of LUT entries used is de termi ned by the c olor de pth. For each co lor de pth (excl uding 16 bpp) a tab le[...]

Page 24 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 4 bpp color When the S 1D1370 8 is config ured f or 4 bpp col or mode th e fir st 16 entr ies i n the LUT are used. The remai ning indi ces of th e LUT are u nused[...]

Epson Research and Development Page 25 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 8 bpp color When the S1D1370 8 is c onfigured for 8 bpp color mode all 256 entries i n the LUT are used. The S1D13708 LUT has six bi ts (64 values) of int ensity c[...]

Page 26 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 16 bpp color The Look-Up Table is bypassed at t his color dept h, therefor e programming th e LUT is not requi red. 25 55 00 00 65 00 FF AB A5 AB 00 FF E5 55 FF 55[...]

Epson Research and Development Page 27 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 6 P ower Sa ve Mode The S1D13708 i s desi gned f or ver y low-p ower app lica tions. During nor mal oper atio n, the internal clocks a re dyna mically di sable d w[...]

Page 28 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 6.2 Register s 6.2.1 P o wer Sa ve Mode Enable The Power Save Mo de Enabl e bit i nitia tes Powe r Save M ode when se t to 1. Se ttin g th e bit to 0 disa bles Pow[...]

Epson Research and Development Page 29 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 6.3 LCD P owe r Sequencing The S1D1370 8 require s LCD power s equencing (the p rocess of powerin g-on an d powering-o ff th e LCD panel). LCD p ower sequenc ing a[...]

Page 30 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 6.4 Enabling P ower Sa ve Mo de Power Sa ve Mode must be enable d using the foll owing st eps. 1. Disable the LCD b ias power us ing GPO0. Not e The S5U1370 8B00B [...]

Epson Research and Development Page 31 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 7 SwivelView  Most comput er displ ays opera te in l andscape mod e. In l andscape mode the di splay is typicall y wider t han it is high. For example, a d ispl[...]

Page 32 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Main W indo w Display St art Add ress The Main W indo w Display St art Addre ss re giste r rep resents a D WORD add ress which points t o the st art of t he main w[...]

Epson Research and Development Page 33 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Mai n Window L ine Add res s O ffset The Main W indo w Line Addr ess Of fs et re gister ind icates t he number of dwords per line in the main wi ndo w image. For S[...]

Page 34 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 2. Determine th e main window line a ddress offset . number of dwor ds per li ne = image width ÷ (32 ÷ bpp ) = 320 ÷ (32 ÷ 4) = 40 = 28h Program the Main Windo[...]

Epson Research and Development Page 35 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Exam ple 3: In Swi velView 1 80 ° mode, program the main window registers for a 320x240 panel at a color depth of 4 bpp. 1. Determine the main wi ndow disp lay st[...]

Page 36 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Example 4: In Swive lVi ew 270 ° mode, program the main window registers for a 320x240 panel at a color depth of 4 bpp. 1. Determine th e main window displ ay sta[...]

Epson Research and Development Page 37 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 7.3 Limitations 7.3.1 SwivelVie w 0° and 180° In SwivelVi ew 0° and 180° , the Mai n Window Lin e Address Of fset regist ers (REG[79h],REG[7 8h]) requi re th e[...]

Page 38 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 8 Picture-In-Picture Plus 8.1 Concept Pictu re- in -Pi ct ure P lus ( P IP + ) enables a s econdary wi ndow (or PIP + window) within th e main disp lay wind ow. Th[...]

Epson Research and Development Page 39 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge PIP + W indow Ena ble The PIP + W indow Ena ble bit e nable s a PIP + windo w within the ma in windo w . The loca- tion o f th e PIP + windo w withi n the lands ca[...]

Page 40 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Not e Truncate a ll fr actiona l valu es befo re writi ng to t he address regi sters . Not e SwivelView 0° and 180° re quire the PIP + wi dth to be a multiple of[...]

Epson Research and Development Page 41 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge number of dwor ds per li ne = ima ge width ÷ (32 ÷ bpp) PIP + X Start Po siti on The PIP + X Star t Positi on bit s dete rmine t he horizo ntal p ositi on of the[...]

Page 42 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge In SwivelVi ew 90° , these bits s et th e vert ical coord ina tes (y ) of th e PI P + window’s top edge. Inc reasing y moves the top ed ge downward i n 1 line s[...]

Epson Research and Development Page 43 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge PIP + Y Start Po siti on The PIP + Y Star t Positi on bit s dete rmine t he ver tica l start posit ion of th e PIP + windo w in 0 ° and 180 ° Swi velV ie w orien[...]

Page 44 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge In Sw ivelV iew 18 0° , t hese bi ts s et t he vert ical coor dinates (y) of t he PI P + window’s bottom edge. Inc reasing y moves the botto m edge downwa rds i[...]

Epson Research and Development Page 45 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge PIP + X End Posit ion The PIP + X End Pos ition bi ts deter mine th e horiz ontal end of the PIP + windo w in 0 ° a nd 180 ° Swiv elV ie w orie nta tio ns . Th e[...]

Page 46 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge In Sw ivel Vie w 18 0° , these bits set the hori zontal coordinat es (x) of the PIP + window’s left edge. Incr easing x mo ves the lef t edge towar ds the right[...]

Epson Research and Development Page 47 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge In SwivelVie w 0° , the se bit s se t the v erti cal coord inate s (y ) of th e PI P + windows’s bott om edge. Incr easin g y moves the b ottom ed ge downwards [...]

Page 48 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 8.3 Picture-In-Pic ture-Plus Examples 8.3.1 SwivelVie w 0° (La ndscape Mode ) Figure 8-2 : Picture -in- Picture Pl us with Swi velVie w disabled SwivelVie w 0 ° [...]

Epson Research and Development Page 49 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Exam ple 5: Prog ram the PIP + window registers for a 320x240 panel at 4 bpp, with the PIP + window pos itioned at (80, 60 ) with a width of 160 and a height of 12[...]

Page 50 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge afte r REG [91 h] is w ritte n. Due to trun cation, t he dimensio ns of the P IP + window may have change d. Recalcul ate the PIP + windo w width an d height be lo[...]

Epson Research and Development Page 51 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 8.3.2 SwivelVie w 90° Figure 8-3 : Pict ure-in-Pi cture Pl us with SwivelVie w 90° enab led SwivelView 90 ° is a m ode in whic h both t he main and PIP + wi ndo[...]

Page 52 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Example 6: In Swive lView 90 ° , program the PIP + window registers for a 3 20x240 panel at 4 bpp, with the PIP + window positioned at SwivelView 90 ° coor- dina[...]

Epson Research and Development Page 53 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Note that the values of REG[84h] thr ough REG[91h] do not go int o effect until after REG[9 1h] is writ te n. Due to tr uncation, the di mensions of the PIP + wind[...]

Page 54 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 8.3. 3 SwivelVie w 18 0° Figure 8- 4: Picture-i n-Pic ture Plus with Swivel View 180 ° enabled SwivelVie w 180 ° is a mode in whic h both the ma in and PIP + wi[...]

Epson Research and Development Page 55 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Exam ple 7: In Swi velView 1 80 ° , program the PIP + window registers for a 320x240 panel at 4 bpp, with the PIP + window positioned at SwivelView 180 ° co- ord[...]

Page 56 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Due to trun cation, t he dimensio ns of the P IP + window may have change d. Recalcul ate the PIP + windo w width an d height be low: PIP + Width = ((REG[8 Dh],REG[...]

Epson Research and Development Page 57 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 4. Dete rm ine t he P IP + line a ddress of fset. number of dword s per lin e = image widt h ÷ (32 ÷ bpp) = 160 ÷ (32 ÷ 4) = 20 = 14h Program t he PIP + Line A[...]

Page 58 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 8.3. 4 SwivelVie w 27 0° Figure 8- 5: Picture-i n-Pic ture Plus with Swivel View 270 ° enabled SwivelVie w 270 ° is a mode in whic h both the ma in and PIP + wi[...]

Epson Research and Development Page 59 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Exam ple 8: In Swi velView 2 70 ° , program the PIP + window registers for a 320x240 panel at 4 bpp, with the PIP + window positioned at SwivelView 270 ° co- ord[...]

Page 60 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Note that t he value s of REG[84h ] through REG [91h] do not go into effect u ntil afte r REG [91 h] is w ritte n. Due to trun cation, t he dimensio ns of the P IP[...]

Epson Research and Development Page 61 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 4. Dete rm ine t he P IP + line a ddress of fset. number of dword s per lin e = image widt h ÷ (32 ÷ bpp) = 128 ÷ (32 ÷ 4) = 16 = 10h Program t he PIP + Line A[...]

Page 62 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 8.4 Limitations 8.4.1 SwivelVie w 0° and 1 80° The PIP + Line Address Off set regi sters ( REG[81h],REG[ 80h]) req uires the PIP + window image width to be a m u[...]

Epson Research and Development Page 63 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 9 Har dware Abstra ction La yer 9.1 Intr oduction The S1D13708 Ha rdware Abstract ion Laye r (HAL) is a col lectio n of rout ines int ended t o simplify the progra[...]

Page 64 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 9.2.1 Star tu p R outi nes There are two routi nes dedi cated to star tup and init iali zing the S1D13708. Typi call y these two fu nctions a re the fi rst t wo HA[...]

Epson Research and Development Page 65 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Boolean halIni tContr oller(UI nt32 Fl ags) Descripti on: This routine pe rfor ms the i nitia lizati on port ion of the star tup se quence. Initi aliza tion of t h[...]

Page 66 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 9.2.2 Memo ry Access The S1D13708 HAL i nclude s six memo ry access funct ions. The pr imary purpo se of t he memory acce ss functi ons is to demonstr ate ho w to [...]

Epson Research and Development Page 67 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge v oid halWrite Displ a y16(UInt32 Of fset, UInt 16 V alue, UInt32 Count) Descripti on: Write s a word into di splay m emory at the reque sted of fset. Par amet ers[...]

Page 68 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge Not e There are two means of access ing re gisters: point ers int o registe r address ing sp ace, or through t he indi rect int erface. The fol lowing regi ster ac[...]

Epson Research and Development Page 69 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge v oid halWri teReg16(UI nt32 Inde x, UI nt16 V alue) Descripti on: Writes a 16 bit v alue to the S1D13708 re gister at the req uested of fset . Par amet ers : Inde[...]

Page 70 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge UInt32 halGetCl oc k(CLOCKSELECT Cloc k) Desc rip tio n: Retu rn s the fr equ ency of the c loc k inpu t id enti fied by 'Cl oc k'. Paramet ers: Cloc k I[...]

Epson Research and Development Page 71 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge int halGetL astErr or(c har * ErrMsg, in t MaxSize) Descripti on: This r o utin e retr iev es the last error d ete cted b y the HAL . Parameter s: ErrMsg When halG[...]

Page 72 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 10 Sample Code Example source cod e demonstrating programmin g the S1D13708 usi ng the HAL library is availa ble on the inter net at www.er d.epson.com.[...]

Epson Research and Development Page 73 Vancouver Des ign Center Programming Note s and Exam ples S1D13708 Issue Date: 01/11/20 X39A-G-003-01 ADVANCE D IN F ORMAT ION Subje ct to C ha nge 11 Sales and T ech nical Support Japan Seiko Epson Corporation Electronic Device s Marketing D ivision 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-581[...]

Page 74 Epson Research and Development Vancouver Des ign Center S1D13708 Progra mming Notes and Examp les X39A-G-003-01 Issue Date: 01/11/20 ADVANCE D IN F ORMAT ION Subje ct to C ha nge THIS P A GE LEFT BLANK[...]

S1D137 08 Register Summ ary X39A-R-0 01-01 Pa g e 1 01/01/ 25 READ-ONLY CONFIGURATION REGISTERS CLOCK CONFIGURATION REGISTERS LOOK-UP TABLE REGISTERS PANEL CONFIGURATION REGISTERS DISPLAY MODE REGISTERS PICTURE-IN-PICTURE PLUS REGISTERS MISCELLAN EOUS REGIS TERS REG[00 h ] R EVISION C ODE R EGISTER 1 RO Product Code = 001101 (0Dh) Revision Code = 0[...]

S1D137 08 Register Summ ary X39A-R-0 01-01 Pa g e 2 01/01/ 25 GENERAL IO P INS REGISTERS PWM CLOCK AND CV PULSE CONFIGURATION REGISTERS EXTENDED REGISTERS Notes 1 REG[00h] These bits are used to id entify the SED13708. For the SED13708, the product code should be 001101. 2 REG[04h] Memory Clock Configuration Register REG[A2h] S OFTWARE R ESET R EGI[...]

S1D137 08 Register Summ ary X39A-R-0 01-01 Pa g e 3 01/01/ 25 3 REG[05h] Pix el Clock Configurat ion Register 4 REG[05h] Pix el Clock Configurat ion Register 5 REG[10h] Panel T ype Register 6 REG[10h] Panel T ype Register 7 REG[70h] Displa y Mode Register 8 REG[71h] Special Eff ects Register 9 REG[B1h] PWM Clock / CV Pulse Configuration Register 10[...]

S1D137 08 Register Summ ary X39A-R-0 01-01 Pa g e 4 01/01/ 25[...]

S1D13708 Embedded Memor y LCD Controller 13708CFG Configuration Pr ogram Docume nt Number: X 39A- B -0 01-01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev aluating Seik o Eps[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 13708CFG C onfiguration Program X39A-B-001-01 Issue Date: 01/11/ 16 THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center 13708CFG Configuration Pr ogram S1D13708 Issue Date: 01/11/16 X39A-B-001-01 T able of Contents 13708CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 S1D13708 Suppo rted Evaluat ion Platfor ms . . . . . . . . . . . . . . . . . . . . . [...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 13708CFG C onfiguration Program X39A-B-001-01 Issue Date: 01/11/ 16 THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 5 Vancouver Des ign Center 13708CFG Configuration Pr ogram S1D13708 Issue Date: 01/11/16 X39A-B-001-01 13708CFG 13708CFG is an inter active Win dows® 9x/ME/ NT/2000 prog ram tha t calcul ates r egister values fo r a use r-defin ed S1D13708 config urati on. The conf igurat ion info rmatio n can be used to di rect[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 13708CFG C onfiguration Program X39A-B-001-01 Issue Date: 01/11/ 16 13708CFG Configuration T abs 13708CFG prov ides a ser ies o f tabs which c an be sele cted a t the top of the main window. Each tab allows the confi guration of a sp ecifi c aspect of S1D1370 8 opera tion. The [...]

Epson Research and Development Page 7 Vancouver Des ign Center 13708CFG Configuration Pr ogram S1D13708 Issue Date: 01/11/16 X39A-B-001-01 Note When “Epson S5U13 708B00B” i s selected , the regist er and dis play buffe r address es are blanked b ecause the ev aluation board u ses th e PCI inter face and t he dec ode address es are det ermined b[...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 13708CFG C onfiguration Program X39A-B-001-01 Issue Date: 01/11/ 16 Prefere nces T ab The Prefe rence tab con tains se tting s pertai ning t o the init ial displa y state. During r untime these s ettings ma y be cha nged. Panel Swiv elView The S1D13708 Swive lView feat ure is c[...]

Epson Research and Development Page 9 Vancouver Des ign Center 13708CFG Configuration Pr ogram S1D13708 Issue Date: 01/11/16 X39A-B-001-01 Clocks T ab The Clocks t ab simplif ies the selec tion of i nput clock frequ encies and the so urces of internal clockin g signa ls. For further informa tion reg arding clocking and clo ck sources , refer t o th[...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 13708CFG C onfiguration Program X39A-B-001-01 Issue Date: 01/11/ 16 The S1D13708 may use one or two clo ck sources . Two cloc k sources a llow grea ter f lexi- bilit y in displ ay type and memory spe ed. CLKI This s etti n g de te rm in es th e freq uenc y of CLK I. Timing Set[...]

Epson Research and Development Page 11 Vancouver Des ign Center 13708CFG Configuration Pr ogram S1D13708 Issue Date: 01/11/16 X39A-B-001-01 Timing This fie ld shows th e actua l PCLK used by the configu- ration p rocess . BCLK These settin gs selec t the cl ock sour ce and diviso r for th e interna l bus i nterfac e cloc k (BCLK). Sou rce Select s [...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 13708CFG C onfiguration Program X39A-B-001-01 Issue Date: 01/11/ 16 PWMCLK These contr ols co nfigure va rious PWMCLK se ttings. The P W MC L K is th e in terna l clo ck us ed by t he Puls e Width Modula tor f or output to the panel. Enable When this box is checked, the PWMCLK[...]

Epson Research and Development Page 13 Vancouver Des ign Center 13708CFG Configuration Pr ogram S1D13708 Issue Date: 01/11/16 X39A-B-001-01 Divide Specifies t he div ide rati o for t he clock s ource. The divide ra tio i s applied t o the CVOUT Puls e clock sour ce to deriv e the CV Pu lse clock frequ ency. Timing This fiel d shows the actu al CV P[...]

Page 14 Epson Research and Development Vancouver Des ign Center S1D13708 13708CFG C onfiguration Program X39A-B-001-01 Issue Date: 01/11/ 16 Pa n e l T a b The S1D13708 s upport s many pan el types. This ta b allows c onfigu ration of most panel relat ed setti ngs such as dimensions, type a nd timings. Panel Type Selects be tween pass ive (STN) and[...]

Epson Research and Development Page 15 Vancouver Des ign Center 13708CFG Configuration Pr ogram S1D13708 Issue Date: 01/11/16 X39A-B-001-01 availabl e options are 4, 8, and 16 bit . When an a ctive panel typ e (TFT/D-TFD/HR- TFT) is selec ted, t he availabl e options are 9 , 12, and 1 8 bit. Mono / Colo r Selects between a monochr ome or color pane[...]

Page 16 Epson Research and Development Vancouver Des ign Center S1D13708 13708CFG C onfiguration Program X39A-B-001-01 Issue Date: 01/11/ 16 displa yed image by fin e tuning t he hori zontal a nd vertic al d ispla y to ta ls. The d isplay to tal equal s the display pe riod plus the non- displa y peri od. Refer t o S1D13708 Hardware Functio nal Spec[...]

Epson Research and Development Page 17 Vancouver Des ign Center 13708CFG Configuration Pr ogram S1D13708 Issue Date: 01/11/16 X39A-B-001-01 VRTC/FPFRAME (lines ) These s ettings allow fin e tuning of the fra me pulse para mete rs. R ef er to S1D13708 Hardwa re Functio nal Specifi catio n , documen t number X39A- A-001-xx, f or a complete d escripti[...]

Page 18 Epson Research and Development Vancouver Des ign Center S1D13708 13708CFG C onfiguration Program X39A-B-001-01 Issue Date: 01/11/ 16 Pa n e l Pow e r T a b The S5U13708B00B e valua tion boar d is desi gned to use the GPO0 si gnal t o control the LCD bias power . The fo llowing se ttin gs configu re pane l power support. Power Do wn Time Del[...]

Epson Research and Development Page 19 Vancouver Des ign Center 13708CFG Configuration Pr ogram S1D13708 Issue Date: 01/11/16 X39A-B-001-01 Regist ers T a b The Registe rs tab al lows vi ewing and di rect editing t he S1D13708 r egist er values . Scroll u p an d do wn t he li st to view r egi st er va lues wh ich are det er mi ned fr om t h e con f[...]

Page 20 Epson Research and Development Vancouver Des ign Center S1D13708 13708CFG C onfiguration Program X39A-B-001-01 Issue Date: 01/11/ 16 13708CFG Menus The foll owing se ction s describ e each of the opt ions i n the F ile an d H elp menus. Open... From the Menu Bar, sel ect “Fil e”, th en “Open...” t o display the Open File Dial og Box[...]

Epson Research and Development Page 21 Vancouver Des ign Center 13708CFG Configuration Pr ogram S1D13708 Issue Date: 01/11/16 X39A-B-001-01 Save From the M enu Ba r, sel ec t “F il e”, then “ Sa ve ” to in itia te th e sav e a ctio n. T he Sa ve me nu option all ows a fast save of the co nfiguratio n information t o a file that was opened w[...]

Page 22 Epson Research and Development Vancouver Des ign Center S1D13708 13708CFG C onfiguration Program X39A-B-001-01 Issue Date: 01/11/ 16 From th e Menu Bar, selec t “File” , then “ Configure M ultipl e” to d isplay th e Confi gure Multiple Dialog Box. Th is dia log box is also d ispla yed when a fi le(s ) is drag ged ont o the 13708CFG [...]

Epson Research and Development Page 23 Vancouver Des ign Center 13708CFG Configuration Pr ogram S1D13708 Issue Date: 01/11/16 X39A-B-001-01 Export After det er m ini ng the desi red confi gur ation , “Ex por t” permit s the us er to sa ve t he re gis ter info rmat ion as a v a riet y of A SCII text file form ats. T he f oll ow in g i s a li st [...]

Page 24 Epson Research and Development Vancouver Des ign Center S1D13708 13708CFG C onfiguration Program X39A-B-001-01 Issue Date: 01/11/ 16 Enable T ooltips Tooltip s provide u seful in formati on abou t many of the items on the conf igura tion tabs . Placing the mouse pointer over near ly any i tem on any t ab generat es a po pup window contain i[...]

S1D13708 Embedded Memor y LCD Controller 13708PLA Y Diagnostic Utility Docume nt Number: X 39A- B -0 02-01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev aluating Seik o Epson[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 13708PLAY Diagnostic Utility X39A-B-002-01 Issue Date: 01/11/ 16 THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center 13708PLAY Diagnostic Utility S1D13708 Issue Date: 01/11/16 X39A-B-002-01 13708PLA Y 13708PLAY is a d iagnos tic ut ility whi ch allows a user to re ad/write all t he regist ers a nd display b uffer of the S1D137 08. Commands a re recei ved fr om the stan dard in put device , and message[...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 13708PLAY Diagnostic Utility X39A-B-002-01 Issue Date: 01/11/ 16 Installat ion PC platf orm Copy the fi le 13708play.exe to a direct ory in t he path ( e.g. PATH=C: S1D13708) . Embedded platf orm Download th e program 137 08play to the sys tem. Usage PC platf orm At the pr omp[...]

Epson Research and Development Page 5 Vancouver Des ign Center 13708PLAY Diagnostic Utility S1D13708 Issue Date: 01/11/16 X39A-B-002-01 Commands The following c ommands ar e intende d to be used fr om within t he 1 3708PLAY prog ram. However, simpl e commands can also b e executed from th e command l ine (e.g. 13708PLAY F 0 1 3FFF 0 ). Not e If the[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 13708PLAY Diagnostic Utility X39A-B-002-01 Issue Date: 01/11/ 16 F[S][8|16|32 ] starta ddr endaddr|len d ata1 [da ta2 data3 ...] Fills a speci fied addr ess range in the display b uffer . Where: S Set s th e b ase add re ss t o th e be gi nni ng o f s yst em m emor y. Without t[...]

Epson Research and Development Page 7 Vancouver Des ign Center 13708PLAY Diagnostic Utility S1D13708 Issue Date: 01/11/16 X39A-B-002-01 L index [red green blue] Reads/writ es the red, gre en, an d blue Lo ok-Up Table (LUT) co mponents. I f the red , gree n, and blue co mponents are not specifi ed, th e LUT for the given i ndex is r ead and the RGB [...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 13708PLAY Diagnostic Utility X39A-B-002-01 Issue Date: 01/11/ 16 RI [8|16] [cyc le s] For t est in g th e i ndi re ct in ter fa ce ON LY. RI will is sue one or more dat a read cycles f rom the indi rect in terface cmd/data cy cle. Wh ere: 8|16 The unit size: 8-bit ( bytes) , 16[...]

Epson Research and Development Page 9 Vancouver Des ign Center 13708PLAY Diagnostic Utility S1D13708 Issue Date: 01/11/16 X39A-B-002-01 SHOW Shows a test pat tern on the displ ay. The test pat tern is bas ed on current register settings and may not di spla y correct ly if th e regi sters are not c onfigu red pr operly. Use this command to di spl ay[...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 13708PLAY Diagnostic Utility X39A-B-002-01 Issue Date: 01/11/ 16 X[8|16|32] [index [d ata]] Read s/wr ites data to the regi ste r at ind ex. If no d ata is s pec ifie d, the regis ter i s read and the conte nts are disp l aye d. Where: 8|16|32 The unit size: 8 -bit (by tes ), [...]

Epson Research and Development Page 11 Vancouver Des ign Center 13708PLAY Diagnostic Utility S1D13708 Issue Date: 01/11/16 X39A-B-002-01 13708PLA Y Example 1. Configure 13708PLAY using the ut ilit y 13708CFG . For furt her in for m ati on on 13708CFG, see the 13708CFG Use r Manual , docu men t num be r X 39 A-B- 001 -x x. 2. Type 13708PLAY to start[...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 13708PLAY Diagnostic Utility X39A-B-002-01 Issue Date: 01/11/ 16 Script Files 13708PLAY can b e contr olled by a script file . This is us eful when: • there is no displa y to monitor comman d keystrok e accur acy. • various regi ster s must be qui ckly chang ed to view r e[...]

S1D13708 Embedded Memor y LCD Controller 13708BMP Demonstration Pr ogram Docume nt Number: X 39A- B -0 03-01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev aluating Seik o Eps[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 13708 BMP Demons tration Program X39A-B-003-01 Issue Date: 01/11/ 16 THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center 13708BMP Demonstration Program S1D13708 Issue Date: 01/11/16 X39A-B-003-01 13708BMP 13708BMP is a demonst ration ut ility used to show the S1D13708 disp lay ca pabilit ies by renderin g bitmap imag es on t he displa y devic e. The progr am displays a bitma p stored i n Windows BMP fi le[...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 13708 BMP Demons tration Program X39A-B-003-01 Issue Date: 01/11/ 16 Usage At a command pr ompt, type: 13708bmp bmpfil e [/?] Where: bmpfile Specifies filename of t he windows format bmp i mage to be display ed. /? Displays the he lp message. Not e 13708BMP dis plays the bmpfil[...]

S1D13708 Embedded Memor y LCD Controller Wind River WindML v2.0 Displa y Driver s Document Numb er: X39A -E-002- 0 1 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev aluating Se[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Wind R iver WindML v 2.0 Display Drivers X39A-E-002-01 Issue Date: 01/11/ 14 THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Wind River WindML v2.0 Display Dr ivers S1D13708 Issue Date: 01/11/14 X39A-E-002-01 Wind River WindML v2.0 DISPLA Y DRIVERS The Wind River Win dM L v2.0 di splay d r ivers f or the S1 D 13708 Embedd ed Memory LCD Controlle r are i ntended as “refe rence” s ource cod e for OEMs d eve[...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Wind R iver WindML v 2.0 Display Drivers X39A-E-002-01 Issue Date: 01/11/ 14 Bui ld i ng a W i n dML v2 . 0 Di sp lay Dri v er The fo llow ing instruc tio ns pr oduc e a boot able disk th at aut oma tica lly st arts th e UGL demo program. Th ese ins tructi ons assume t hat Wind[...]

Epson Research and Development Page 5 Vancouver Des ign Center Wind River WindML v2.0 Display Dr ivers S1D13708 Issue Date: 01/11/14 X39A-E-002-01 Not e Mode0.h should be crea ted using t he conf igura tion util ity 13708CFG. F or more i nfor- mation on 1370 8CFG, see the 13708 CFG Configurati on Progra m User Manual , doc u- ment number X3 9A-B-00[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Wind R iver WindML v 2.0 Display Drivers X39A-E-002-01 Issue Date: 01/11/ 14 THIS P A GE LEFT BLANK[...]

S1D13708 Embedded Memor y LCD Controller Lin ux Console Driver Docu ment Numb er: X39 A-E -004 -01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev aluating Seik o Epson/EPSON p[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Linux Cons ole Driver X39A-E-004-01 Issue Date: 01/11/ 14 THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Linux Console Driver S1D13708 Issue Date: 01/11/14 X39A-E-004-01 Linux Console Driver The Linux con sole dri ver for t he S1D13708 Embedded Memory LCD Cont roll er is intended as “referenc e” so urce code for OEMs develop ing for Linux, and supports 4 , 8, a nd 16 bit-pe r-pixel col[...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Linux Cons ole Driver X39A-E-004-01 Issue Date: 01/11/ 14 Building the Console Driver f or Lin u x K ernel 2. 2.x Follow th e step s below to c onstr uct a copy o f the Linux operat ing syst em using the S1D13708 as the cons ole displ ay dev ice. These i nstruct ions a ssume th[...]

Epson Research and Development Page 5 Vancouver Des ign Center Linux Console Driver S1D13708 Issue Date: 01/11/14 X39A-E-004-01 4. Modify s1d1 3708.h The fil e s1d1370 8.h contai ns the register values r equir ed to set the sc reen reso lutio n, color de pth (b pp), di splay type , active d ispla y (LCD), di splay rotatio n, etc. Before bu ildin g [...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Linux Cons ole Driver X39A-E-004-01 Issue Date: 01/11/ 14 7. Boot to the Linux oper ating system. If you ar e using lilo (Li nux Load er), modi fy th e lilo co nfigur ation fi le as di scusse d in the kernel build README fi le. If there wer e no error s durin g the buil d, from[...]

Epson Research and Development Page 7 Vancouver Des ign Center Linux Console Driver S1D13708 Issue Date: 01/11/14 X39A-E-004-01 Building the Consol e Driver for Linux Kernel 2.4.x Follow the steps below to con struct a copy of the Linux o perati ng system u sing the S1D13708 as t he conso le displ ay device. T hese in struc tions ass ume that t he [...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Linux Cons ole Driver X39A-E-004-01 Issue Date: 01/11/ 14 Copy the rema ining s ource fi les /tmp/ Con fig.i n /tmp/ fbme m.c /tmp/ fbc on-c fb4 .c /tmp /Makefi le into the di rect ory /u sr/ src/ linux /dr ive rs /vid e o re placi ng t he fi le s of the sa me na me. If your ke[...]

Epson Research and Development Page 9 Vancouver Des ign Center Linux Console Driver S1D13708 Issue Date: 01/11/14 X39A-E-004-01 6. Comp ile a nd ins tal l the k erne l Build th e kerne l with the foll owing se quence o f commands : make dep make clea n make bzImage /sbin/ lilo (if runn ing li lo) 7. Boot to the Li nux operat ing sy stem If you a re[...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 Linux Cons ole Driver X39A-E-004-01 Issue Date: 01/11/ 14 THIS P A GE LEFT BLANK[...]

S1D13708 Embedded Memor y LCD Controller QNX Photon v2.0 Displa y Driver Docume nt Number: X39A- E-005- 01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev aluating Seik o Epson[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 QNX Pho ton v2.0 Display Driver X39A-E-005-01 Issue Date: 01/11/ 14 THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center QNX Photon v2.0 Display Driver S1D13708 Issue Date: 01/11/14 X39A-E-005-01 QNX Photon v2.0 Displa y Driver The Photon v 2.0 display driv ers for the S1D13708 Embedde d Memory LCD Contr oller ar e intended as “r efe re nce ” sourc e c ode for OEMs deve lopin g for QNX pla tforms . Th[...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 QNX Pho ton v2.0 Display Driver X39A-E-005-01 Issue Date: 01/11/ 14 Building the Photon v2.0 Displa y Driver The foll owing st eps buil d the Pho ton v2.0 display dr iver and integr ate it into the QNX operati ng s ystem. Th ese in struc ti ons ass ume the QNX de vel ope r envi[...]

Epson Research and Development Page 5 Vancouver Des ign Center QNX Photon v2.0 Display Driver S1D13708 Issue Date: 01/11/14 X39A-E-005-01 Installi ng the Drive r The build s tep pr oduces two l ibrary i mages: • lib/di sputi l/nto/x 86/li bdispu til.so • lib/disputi l/nt o/x86/li bffb.s o For t he l oa der to loc ate t hem, the fi les nee d t o[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 QNX Pho ton v2.0 Display Driver X39A-E-005-01 Issue Date: 01/11/ 14 Comme nt s • To restore t he disp lay drive r to t he defaul t, comment out change s made to th e trap file crt.$NODE.[...]

S1D13708 Embedded Memor y LCD Controller Windo ws® CE 3.x Displa y Driver s Docu ment Numb er: X39 A-E -006 -01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev aluating Seik o[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Windows ® CE 3.x Display Drivers X39A-E-006-01 Issue Date: 01/11/ 14 THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Windows® CE 3.x Display Drivers S1D13708 Issue Date: 01/11/14 X39A-E-006-01 WINDO WS® CE 3.0 DISPLA Y DRIVER Windows CE v3.0 displ ay driver for th e S1D13708 Embedded Memory LCD Cont roller is intended a s “refer ence” sour ce cod e for OEMs deve loping for the Mic rosoft W indow[...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Windows ® CE 3.x Display Drivers X39A-E-006-01 Issue Date: 01/11/ 14 Exam pl e D ri v er Bu ild s The follo wing sect ions descr ibes how to build the Wi ndows CE display driver for Windows CE Platfo rm Builde r 3.00 u sing the GUI interfa ce. Build for CEPC (X86) on Windows C[...]

Epson Research and Development Page 5 Vancouver Des ign Center Windows® CE 3.x Display Drivers S1D13708 Issue Date: 01/11/14 X39A-E-006-01 6. Add the env ironment va riable DDI _S1D13708. a. From the Platform menu, se lect “Set ting s”. b. Select the “ Environ ment” t ab. c. In the Variab le box, type “DDI_S1D13 708”. d. In the Val ue [...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Windows ® CE 3.x Display Drivers X39A-E-006-01 Issue Date: 01/11/ 14 10. From the Pla tform window, click the P arameterV iew Tab. Show th e tree f or MY- PLATFORM Param eters by c licking t he ‘+ ’ sign at the ro ot of the tree. Expand the WINCE300 tree a nd then click ?[...]

Epson Research and Development Page 7 Vancouver Des ign Center Windows® CE 3.x Display Drivers S1D13708 Issue Date: 01/11/14 X39A-E-006-01 11. Modify MODE0.H. The file MODE0.H (located i n x:win ce300p latform cepcdri versdi splayS1D13708) conta ins the re gis t e r va lu es re quir ed to s et th e scre en r esolu tio n, co lor de pth (b pp)[...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Windows ® CE 3.x Display Drivers X39A-E-006-01 Issue Date: 01/11/ 14 Installat ion f or CEPC En vir onment Once the nk.bi n file is bu ilt, the CEPC envir onment can be started by b ooting either f rom a floppy or hard dr ive confi gured wi th a Windows 9 x opera ting s ystem.[...]

Epson Research and Development Page 9 Vancouver Des ign Center Windows® CE 3.x Display Drivers S1D13708 Issue Date: 01/11/14 X39A-E-006-01 Configu ration The re ar e se ver al is sues to co nsid er w hen conf igu rin g the d isp lay driv er. T he i ssue s co ver debugging s upport , registe r initi alizati on val ues and memory alloc ation. Each o[...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 Windows ® CE 3.x Display Drivers X39A-E-006-01 Issue Date: 01/11/ 14 This opt ion sho uld re main di sabled unl ess yo u are performing speci fic debug ging t asks t hat requir e the de bug monit or. MonoP anel This opt ion is intended f or th e support o f monochr ome panels[...]

Epson Research and Development Page 11 Vancouver Des ign Center Windows® CE 3.x Display Drivers S1D13708 Issue Date: 01/11/14 X39A-E-006-01 “Width”=dwor d:140 “Height”= dword:F0 “Bp p”=d word :8 “Rotation ”=dword: 0 Note that a ll dwo rd val ues a re i n hexad ecimal, t heref ore 140h = 320 a nd F0h = 2 40. Wh en the displ ay driv [...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 Windows ® CE 3.x Display Drivers X39A-E-006-01 Issue Date: 01/11/ 14 2. Using off-sc reen d is pla y memory s ign if ic antly impr ove s d ispla y pe rforma nce. For ex - ample, sli der bars a ppear mo re smooth when using o ff-screen me mory. To en able or disa ble the u s e[...]

Epson Research and Development Page 13 Vancouver Des ign Center Windows® CE 3.x Display Drivers S1D13708 Issue Date: 01/11/14 X39A-E-006-01 c. PORepaint=2 • This mode t ells WinCE t o not sa ve the main displ ay data on s uspend, and causes Win CE to REPAINT t he main d isplay on resume. • Th is mo de is used if d ispla y m emor y pow er i s g[...]

Page 14 Epson Research and Development Vancouver Des ign Center S1D13708 Windows ® CE 3.x Display Drivers X39A-E-006-01 Issue Date: 01/11/ 14 Comme nt s • The displa y driv er is CP U indepen dent, a llowing us e of th e driv er for se veral Windows CE Platfor m Builder su pporte d platfor ms. The fi le s1dfl at.cpp will requ ir e ed it ing fo r[...]

S1D13708 Embedded Memor y LCD Controller P ower Consumption Docu ment Numb er: X39 A-G -006 -01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev aluating Seik o Epson/EPSON prod[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Power Cons umption X39A-G-006-01 Issue Date: 01/11/25 THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Power Consumption S1D13708 Issue Date: 01/11/25 X39A-G-006-01 1 S1D13708 P o wer Consumption The S1D1370 8 power consu mption can be affe cted by many s ystem de sign vari ables. Some of the v ariab les to con sider are: • Input Clock Frequency (CLKI/CLKI2/XTAL): CLKI/CLKI 2/XTAL freq[...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Power Cons umption X39A-G-006-01 Issue Date: 01/11/25 1.1 Conditio ns To ill ust rate th e va rious fac tors th at c an eff ect powe r, th e foll owin g ta b le li st th e p ow e r consump tion for a typical Motorol a DragonBal l VZ interf ace i mplementa tion. The DragonBall c[...]

Epson Research and Development Page 5 Vancouver Des ign Center Power Consumption S1D13708 Issue Date: 01/11/25 X39A-G-006-01 2 Summary Table 1-1:, “S1D13708 Po wer Consumpt io n,” on page 4 shows that t he S1 D13708 p ower consumption depends on the spe cific i mplementati on. Acti ve Mode power c onsumption depends o n t he desi re d CP U pe r[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Power Cons umption X39A-G-006-01 Issue Date: 01/11/25 THIS P A GE LEFT BLANK[...]

S1D13708 Embedded Memor y LCD Controller Interfacing to the NEC VR4102 / VR4111 Micr oprocessor s Docu ment Numb er: X39 A-G -007 -01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use [...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the NEC VR4102 / VR4111 Microprocessors X39A-G-007-01 Issue Date: 01/11/05 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Interfacing to the NEC VR410 2 / VR4111 Mi croprocessors S1D1 3708 Issue Date: 01/11/05 X39A-G-007-01 T able of Contents 1 Introducti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfaci ng to the NEC VR4102/VR4111 . . . . . . . . . . . . . . [...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the NEC VR4102 / VR4111 Microprocessors X39A-G-007-01 Issue Date: 01/11/05 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 5 Vancouver Des ign Center Interfacing to the NEC VR410 2 / VR4111 Mi croprocessors S1D1 3708 Issue Date: 01/11/05 X39A-G-007-01 List o f T ab le s Table 3-1: Host Bus Inte rface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4- 1: Summary of Power-On/Reset Configura tion Options[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the NEC VR4102 / VR4111 Microprocessors X39A-G-007-01 Issue Date: 01/11/05 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 7 Vancouver Des ign Center Interfacing to the NEC VR410 2 / VR4111 Mi croprocessors S1D1 3708 Issue Date: 01/11/05 X39A-G-007-01 1 Introduction This appli cation no te des cribes t he hard ware and software environment requi red to interfa ce the S1D137 08 Embedded Memory LCD Contr oller a nd the NEC VR41 02/4111[...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the NEC VR4102 / VR4111 Microprocessors X39A-G-007-01 Issue Date: 01/11/05 2 Interfacing to the NEC VR4102/VR4111 2.1 The NEC VR41XX System Bus The VR-Seri es fami ly of mi croproce ssors features a high -speed syn chronou s syst em bus typical of modern mi crop[...]

Epson Research and Development Page 9 Vancouver Des ign Center Interfacing to the NEC VR410 2 / VR4111 Mi croprocessors S1D1 3708 Issue Date: 01/11/05 X39A-G-007-01 2.1.2 LCD Memory Acce ss Cyc l es Once an address in the LCD block of me mory is p laced on the ext ernal address bu s (ADD[25:0 ]) the LCD c hip select (LCDCS#) is dri ven low. The rea[...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the NEC VR4102 / VR4111 Microprocessors X39A-G-007-01 Issue Date: 01/11/05 3 S1D13708 Host Bus Interface The S1D13708 dir ect ly suppor ts mu lt ipl e p roc es sor s. The S1D13708 i mplements a 16-bit Generic #2 Host Bus In terf ace which i s most s uitable f o[...]

Epson Research and Development Page 11 Vancouver Des ign Center Interfacing to the NEC VR410 2 / VR4111 Mi croprocessors S1D1 3708 Issue Date: 01/11/05 X39A-G-007-01 3.2 Hos t Bus Interface Signals The Host Bus In ter face re qu i r es th e foll ow ing si gna ls: • CLKI is a clock input whic h is re quired by the S 1D13708 Host Bus Inter face as [...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the NEC VR4102 / VR4111 Microprocessors X39A-G-007-01 Issue Date: 01/11/05 4 VR4102/VR4111 to S1D13708 Interfac e 4.1 Har dware Descr iption The NEC VR4102/VR4 111 micr oproces sor i s spec ific ally design ed to s upport an ext ernal LCD control ler by pr ovid[...]

Epson Research and Development Page 13 Vancouver Des ign Center Interfacing to the NEC VR410 2 / VR4111 Mi croprocessors S1D1 3708 Issue Date: 01/11/05 X39A-G-007-01 4.2 S1D137 08 Har d ware Configuration The S1D13708 use s CNF7 thr ough CNF0 to al low sel ection o f the bus mod e and other configur ation d ata on t he ri sing edg e of RESET#. Fo r[...]

Page 14 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the NEC VR4102 / VR4111 Microprocessors X39A-G-007-01 Issue Date: 01/11/05 4.3 NEC VR4102/VR4111 Configuration The NEC VR4102/41 11 provi des the i ntern al addres s decod ing necess ary to map a n externa l LCD control ler. Physical a ddress 0A00_ 0000h t o 0A[...]

Epson Research and Development Page 15 Vancouver Des ign Center Interfacing to the NEC VR410 2 / VR4111 Mi croprocessors S1D1 3708 Issue Date: 01/11/05 X39A-G-007-01 5 Software Test util ities a nd dis play driv ers ar e avai lable fo r the S1 D13708. Ful l source code is avai lab le for b o th th e tes t u tilit ies an d the d riv ers. The test ut[...]

Page 16 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the NEC VR4102 / VR4111 Microprocessors X39A-G-007-01 Issue Date: 01/11/05 6 Ref erences 6.1 Documents • NEC Electronics Inc., VR4102/ VR4111 64/ 32-bit Mi croproc essor Prel iminary Use r’s Manual . • Epson Resear ch and Developme nt, Inc., S1D1370 8 Har[...]

Epson Research and Development Page 17 Vancouver Des ign Center Interfacing to the NEC VR410 2 / VR4111 Mi croprocessors S1D1 3708 Issue Date: 01/11/05 X39A-G-007-01 7 T echnical Suppor t 7.1 Epson LCD Con tr oller s (S1D13708) 7.2 NEC El ectr o nics Inc. Japan Seiko Epson Corporation Electronic Device s Marketing D ivision 421-8, Hino, Hino-shi To[...]

Page 18 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the NEC VR4102 / VR4111 Microprocessors X39A-G-007-01 Issue Date: 01/11/05 THIS P AGE LEF T BLANK[...]

S1D13708 Embedded Memor y LCD Controller Interfacing to the NEC VR4181A™ Micr oprocessor Docu ment Numb er: X39 A-G -008 -01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev a[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the NEC VR4181A™ Microproc essor X39A-G-008-01 Issue Date: 01/11/05 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Interfacing to the NEC VR418 1A™ Microprocessor S1D13708 Issue Date: 01/11/05 X39A-G-008-01 T able of Contents 1 Introducti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfaci ng to the NEC VR4181A . . . . . . . . . . . . . . . . . . . . . [...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the NEC VR4181A™ Microproc essor X39A-G-008-01 Issue Date: 01/11/05 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 5 Vancouver Des ign Center Interfacing to the NEC VR418 1A™ Microprocessor S1D13708 Issue Date: 01/11/05 X39A-G-008-01 List o f T ab le s Table 3-1: Host Bus Inte rface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4- 1: Summary of Power-On/Reset Configura tion Options . . . .[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the NEC VR4181A™ Microproc essor X39A-G-008-01 Issue Date: 01/11/05 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 7 Vancouver Des ign Center Interfacing to the NEC VR418 1A™ Microprocessor S1D13708 Issue Date: 01/11/05 X39A-G-008-01 1 Introduction This appli cation no te des cribes t he hard ware and software environment requi red to interface the S1D137 08 Embedded Memory LCD Contr oller a nd the NEC VR4181A microproce ss[...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the NEC VR4181A™ Microproc essor X39A-G-008-01 Issue Date: 01/11/05 2 Interfacing to the NEC VR4181A 2.1 The NEC VR4181A System Bus The VR-Seri es fami ly of mi croproce ssors features a high -speed syn chronou s syst em bus typical of modern mi croproces sors.[...]

Epson Research and Development Page 9 Vancouver Des ign Center Interfacing to the NEC VR418 1A™ Microprocessor S1D13708 Issue Date: 01/11/05 X39A-G-008-01 2.1.2 LCD Memory Access Signals The S1D13708 requi res an addr ess in g rang e of 256K byt es . When the VR4181 A ex ter nal LCD controll er chip s elect si gnal is p rogrammed to a win dow of [...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the NEC VR4181A™ Microproc essor X39A-G-008-01 Issue Date: 01/11/05 3 S1D13708 Host Bus Interface The S1D13708 dir ect ly suppor ts mu lt ipl e p roc es sor s. The S1D13708 i mplements a 16-bit Generic #2 Host Bus In terf ace which i s most s uitable f or dire[...]

Epson Research and Development Page 11 Vancouver Des ign Center Interfacing to the NEC VR418 1A™ Microprocessor S1D13708 Issue Date: 01/11/05 X39A-G-008-01 3.2 Hos t Bus Interface Signals The interf ace re qui re s th e f ollo win g sign als. • CLKI is a clock input whic h is re quired by the S 1D13708 Host Bus Inter face as a s ource for it s [...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the NEC VR4181A™ Microproc essor X39A-G-008-01 Issue Date: 01/11/05 4 VR4181A to S1D13708 Interfa ce 4.1 Har dware Descr iption The NEC VR4181A micr oproce ssor is s pecif ically d esigne d to suppor t an ex ternal LCD control ler by providin g the i ntern al [...]

Epson Research and Development Page 13 Vancouver Des ign Center Interfacing to the NEC VR418 1A™ Microprocessor S1D13708 Issue Date: 01/11/05 X39A-G-008-01 4.2 S1D137 08 Har d ware Configuration The S1D13708 use s CNF7 thr ough CNF0 to al low sel ection o f the bus mod e and other configur ation d ata on t he ri sing edg e of RESET#. Fo r deta il[...]

Page 14 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the NEC VR4181A™ Microproc essor X39A-G-008-01 Issue Date: 01/11/05 4.3 NEC VR4181A Co nfiguration The S1D13708 i s a memory mappe d devic e. The S1D13708 uses t wo 128K byte bl ocks which are selec ted using A17 from th e NEC VR181A (A 17 is co nnected to the[...]

Epson Research and Development Page 15 Vancouver Des ign Center Interfacing to the NEC VR418 1A™ Microprocessor S1D13708 Issue Date: 01/11/05 X39A-G-008-01 5 Software Test util ities a nd dis play driv ers ar e avai lable fo r the S1 D13708. Ful l source code is avai lab le for b o th th e tes t u tilit ies an d the d riv ers. The test ut ilit ie[...]

Page 16 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the NEC VR4181A™ Microproc essor X39A-G-008-01 Issue Date: 01/11/05 6 Ref erences 6.1 Documents • NEC Electronics Inc., NEC VR4181A Target S pecific ation , Revision 0.5 , 9/11/98 • Epson Resear ch and Developme nt, Inc., S1D1370 8 Hardware Funct ional Spe[...]

Epson Research and Development Page 17 Vancouver Des ign Center Interfacing to the NEC VR418 1A™ Microprocessor S1D13708 Issue Date: 01/11/05 X39A-G-008-01 7 T echnical Suppor t 7.1 Epson LCD Con tr oller s (S1D13708) 7.2 NEC El ectr o nics Inc. Japan Seiko Epson Corporation Electronic Device s Marketing D ivision 421-8, Hino, Hino-shi Tokyo 191-[...]

Page 18 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the NEC VR4181A™ Microproc essor X39A-G-008-01 Issue Date: 01/11/05 THIS P AGE LEF T BLANK[...]

S1D13708 Embedded Memor y LCD Controller Interfacing to the Motor ola MPC821 Micr oprocessor Document Number: X39A-G-009-0 1 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev alu[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Motorola MPC821 Microproc esso r X39A-G-009-01 Issue Date: 01/11/06 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Interfacing to the Motorola MPC82 1 Microprocessor S1D13708 Issue Date: 01/11/06 X39A-G-009-01 T able of Contents 1 Introducti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfaci ng to the MPC821 . . . . . . . . . . . . . . . . . . . . . . . [...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Motorola MPC821 Microproc esso r X39A-G-009-01 Issue Date: 01/11/06 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 5 Vancouver Des ign Center Interfacing to the Motorola MPC82 1 Microprocessor S1D13708 Issue Date: 01/11/06 X39A-G-009-01 List o f T ab le s Table 3-1: Host Bus Inte rface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4- 1: List of Connection s from MPC821ADS to S1D1370 8 . . . [...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Motorola MPC821 Microproc esso r X39A-G-009-01 Issue Date: 01/11/06 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 7 Vancouver Des ign Center Interfacing to the Motorola MPC82 1 Microprocessor S1D13708 Issue Date: 01/11/06 X39A-G-009-01 1 Introduction This appli cation no te des cribes t he hard ware and software environment requi red to interfa ce the S1D137 08 Embedded Memory LCD Co ntrolle r and the Mot orola MPC8 21 micro[...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Motorola MPC821 Microproc esso r X39A-G-009-01 Issue Date: 01/11/06 2 Interfacing to the MPC821 2.1 The MPC8XX System Bus The MPC8xx famil y of proce ssors fe ature a hi gh-speed s ynchronous system bus t ypical of modern RISC micro processor s. This section [...]

Epson Research and Development Page 9 Vancouver Des ign Center Interfacing to the Motorola MPC82 1 Microprocessor S1D13708 Issue Date: 01/11/06 X39A-G-009-01 2.2.1 Normal (Non-Bu r s t) Bus T ransact ions A data tra nsfer is init iated by the bus master by plac ing the memory addre ss on ad dress lines A0 t hrough A31 and drivi ng TS (Tr ansfer St [...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Motorola MPC821 Microproc esso r X39A-G-009-01 Issue Date: 01/11/06 Figure 2 -2: “ Power PC M emor y W r it e Cyc le” il lu strat es a typic al m emory write cy cle o n the Po we r P C s ystem bu s . Figure 2- 2: Power PC Memory Write Cycl e If an er ror[...]

Epson Research and Development Page 11 Vancouver Des ign Center Interfacing to the Motorola MPC82 1 Microprocessor S1D13708 Issue Date: 01/11/06 X39A-G-009-01 If a peri phera l is not c apable of support ing bu rst cy cles, it can as sert Burst Inhibit (BI ) sim ulta neou sly with TA , and the processo r rev erts to normal bus cy cles for the remai[...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Motorola MPC821 Microproc esso r X39A-G-009-01 Issue Date: 01/11/06 Figure 2- 3: “GPCM Memory Devices Timi ng” illu strat es a typi cal cycl e for a memory mapped devi ce usi ng the GP CM of the Powe r PC. Figure 2- 3: GPCM Memory Devic es Timing 2.3.2 U[...]

Epson Research and Development Page 13 Vancouver Des ign Center Interfacing to the Motorola MPC82 1 Microprocessor S1D13708 Issue Date: 01/11/06 X39A-G-009-01 3 S1D13708 Host Bus Interface The S1D1370 8 di rec tl y s uppo rt s mul tipl e pr oce sso rs . The S 1D13708 impl emen ts a 16 -bi t Generic #1 Host Bus Interface whi ch is most suitab le for[...]

Page 14 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Motorola MPC821 Microproc esso r X39A-G-009-01 Issue Date: 01/11/06 3.2 Host Bus Interface Signals The Host Bus Inter face req uires the fo llowing si gnals . • CLKI is a clo ck input whi ch is requ ired by th e S1D13708 Host Bu s Interf ace as a so urce f[...]

Epson Research and Development Page 15 Vancouver Des ign Center Interfacing to the Motorola MPC82 1 Microprocessor S1D13708 Issue Date: 01/11/06 X39A-G-009-01 4 MPC821 to S1D13708 Interface 4.1 Har dware Descr iption The interf ace between th e S1D13708 and the MPC821 requ ires no exter nal glue logic. The polarit y of the WAIT# s ignal must be sel[...]

Page 16 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Motorola MPC821 Microproc esso r X39A-G-009-01 Issue Date: 01/11/06 Not e The inter face was de signed usi ng a Motor ola MPC821 Applicati on Development System (ADS ). The ADS board has 5 vo lt log ic connect ed to the data b us, so the interfa ce includ ed[...]

Epson Research and Development Page 17 Vancouver Des ign Center Interfacing to the Motorola MPC82 1 Microprocessor S1D13708 Issue Date: 01/11/06 X39A-G-009-01 Not e The bit n umbering of the Mo torola MPC821 bus sig nals is r evers ed from the normal conventi on, e.g.: t he most s ignific ant addres s bit is A0, the n ext is A1, A2, etc. D12 P12-B1[...]

Page 18 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Motorola MPC821 Microproc esso r X39A-G-009-01 Issue Date: 01/11/06 4.3 S1D13708 Har d w are Configuration The S1D13708 uses CNF7 thro ugh CNF0 to all ow select ion of the bus mode a nd other configur atio n data o n th e risi ng edge of RESET#. For detai ls[...]

Epson Research and Development Page 19 Vancouver Des ign Center Interfacing to the Motorola MPC82 1 Microprocessor S1D13708 Issue Date: 01/11/06 X39A-G-009-01 4.5 MPC821 Chip Selec t Configuration Chip selec t 4 is used to con trol the S1D13708. Th e foll owing opti ons are se lect ed in the base add r ess r egi ster (BR4 ). • BA (0:16) = 000 0 0[...]

Page 20 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Motorola MPC821 Microproc esso r X39A-G-009-01 Issue Date: 01/11/06 4.6 T est Softwar e The test soft war e to exe rcise thi s int erfa ce is ve ry s imp le. It co nfi gures ch ip se lec t 4 (C S4) on the MPC821 to map the S1D13708 to an unused 256K byt e bl[...]

Epson Research and Development Page 21 Vancouver Des ign Center Interfacing to the Motorola MPC82 1 Microprocessor S1D13708 Issue Date: 01/11/06 X39A-G-009-01 5 Software Test util ities a nd dis play driv ers ar e avai lable fo r the S1 D13708. Ful l source code is avai lab le for b o th th e tes t u tilit ies an d the d riv ers. The test ut ilit i[...]

Page 22 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Motorola MPC821 Microproc esso r X39A-G-009-01 Issue Date: 01/11/06 6 Ref erences 6.1 Documents • Motorola Inc., P ower PC MPC821 Por table Systems Mic roproce ssor User’ s Manual , Motorol a Publicat ion no. MPC821UM/; ava ilable on the I nternet a t ht[...]

Epson Research and Development Page 23 Vancouver Des ign Center Interfacing to the Motorola MPC82 1 Microprocessor S1D13708 Issue Date: 01/11/06 X39A-G-009-01 7 T echnical Suppor t 7.1 EPSO N LCD/CR T Contr oller s (S1 D13708) 7.2 Mot or ola MPC82 1 Pr ocessor • Motorola Desi gn Line, (800) 5 21-6274 . • Local M oto rola sa les offi ce or a uth[...]

Page 24 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Motorola MPC821 Microproc esso r X39A-G-009-01 Issue Date: 01/11/06 THIS P AGE LEF T BLANK[...]

S1D13708 Embedded Memor y LCD Controller Interfacing to the Motor ola MCF5307 "ColdFire" Micr oprocessor Docu ment Numb er: X39A -G-0 10-0 1 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola MCF5307 "ColdFire" Microprocesso r X39A-G-010-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor S1D13708 Issue Date: 01/11/25 X39A-G-010-01 T able of Contents 1 Introducti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfaci ng to the MCF5307 . . . . . . . . . . . . [...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola MCF5307 "ColdFire" Microprocesso r X39A-G-010-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 5 Vancouver Des ign Center Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor S1D13708 Issue Date: 01/11/25 X39A-G-010-01 List o f T ab le s Table 3-1: Host Bus Inte rface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4- 1: Summary of Power-On/Reset Configur[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola MCF5307 "ColdFire" Microprocesso r X39A-G-010-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 7 Vancouver Des ign Center Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor S1D13708 Issue Date: 01/11/25 X39A-G-010-01 1 Introduction This appli cation no te des cribes t he hard ware and software environment requi red to interfa ce the S1 D13708 Embed ded Memory LCD Controll er and t he M[...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola MCF5307 "ColdFire" Microprocesso r X39A-G-010-01 Issue Date: 01/11/25 2 Interfacing to the MC F5307 2.1 The MCF5307 System Bus The MCF5200/530 0 famil y of proce ssors feature a high-spe ed sync hronous sys tem bus typical of modern micr o[...]

Epson Research and Development Page 9 Vancouver Des ign Center Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor S1D13708 Issue Date: 01/11/25 X39A-G-010-01 Figure 2-1 : “MCF5307 Memor y Read Cyc le,” ill ustra tes a typ ical memory rea d cycle on the MCF5307 sys tem bus. Figure 2-1 : MCF5307 Memory Rea d Cycle Figure 2-2:[...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola MCF5307 "ColdFire" Microprocesso r X39A-G-010-01 Issue Date: 01/11/25 caches fr om prog ram or data memory. They are t ypi cal ly not use d for tra nsf er s to or from IO perip heral devi ces s uch as the S1D13708. The MCF5307 chi p selec[...]

Epson Research and Development Page 11 Vancouver Des ign Center Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor S1D13708 Issue Date: 01/11/25 X39A-G-010-01 3 S1D13708 Host Bus Interface The S1D1370 8 di rec tl y s uppo rt s mul tipl e pr oce sso rs . The S 1D13708 impl emen ts a 16 -bi t Generic #1 Host Bus Interface whi ch [...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola MCF5307 "ColdFire" Microprocesso r X39A-G-010-01 Issue Date: 01/11/25 3.2 Host Bus Interface Signals The Host Bus Inter face req uires the fo llowing si gnals . • CLKI is a clo ck input whi ch is requ ired by th e S1D13708 Host Bu s Int[...]

Epson Research and Development Page 13 Vancouver Des ign Center Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor S1D13708 Issue Date: 01/11/25 X39A-G-010-01 4 MCF5307 T o S1D13708 Interface 4.1 Har dware Descr iption The inter face betwe en the S1D13708 and th e MCF5307 re quires no extern al glu e logic. The polari ty of the[...]

Page 14 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola MCF5307 "ColdFire" Microprocesso r X39A-G-010-01 Issue Date: 01/11/25 4.2 S1D13708 Har d w are Configuration The S1D13708 u ses CNF7 t hrough CNF0 to a llow sele ction of the bus mode and o ther configur atio n data o n th e risi ng edge [...]

Epson Research and Development Page 15 Vancouver Des ign Center Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor S1D13708 Issue Date: 01/11/25 X39A-G-010-01 4.3 Register/Memory Mapping The S1D1370 8 uses two 12 8K byte bloc ks which are sele cted us ing A17 fro m the MCF5307 (A17 i s conne cted to t he S1D137 08 M/R# pin). Th[...]

Page 16 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola MCF5307 "ColdFire" Microprocesso r X39A-G-010-01 Issue Date: 01/11/25 5 Softw are Test uti litie s and displ ay dri vers are availabl e for the S1D13708. F ull so urce code i s availa ble fo r both t he te st util ities and th e drivers .[...]

Epson Research and Development Page 17 Vancouver Des ign Center Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor S1D13708 Issue Date: 01/11/25 X39A-G-010-01 6 References 6.1 Do cu me nt s • Motorola Inc., MCF5307 Cold Fire® Int egrated Mic roprocess or User’ s Manual , Motorola Public ation no. MCF5307 UM; avail able on [...]

Page 18 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola MCF5307 "ColdFire" Microprocesso r X39A-G-010-01 Issue Date: 01/11/25 7 T echnical Suppor t 7.1 EPSON LCD Controll er s (S1D13708) 7.2 Motor o la MCF5 307 Pr ocessor • Motorola Design Line, ( 800) 521-62 74. • Local Motoro la sales of[...]

S1D13708 Embedded Memor y LCD Controller Connecting to the Sharp HR-TFT Pa n e l s Docu ment Numb er: X39 A-G -011 -01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev aluating [...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to the Sharp HR-TFT Panels X39A-G-011-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Connecting to the Sharp HR-TFT Panels S1D13708 Issue Date: 01/11/25 X39A-G-011-01 T able of Contents 1 Introducti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Connecting to the Sharp LQ039Q2DS01 HR-TFT . . . . . . . . . . . . . . . . . . . . 8 2[...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to the Sharp HR-TFT Panels X39A-G-011-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 5 Vancouver Des ign Center Connecting to the Sharp HR-TFT Panels S1D13708 Issue Date: 01/11/25 X39A-G-011-01 List o f T ab le s Table 2-1: HR-TFT Power-On/Of f Sequence Timin g . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2- 2: S1D13708 to LQ039Q2DS01 Pin Mappi ng . . . . . . . . . . . . . . . . . .[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to the Sharp HR-TFT Panels X39A-G-011-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 7 Vancouver Des ign Center Connecting to the Sharp HR-TFT Panels S1D13708 Issue Date: 01/11/25 X39A-G-011-01 1 Introduction This appli cation no te descri bes the ha rdware envi ronment require d to connect to the Sharp HR-TFT panels directl y suppor ted by the S1D13708. Th ese pan els are: • Sharp LQ031B1DDXX [...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to the Sharp HR-TFT Panels X39A-G-011-01 Issue Date: 01/11/25 2 Connecting to the Sharp LQ039Q2DS01 HR-TFT 2.1 External P o we r Supplies The S1D13708 prov ides a ll necess ary da ta and cont rol s ignals to connec t to t he Sharp LQ039Q2DS01 320 x 240 HR-TFT pa nel.[...]

Epson Research and Development Page 9 Vancouver Des ign Center Connecting to the Sharp HR-TFT Panels S1D13708 Issue Date: 01/11/25 X39A-G-011-01 2.1.2 Digital/Analog P ower Supplies The digita l p ower supp ly ( V SHD) must be conn ect ed t o a 3.3V su pply. The a nal og p ower supply (VSHA) must be c onnect ed to a 5.0V su pply. 2.1.3 DC Gate D ri[...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to the Sharp HR-TFT Panels X39A-G-011-01 Issue Date: 01/11/25 2.1.4 A C Gate Driver P owe r Suppl ies The g ate drive low le vel powe r su ppl y ( V EE ) is an AC power suppl y with a DC of fset voltage (off set typi cally -9.0V). The AC compon ent is the common e l[...]

Epson Research and Development Page 11 Vancouver Des ign Center Connecting to the Sharp HR-TFT Panels S1D13708 Issue Date: 01/11/25 X39A-G-011-01 2.2 HR-TF T M OD S i g n a l The HR-TFT panel use s an input signal (MOD) to contr ol the power -on seq uencing of the panel. This HR-TFT si gnal shoul d not be conf used wi th the S1D137 08 sign al DRDY [...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to the Sharp HR-TFT Panels X39A-G-011-01 Issue Date: 01/11/25 2.3 S 1D13708 to LQ0 39Q2DS01 Pin Mapping Table 2-2: S1D13708 to LQ039Q2DS0 1 Pin Mapping LCD Pin No. LCD Pin Name S1D137 08 Pin Name Desc rip tion Re mar ks 1 VDD - Power supply o f gate d river (h igh l[...]

Epson Research and Development Page 13 Vancouver Des ign Center Connecting to the Sharp HR-TFT Panels S1D13708 Issue Date: 01/11/25 X39A-G-011-01 26 B0 FPDAT17 Blue data signa l (LSB) 27 B1 FPDAT16 Blue d ata si gnal 28 B2 FPDAT15 Blue d ata si gnal 29 B3 FPDA T8 Blue data si gnal 30 B4 FPDA T7 Blue data si gnal 31 B5 FPDAT6 Blue d ata signa l (MSB[...]

Page 14 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to the Sharp HR-TFT Panels X39A-G-011-01 Issue Date: 01/11/25 3 Connecting to the Sharp LQ031B1DDxx HR-TFT 3.1 External P o we r Supplies The S1D13708 prov ides a ll necess ary da ta and cont rol s ignals to connec t to t he Sharp LQ031B1DDxx 160x16 0 HR-TFT pane l([...]

Epson Research and Development Page 15 Vancouver Des ign Center Connecting to the Sharp HR-TFT Panels S1D13708 Issue Date: 01/11/25 X39A-G-011-01 3.1.2 Digital/Analog P ower Supplies The digita l p ower supp ly ( V SHD) must be conn ect ed t o a 3.3V su pply. The a nal og p ower supply (VSHA) must be c onnect ed to a 5.0V su pply. 3.1.3 DC Gate D r[...]

Page 16 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to the Sharp HR-TFT Panels X39A-G-011-01 Issue Date: 01/11/25 3.3 S 1D13708 to LQ0 31B1DDxx Pin Mapping Table 3-1: S1D13708 to L Q031B1DDxx Pi n Mapping LCD Pin No. LCD Pin Name S1D137 08 Pin Name D esc rip tion R em arks 1 VDD - Power suppl y of ga te driver (h igh[...]

Epson Research and Development Page 17 Vancouver Des ign Center Connecting to the Sharp HR-TFT Panels S1D13708 Issue Date: 01/11/25 X39A-G-011-01 26 B0 FPDAT17 Blue data signal ( LSB) 27 B1 FPDAT16 Blue data signal 28 B2 FPDAT15 Blue data signal 29 B3 FPDAT8 Blue data signal 30 B4 FPDAT7 Blue data signal 31 B5 FPDAT6 Blue data signal ( MSB) 32 VSHD[...]

Page 18 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to the Sharp HR-TFT Panels X39A-G-011-01 Issue Date: 01/11/25 4 T est Software Test uti litie s and displ ay dri vers are availabl e for the S1D13708. F ull so urce code i s availa ble fo r both t he te st util ities and th e drivers . The test util ities a re conf [...]

Epson Research and Development Page 19 Vancouver Des ign Center Connecting to the Sharp HR-TFT Panels S1D13708 Issue Date: 01/11/25 X39A-G-011-01 5 References 5.1 Do cu me nt s • Sharp Elect ronics Cor porati on, LQ039Q2DS01 Speci ficat ion . • Sharp Elect ronics Cor porati on, LQ031B1DDxx Sp ecifica tion . • Epson Research and Dev elopment, [...]

Page 20 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to the Sharp HR-TFT Panels X39A-G-011-01 Issue Date: 01/11/25 6 T echnical Suppor t 6.1 EPSON LCD Controll er s (S1D13708) 6.2 Sharp HR-TFT P anel http:/ /www.sharpsma.c om Japan Seiko Epson Corporation Electronic Device s Marketing D ivision 421-8, Hino, Hino-shi T[...]

S1D13708 Embedded Memor y LCD Controller Interfacing to the Motor ola RedCap2 Docu ment Numb er: X39 A-G -014 -01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev aluating Seik [...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola RedC ap2 X39A-G-014-01 Issue Date: 01/11/06 THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Interfacing to the Motorola RedCap2 S1D13708 Issue Date: 01/11/06 X39A-G-014-01 T able of Contents 1 Introducti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfaci ng to the REDCAP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola RedC ap2 X39A-G-014-01 Issue Date: 01/11/06 THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 5 Vancouver Des ign Center Interfacing to the Motorola RedCap2 S1D13708 Issue Date: 01/11/06 X39A-G-014-01 List o f T ab le s Table 3-1: Host Bus Inte rface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4- 1: List of Conne ctions f or REDCAP2 ADM . . . . . . . . . . . . . . . . [...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola RedC ap2 X39A-G-014-01 Issue Date: 01/11/06 THIS P A GE LEFT BLANK[...]

Epson Research and Development Page 7 Vancouver Des ign Center Interfacing to the Motorola RedCap2 S1D13708 Issue Date: 01/11/06 X39A-G-014-01 1 Introductio n This appli c ation n ote describes the hardware and software environment requi red to provide an interfa ce between the S1D13708 Embedded Memory LCD Controller and the Motorola REDCAP2 proces[...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola RedC ap2 X39A-G-014-01 Issue Date: 01/11/06 2 Interfacing to the RED CAP2 2.1 The REDCAP2 System Bus REDCAP2 integr ates a RI SC micropr ocessor ( MCU) an d a genera l purpo se digi tal si gnal process or (DSP) on a singl e chip. The Exte rnal Int e[...]

Epson Research and Development Page 9 Vancouver Des ign Center Interfacing to the Motorola RedCap2 S1D13708 Issue Date: 01/11/06 X39A-G-014-01 Figure 2-1: “REDCAP2 Memory Read Cycle” on pag e 9 illustrates a typical memory rea d cycle on t he REDCAP2 bus. Figure 2- 1: REDCAP2 Memory Read Cycle Figu re 2 -2: “RED C A P2 Mem or y W ri t e Cy cl[...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola RedC ap2 X39A-G-014-01 Issue Date: 01/11/06 3 S1D13708 Host Bus Interface The S1D13708 i mplement s a 16- bit nati ve REDCAP2 host bus inte rface whic h is us ed to interf ace to th e REDCAP2 process or. The REDCAP2 host bus int erface i s select e[...]

Epson Research and Development Page 11 Vancouver Des ign Center Interfacing to the Motorola RedCap2 S1D13708 Issue Date: 01/11/06 X39A-G-014-01 3.2 Host Bus Interface Si gnals The Hos t Bus In ter face re qu i r es th e foll ow ing si gna ls: • CLKI is a clock i nput whi ch is requ ired by th e S1D13708 host bus interf ace and connects to CKO of [...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola RedC ap2 X39A-G-014-01 Issue Date: 01/11/06 4 REDCAP2 to S1D13708 Interface 4.1 Har dware Descr iption The inte rface between the S1D13708 a nd the REDCAP2 requi res no ext ernal gl ue logi c. The infor mation in thi s secti on descr ibes the envir[...]

Epson Research and Development Page 13 Vancouver Des ign Center Interfacing to the Motorola RedCap2 S1D13708 Issue Date: 01/11/06 X39A-G-014-01 4.2 Har dware Connect ions The followi ng table details the con nections for the pins and si gnals of t he REDCAP2. Table 4- 1: List of Con nections for REDCAP2 ADM REDCAP2 Signal Na me REDCAP2ADS Connector[...]

Page 14 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola RedC ap2 X39A-G-014-01 Issue Date: 01/11/06 Not e Pin 5 and pi n 13 of U2 8 on the ADM must be connected to V DD. This en sures tha t the DIR signal of transcei vers U17 and U18 is low only du ring read acce ss, even when EBC in the CS1 Con trol Re[...]

Epson Research and Development Page 15 Vancouver Des ign Center Interfacing to the Motorola RedCap2 S1D13708 Issue Date: 01/11/06 X39A-G-014-01 4.3 S1D137 08 Har d ware Configuration The S1D13708 use s CNF7 thr ough CNF0 to al low sel ection o f the bus mod e and other configur ation d ata on t he ri sing edg e of RESET#. Fo r deta ils on config ur[...]

Page 16 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola RedC ap2 X39A-G-014-01 Issue Date: 01/11/06 4.5 REDCAP2 Chip Selec t Configuration In thi s examp le, Chip Select 1 co ntrols the S1 D13708. The f ollowing optio ns ar e select ed in the CS1 C ontr ol R e gis ter. • CSEN = 1 — Chip Sele ct func[...]

Epson Research and Development Page 17 Vancouver Des ign Center Interfacing to the Motorola RedCap2 S1D13708 Issue Date: 01/11/06 X39A-G-014-01 5 Software Test util ities a nd dis play driv ers ar e avai lable fo r the S1 D13708. Ful l source code is avai lab le for b o th th e tes t u tilit ies an d the d riv ers. The test ut ilit ies a re c on fi[...]

Page 18 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola RedC ap2 X39A-G-014-01 Issue Date: 01/11/06 6 Ref erences 6.1 Documents • Motorola Inc., R EDCAP2 Dig ital Sign al Process or Int egrated Wit h MCU Product Specific ations Rev . 1.2ext . • Epson Resear ch and Developme nt, Inc., S1D1370 8 Hardw[...]

Epson Research and Development Page 19 Vancouver Des ign Center Interfacing to the Motorola RedCap2 S1D13708 Issue Date: 01/11/06 X39A-G-014-01 7 T echnical Suppor t 7.1 EPSO N LCD/CR T Contr oller s (S1 D13708) 7.2 Mot oro la REDCAP2 Pr ocessor • Motorola Desi gn Line, (800) 5 21-6274 . • Local M oto rola sa les offi ce or a uth orize d di str[...]

Page 20 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to t he Motorola RedC ap2 X39A-G-014-01 Issue Date: 01/11/06 THIS P A GE LEFT BLANK[...]

S1D13708 Embedded Memor y LCD Controller Interfacing to 8-bit Pr ocessors Docu ment Numb er: X39 A-G -015 -01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use in ev aluating Seik o Ep[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to 8-bit Proce ssors X39A-G-015-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Interfacing to 8 -bit Processors S1D13708 Issue Date: 01/11/25 X39A-G-015-01 T able of Contents 1 Introducti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfaci ng to an 8-bit Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to 8-bit Proce ssors X39A-G-015-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 5 Vancouver Des ign Center Interfacing to 8 -bit Processors S1D13708 Issue Date: 01/11/25 X39A-G-015-01 List o f T ab le s Table 3-1: Host Bus Inte rface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4- 1: Summary of Power-On/Reset Configura tion Options . . . . . . . . . . . .[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to 8-bit Proce ssors X39A-G-015-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 7 Vancouver Des ign Center Interfacing to 8 -bit Processors S1D13708 Issue Date: 01/11/25 X39A-G-015-01 1 Introduction This appli cation no te des cribes t he hard ware and software environment requi red to interfa ce the S1D137 08 Embedded Memory LCD Controlle r and 8-bi t proc essors. Thi s document is not in t[...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to 8-bit Proce ssors X39A-G-015-01 Issue Date: 01/11/25 2 Interfacing to an 8-bit Pr ocessor 2.1 The Generic 8-bit Pr ocessor Syst em Bus Although t he S1D137 08 does n ot direct ly sup port an 8- bit CPU, a n 8-bit i nterfac e can be achieve d with minimal exte rna[...]

Epson Research and Development Page 9 Vancouver Des ign Center Interfacing to 8 -bit Processors S1D13708 Issue Date: 01/11/25 X39A-G-015-01 3 S1D13708 Host Bus Interface The S1D1370 8 di rec tl y s uppo rt s mul tipl e pr oce sso rs . The S 1D13708 impl emen ts a 16 -bi t Generic #2 Host Bus I nterfac e which can be adapt ed for use with a n 8-bit [...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to 8-bit Proce ssors X39A-G-015-01 Issue Date: 01/11/25 3.2 Host Bus Interface Signals The S1D13708 Gene ric # 2 Host Bu s Int erfac e requ ires the f ollowi ng sig nals f rom an 8-b it process or. • CLKI is a clo ck input whi ch is requ ired by th e S1D13708 Hos[...]

Epson Research and Development Page 11 Vancouver Des ign Center Interfacing to 8 -bit Processors S1D13708 Issue Date: 01/11/25 X39A-G-015-01 4 8-Bit Proce ssor to S1D13708 Interface 4.1 Har dware Connect ions The interf ace bet ween the S1D13708 and an 8-bit proc essor requires mini mal glue logi c. A decoder i s used to gene rate th e chip select [...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to 8-bit Proce ssors X39A-G-015-01 Issue Date: 01/11/25 4.2 S1D13708 Har dware Configuration The S1D13708 uses CNF7 thro ugh CNF0 to all ow select ion of the bus mode a nd other configur atio n data o n th e risi ng edge of RESET#. For detai ls on co nfigur atio n,[...]

Epson Research and Development Page 13 Vancouver Des ign Center Interfacing to 8 -bit Processors S1D13708 Issue Date: 01/11/25 X39A-G-015-01 5 Software Test util ities a nd dis play driv ers ar e avai lable fo r the S1 D13708. Ful l source code is avai lab le for b o th th e tes t u tilit ies an d the d riv ers. The test ut ilit ies a re c on fig u[...]

Page 14 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to 8-bit Proce ssors X39A-G-015-01 Issue Date: 01/11/25 6 Ref erences 6.1 Documents • Epson Resear ch and Developme nt, Inc., S1D1370 8 Hardware Funct ional Speci ficati on , document number X39A-A-00 1-xx. • Epson Research a nd Devel opment, Inc., S5U13708B00 [...]

Epson Research and Development Page 15 Vancouver Des ign Center Interfacing to 8 -bit Processors S1D13708 Issue Date: 01/11/25 X39A-G-015-01 7 T echnical Suppor t 7.1 EPSO N LCD Contr o llers (S1D13708) Japan Seiko Epson Corporation Electronic Device s Marketing D ivision 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-55[...]

Page 16 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to 8-bit Proce ssors X39A-G-015-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

S1D13708 Embedded Memor y LCD Controller Interfacing to the Motor ola MC68VZ328 Dra gonball Micr oprocessor Document Number: X39A-G-016-0 1 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your ow[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Moto rola MC68VZ328 Dragonball Microprocesso r X39A-G-016-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Interfacing to the Motorola MC68VZ328 Dragonball Microprocess or S1D1 3708 Issue Date: 01/11/25 X39A-G-016-01 T able of Contents 1 Introducti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 In terfa cing to the M C6 8VZ3 28 . . . . . . . . . . . . [...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Moto rola MC68VZ328 Dragonball Microprocesso r X39A-G-016-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 5 Vancouver Des ign Center Interfacing to the Motorola MC68VZ328 Dragonball Microprocess or S1D1 3708 Issue Date: 01/11/25 X39A-G-016-01 List o f T ab le s Table 3-1: Host Bus Inte rface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4- 1: Summary of Power-On/Reset Configura tio[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Moto rola MC68VZ328 Dragonball Microprocesso r X39A-G-016-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 7 Vancouver Des ign Center Interfacing to the Motorola MC68VZ328 Dragonball Microprocess or S1D1 3708 Issue Date: 01/11/25 X39A-G-016-01 1 Introduction This appli cation no te des cribes t he hard ware and software environment requi red to interfa ce the S1D137 08 Embedded Memory LCD Controlle r and the Mot orola[...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Moto rola MC68VZ328 Dragonball Microprocesso r X39A-G-016-01 Issue Date: 01/11/25 2 Interfacing to the MC 68VZ328 2.1 The MC68VZ328 System Bus The Mo toro la MC6 8VZ 328 “ Drag onba ll VZ ” is th e thir d gen er ati on in t he Dra go nb all micropro cesso[...]

Epson Research and Development Page 9 Vancouver Des ign Center Interfacing to the Motorola MC68VZ328 Dragonball Microprocess or S1D1 3708 Issue Date: 01/11/25 X39A-G-016-01 3 S1D13708 Host Bus Interface The S1D1370 8 directl y support s multipl e proce ssors. The S 1D13708 impl ements a Dragonball Host Bus Interfa ce whic h directl y suppo rts the [...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Moto rola MC68VZ328 Dragonball Microprocesso r X39A-G-016-01 Issue Date: 01/11/25 3.2 Host Bus Interface Signals The Host Bus Inter face req uires the fo llowing si gnals . • CLKI is a cl ock input r equir ed by the S1 D13708 Host Bus I nter face as a sour[...]

Epson Research and Development Page 11 Vancouver Des ign Center Interfacing to the Motorola MC68VZ328 Dragonball Microprocess or S1D1 3708 Issue Date: 01/11/25 X39A-G-016-01 4 MC68VZ328 to S1D13708 Interfac e 4.1 Har dware Descr iption The inter fac e b etween t he S1D 13708 an d th e MC68VZ328 doe s not r equ ir es any e xte rn al glue logi c. Chi[...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Moto rola MC68VZ328 Dragonball Microprocesso r X39A-G-016-01 Issue Date: 01/11/25 4.2 S1D13708 Har dware Configuration The S1D13708 uses CNF7 thro ugh CNF0 to all ow select ion of the bus mode a nd other configur atio n data o n th e risi ng edge of RESET#. [...]

Epson Research and Development Page 13 Vancouver Des ign Center Interfacing to the Motorola MC68VZ328 Dragonball Microprocess or S1D1 3708 Issue Date: 01/11/25 X39A-G-016-01 4.2.1 Register /Memory Mapping The S1D13708 r e quir es two 1 28K byte s egmen ts in memor y for t he d is pla y buffe r a nd i ts internal regist ers. To a ccommodate this blo[...]

Page 14 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Moto rola MC68VZ328 Dragonball Microprocesso r X39A-G-016-01 Issue Date: 01/11/25 5 Softw are Test uti litie s and displ ay dri vers are availabl e for the S1D13708. F ull so urce code i s availa ble fo r both t he te st util ities and th e drivers . The tes[...]

Epson Research and Development Page 15 Vancouver Des ign Center Interfacing to the Motorola MC68VZ328 Dragonball Microprocess or S1D1 3708 Issue Date: 01/11/25 X39A-G-016-01 6 References 6.1 Do cu me nt s • Motorola Inc., MC68VZ328 DragonBal l-VZ® Int egrated Pr ocessor Us er’s Manual , Motorola Public ation no. MC683VZ2 8UM; avail able on the[...]

Page 16 Epson Research and Development Vancouver Des ign Center S1D13708 Interfacing to the Moto rola MC68VZ328 Dragonball Microprocesso r X39A-G-016-01 Issue Date: 01/11/25 7 T echnical Suppor t 7.1 EPSON LCD/CR T Contro l ler s (S1D13708) 7.2 Motor o la MC68VZ328 Pr ocessor • Motorola Design Line, ( 800) 521-62 74. • Local Motoro la sales off[...]

S1D13708 Embedded Memor y LCD Controller Interfacing to the Intel Str ongARM SA-1110 Micr opr ocessor Document Number: X39A-G-019-0 1 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your own use [...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the Intel StrongARM SA- 1110 Microproc esso r X39A-G-019-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Interfacing to the Intel StrongARM SA-1110 Micr oprocessor S1D13708 Issue Date: 01/11/25 X39A-G-019-01 T able of Contents 1 Introducti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfaci ng to the StrongARM SA-1110 Bus . . . . . . . . . . . .[...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the Intel StrongARM SA- 1110 Microproc esso r X39A-G-019-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 5 Vancouver Des ign Center Interfacing to the Intel StrongARM SA-1110 Micr oprocessor S1D13708 Issue Date: 01/11/25 X39A-G-019-01 List o f T ab le s Table 3-1: Host Bus Inte rface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4- 1: Summary of Power-On/Reset Configura tion Option[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the Intel StrongARM SA- 1110 Microproc esso r X39A-G-019-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 7 Vancouver Des ign Center Interfacing to the Intel StrongARM SA-1110 Micr oprocessor S1D13708 Issue Date: 01/11/25 X39A-G-019-01 1 Introduction This appli c ation n ote describes the hardware and software environment requi red to provide an inter face betwe en the S 1D13708 Embedded Memor y LCD Controll er an d [...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the Intel StrongARM SA- 1110 Microproc esso r X39A-G-019-01 Issue Date: 01/11/25 2 Interfacing to the Str ongARM SA-1110 Bus 2.1 The Str o ngARM SA-1110 System Bus The Stron gARM SA-1110 micr oprocess or is a highly i ntegrate d communica tions mic ro- control l[...]

Epson Research and Development Page 9 Vancouver Des ign Center Interfacing to the Intel StrongARM SA-1110 Micr oprocessor S1D13708 Issue Date: 01/11/25 X39A-G-019-01 2.1.3 V ariab le -La t enc y IO Access Cyc les The first nOE asserti on occurs two memor y cycles af ter the as sertion of chip sel ect (nCS3, nCS4, or nCS5). Two memory cy cl es pr io[...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the Intel StrongARM SA- 1110 Microproc esso r X39A-G-019-01 Issue Date: 01/11/25 Figure 2 -2: i llus tr ate s a t ypi cal va ri abl e- la tency IO a cc ess wri te cy cl e on t he S A-1110 bu s. Figure 2- 2: SA-11 10 Varia ble-Late ncy IO Wri te Cycle A[25:0] nC[...]

Epson Research and Development Page 11 Vancouver Des ign Center Interfacing to the Intel StrongARM SA-1110 Micr oprocessor S1D13708 Issue Date: 01/11/25 X39A-G-019-01 3 S1D13708 Host Bus Interface The S1D1370 8 di rec tl y s uppo rt s mul tipl e pr oce sso rs . The S 1D13708 impl emen ts a 16 -bi t Gen eric # 2 Hos t Bus Inte rf ace whic h is m ost[...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the Intel StrongARM SA- 1110 Microproc esso r X39A-G-019-01 Issue Date: 01/11/25 3.2 Host Bus Interface Signal Descri ptions The S1D13708 Ge neric #2 Host Bus I nterface requi res the f ollowing s ignal s. • CLKI is a clo ck input whi ch is requ ired by th e [...]

Epson Research and Development Page 13 Vancouver Des ign Center Interfacing to the Intel StrongARM SA-1110 Micr oprocessor S1D13708 Issue Date: 01/11/25 X39A-G-019-01 4 Str ongARM SA-1110 to S1D13708 Interface 4.1 Har dware Descr iption The SA-1110 micropr ocess or pro vid es a varia ble lat enc y I/O in ter f ace that can be use d to support an ex[...]

Page 14 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the Intel StrongARM SA- 1110 Microproc esso r X39A-G-019-01 Issue Date: 01/11/25 4.2 S1D13708 Har dware Configuration The S1D13708 uses CNF7 thro ugh CNF0 to all ow select ion of the bus mode a nd other configur atio n data o n th e risi ng edge of RESET#. For [...]

Epson Research and Development Page 15 Vancouver Des ign Center Interfacing to the Intel StrongARM SA-1110 Micr oprocessor S1D13708 Issue Date: 01/11/25 X39A-G-019-01 4.3 Str ongARM SA-1110 Register Configuration The SA-1 110 r equ ir es c onfig ura ti on o f s eve ral of its in t ern al re gi ste rs to in ter face to the S1D 1370 8 G e ner ic #2 H[...]

Page 16 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the Intel StrongARM SA- 1110 Microproc esso r X39A-G-019-01 Issue Date: 01/11/25 4.4 Register/Memory Mapping The S1D1 3708 is a memor y-ma pped devic e. The SA-1110 u ses t he memory as si gned to a chip sel ect (nCS4 i n this ex ample) t o map the S1D13 708 in[...]

Epson Research and Development Page 17 Vancouver Des ign Center Interfacing to the Intel StrongARM SA-1110 Micr oprocessor S1D13708 Issue Date: 01/11/25 X39A-G-019-01 5 Software Test util ities a nd dis play driv ers ar e avai lable fo r the S1 D13708. Ful l source code is avai lab le for b o th th e tes t u tilit ies an d the d riv ers. The test u[...]

Page 18 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the Intel StrongARM SA- 1110 Microproc esso r X39A-G-019-01 Issue Date: 01/11/25 6 Ref erences 6.1 Documents • Intel Corpor ation, Strong ARM® SA-1110 Micropr ocessor Adv anced Devel oper’s Manual, Order Number 278240- 001. • Epson Resear ch and Developm[...]

Epson Research and Development Page 19 Vancouver Des ign Center Interfacing to the Intel StrongARM SA-1110 Micr oprocessor S1D13708 Issue Date: 01/11/25 X39A-G-019-01 7 T echnical Suppor t 7.1 EPSO N LCD Contr o llers (S1D13708) 7.2 Intel Str ongARM SA-1110 Pr ocessor Japan Seiko Epson Corporation Electronic Device s Marketing D ivision 421-8, Hino[...]

Page 20 Epson Research and Development Vancouver Des ign Center S1D13708 Interfac ing to the Intel StrongARM SA- 1110 Microproc esso r X39A-G-019-01 Issue Date: 01/11/25 THIS P AGE LEF T BLANK[...]

S1D13708 Embedded Memor y LCD Controller Connecting to a Micr o- Contr oller via the Indirect Interface Docu ment Numb er: X39 A-G -020 -01 Copyright © 2001 Epson Research and De v elopment, Inc. All Rights Reserved. Inf ormation in this document is subject to change without notice . Y ou m ay downl oad and use this document, but only f or your ow[...]

Page 2 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to a Micro-Controller via the Indirect I nterface X39A-G-020-01 Issue Date: 01/12/12 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 3 Vancouver Des ign Center Connecting to a Mic ro-Controller via the I ndirect Interface S1D13708 Issue Date: 01/12/12 X39A-G-020-01 T able of Contents 1 Introducti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 In terfa cing to a Mi cro- Con troll er . . . . . . . . . . . [...]

Page 4 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to a Micro-Controller via the Indirect I nterface X39A-G-020-01 Issue Date: 01/12/12 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 5 Vancouver Des ign Center Connecting to a Mic ro-Controller via the I ndirect Interface S1D13708 Issue Date: 01/12/12 X39A-G-020-01 List o f T ab le s Table 3- 1: Mode 68 8-Bit Data Host Bus Interfac e Pin Mapping . . . . . . . . . . . . . . . . . . . . 9 Table 3- 2: Mode 68 16-Bit Data Host Bus Interface Pi n M[...]

Page 6 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to a Micro-Controller via the Indirect I nterface X39A-G-020-01 Issue Date: 01/12/12 THIS P AGE LEF T BLANK[...]

Epson Research and Development Page 7 Vancouver Des ign Center Connecting to a Mic ro-Controller via the I ndirect Interface S1D13708 Issue Date: 01/12/12 X39A-G-020-01 1 Introductio n This applic ation not e describe s the hardwar e and software routine s required to interf ace the S1D13708 Embedded Memory LCD Co ntrolle r to a micr o-control ler [...]

Page 8 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to a Micro-Controller via the Indirect I nterface X39A-G-020-01 Issue Date: 01/12/12 2 Interfacing to a Micr o-Contr oller 2.1 The Indir ect Interfa ce Although t he S1D137 08 dire ctly supp orts v arious CPU in terf aces, the I ndire ct Inter face allows micro -cont[...]

Epson Research and Development Page 9 Vancouver Des ign Center Connecting to a Mic ro-Controller via the I ndirect Interface S1D13708 Issue Date: 01/12/12 X39A-G-020-01 3 S1D13708 Host Bus Interface The S1D1370 8 directl y support s many micr oprocess or buss es, of wh ich two are Indir ect Interfa ce modes, Mode 68 and Mode 80. Bot h modes can be [...]

Page 10 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to a Micro-Controller via the Indirect I nterface X39A-G-020-01 Issue Date: 01/12/12 Table 3- 2: Mode 68 16- Bit Data Host Bus Inte rface Pin Map ping S1D1370 8 Pin Names connect t o V ss AB[16:0] connec t to V ss DB[15:0] D[15:0] CS# Chip Select M/R# A0 CLKI BUSCLK[...]

Epson Research and Development Page 11 Vancouver Des ign Center Connecting to a Mic ro-Controller via the I ndirect Interface S1D13708 Issue Date: 01/12/12 X39A-G-020-01 Table 3-4: Mode 80 16-Bi t Data Host Bus Interf ace Pi n Mapping S1D137 08 Pin Names connect to V ss AB[16:0] connec t to V ss DB[15:0] D[7:0] CS# Chip Select M/R# A0 CLKI BUSCLK R[...]

Page 12 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to a Micro-Controller via the Indirect I nterface X39A-G-020-01 Issue Date: 01/12/12 3.2 Host Bus Interface Signals The S1D13708 Indirec t Interface mode 68 and 80 host bus int erface requires the following signals from a micro-c ontroll er. • CLKI is a clo ck inp[...]

Epson Research and Development Page 13 Vancouver Des ign Center Connecting to a Mic ro-Controller via the I ndirect Interface S1D13708 Issue Date: 01/12/12 X39A-G-020-01 4 Micro-Contr oller to S1D1 3708 Interface 4.1 Har dware Connect ions The inter face betwe en the S1D 13708 an d a micro-c ontrol ler requ ires no exte rnal l ogic i f there are en[...]

Page 14 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to a Micro-Controller via the Indirect I nterface X39A-G-020-01 Issue Date: 01/12/12 4.2 S1D13708 Har dware Configuration The S1D13708 uses CNF7 thro ugh CNF0 to all ow select ion of the bus mode a nd other configur atio n data o n th e risi ng edge of RESET#. For d[...]

Epson Research and Development Page 15 Vancouver Des ign Center Connecting to a Mic ro-Controller via the I ndirect Interface S1D13708 Issue Date: 01/12/12 X39A-G-020-01 4.3 Register/Memory Mapping When the S1D13708 is in Indir ect mode it is not a memory mapped device . It uses the protocol of fi rs t placi ng t he regis te r a ddress on the data [...]

Page 16 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to a Micro-Controller via the Indirect I nterface X39A-G-020-01 Issue Date: 01/12/12 5 So ftware To im p lem e nt th e bus cyc l e s in soft w are , refe r t o th e S1D13708 Hardwar e Functiona l Specifi cati on , document numbe r X39A-A-001- xx, for the bus timing [...]

Epson Research and Development Page 17 Vancouver Des ign Center Connecting to a Mic ro-Controller via the I ndirect Interface S1D13708 Issue Date: 01/12/12 X39A-G-020-01 The foll owin g is a C impl em entat ion of th e bus cyc les : // these are the simplified mode 68 bus cycles to m imic on the PIC general IO pins #define CommandWriteStep1 0b10010[...]

Page 18 Epson Research and Development Vancouver Des ign Center S1D13708 Connecting to a Micro-Controller via the Indirect I nterface X39A-G-020-01 Issue Date: 01/12/12 6 Ref erences 6.1 Documents • Epson Resear ch and Developme nt, Inc., S1D1370 8 Hardware Funct ional Speci ficati on , document number X39A-A-00 1-xx. • Epson Researc h and Deve[...]

Epson Research and Development Page 19 Vancouver Des ign Center Connecting to a Mic ro-Controller via the I ndirect Interface S1D13708 Issue Date: 01/12/12 X39A-G-020-01 7 T echnical Suppor t 7.1 EPSO N LCD Contr o llers (S1D13708) Japan Seiko Epson Corporation Electronic Device s Marketing D ivision 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel:[...]

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