Freescale Semiconductor MCF5481 Bedienungsanleitung

MCF548x Ref erence Man ual Devices Supported: MCF5485 MCF5482 MCF5484 MCF5481 MCF5483 MCF5480 Document Number : MCF5485RM Re v . 3 01/2006[...]

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Ov er vie w Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMA C) Memor y Management Unit (MMU) Floating-P oint Unit (FPU) Deb ug Suppor t System Integr ation Unit (SIU) Local Memor y Edge P or t Module (EPOR T) Inde x Interrupt Controller (INTC) 20 General Pur pose I/O (GPIO) 14 13 15 PCI Bus Arbiter (PCIARB) 2 3 5 6 7 8 9 4 [...]

Ov er view Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMA C) Memor y Management Unit (MMU) Floating-P oint Unit (FPU) Deb ug Suppor t System Integr ation Unit (SIU) Local Memor y Edge P or t Module (EPOR T) Inde x Interrupt Controller (INTC) 20 General Pur pose I/O (GPIO) 14 13 15 PCI Bus Arbiter (PCIARB) 2 3 5 6 7 8 9 4 G[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor v Content s P aragraph Number Title Pag e Number Chapter 1 Overview 1.1 MCF548x Family Overview ........................................................................................... 1-1 1.2 MCF548x Block Diag ram .......................................................................[...]

MCF548x Refere nce Manual, Rev . 3 vi F reescale Semiconductor Content s P aragraph Number Title Pag e Number 2.2.1.4 Read/Write (R/ W ) ................................................................................................. 2-17 2.2.1.5 Transfer Burst (TBST ) ...............................................................................[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor vii Content s P aragraph Number Title Pag e Number 2.2.5.1 Reset In (RSTI ) ..................................................................................................... 2-22 2.2.5.2 Reset Out (RST O ) ................................................................................[...]

MCF548x Refere nce Manual, Rev . 3 viii F reescale Semiconductor Content s P aragraph Number Title Pag e Number 2.2.11 I 2 C I/O Signals .......................................................................................................... 2-27 2.2.11.1 Serial Clock (S CL) ........................................................................[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor ix Content s P aragraph Number Title Pag e Number Chapter 3 ColdFire Core 3.1 Core Overview .............................................................................................................. .. 3-1 3.2 Features ...................................................................[...]

MCF548x Refere nce Manual, Rev . 3 x F reescale Semiconductor Content s P aragraph Number Title Pag e Number 3.7.4 Miscellaneous Instruction Execution Timi ng ........................................................... 3-32 3.7.5 Branch Instruction Ex ecution Timing ....................................................................... 3-33 3.7.6 [...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xi Content s P aragraph Number Title Pag e Number 5.2.3.9 Changes to ACRs and CACR ................................................................................. 5-5 5.2.3.10 ACR Address Impr ovements .................................................................................. 5-6[...]

MCF548x Refere nce Manual, Rev . 3 xii F reescale Semiconductor Content s P aragraph Number Title Pag e Number 6.2.3.5 Denormalized Nu mbers .......................................................................................... 6-5 6.3 Register Defi nition .........................................................................................[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xiii Content s P aragraph Number Title Pag e Number 7.8.1 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified ......................... 7-8 7.8.2 The Cache at Star t-Up ................................................................................................. 7-8 7.9 Ca[...]

MCF548x Refere nce Manual, Rev . 3 xiv F reescale Semiconductor Content s P aragraph Number Title Pag e Number 8.4.5 Address Attribute Trigger Re gisters (AATR, AATR1) ............................................ 8-16 8.4.6 Trigger Definition Regi ster (TDR) ........................................................................... 8-17 8.4.7 Prog[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xv Content s P aragraph Number Title Pag e Number 9.3.1.4 JTAG Device Identification Number (JTAGID) .................................................... 9-5 Chapter 10 Internal Clocks and Bus Architecture 10.1 Introducti on .................................................................[...]

MCF548x Refere nce Manual, Rev . 3 xvi F reescale Semiconductor Content s P aragraph Number Title Pag e Number 11.1.1 Overview ................................................................................................................ ... 11-1 11.1.2 Modes of Operat ion ..........................................................................[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xvii Content s P aragraph Number Title Pag e Number Chapter 14 Edge Port Module (EPORT) 14.1 Introducti on .............................................................................................................. ..... 14-1 14.2 Interrupt/General-Purpose I/O Pin Descripti ons ........[...]

MCF548x Refere nce Manual, Rev . 3 xviii F reescale Semiconductor Content s P aragraph Number Title Pag e Number 15.4 Functional Descri ption ................................................................................................ 15-3 2 15.4.1 Overview ........................................................................................[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xix Content s P aragraph Number Title Pag e Number 17.5.1.2 Global Chip-Select Operation ............................................................................... 17-6 17.5.2 Chip-Select Registers .......................................................................................[...]

MCF548x Refere nce Manual, Rev . 3 xx F reescale Semiconductor Content s P aragraph Number Title Pag e Number 18.3.13 SDR SDRAM Data Strobe (SDRDQS) .................................................................... 18-4 18.3.14 SDRAM Memory Supply (SDVDD) ........................................................................ 18-4 18.3.15 SDRAM[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xxi Content s P aragraph Number Title Pag e Number 18.8.9 Perform Two Refres h Cycles .................................................................................. 18-31 18.8.10 Clear the Reset DLL Bit in the Mode Regist er ...................................................... 18-32 [...]

MCF548x Refere nce Manual, Rev . 3 xxii F reescale Semiconductor Content s P aragraph Number Title Pag e Number 19.3.2.2 Target Base Address Translati on Register 0 (PCITBATR0) ............................. 19-15 19.3.2.3 Target Base Address Translati on Register 1 (PCITBATR1) ............................. 19-16 19.3.2.4 Target Control Regist er (P[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xxiii Content s P aragraph Number Title Pag e Number 19.4.6.6 PCI Commands ................................................................................................... 19-69 19.4.6.7 FIFO Considerat ions ........................................... ...................................[...]

MCF548x Refere nce Manual, Rev . 3 xxiv F reescale Semiconductor Content s P aragraph Number Title Pag e Number 20.6 Interrupts ................................................................................................................ ..... 20-10 Chapter 21 FlexCAN 21.1 Introducti on ...........................................................[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xxv Content s P aragraph Number Title Pag e Number 21.4.7 CAN Protocol Relate d Frames ............................................................................... 21-27 21.4.7.1 Remote Frames ..............................................................................................[...]

MCF548x Refere nce Manual, Rev . 3 xxvi F reescale Semiconductor Content s P aragraph Number Title Pag e Number 22.6.4.8 Master Error Address Register (MEAR) ............................................................ 22-18 22.7 Channels ...............................................................................................................[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xxvii Content s P aragraph Number Title Pag e Number 22.13.1.2 Descriptor Length and Pointer Fields ................................................................. 22-60 22.13.1.3 Null Fiel ds ...............................................................................................[...]

MCF548x Refere nce Manual, Rev . 3 xxviii F reescale Semiconductor Content s P aragraph Number Title Pag e Number 23.2.1.3 Test Mode Select/B reakpoint (TMS/BKP T ) ........................................................ 23-3 23.2.1.4 Test Data Input/Development Se rial Input (TDI/DSI) ......................................... 23-3 23.2.1.5 Test R[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xxix Content s P aragraph Number Title Pag e Number 24.2.1 DREQ [1:0] ............................................................................................................... 24-3 24.2.2 D ACK [1:0] ....................................................................................[...]

MCF548x Refere nce Manual, Rev . 3 xxx F reescale Semiconductor Content s P aragraph Number Title Pag e Number 24.4.8.1 LURC Features ................................................................................................... 24-25 24.4.9 Line Buffers ..........................................................................................[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xxxi Content s P aragraph Number Title Pag e Number 26.1.1 Block Diagra m .......................................................................................................... 2 6-1 26.1.2 Overview .......................................................................................[...]

MCF548x Refere nce Manual, Rev . 3 xxxii F reescale Semiconductor Content s P aragraph Number Title Pag e Number 26.3.3.28 Rx and Tx FIFO Last Read Frame Pointer (PSCRLRFPn, PSCTLRFPn) ......... 26-33 26.3.3.29 Rx and Tx FIFO Last Write Fram e Pointer (PSCRLWFPn, PSCTLWFPn) ...... 26-34 26.4 Functional Descri ption .................................[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xxxiii Content s P aragraph Number Title Pag e Number 26.7.2.5 SIR Mode ............................................................................................................ 26 -52 26.7.2.6 MIR Mode ....................................................................................[...]

MCF548x Refere nce Manual, Rev . 3 xxxiv F reescale Semiconductor Content s P aragraph Number Title Pag e Number 27.7.2.4 Tx FIFO Buffering Mechanism .......................................................................... 27-21 27.7.2.5 Rx FIFO Buffering Mechanism .......................................................................... 27-22 2[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xxxv Content s P aragraph Number Title Pag e Number 28.3.2.1 I 2 C Address Register (I2ADR) ............................................................................. 28-3 28.3.2.2 I 2 C Frequency Divider Regi ster (I2FDR) ............................................................ 28-[...]

MCF548x Refere nce Manual, Rev . 3 xxxvi F reescale Semiconductor Content s P aragraph Number Title Pag e Number 29.2.2.3 USB Descriptor RAM Control Register (DRAMCR) ........................................ 29-12 29.2.2.4 USB Descriptor RAM Data Register (DRAMDR) ............................................ 29-13 29.2.2.5 USB Interrupt Status Regi[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xxxvii Content s P aragraph Number Title Pag e Number 29.2.5.6 USB Endpoint n FIFO Status Register (EPnFSR) ............................................. 29-40 29.2.5.7 USB Endpoint n FIFO Control Register (EPnFCR) ........................................... 29-42 29.2.5.8 USB Endpoint n F[...]

MCF548x Refere nce Manual, Rev . 3 xxxviii F reescale Semiconductor Content s P aragraph Number Title Pag e Number 30.1.5.4 Internal Loopb ack ................................................................................................. 30-4 30.2 External Si gnals .................................................................................[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xxxix Content s P aragraph Number Title Pag e Number 30.3.3.24 FEC Receive FIFO Read Poin ter Register (FECRFRP) ..................................... 30-32 30.3.3.25 FEC Receive FIFO Write Poin ter Register (FECRFWP) ................................... 30-33 30.3.3.26 FEC Transmit FIFO Da[...]

MCF548x Refere nce Manual, Rev . 3 xl F reescale Semiconductor Content s P aragraph Number Title Pag e Number 31.3.2 MCF5483/5482 Mechanical Diagram .................................................................... 31-12 31.4 MCF5481/5480 Mechanical Diagram ........................................................................ 31-16 31.5 Mecha[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xli About This Book The primary objective of this reference manual is to define the functionality of the MCF548x processors for use by software and hardware developers. The information in this book is subjec t to change without notic e, as described in the disclaimers on the title page of [...]

MCF548x Refere nce Manual, Rev . 3 xlii F reescale Semiconductor — Chapter 7, “Local Memory,” describes the MCF548x implemen tation of the ColdFire V4e local memory specification. — Chapter 8, “Debug Support,” describes the Revision C enhanc ed hardware debug support in the MCF548x. This revision of the ColdFire debug architecture encom[...]

Suggested Reading MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xliii — Chapter 21, “FlexCAN,” describes the MCF548 implementation of the controller area network (CAN) protocol. This chapter describe s FlexCAN module operation and provides a programming model. — Chapter 22, “Integrated Security Engine (SEC),” provides an o[...]

MCF548x Refere nce Manual, Rev . 3 xliv F reescale Semiconductor General Inf ormation The following documentation provides useful information about the Cold Fire architecture and computer architecture in general: • ColdFir e Pr ogrammers Refer ence Manual (CFPRM) • Using Micr oprocessors and Micr ocomputers: The Motor ola Family , W illiam C. W[...]

Acr ony ms and Abbre viati ons MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xlv longword A 32-bit data unit x In some contexts, such as signal encodings, x indicates a don’ t care. n Used to express an undefined numerical value ¬ NOT logical operator & AND logical operator | OR logical operator Register Con ventions This refer[...]

MCF548x Refere nce Manual, Rev . 3 xlvi F reescale Semiconductor EA Eff ective address EDO Extended data output (DRAM) FIFO First-in, first-out GPIO General-purp ose I/O I 2 C I nter-integrated circuit IEEE Institute for Electrical and El ectronics Engineers IFP Instruction fetch pipeline IPL Interrupt pr iority lev el JEDEC Joint Electron Device E[...]

T erminology and Notational Conventions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xlvii T erminology and Notational Con ventions Ta b l e i i i shows notational conventions used throughout this document. U ART Universal asynchronous/synchronous receiver transmitter XLB bus Inter nal 64-bit bus Table iii. Notational Con ventions In[...]

MCF548x Refere nce Manual, Rev . 3 xlviii F reescale Semiconductor <ea>y ,<ea>x Source and destination effective addresses, respectiv ely <label> Assembly language program label <list> List of registers for MO VEM instr uction (example: D3–D0) <shift> Shift operation: shift left (<<), shift right (>>) <[...]

T erminology and Notational Conventions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor xlix Address Calculated eff ectiv e address (pointer) Bit Bit selection (example: Bit 3 of D0) lsb Least significant bit (example: lsb of D0) LSB Least significant byte LSW Least significant word msb Most significant bit MSB Most significant byte MSW[...]

MCF548x Refere nce Manual, Rev . 3 l F reescale Semiconductor T ab le 2-1/2- 3 Add column to indicate whether the signal has a pull-up resistor . These signals hav e a pull-up resistor at all times: DSCLK/TRST , BKPT/TMS, DSI/TDI These signals hav e a pull-up resistor whenev er configured for general-purpose input (default state after reset): PCIBR[...]

T erminology and Notational Conventions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor li 2.2.6.1/2-22 Add the follo wing after T able 2-4: Figure 1 correlates CLKIN, inter nal bus, and core clock frequencies f or the 1x–4x multipliers. Figure 1. CLKIN, Internal Bus, an d Core Clock Ratios 3.8.1/ 3-38 Change the second sentence of th[...]

MCF548x Refere nce Manual, Rev . 3 lii F reescale Semiconductor 10.2/10-5 Inser t the following section bef o re section 10.2 “XL Bus Arbiter”. 10.2 PLL 10.2.1 PLL Memory Map/ Register Descriptions 10.2.2 System PLL Contr ol Register (SPCR) The system PLL control register (SPCR) defi nes the cloc k enables used to control clocks to a set of per[...]

T erminology and Notational Conventions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor liii T able 10-3/10-5 Bits BA, DT , and A T: The 0 and 1 are switched. Setting each bit ena bles operation, while clearing di sables operation. The 0 and 1 (or the correspond ing descriptions) need to be swapped f or al l three bits. 11.4.2/11-8 Remo[...]

MCF548x Refere nce Manual, Rev . 3 liv F reescale Semiconductor 21.4.9/2 1-28 Add the follo wing table below the note at the end of the section and corre ct the cross-ref erence pointing to it: T able 23-5/23-7 The JT AG IR codes are incorrect. Replace table with the f ollowing: 23.4.3/23-7 Remov e the TEST_LEAKA GE section, as the instruction is n[...]

T erminology and Notational Conventions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor lv 25.1.2/25-2 Add the following section after section 24.1.2: 24.1.3 Comm Timer External Clock[7:0] The comm timer e xter nal clock is the altern ate clock signal and is pro vided by the user . The user must write a 1 to CTCR[S] in the variable chan[...]

MCF548x Refere nce Manual, Rev . 3 lvi F reescale Semiconductor 27.6.1/27-5 Remov e instances of MDIS bit as it is not present on this v ersion of the DSPI. T able 29-3/29-11 USBCR[APPLOCK] bit description, th e bit setting numbers are incorrrect . When cleared (0 ), APPLOCK is deasser ted. When set (1), APPLOCK is asser t ed. T able 29-29/29-30 En[...]

T erminology and Notational Conventions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor lvii Figure 31-3/Page 31-10 Remov e overbar from ALE at location AD6. Figure 31-7/Page 31-14 Remov e overbar from ALE at location AD6. Figure 31-11/Page 31-18 Remov e overbar from ALE at location AD6. Table iv. MCF548 x Revision History (cont inued) [...]

MCF548x Refere nce Manual, Rev . 3 lviii F reescale Semiconductor[...]

MCF548x Reference Manual, Rev . 3 F reescale Semiconductor 1-1 Chapter 1 Overview This chapter provides an overview of the MCF548 x microprocessor features , including the major functional components. 1.1 MCF548 x F amily Overview The MCF548 x family is based on the ColdFire V4e core, a complex which compr ises the ColdFire V4 central processor uni[...]

MCF548x Reference Manual, Rev . 3 1-2 F reescale Semiconductor W ith on-chip support for multiple co mmon communications interfaces, MCF548 x products require only the addition of memories and certain physical layer transceivers to be cost-ef fective system solutions for many applications. Such applicatio ns include industrial routers, high-end POS[...]

MCF548x Family Pr oducts MCF548x Reference Manual, Rev . 3 F reescale Semiconductor 1-3 1.3 MCF548 x F amily Pr oducts Ta b l e 1 - 1 summarizes the products ava ilable within the MCF548 x product family . All products are available in pin-compatible, 388- pin PBGA packaging allowing for ea se of migrati on between products within the family . A pr[...]

MCF548x Reference Manual, Rev . 3 1-4 F reescale Semiconductor — Memory management unit (MMU) – Separate, 32-entry , fully-associative instru ction and data transl ation lookahead buf fers — Floating point unit (FPU) – Double-precision support that c onforms to IEEE-754 standard – Eight floating point registers • Internal master bus (XL[...]

MCF548x Family Features MCF548x Reference Manual, Rev . 3 F reescale Semiconductor 1-5 — Execution units for the following: – DES/3DES block cipher – AES block cipher – RC4 stream cipher – MD5/SHA-1/SHA-256/HMAC hashing – Random number generator compliant with FIPS 140-1 standard s for randomness and non-determinism — Dual-channel arc[...]

MCF548x Reference Manual, Rev . 3 1-6 F reescale Semiconductor The ColdFire V4e processor contai ns a double-precision floating point unit (FPU). The FPU conforms to the American National S tandards Inst itute (ANSI)/Institute of Electrical and Electr onics Engineers (IEEE) S tandard for Binary Floating-Point Arithmetic (ANSI/IEEE S tandard 754). T[...]

MCF548x Family Features MCF548x Reference Manual, Rev . 3 F reescale Semiconductor 1-7 boundary-scan register , and a 32-bit ID register). The boundary scan regi ster links the device’ s pins into one shift register . T est logic, implemented using stat ic logic design, is independe nt of the device system logic. The MCF548 x implementation can d[...]

MCF548x Reference Manual, Rev . 3 1-8 F reescale Semiconductor 1.4.6 Comm unications I/O Subsystem 1.4.6.1 DMA Controller The communications subsystem contains an intelligent DMA unit that provides front line interrupt control and data movement interface via a separate peripheral bus to the on-ch ip peripheral functions, leaving the processor core [...]

MCF548x Family Features MCF548x Reference Manual, Rev . 3 F reescale Semiconductor 1-9 • 4 Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint descriptor RAM 1.4.6.4 Programmab le Seri al Controller s (PSCs) The MCF548 x product family supports four PSC s that can be independently co nfigured to operate in the following modes: • Universa[...]

MCF548x Reference Manual, Rev . 3 1-10 F reescale Semiconductor • DMA support 1.4.6.7 Controller Area Netw o rk (CAN) The FlexCAN modules are communication controll ers implementing the C AN protocol. The CAN protocol can be used as an industr ial control serial data bus, meeting the specific requireme nts of real-time processing and reliable ope[...]

MCF548x Family Features MCF548x Reference Manual, Rev . 3 F reescale Semiconductor 1-11 frequency from 33–66 MHz. The Flexbus is targeted to support extern al Flash memories, boot ROMs, gate-array logic, or othe r simple tar get interfaces. Up to six chip selects are supported by the FlexBus. Possible combinations of address and data bits are the[...]

MCF548x Reference Manual, Rev . 3 1-12 F reescale Semiconductor 1.4.11.2 Interrupt Controller The interrupt cont roller on the MCF548 x family can support up to 63 interrupt sources. The interrupt controller is organized as seven levels with nine inte rrupt sources per level. Ea ch interrupt source has a unique interrupt vector , and 56 of th e 63 [...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-1 Chapter 2 Signal Descriptions 2.1 Intr oduction This chapter describes the MCF548 x signals . NO TE The terms ‘assertion’ and ‘negation’ are used to avoid confusion when dealing with a mixture of active-lo w and active-high signals. The term ‘asserted’ indicates that a sign[...]

MCF548x Refere nce Manual, Rev . 3 2-2 F reescale Semiconductor Figure 2 -1. MCF5 48 x Signals MCF548x E0MDIO / PFECI2C3 E0CRS / PFEC0H0 E0TXD[3:1] / PFEC0L[7:5] E0TXER / PFEC0L4 E0RXD[3: 1] / PFE C0L[3:1] E0RXER / PFEC0L0 E1MDIO / SDA / CANRX0 E1MDC / SCL / CANTX0 E1 TXCLK / PFEC1H7 E1 TXEN / PFEC1H6 E1 TXD0 / PFEC1H5 E1COL / PFEC1H4 E1RXCLK / PFE[...]

Introduction MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-3 Ta b l e 2 - 1 lists the signals for the MCF548 x in functional group order . T able 2-1. MCF548 x Signal Descr iption PBGA Pin Pin Functions Description I/O Pull-up Drive Reset State Primary GPIO Secondary Te r t i a r y FlexBus AE2, AF3, AF1, AE3, AE4, AD5, AF2, AD4 AD[3[...]

MCF548x Refere nce Manual, Rev . 3 2-4 F reescale Semiconductor M2, M3 SDBA[1:0] — — — SDRAM bank addresses O2 4 L o w E3 RAS — — — SDRAM row address strobe O2 4 H i g h C2 CAS — — — S DRAM column address strobe O2 4 H i g h R2, P2, P1, N3 SDCS [3:0 ] — — — SDRAM chip selects O 24 High B8, A3, G3, J2 SDDM[3:0] — — — SD[...]

Introduction MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-5 D24 PCIIRD Y —— — PCI initiator ready I/O 16 Hi-Z F23 PCIP AR — — — PCI parity I/O 16 Hi-Z D26 PCIPERR —— — PCI parity error I/O 16 Hi-Z G23 PCIRESET —— — PCI reset O 16 Low F24 PCISERR —— — PCI system error I/O 16 Hi-Z E25 PCIST OP —— —[...]

MCF548x Refere nce Manual, Rev . 3 2-6 F reescale Semiconductor AD8, AC6, AF7 E0TXD[3:1] PFEC0L[7:5] — — MA C transmit data O:I/O 8 GPI AE9 E0TXER PFEC0L4 — — MAC tr ansmit error O:I/O 8 GPI AF11, AF12, AF13 E0RXD[3:1] PFEC0L[3:1] — — MA C receive data I:I/O 8 GPI AC1 4 E0RXER PFEC0L0 — — MAC receiv e error I:I/O 8 GPI Ethernet MA C[...]

Introduction MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-7 AC2 4 DSPISIN PDSPI1 PSC3RXD — QSPI data in I:I/O 24 GPI AD22 DSPISCK PDSPI2 PSC3CTS PSC3BCLK QSPI cloc k I/O 24 GPI W23 DSPICS5 / PCSS PDSPI6 — — QSPI chip select O:I/O 24 GPI V23 DSPICS3 PDSPI5 TO U T 3 CANTX1 QSPI chip select O:I/O 24 GPI AA26 DSPICS2 PDSPI4 TO U [...]

MCF548x Refere nce Manual, Rev . 3 2-8 F reescale Semiconductor Timer Module AD19 TIN3 PTIM7 IRQ3 CANRX1 Timer input I:I/O 8 GPI AD23 TO U T 3 PTIM6 CANTX1 — Timer output O:I/O 8 GPI AF21 TIN2 PTIM5 IRQ2 CANRX1 Timer input I:I/O 8 GPI AC2 2 TO U T 2 PTIM4 CANTX1 — Timer output O:I/ O 8 GPI AE20 TIN1 — — — Timer input I 8 GPI AC2 3 TO U T [...]

Introduction MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-9 P ower Supplies C16, C22, E24, H24, M24, R3, U24, Y3, AA24, AB3, AD7, AD10, AD18 EVDD — — — P ositive I/O supply I — — C18, D11, D12, D19, D22, H4, H23, L23, P4, R23, V4, AA23, AC 1 2, A C 20 IVDD — — — P ositiv e core supply I — — A2, B2, C3, C17, C19,[...]

MCF548x Refere nce Manual, Rev . 3 2-10 F reescale Semiconductor Ta b l e 2 - 2 lists the MCF548 x signals in pin number orde r for the 388 PBGA package. AD16 4 USB_PLL VDD — — — USB PLL supply AE18 4 USBVDD — — — USB supply 1 Pull-up resistor when configu red f or general purp ose input (def ault state after reset). 2 This pin is a “[...]

Introduction MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-11 A21 PSTDD A T A1 — — — R13 VSS — — — A22 PSTDD A T A3 — — — R14 VSS — — — A23 PSTDD A T A7 — — — R15 VSS — — — A24 PCIBR0 PPCIBR0 TIN0 — R16 VSS — — — A25 PCIBR2 PPCIBR2 TIN2 — R23 IVDD — — — A26 1 E1RXD1 PFEC1L5 — —[...]

MCF548x Refere nce Manual, Rev . 3 2-12 F reescale Semiconductor B26 1 E1RXD2 PFEC1L2 — —V 2 A D 2 — — — C1 SD VDD — —— V 3 A D 4 — — — C2 CAS — —— V 4 I V D D — — — C3 VSS — — — V23 DSPICS3 PDSPI5 TOUT3 CANTX1 C4 SDD A T A17 — — — V24 PCIBG1 PPC IBG1 TOUT1 — C5 SDD A T A19 — — — V25 PCIAD31 —[...]

Introduction MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-13 D5 SDD A T A28 — — — AB1 AD12 — — — D6 VSS — — — AB2 AD15 — — — D7 SD ADDR2 — — — AB3 EVDD — — — D8 SD ADDR6 — — — AB4 VSS — — — D9 VSS — — — AB23 PSC3RTS PPSC3PSC26 PSC3FSYNC — D10 SD ADDR10 — — — AB24 D A CK0[...]

MCF548x Refere nce Manual, Rev . 3 2-14 F reescale Semiconductor F2 SDDQS1 — — — AC 24 DSPISIN PDSPI1 PSC3RXD — F3 SD VDD — —— A C 2 5 D A C K 1 PDMA3 T OUT1 — F4 VSS — — — AC26 PSC2TXD PPSC3PSC20 — — F23 PCIP AR — —— A D 1 A D 1 6 — — — F24 PCISERR — —— A D 2 A D 2 1 — — — F25 PCIFRM — —— A D[...]

Introduction MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-15 K1 SD WE — — — AE3 AD28 — — — K2 SDD A T A0 — — — AE4 AD27 — — — K3 SDD A T A1 — — — AE5 R/W PFBCTL2 TBST — K4 SDD A T A11 — — — AE6 OE PFBCTL3 — — K23 PCIAD0 — FBADDR0 — AE7 BE/BWE0 PFBCTL4 FBADDR0 — K24 PCIAD6 — F BADDR6[...]

MCF548x Refere nce Manual, Rev . 3 2-16 F reescale Semiconductor 2.2 MCF548 x External Signals 2.2.1 FlexBus Signals 2.2.1.1 Address/Data Bus (AD[31:0]) The AD[31:0] bus carries address and data. The full 32-bi t address is always driven on the first clock of a bus cycle (address phase). The number of bytes used for data during the data phase is de[...]

MCF548x External Signals MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-17 2.2.1.2 Chip Select (FBCS [5:0]) FBCS [5:0] are asserted to indicate wh ich device is being selected. A part icular chip select asserts when the transfer address is within the device’ s address spa ce as defined in the base and mask address registers. Each c[...]

MCF548x Refere nce Manual, Rev . 3 2-18 F reescale Semiconductor For burst-inhibited transfers, TSIZ[1:0] changes with each ALE asserti on to reflect the next transfer size. For transfers to port sizes smaller than the transfer si ze, TSIZ[1:0] indicates the si ze of the entire tran sfer on the first access and the size of the current port transfer[...]

MCF548x External Signals MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-19 2.2.2.3 SDRAM Bank Addresses (SDB A [1:0]) Each SDRAM module has four internal row banks. The SDBA[1:0] signals are used to select the row bank. It is also used to select the SDRAM intern al mode register duri ng power -up initialization. 2.2.2.4 SDRAM Row Ad [...]

MCF548x Refere nce Manual, Rev . 3 2-20 F reescale Semiconductor 2.2.2.14 SDRAM Reference V oltage (VREF) This is the input referenc e voltage for differential SSTL_2 inputs. It is used in both DDR and SDR modes. 2.2.3 PCI Contr oller Signals 2.2.3.1 PCI Address/Data Bus (PCIAD[31:0]) The PCIAD[31:0] lines are a time-mul tiplexed address data bus. [...]

MCF548x External Signals MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-21 2.2.3.9 Reset (PCIRESET ) The PCIRESET signal is asserted active low by MCF548 x to reset the PCI bus. This signal is asserted af ter the MCF548 x is reset and must be negated to enable usage of the PCI bus. 2.2.3.10 System Error (PCISERR ) The PCISERR signal,[...]

MCF548x Refere nce Manual, Rev . 3 2-22 F reescale Semiconductor 2.2.5 Clock and Reset Signals The clock and reset signals configure the MCF548 x and provide interface signals to the external system. 2.2.5.1 Reset In (RSTI ) Asserting RSTI causes the MCF548 x to enter reset excep tion processing. RST O is asserted automatically when RSTI is asserte[...]

MCF548x External Signals MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-23 Figure 2-2. CLKIN, Internal Bus, and Core Clock Ratios 2.2.6.2 AD5— F le xB u s S i z e Configuration (FBSIZE) At reset, the enabli ng and disabling of BE /BWE [3:0] versus TSIZ[1:0] and ADDR[1:0] is determined by the logic level driven on AD5 at the rising [...]

MCF548x Refere nce Manual, Rev . 3 2-24 F reescale Semiconductor 2.2.6.5 AD2— A uto Ac knowledg e Configuration (AA CONFIG) At reset, the enabling and disabli ng of auto acknowledge for boot FBCS0 is determined by the logic level driven on AD2 at the rising edge of RSTI . AACONFIG is multiplexed with AD2 and sampled only at reset. The AD2 logic l[...]

MCF548x External Signals MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-25 2.2.7.2 Management Data Clock (E0MDC, E1MDC) EMDC is an output clock that pr ovides a timing reference to the PHY for data transfers on the EMDIO signal; it applies to MII mode operation. 2.2.7.3 T ransmit Clock (E0TXCLK, E1TXCLK) This is an input clock that p[...]

MCF548x Refere nce Manual, Rev . 3 2-26 F reescale Semiconductor 2.2.7.12 T r ansmit Err or (E0TXER, E1TXER) When the ETXER output is asserted for one or more clock cycles while ETXEN is also asserted, the PHY sends one or more illegal symbol s. ETXER has no effect at 10 Mbps or when ETXEN is negated, and applies to MII mode operation. 2.2.7.13 Rec[...]

MCF548x External Signals MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-27 2.2.9.2 DSPI Synchr onous Se rial Data Input (DSPISIN) The DSPISIN input provides the seri al data to the DSPI and can be programmed to be sampled on the rising or falling edge of DSPISCK. 2.2.9.3 DSPI Serial Clock (DSPISCK) DSPISCK is a serial communication c[...]

MCF548x Refere nce Manual, Rev . 3 2-28 F reescale Semiconductor 2.2.11.1 Serial Clock (SCL) This bidirectional open-drain signa l is the clock signal for the I 2 C interface. It is either driven by the I 2 C module when the bus is in master mode, or it becomes the clock input when the I 2 C is in slave mode. 2.2.11.2 Serial Data (SD A ) This bidir[...]

MCF548x External Signals MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-29 2.2.14 Timer Module Signals The signals in the following sections are extern al interfaces to the fo ur general-purpose MCF548 x timers. These 32-bit timers can capture time r values, trigger external events or internal interrupts, or count external events. 2.[...]

MCF548x Refere nce Manual, Rev . 3 2-30 F reescale Semiconductor 2.2.15.4 Breakpoint/T est Mode Select (BKPT /TMS) If MTMOD0 is low , BKP T is selected. BKP T signals a hardware breakpoint to the processor in debug mode. If MTMOD0 is high, TMS is select ed. The TMS input provides informa tion to determine the JT AG test operation mode. The state of[...]

MCF548x External Signals MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 2-31 2.2.17 P ower and Reference Pins These pins provide system power , ground, and references to the device. Multiple pins are provided for adequate current capability . All power supply pi ns must have adequate bypass capacitance for high-frequency noise suppress[...]

MCF548x Refere nce Manual, Rev . 3 2-32 F reescale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor i Part I Processor Core Part I is intended for system designers who need to understand the operation of the MCF548 x ColdFire core and its enhanced multiply/a ccumulate (EMAC) execution unit. It describes the programming and exception models, Harvard memory implementation, and debug module[...]

MCF548x Refere nce Manual, Rev . 3 ii F reescale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-1 Chapter 3 ColdFire Core This chapter provides an overview of the microprocessor core of the MCF548 x . The CF4e implementation of the V ersion 4 (V4) core incl udes the floating-point unit (FPU), enhanced multiply-accumulate unit (EMAC), and memory management uni t (MMU); all are defin[...]

MCF548x Refere nce Manual, Rev . 3 3-2 F reescale Semiconductor 3.2.1 Enhanced Pipelines The IFP prefetches instructions. Th e OEP decodes instructio ns, fetches required operands, then executes the specified function. The two inde pendent, decoupled pipeline stru ctures maximize performance while minimizing core size. Pipeli ne stages are shown in[...]

Features MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-3 Figure 3-1. ColdFire Enhanced Pipeline 3.2.1.1 Instruction Fetch Pipeline (IFP) Because the fetch and exec ution pipelines are decoupled by a ten-instructi on FIFO buf fer , the IFP can prefetch instructions before the OEP needs them, minimizing stalls. Inter nal IAG IC1 IC2 I[...]

MCF548x Refere nce Manual, Rev . 3 3-4 F reescale Semiconductor 3.2.1.1.1 Branch Acceleration T o maximize the performance of conditional branch inst ructions, the IFP impl ements a sophisticated two-level acceleration mechanism. The first le vel is an 8-entry , direct-m apped branch cache with 2 bits for indicating four prediction st ates (strongl[...]

Features MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-5 ColdFire microprocessor family . Th e MAC features a four-stage ex ecution pipeline, optimized for 32 × 32 multiplies. It is tightly coupled to the OEP , which can issue a 32 x 32 multiply with a 32-bit accumulation and fetch a 32-bit operand in a singl e cycle. A 32 x 32 mul[...]

MCF548x Refere nce Manual, Rev . 3 3-6 F reescale Semiconductor The hardware unit is optimized for real-time execution with exceptio ns disabled and default results provided for specific operations, operands, and number types. The FPU does not support all IEEE-754 number types and operations in hardware. Exceptions can be enabled to support these c[...]

Program ming Model MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-7 • The ASID is optionally included in the specification of the hardwa re breakpoint registers. As an example, the four PC breakpoint registers are each expanded by 8 bits, so that a specific ASID value may be programmed as part of the breakpoint instruction address.[...]

MCF548x Refere nce Manual, Rev . 3 3-8 F reescale Semiconductor Figure 3-3. ColdFire Pr ogramming Model 31 0 D0 Data registers D1 D2 D3 D4 D5 D6 D7 31 0 A0 Address registers A1 A2 A3 A4 A5 A6 A7 User stack pointer PC Program counter CCR Condition code register 63 0 FP0 Floating-point data registers FP1 FP2 FP3 FP4 FP5 FP6 FP7 FPCR Floating-poin t c[...]

Program ming Model MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-9 3.3.1 User Pr ogramming Model The user programming model, shown in Figure 3-3 , consists of the following registers: • 16 general-purpose, 32-bit registers (D7–D 0 and A7–A0); A7 is a user stack pointer • 32-bit program counter • 8-bit condition code regist[...]

MCF548x Refere nce Manual, Rev . 3 3-10 F reescale Semiconductor 3.3.3 EMA C Programming Model The registers in the EMAC portion of the user programmi ng model are described in Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC) ,” and include the following registers: • Four 48-bit accumulator regist ers partitioned as follows: — Four 32-b[...]

Program ming Model MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-11 • Eight 64-bit floa ting-point data registers (FP0–FP7) • One 32-bit floating-point control register (FPCR) • One 32-bit floating-point status register (FPSR) • One 32-bit floating-point instruction address register (FPIAR) Figure 3-6 shows the FPU program[...]

MCF548x Refere nce Manual, Rev . 3 3-12 F reescale Semiconductor 3.3.5.1 Status Register (SR) The SR stores the processor status, the interrupt priority ma sk, and other control bi ts. Supervisor software can read or write the entire SR; user software can read or write onl y SR[7–0], described in Section 3.3.2.2, “Condition Code Register (CCR) [...]

Program ming Model MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-13 3.3.5.3 Cache Contr ol Register (CA CR) The CACR controls operation of both the instruction a nd data cache memory . It includes bits for enabling, freezing, and invalidating cache conten ts. It also includes bits for de fining the default cache mo de and write-prot[...]

MCF548x Refere nce Manual, Rev . 3 3-14 F reescale Semiconductor T able 3-4. ColdFire CPU Registers Name CPU Space (Rc) Written with MO VEC Register Name Memory Management Contr ol Registers CA CR 0 x002 Y es C ache control register ASID 0x003 Y es Address space ide ntifier A CR0–ACR3 0x004–0x007 Y es A ccess control registers 0–3 MMUBAR 0x00[...]

Data Format Summary MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-15 3.4 Data Format Summary Ta b l e 3 - 5 lists the operand data fo rmats. Integer operands can reside in registers, memory , or instructions. The operand size is either explicitly encoded in the instruction or implicitly define d by the instruction operation. 3.4.1 D[...]

MCF548x Refere nce Manual, Rev . 3 3-16 F reescale Semiconductor Instruction encodings disallow use of address regist ers for byte operands. When an address register is a source operand, either the low-order word or the entire longw ord operand is used, depending on the operation size. W ord-length source ope rands are sign-extended to 32 bits and [...]

Data Format Summary MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-17 3.4.2 EMA C Data Representation The EMAC supports the following three modes, where each mode define s a unique operand type. • T wo’ s complement signed integer: In this format, an N-bit operand value lies in the range -2 (N-1) < operand < 2 (N-1) - 1. Th[...]

MCF548x Refere nce Manual, Rev . 3 3-18 F reescale Semiconductor 3.4.2.1.1 Signed-Integer Data Formats The FPU supports 8-bit byte (B), 16-bit word (W), and 32-bit longword (L) integer data formats. 3.4.2.1.2 Floating-P o int Data Formats Figure 3-13 shows the two binary floating-point data formats. Figure 3-13. Floating-P oint Data Formats Note th[...]

Instruction Set Summar y MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-19 3.6 Instruction Set Summary The ColdFire instruction set is a simplified ve rsion of the M68000 instru ction set. The removed instructions include BCD, bit field, logical rotate, decrement and branch, and integer multiply with a 64-bit result. “ About This B[...]

MCF548x Refere nce Manual, Rev . 3 3-20 F reescale Semiconductor • Enhanced support for byte and word-si zed operands through new move operations • Enhanced support for pos ition-independent code For descriptions of the Cold Fire instruction set, see the latest version of the ColdFir e Pr ogrammer ’ s Refer ence Manual . The following list su[...]

Instruction Set Summar y MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-21 Move t o USP move.l Ay U SP Y es Mov e with Sign Extend mvs.{b ,w} <ea>y Dx Mov e with Zero-Fill mvz.{b ,w} <ea>y Dx Signed Saturate sats.l Dx T est and Set an Operand tas.b <ea>x Y es EMA C Extensions Mov e from an Accumulator and Clear mo v[...]

MCF548x Refere nce Manual, Rev . 3 3-22 F reescale Semiconductor 3.6.2 Instruction Set Summary Ta b l e 3 - 8 lists user -mode in structions by opcode. Sav e Inter nal Floating P oint State fsav e <ea>x Y es Floating-P oint Square Root fsqr t.{b ,w ,l,s,d} <ea>y FPx Y es Floating-P oin t Subtract fsub .{b,w ,l,s,d} <ea>y FPx Y es [...]

Instruction Set Summar y MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-23 CMP CMP A <ea>y ,Dx <ea>y ,Ax B, W , L W, L Destination – Source → CCR CMPI #<d ata>,Dx B, W , L Destination – Immediate Data → CC R DIVS/DIVU <ea>y ,Dx W , L Destination / Source → Destination (Signed or Unsigned) EOR Dy ,<[...]

MCF548x Refere nce Manual, Rev . 3 3-24 F reescale Semiconductor FINT <ea>y ,FPx FPy ,FPx FPx B,W , L ,S, D D D Integer P ar t of Source → FPx Integer P ar t of FPx → FPx FINTRZ <ea>y ,FPx FPy ,FPx FPx B,W , L ,S, D D D Integer P ar t of Source → FPx; round to z ero Integer P ar t of FPx → FPx; round to zero FMO VE <ea>y ,[...]

Instruction Set Summar y MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-25 FSUB <ea>y ,FPx FPy ,FPx B,W , L ,S, D D FPx - Source → FPx FTST <ea>y B , W , L, S, D Source Operand T ested → FPCC ILLEGAL none none SP – 4 → SP; PC → (SP) → PC; SP – 2 → SP; SR → ( SP); SP – 2 → SP; V ector Offset → ( SP)[...]

MCF548x Refere nce Manual, Rev . 3 3-26 F reescale Semiconductor Ta b l e 3 - 9 describes supervisor -mode instructions. NO T Dx L ~ Destination → Destination OR <ea>y ,Dx Dy ,<ea >x L L Source | Destination → Destination ORI #<data>,Dx L Immediate Data | Destina tion → Destination PEA <ea>y L SP – 4 → SP; <ea&g[...]

Instruction Execution Timing MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-27 3.7 Instruction Ex ecution Timing The timing data in this section assumes the following: • Execution times for individual instructions make no assumptions concerning the OEP’ s ability to dispatch multiple instructions in one machine cycle. For sequen [...]

MCF548x Refere nce Manual, Rev . 3 3-28 F reescale Semiconductor • The OEP can complete all memory accesses wi thout memory causing any stalls. Thus, these timings assume an infinite, zero-wait state memory attached to the core. • Operand accesses are assumed to be aligned as follows: — 16-bit operands are aligne d on 0-modulo-2 addresses —[...]

Instruction Execution Timing MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-29 T able 3-12 lists timings for MOVE.L. T able 3-13 gives timings for MOVE.L instructions acces sing program-visible EMAC registers, along with other MOVE.L timings. Execution time s for moving ACC or MACSR conten ts into a destination location represent the[...]

MCF548x Refere nce Manual, Rev . 3 3-30 F reescale Semiconductor 3.7.2 One-Operand Instruction Ex ecution Timing T able 3-14 shows standard timings for single-operand instructions. T able 3-13. MA C and Miscellaneous Mo ve Execution Time s Opcode <ea> Effect ive Addr ess Rn (An) (An)+ –(An) (d16,An) (d8 ,An,Xi*SF) (xxx).wl #<xxx> mov [...]

Instruction Execution Timing MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-31 3.7.3 T wo-Operand Instruction Execution Timing T able 3-15 shows standard timings for double operand instructions. T able 3-15. T wo-Oper and Instruction Ex ecution Time s Opcode <ea> Effect ive Addr ess Rn (An) (An)+ –(An) (d16,An) (d 8 ,An,Xi*SF[...]

MCF548x Refere nce Manual, Rev . 3 3-32 F reescale Semiconductor 3.7.4 Miscellaneous Instruction Execution Timing T able 3-16 lists timings for miscellaneous instructions. lsr .l <ea>,Dx 1(0/0) — — — — — — 1(0/0) mac.w Ry ,Rx 1(0/0) — — — — — — — mac.l Ry ,Rx 3(0/0) — — — — — — — msac.w Ry ,Rx 1(0/0) ?[...]

Instruction Execution Timing MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-33 3.7.5 Branch Instruction Ex ecution Timing T able 3-17 shows general branch instruction timing. mov e.w SR,Dx 1(0/0) — — — — — — — mov e.w <ea>,SR 4(0/0) — — — — — — 4(0/0) mov ec Ry ,Rc 20(0/1) — — — — — — — m[...]

MCF548x Refere nce Manual, Rev . 3 3-34 F reescale Semiconductor T able 3-18 shows timing for Bcc instructions. 3.7.6 EMA C Instruction Execution Times T able 3-19 specifies instruction executi on times associated with the enhanced multiply-accumulate (EMAC) execute engine. 2 If predicted corre ctly by the hardware return stack. 3 If mispredicted b[...]

Instruction Execution Timing MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-35 Execution times for moving the contents of the ACC, ACCext[0 1,23], MACSR, or MASK into a destination location <ea>x in this table represent the best-case scenario when th e store is executed and no load, copy , MAC, or MSAC instructions are in the E[...]

MCF548x Refere nce Manual, Rev . 3 3-36 F reescale Semiconductor 3.8 Exception Pr ocessing Over view Exception processing for ColdFire pr ocessors is streamlined for perfor mance. Dif ferences from previous ColdFire Family processors include the following: • An instruction restart model for translation ( TLB mis s) and access faults. This new fun[...]

Exception Processing Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-37 If the exception is caused by an FPU instruction, the PC contains the address of either the next floating-point instruction (nextFP) if the exception is pre-instruction, or the faulting instruction (fault) if the exception is post-instruction. 3. The proc[...]

MCF548x Refere nce Manual, Rev . 3 3-38 F reescale Semiconductor ColdFire processors inhibi t sampling for interr upts during the first instruction of all exception handlers. This allows any handler to ef fectively disable interr upts, if necessary , by raisi ng the interrupt mask level in the SR. 3.8.1 Exception Stac k Frame Definition The first l[...]

Exception Processing Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-39 3.8.2 Processor Exceptions T able 3-23 describes CF4e exceptions. Note that if a ColdFire processor enc ounters any fault while processing another fault, it imme diately halts execution with a cat astrophic fault-on-fault condition. A reset is required to[...]

MCF548x Refere nce Manual, Rev . 3 3-40 F reescale Semiconductor T able 3-23. Pr ocessor Exceptions T ype Description Access error If the MMU is disabled, a ccess errors are repor ted only in conjunction with an atte mpted store to write-protected me mor y . Thus, access e rrors associated with instr uction fetch or operand read accesses are not po[...]

Exception Processing Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-41 Unimplemented line-a opcode A line-a opcode results when bits 15–12 of th e opwor d are 1010. This e xception is generated by the attempted ex ecution of an undefined line-a opcode. Unimplemented line-f o pcode A line-f opcode results when bits 15–12 [...]

MCF548x Refere nce Manual, Rev . 3 3-42 F reescale Semiconductor 3.9 Precise F aults T o support a demand-paged virtual memory environm ent, all memory references require precise, recoverable faults. The ColdFire in struction restart mec hanism ensures that a faulted instruction restarts from the beginning of execution; that is, no internal state i[...]

Precise Faults MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 3-43 NO TE For access errors signaled on instru ction prefetches, an access error exception is generated only if inst ruction execution is attempted. If an instruction fetch access error excep tion is generated and the FS field indicates the fault occurr ed on an extension w[...]

MCF548x Refere nce Manual, Rev . 3 3-44 F reescale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 4-1 Chapter 4 Enhanced Multipl y-Accum ulate Unit (EMA C) This chapter describes the func tionality , microarchitecture, and performance of the enhanced multiply-accumulate (EMAC) unit in th e ColdFire family of processors. 4.1 Intr oduction The MAC design provides a set of DSP operations [...]

MCF548x Refere nce Manual, Rev . 3 4-2 F reescale Semiconductor 4.1.1 MA C Overview The MAC is an extension of the basic multiplier found in most mi croprocessors. It is typically implemented in hardware within a n architecture and supports rapid execu tion of signal processing algorithms in fewer cycles than comparable non-MAC architectures. For e[...]

Introduction MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 4-3 execution times are minimized and de terministic compared to the 2- bit/cycle a lgorithm with early termination that the OEP normally us es if no MAC hardware is present. The added MAC instructions to the ColdFire ISA provide for the mult iplication of two numbers, followe[...]

MCF548x Refere nce Manual, Rev . 3 4-4 F reescale Semiconductor Figure 4-5. Signed and Unsigned Integer Alignment Thus, the 48-bit accumulator defini tion is a function of the EMAC ope rating mode. Given that each 48 -bit accumulator is the concate n ation of 16-bit accumulator extension register (ACCext n ) contents and 32-bit ACC n contents, the [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 4-5 The need to move large amounts of data presents an obstacle to obt aining high throughput rates in DSP engines. New and existing ColdFire instructio ns can accommodate these req uirements. A MOVEM instruction can move large blocks of data efficiently by [...]

MCF548x Refere nce Manual, Rev . 3 4-6 F reescale Semiconductor Ta b l e 4 - 1 describes MACSR fields. 31 30 29 28 27 26 25 24 2 3 22 21 20 19 18 17 16 R 0000000000 000000 W R e s e t 0000000000 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 P A Vx OMC S/U F/I R/T N Z V EV W R e s e t 0000000000 000000 Reg Addr Figure 4-7. M A C Stat us Reg[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 4-7 Ta b l e 4 - 2 summarizes the interac tion of th e MACSR[S/U,F/I,R/T] control bits. 5 F/I Operational mode field: F racti onal/integer mode Deter mines whethe r i nput operands are treated as fractions or integers. 0 Integers can be represented in either[...]

MCF548x Refere nce Manual, Rev . 3 4-8 F reescale Semiconductor 4.2.1.1 Fractional Operation Mode This section describes behavior when the fr actional mode is used (MACSR[F/I] is set). 4.2.1.1.1 Rounding When the processor is in fractional mode, ther e are two operations during which rounding can occur . • Execution of a store accumulat or instru[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 4-9 then Result = R0.U + 1 else if lsb of R0.U = 0 /* R0.L = 0x8000 */ then Result = R0.U else Result = R0.U + 1 The round-to-nearest-even technique is also known as conver gent rounding. 4.2.1.1.2 S av ing and Restori ng the EMA C Programming Model The pres[...]

MCF548x Refere nce Manual, Rev . 3 4-10 F reescale Semiconductor move.l d6,mask ; restore the address mask move.l d7,macsr ; restore the macsr By executing this type of sequence, the exact st ate of the EMAC programmi ng model can be correctly saved and restored. 4.2.1.1.3 MULS/MULU MULS and MULU are unaffected by fr actional mode operation; operan[...]

EMA C Instruction Set Summary MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 4-11 4.3 EMA C Instruction Set Summar y Ta b l e 4 - 3 summarizes EMAC unit instructions. 4.3.1 EMA C Instruction Execution Timing The instruction execut ion times for the EM AC can be found in Section 3.7, “Instruction Execution T iming.” The ColdFire fam[...]

MCF548x Refere nce Manual, Rev . 3 4-12 F reescale Semiconductor The mov .l instruction that stores the accumulator to an intege r register (Rz ) stalls until the program-visible copy of the accumulat or is available. Figure 4-8 shows EMAC timing. Figure 4-8. EMA C-Specific OEP Sequence Sta ll In Figure 4-8 , the OEP stalls the store-accumulator in[...]

EMA C Instruction Set Summary MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 4-13 This format can represent numbers in the range -1 < operand < 1 - 2 (N-1) . For words and longwords, the larges t negative number that can be re presented is -1, whose internal representation is 0x8000 and 0x8000_0000, respectively . The largest pos[...]

MCF548x Refere nce Manual, Rev . 3 4-14 F reescale Semiconductor } else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0] } /* perform the multiply */ product[63:0] = operandY[31:0] * oper andX[31:0] /* check for product overflow */ if ((product[63:39] != 0x0000_00_0) & & (product[63:39] != 0xfff f_ff_1)) then { /* product overflow */ MA[...]

EMA C Instruction Set Summary MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 4-15 MACSR.V = 1 if (MACSR.OMC == 1) then /* accumulation overflow, saturationMode enabled */ if (result[47] == 1) then result[47:0] = 0x0000_7fff_f fff else result[47:0] = 0xffff_8000_0 000 } /* transfer the result to the accumul ator */ ACCx[47:0] = result[4[...]

MCF548x Refere nce Manual, Rev . 3 4-16 F reescale Semiconductor /* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.PAVx = 1 MACSR.V = 1 if (MACSR.OMC == 1) then /* accumulation overflow, saturationMode enabled */ if (result[47] == 1) then result[47:0] = 0x007f_ffff_f f00 else result[47:0] = 0xff80_0000_0 000 } /* tran[...]

EMA C Instruction Set Summary MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 4-17 result[47:0] = 0xffff_ffff_ffff } /* zero-fill to 48 bits before perfor ming any scaling */ product[47:40] = 0 /* zero-fill upper byte */ /* scale product before combining wit h accumulator */ switch (SF) /* 2-bit scale factor */ { case 0: /* no scaling s[...]

MCF548x Refere nce Manual, Rev . 3 4-18 F reescale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 5-1 Chapter 5 Memory Management Unit (MMU) This chapter describes the ColdFire virtual memory management unit (MMU), which provides virtual-to-physical addre ss translation and memory access control. The MMU consists of memory-mapped control, status, and fault registers that provide access[...]

MCF548x Refere nce Manual, Rev . 3 5-2 F reescale Semiconductor • The address access control logic, address attrib ute logic, memories, and co ntroller function as in previous ColdFire versions with the addition of the MMU. The MMU, its TLB, and associated control reside in the logic. • The MMU appears as a memory-mapped device in the space. In[...]

Virtual Mem ory Management Architecture MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 5-3 Figure 5-1. CF4e Pr ocessor Core Block with MMU 5.2.3 MMU Arc hitecture Implemen tation This section describes ColdFire design additions and changes for th e MMU architecture. It includes precise faults, MMU access, virtua l mode, virtual memory [...]

MCF548x Refere nce Manual, Rev . 3 5-4 F reescale Semiconductor 5.2.3.1 Precise Faults The MMU architecture performs virtual-to-physical address translation and permission checking in the core. T o support demand-paging, the co re design provides a precise, recove rable fault for all references. 5.2.3.2 MMU Access The MMU TLB control registers ar e[...]

Virtual Mem ory Management Architecture MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 5-5 more bits than the in-page address, one or more of the low-order vi rtual page number bits are used to address the cache. The MMU translat es these bits; the resulting low-or der physical page number bits are used to determine cache hits. Address[...]

MCF548x Refere nce Manual, Rev . 3 5-6 F reescale Semiconductor 5.2.3.10 A CR Address Impr ovements ACRs provide a 16-Mbyte a ddress window . For a given request address, if the ACR is valid and the request mode matches the mode specified in the superv isor mode field, ACR n [S], hit determinat ion is specified as follows: ACRx_Hit = 0; if ((addres[...]

Debugging in a Virtual En vironment MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 5-7 5.2.3.11 Supervisor Protection Each instruction or data re ference is either a supervis or or user access. The CPU’ s status register supervisor bit (SR[S]) determines the operating mode. New AC R and CACR bits protect supervisor space. See Ta b l [...]

MCF548x Refere nce Manual, Rev . 3 5-8 F reescale Semiconductor In addition, the following two privil eged M68000 family instructions to load/store the USP are added to the ColdFire instruction set architecture: mov.l Ay,USP # move to USP: opcode = 0x4E6{0-7} mov.l USP,Ax # move from USP: opcode = 0x4E6{8–F} The address register number is encoded[...]

MMU Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 5-9 5.5 MMU Definition The ColdFire MMU provides a virt ual address, demand-paged memory architecture. The MMU supports hardware address translat ion acceleration using software-managed TLBs. It enforces permission checking on a per-memory request basis, and has control, sta[...]

MCF548x Refere nce Manual, Rev . 3 5-10 F reescale Semiconductor • If virtual mode is enabled, any normal m ode access that does not hit in the MMUBAR, RAMBARs, ROMBARs, or ACRs is considered a normal mode virtual address request and generates its access attributes from the MMU. For this case, the default CACR address attribute s are not used. Th[...]

MMU Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 5-11 5.5.3.2 MMU Memor y Map MMUBAR holds the base address for th e 64-Kbyte MMU memory map, shown in Ta b l e 5 - 4 . The MMU memory map area is not vi sible unless the MMUBAR is valid and must be refe renced aligned. A large portion of the map is reserved for future use. T[...]

MCF548x Refere nce Manual, Rev . 3 5-12 F reescale Semiconductor Ta b l e 5 - 5 describes MMUCR fields. 5.5.3.4 MMU Operation Register (MMUOR) Figure 5-5 shows the MMUOR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R0 00 0 00 0 00 0 00 0 00 W R e s e t 0 0 0 0 0000 0000 0 0 0 0 15 14 13 12 11 1 0 9 8 7 6 5 4 3 2 1 0 R0 00 0 00 0 00 0 00 0 0 ASM[...]

MMU Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 5-13 Ta b l e 5 - 6 describes MMUOR fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RA A W R e s e t 0 0 0 0 0000 0 0 0 0 00 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R0 00 0 00 0 STLB CA CNL CAS ITLB ADR R/W ACC U AA W R e s e t 0 0 0 0 0000 0 0 0 0 00 0 0 Reg Addr [...]

MCF548x Refere nce Manual, Rev . 3 5-14 F reescale Semiconductor 5.5.3.5 MMU Status Register (MMUSR) MMUSR, Figure 5-6 , is updated on all data access fa ults and search TLB operations. Ta b l e 5 - 7 describes MMUSR fields. 5 CAS Clear all non-lock ed TLB entries that match ASID . CAS is alwa ys reads as a zero . 0 No operation 1 Clear all non-loc[...]

MMU Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 5-15 5.5.3.6 MMU Fault, T est, or TLB Address Register (MMU AR) The MMUAR format, Figure 5-7 , depends on how the register is used. Ta b l e 5 - 8 describes MMUAR fields. T able 5-7. MMUSR Field Descriptions Bits Name Description 31–6 — Reser ved, should be cleared. Writ[...]

MCF548x Refere nce Manual, Rev . 3 5-16 F reescale Semiconductor 5.5.3.7 MMU Read/Write T ag and Data Entry Registers (MMUTR and MMUDR) Each TLB entry consists of a 32-bit TLB tag entry and a 32-b it TLB data entry . TLB entries are referenced through MMUTR and MMUDR. For read TLB accesses, the contents of the TLB tag and data entries referenced by[...]

MMU Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 5-17 MMUDR, Figure 5-9 , contains the physical addre ss, page size, cache mode fi eld, supervisor-protect bit, read, write, execute permissi on bits, and lock-entry bit. T able 5-10 describes MMUDR fields. 1 SG Shared global. Indicates wh en the entr y is shared among user a[...]

MCF548x Refere nce Manual, Rev . 3 5-18 F reescale Semiconductor 5.5.4 MMU TLB Each TLB entry consists of two 32-b it fields. The first is the TLB tag entry , and the second is the TLB data entry . TLB size and organi zation are implementation de pen dent. TLB entries ca n be read and written through MMU registers. TLB cont ents are unaffected by r[...]

MMU Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 5-19 5.5.5 MMU Operation The processor sends instruction fetch requests and data read/write reque sts to the MMU in the in struction and operand address ge neration cycles (IAG and OAG). The controller and memo ries occupy the next two pipeline stages, instruction fetch cy c[...]

MCF548x Refere nce Manual, Rev . 3 5-20 F reescale Semiconductor Figure 5-10 shows more details of the MMU structure. The TLB is acces se d at the beginning of th e KC1 pipeline stage so the result ing physical address can be sourced to the cache c ontrollers to factor in to the cache hit/miss determination. This is required becaus e caches are vir[...]

MMU Implementation MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 5-21 When MMUAR is used for a TLB addr ess, bits F A[5–0] also have th is address format for CF4e. The remaining form address bits (F A[31–6]) are ignored when this register is being used for a TLB address. 5.6.2 TLB Replacement Algor ithm The instruction and data TL[...]

MCF548x Refere nce Manual, Rev . 3 5-22 F reescale Semiconductor Binary state bits are updated on all TLB write (load) operations, as well as normal ITLB and DTLB hits of non-locked entries. Also, if all entries in a binary st ate are locked, than that stat e is always set. That is, if entries 15, 14, 13, and 12 were locked, LRU state bit rdRecent1[...]

MMU Instructions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 5-23 Figure 5-11. V ersion 4 Co ldFire MMU Harv ar d TLB 5.7 MMU Instructions The MOVE to USP and MOVE from USP instructions have been adde d for accessing the USP . Refer to the ColdFir e Pr ogrammer ’ s Refer ence Manual for more information. KC1 J Current address spac[...]

MCF548x Refere nce Manual, Rev . 3 5-24 F reescale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-1 Chapter 6 Floating-P oint Unit (FPU) 6.1 Intr oduction This chapter describes instructions implemented in the floating-point unit (FPU) designed for use with the ColdFire family of microprocesso rs. The FPU conforms to the American National Stand ards Institute (ANSI)/Institute of Elec[...]

MCF548x Refere nce Manual, Rev . 3 6-2 F reescale Semiconductor Ta b l e 6 - 2 describes addressing modes and syntax for floating-point instructions. & Logical AND | Logical OR → Source operand is mov ed to destination operand <op> Any double-operand operation <operand>tested Op erand is compared to z ero and the condition codes a[...]

Operand Data Formats and T ypes MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-3 6.2 Operand Data Formats and T ypes The FPU supports signed byte, word, and longword integer form ats, which are identical to those supported by the integer unit. The FPU also supports single- a nd double-precision binary floating-point formats that full[...]

MCF548x Refere nce Manual, Rev . 3 6-4 F reescale Semiconductor yields a signed, two’ s co mplement power of two. This represents the magnitude of a normalized floating-point number when multiplied by the mantissa. By definition, a normalized mant issa always takes va lues starting from 1.0 and going up to, but not including, 2.0; that is, [1.0..[...]

Operand Data Formats and T ypes MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-5 6.2.3.4 Not-A-Number When created by the FPU, NANs repr esent the results of ope rations having no mathem atical interpretation, such as infinity divided by infin ity . Operations using a NAN operand as an input return a NAN result. User -created NANs ca[...]

MCF548x Refere nce Manual, Rev . 3 6-6 F reescale Semiconductor Biased exponent (e) 8 1 1 F racti on (f) 23 52 To t a l 3 2 6 4 Interpretation of Sign P ositive frac tion s = 0 s = 0 Negative fraction s = 1 s = 1 Normalized Num bers Bias of biased exponent +127 (0x7F) +1023 (0x3FF) Range of biased exponent 0 < e < 255 (0xFF) 0 < e < 204[...]

Regist er Defini tion MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-7 6.3 Register Definition The programmer ’ s model for the FP U consists of the following: • Eight 64-bit floa ting-point data registers (FP0–FP7) • One 32-bit floating-point control register (FPCR) • One 32-bit floating-point status register (FPSR) • On[...]

MCF548x Refere nce Manual, Rev . 3 6-8 F reescale Semiconductor The user can read or write to FPCR using FMOVE or FREST ORE. A processor reset or a restore operation of the null state clears the FPCR. When this regist er is cleared, the FPU ne ver generates exceptions. Ta b l e 6 - 4 describes FPCR fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 [...]

Regist er Defini tion MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-9 6.3.3 Floating-P oint Stat us Register (FPSR) The FPSR, Figure 6-10 , contains a floati ng-point condition code byte (FP CC), a floating-point exception status byte (EXC), and a floating- point accrued exception byte (AEXC). The user can read or write all FPSR bit[...]

MCF548x Refere nce Manual, Rev . 3 6-10 F reescale Semiconductor For AEXC[OVFL], AEXC[DZ], and AEXC[INEX], the ne xt value is determined by ORing the current AEXC value with the EXC equivale nt, as shown in the following: • Next AEXC[OVFL] = Curre nt AEXC[OVFL] | EXC[OVFL] • Next AEXC[DZ] = Curr ent AEXC[DZ] | EXC[DZ] • Next AEXC[INEX] = Curr[...]

Floating-Point Computational Accuracy MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-11 For FPU instructions that can genera te exception traps, the 32-bit FPIAR is loaded with the instruction PC address before the FPU begins exec ution. In case of an FPU exception, the trap handler can use the FPIAR contents to determine the instru [...]

MCF548x Refere nce Manual, Rev . 3 6-12 F reescale Semiconductor double-precision format. If th e destination is a memory location or an integer data register , rounding precision is ignored. In this case, a number in th e double-precision format is taken from the source floating-point data register , rounded to the destination format precision, an[...]

Floating-Point Computational Accuracy MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-13 Figure 6-12. Rounding Algorithm Flo w chart The 3 additional bits beyond the double-precision format , the dif ference between the intermediate result’ s 56-bit mantissa and the storing resu lt’ s 53-bit mantissa, allow the FPU to perform all [...]

MCF548x Refere nce Manual, Rev . 3 6-14 F reescale Semiconductor The lsb of the rounded result does not increment even though the guard bit is set in the intermediate result. The IEEE-754 standard specifies th is way of handling ties. If th e destination data format is double-precision and there is a differ ence between the infinitely preci se inte[...]

Floating-Point P ost-Processing MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-15 rounding precision and mode. Afte r rounding, the inexact bit (INEX) is set as described in Figure 6-12 . Lastly , the magnitude of the result is checked to see if it exceeds the current rounding precision. If so, the overflow (OVFL) bit is set, and a c[...]

MCF548x Refere nce Manual, Rev . 3 6-16 F reescale Semiconductor unordered condition is present when the conditional test is attempted (IEEE nonaware tests). The other 16 do not cause an exception (IEEE-aware tests). The set of IEEE nonaware test s is best used in one of the following cases: • When porting a program from a system that does not su[...]

Floating-P oint Exceptions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-17 6.6 Floating-P o int Exceptions This section describes floating-point exceptions and how they are handled. Ta b l e 6 - 1 0 lists the vector numbers related to floating-point exce ptions. If the exception is taken pr e-instruction, the PC contains the addres[...]

MCF548x Refere nce Manual, Rev . 3 6-18 F reescale Semiconductor In addition to these vectors, at tempting to execute a FRESTO RE in struction with a unsupported frame value generates a format error exception (vector 14). See the FRESTORE instruction in t he ColdFir e Pr ogrammer ’ s Refer ence Manual . Attempting to execute an FPU instru ction w[...]

Floating-P oint Exceptions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-19 A floating-point arithmetic exception becomes pending when the result of a floating-point instruction sets an FPSR[EXC] bit and the correspondi ng FPCR[ENABLE] bit is set. A user write to the FPSR or FPCR that causes the setting of an ex ception bit in FPSR[[...]

MCF548x Refere nce Manual, Rev . 3 6-20 F reescale Semiconductor 6.6.1.2 Input Not-A-Number (INAN) The INAN exception is a mechanis m for handling a user -defined, non -IEEE data type. If either input operand is a NAN, FPSR[INAN] is set. By enabling this exception, the us er can override the default action taken for NAN operands. Because FMOVEM, FM[...]

Floating-P oint Exceptions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-21 6.6.1.4 Operand Error (OPERR) The operand error exception encompasses problems arisi ng in a variety of operations, including errors too infrequent or trivial to merit a specific exception condition. Basically , an operand error occurs when an operation has [...]

MCF548x Refere nce Manual, Rev . 3 6-22 F reescale Semiconductor 6.6.1.6 Underflow (UNFL) An underflow exception occurs when the intermediate resu lt of an arithmetic inst ruction is too small to be represented as a normalized number in a floating-point register or memory using the selected rounding precision; that is, when the intermediate result [...]

Floating-P oint Exceptions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-23 6.6.1.8 Inexact Result (INEX) An INEX exception condition exists when the infinitely precise manti ssa of a floating- point intermediate result has more significant bits than can be represented exact ly in the selected r ounding precision or in the destinati[...]

MCF548x Refere nce Manual, Rev . 3 6-24 F reescale Semiconductor Note that if no intervention is n eeded, instead of FSA VE, the handler can simply clear the appropriate FPCR and FPSR bits and then return from the exception. Because the FPCR and FPSR are writte n in the FSA VE frame, a context switch needs only execute FSA VE and FMOVEM for data re[...]

Instructions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-25 Normally , an exception handler executes FSA VE, proce sses the exception, clears the exception bit in the FSA VE state frame status word, and executes FRESTORE. If appropriate exception bits set in the status word are not cleared, the same exception is taken again. If mu[...]

MCF548x Refere nce Manual, Rev . 3 6-26 F reescale Semiconductor T able 6-24 defines the terminology used in T able 6-23 . F M O V E 111100100 0 e a mode ea reg 0 r/m 0 src spec dest reg opmode 1111001000 e a mode ea reg 0 1 1 dest fmt src reg 0 0 0 0 0 0 0 1111001000 e a mode ea reg 1 0 d r r e g s e l 00 0 0000000 F M O V E M 1111001000 e a mode [...]

Instructions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-27 6.7.2 Floating-P oint Instruction Execution Timing T able 6-25 shows the ColdFire execution times for the floa ting-point instructions in terms of processor core clock cycles. Each timing entry is presented as C( r/w ). • C = The number of processor clock cycles includi[...]

MCF548x Refere nce Manual, Rev . 3 6-28 F reescale Semiconductor The ColdFire architecture supports concurrent execu tion of integer and floati ng-point instructions. The latencies in this table de fine the execution time ne eded by the FPU. After a multi-cycle FPU instruction is issued, subsequent integer instru ctions can execute concurrently wit[...]

Instructions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 6-29 Some differences af fect function activation and return. M68000 su broutines typically began with FMOVEM #list,-(a7) to save registers on the system stack, with each register occupying three longwords. In ColdFire, each register occupies two longwords a nd the stack point[...]

MCF548x Refere nce Manual, Rev . 3 6-30 F reescale Semiconductor values be moved into a table of cons tants that can be referenc ed using PC-relative addr essing or as an of fset from another address pointer . See T able 6-29 . Finally , ColdFire and the M68000 differ in how exce ptions are made pending. In the ColdFire exception model, asserting b[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-1 Chapter 7 Local Memory This chapter describes the MCF548 x implementation of the ColdFi re V ersion 4e local memory specification. It consists of two major sections. • Section 7.2, “SRAM Overview ,” describes the MCF548 x core’ s local static RAM (SRAM) implementation. It cover[...]

MCF548x Refere nce Manual, Rev . 3 7-2 F reescale Semiconductor • Physical location on the processo r ’ s high-speed local bus with a user -programmed connection to the internal instruction or data bus • Memory location programmable on any 0-modulo-4K address boundary • Byte, word, and longword address capabilities • The RAM base address [...]

SRAM Register Definit ion MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-3 RAMBAR n fields are described in detail in Ta b l e 7 - 1 . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RB A W R e s e t 0 0 0 00 00 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R BA 0 0 0 WP D/I 0 C/I SC SD UC UD V W R e s e t 0 0 0 00 00 0 0 0[...]

MCF548x Refere nce Manual, Rev . 3 7-4 F reescale Semiconductor The mapping of a given access into the SRAM uses the following algorithm to determine if the access hits in the memory: if (RAMBAR[0] = 1) if (((access = instructionFetch) & ( RAMBAR[7] = 1)) | ((access = dataReference) & (RAMBAR[ 7] = 0))) if (requested address[31:10] = RA MBA[...]

SRAM Initialization MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-5 3. After the data is loaded into the SRAM, it ma y be appropriate to revi se the RAMBAR attribute bits, including the write-protect and address-space mask fiel ds. If the SRAM contains instructions, RAMBAR[D/I] must be set to logi cally connect the memory to the pro[...]

MCF548x Refere nce Manual, Rev . 3 7-6 F reescale Semiconductor ; +20 destinationOffset ; +24 bytesToMove move.l RAMBASE+RAMFLAGS,a0 ;define RAMBAR0 contents movec.l a0,rambar0;load it move.l 16(a7),a0;load argument defining *src lea.l RAMBASE,a1;memory pointer to SRAM base add.l 20(a7),a1;include destinationOffset move.l 24(a7),d4;load byte count [...]

Cache Or ganization MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-7 The MCF548 x processor ’ s Harvard memory structure in cludes a 32-Kbyte data cache and a 32-Kbyte instruction cache. Both are nonblocki ng and 4-way set-associative with a 16-byte line. The cache improves system performance by provi ding single-cycle access to th[...]

MCF548x Refere nce Manual, Rev . 3 7-8 F reescale Semiconductor Figure 7-3. Data Cache Or ganization and Line Format A set is a group of four line s (one from each level, or way), corr esponding to the same index into the cache array . 7.8.1 Cache Line States: In valid, V alid-Unmodified, and V a lid-Modi fied As shown in Ta b l e 7 - 3 , a data ca[...]

Cache Or ganization MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-9 Figure 7-4. Data Ca che—A: at Reset, B: aft er In validati on, C and D: Loading P attern A: Cache population at star t-up B: Cache after inv alidati on, bef ore it is enabled C: Cache after loa ds in W ay 0 D: First load in Wa y 1 Way 0Way 1Wa y 2Way 3 Way 0Way 1W[...]

MCF548x Refere nce Manual, Rev . 3 7-10 F reescale Semiconductor 7.9 Cache Operation Figure 7-5 shows the general flow of a caching operation using the 32-Kbyte data cache as an example. The discussion in this chapter assumes a data cache. Instruction cache operations are similar except that there is no support for writing to th e cache; therefore,[...]

Cache Operation MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-11 pseudo-round-robin replacement algorithm to choose th e line to be deallocate d and replaced. First the cache controller looks for an invalid line, with way 0 the highest priority . If all lines have valid data, a 2-bit replacement counter is used to choos e the way . [...]

MCF548x Refere nce Manual, Rev . 3 7-12 F reescale Semiconductor V alid cache entries that match during cache-inhibited address accesses are neithe r pushed nor invalidated. Such a scenario suggests that the associated cache mode for this a ddress space was changed. T o avoid this, it is generally recommended to use the CPUSHL ins tru ction to push[...]

Cache Operation MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-13 7.9.1.1.2 C opybac k Mode (Data Cache Only) Copyback regions are typically used for local data structures or stacks to mi nimize external bus use and reduce write-access latency . W rite acc esses to regions specified as c opyback that hit in the cache update the cache[...]

MCF548x Refere nce Manual, Rev . 3 7-14 F reescale Semiconductor an exception aborts the instruction and the data may be accessed again when the instruction is restarted. These guarantees apply only when ACR n [CM] indicates precise mode and aligned accesses. CPU space-register accesses using the MOVEC instru ction are treated as cach e-inhibited a[...]

Cache Operation MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-15 7.9.2.3 Read Hit On a read hit, the cache provides th e data to the processor core and the cache line state remains unchanged. If the cache mode changes for a sp ecific region of address space, lines in the cache corresponding to that region that contain modified data [...]

MCF548x Refere nce Manual, Rev . 3 7-16 F reescale Semiconductor 7.9.4.2 Cache Pushes Cache pushes occur for line replacem ent and as required for the execution o f the CPUSHL instruction. T o reduce the requested data’ s latency in the new line, the modified line be ing replaced is temporarily placed in the push buf fer while the new line is fet[...]

Cache Operation MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-17 7.9.5 Cache Loc king W ays 0 and 1 of the data cache ca n be locked by setting CACR[DHLCK]; likewise, ways 0 and 1 of the instruction cache can be locked by setting CACR[IHLCK]. If a cache is locked, cache lines in ways 0 and 1 are not subject to being deallo cated by [...]

MCF548x Refere nce Manual, Rev . 3 7-18 F reescale Semiconductor Figure 7-7. Data Cache Locking A: W ays 0 and 1 are filled. W a ys 2 and 3 are inv alid. B: CA CR[DHLCK] is set, locking wa ys 0 and 1. C: When a set in W a y 2 is occupied, the set in wa y 3 is used for a cacheable access. Way 0Way 1Way 2Way 3 Way 0Way 1Way 2Way 3 Way 0Way 1Way 2Way [...]

Cache Register Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-19 7.10 Cache Register Definition This section describes the MCF548 x implementation of the V ersion 4e cache registers. 7.10.1 Cache Contr ol Register (CA CR) The CACR in Figure 7-8 contains bits for configur ing the cache. It can be written by the MOVEC regist[...]

MCF548x Refere nce Manual, Rev . 3 7-20 F reescale Semiconductor 28 DDPI Disable CPUSHL inv al idation. 0 Normal operation. A CPUSHL instr uction causes t he selected line to be pushe d if modified, then inv alid ated. 1 No clear operation. A CPUSHL instruction causes the selected line to be pushed if modifie d, then left valid. 27 DHL CK Hal f-dat[...]

Cache Register Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-21 13 DNFB Default cache-inhibited fill buff er 0 Fill b uff er does not store cache-inhibit ed instr uction accesses (16 or 32 bits). 1 Fill b u ff er can store cache-inhibited accesses. The b uffer is used only f or nor mal (TT = 0) instruction reads of a cach[...]

MCF548x Refere nce Manual, Rev . 3 7-22 F reescale Semiconductor 7.10.2 Access Contr o l Register s (A CR0–A CR3) The ACRs, Figure 7-9 , assign control attributes, such as ca che mode and write protection, to specified memory regions. ACR0 and ACR1 control data attributes; ACR2 and ACR3 control instruction attributes. Registers are accessed with [...]

Cache Manageme nt MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-23 7.11 Cache Mana gement The cache can be enabled and configured by usi ng a MOVEC instruction to access CACR. A hardware reset clears CACR, disabling the c ache and removing all configuration information; however , reset does not affect the tags, state info rmation, a[...]

MCF548x Refere nce Manual, Rev . 3 7-24 F reescale Semiconductor The contents of A n used with CPUSHL specify cache row and line indexes. This differs from the 68K family where a physical address is specified. Figure 7-1 1 shows the A n format for the data cache. The contents of A n used with CPUSHL specify cache row and line indexes. Figure 7-10 s[...]

Cache Manageme nt MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-25 dataCacheLoadAndLock: move.l #0xa3080800,d0; enable and invalidate data cache . .. movec d0,cacr ; ... in the CACR The following code preloads half of the data cache ( 16 Kbytes). It assumes a co ntiguous block of data is to be mapped into the data cache, starting at[...]

MCF548x Refere nce Manual, Rev . 3 7-26 F reescale Semiconductor 7.12 Cache Operation Summary This section gives operational deta ils for the cache and presents inst ruction and data cache-line state diagrams. 7.12.1 Instruction Cache State T ransitions Because the instruction cache does not support writes, it suppor ts fewer operations than the da[...]

Cache Operation Summary MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-27 7.12.2 Data Cache State T ransitions Using the V and M bits, the data c ache supports a line-based protocol allowing individual cache lines to be invalid, valid, or modifi ed. T o maintain memory coherency , the data cach e supports both write-through and copyb[...]

MCF548x Refere nce Manual, Rev . 3 7-28 F reescale Semiconductor The following tables presen t the same information as Ta b l e 7 - 7 , organized by the curre nt state of the cache line. In Ta b l e 7 - 8 the current state is invalid. T able 7-7. Data Cac he Line State T ransitions Access Current State In valid (V = 0) V alid (V = 1, M = 0) Modifie[...]

Cache Operation Summary MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 7-29 In Ta b l e 7 - 9 the current state is valid. T able 7-8. Data Cache Line State T ransitions (Current Stat e In valid) Access Response Read miss (C,W)I1 Read line from memor y and up date cache; supply data to processor; go to valid state. Read hit (C,W)I2 Not [...]

MCF548x Refere nce Manual, Rev . 3 7-30 F reescale Semiconductor In T able 7-10 the current state is modified. 7.13 Cache Initialization Code The following example sets up the cac he for FLASH or ROM space only . move.l #0xA30C8100,D0 //enable cache, invalidate it, //default mode is cache-inhibited imprec ise movec D0, CACR move.l #0xFF00C000,D0 //[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-1 Chapter 8 Deb ug Suppor t 8.1 Intr oduction This chapter describes the Revisi on D enhanced hardware debug suppor t in the ColdFire V ersion 4. This revision of the ColdFire debug ar chitecture encompasses earlier re visions. An expa nded set of debug functionality is defi ned as Revis[...]

MCF548x Refere nce Manual, Rev . 3 8-2 F reescale Semiconductor generations of ColdFire cores. Fo r Revision A, CSR[ HRL] is 0. See Section 8.4.2, “Configuration/St atus Register (CSR) .” The V ersion 3 core implements Re vision B of the debug architecture , offering more flexibility for configuring the hardware breakpoint trigger registers and[...]

Signal Descriptions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-3 Figure 8-2 shows PSTCLK timing with respect to PSTDDA T A. Figure 8-2. PSTCLK Timing 8.2.1 Pr ocessor Status/Debug Data (PSTDD A T A[7:0]) Processor status data output s are used to indicate both processor status and captured address and data values. They operate at[...]

MCF548x Refere nce Manual, Rev . 3 8-4 F reescale Semiconductor output for the processor ’ s sequential execution of singl e-cycle instructions (A, B, C, D...). Cycle counts are shown relative to processor fre quency . These outputs indicate the curr ent processor pipeline status and are not related to the current bus transfer . The signal timing[...]

Real-Time T race Suppor t MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-5 NO TE A PST marker and its data display are sent cont iguously . Except for this transmission, the IDLE stat us (0x0) can appear a nytime. Again, given that real-time trace informati on appears as a sequence of 4-bit values, there are no alignment restrictions[...]

MCF548x Refere nce Manual, Rev . 3 8-6 F reescale Semiconductor 8.3.1 Begin Execution of T aken Branch (PST = 0x5) PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed on PSTDDA T A depending on the CSR settings. CSR also controls the number of address bytes displayed, which is indicated by the PST [...]

Real-Time T race Suppor t MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-7 The simplest example of a branch in struction using a variant address is the compiled code for a C language case statement. T ypically , the evaluation of this statem ent uses the variable of an expression as an index into a table of of fsets, where eac h of f[...]

MCF548x Refere nce Manual, Rev . 3 8-8 F reescale Semiconductor 8.3.3 Pr ocessor Halted (PST = 0xF) PST is 0xF when the pr ocessor is halted (see Section 8.5.1, “CPU Halt ”). Because this encoding defines a multiple-cycle mode, the PSTDDA T A outputs display 0xF until the pr ocessor is restarted or reset. Therefore, PSTDDA T A[7:0] continuously[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-9 8.4 Memory Map/Register Definition In addition to the existin g BDM commands that provi de access to the processor’ s registers and the memory subsystem, the debug module contains 19 registers to support the re quired functionality . These registers ar[...]

MCF548x Refere nce Manual, Rev . 3 8-10 F reescale Semiconductor The registers in Ta b l e 8 - 7 are accessed through the BDM port by BDM commands, WDMREG and RDMREG , described in Section 8.5.3.3, “Command Set Descriptions .” These commands contain a 5-bit field, DRc, that specifies the register , as shown in Ta b l e 8 - 6 . These registers a[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-11 to guarantee that all accesses to these resources are s erialized and logically consiste nt. The hardware provides a locking mechanis m in the CSR to allow the external development system to disable any attempted writes by the proc essor to the breakpoi[...]

MCF548x Refere nce Manual, Rev . 3 8-12 F reescale Semiconductor Ta b l e 8 - 8 describes CSR fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R BST A T FOF TRG HAL T BKPT HRL 0 BKD0 PCD0 IPW0 W R e s e t 0 00 0 0 0 0 0 0 0 1 00 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MAP TRC EMU DDC UHE BTB 0 NPL 0 SSM O TE 0 0 0 W R e s e t 0 00 0 0 [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-13 18 BKD Breakpoint disable . Us ed to disable the normal BKPT input functionality a nd to allow the asser tion of BKPT to generate a debug interrupt. 0 Normal operation 1 BKPT is edge-sensitive: a high-to-lo w edge on BKPT signals a debug interrupt to th[...]

MCF548x Refere nce Manual, Rev . 3 8-14 F reescale Semiconductor 8.4.3 PC Breakpoint ASID Contr ol Register (PB A C) The PBAC configures the breakpoint qualification for each PC breakpoint regi ster (PBR, PBR1, PBR2, and PBR3). Four bits are dedicated for each breakpoint register and specify how the ASID is used in PC breakpoint qualification. PBR3[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-15 qualification. Reset cl ears these fields, disabling qualifications and defaulting to the Revision C debug module functionality . 8.4.4 BDM Address Attrib ute Register (B AAR) The BAAR defines the addre ss space for memory-referenci ng BDM commands. T o[...]

MCF548x Refere nce Manual, Rev . 3 8-16 F reescale Semiconductor 8.4.5 Address Attrib ute T rigger Registers (AA TR, AA TR1) The AA TR and AA TR1, Figure 8-9 , define address attributes and a mask to be matc hed in the trigger . The register value is compared with address attribute signals from the processor ’ s local high-speed bus, as defined b[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-17 8.4.6 T rigger Definition Register (TDR) The TDR, shown in T able 8-10 , configures the operation of the hard ware breakpoint logi c that corresponds with the ABHR/ABLR/AA TR, PBR/ PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the debug module. In [...]

MCF548x Refere nce Manual, Rev . 3 8-18 F reescale Semiconductor taken under the defined conditions. Br eakpoint logic may be configured as one- or two-level triggers. TDR[31–16] or XTDR[31–16] define second-level triggers, and bits 15–0 define first-level triggers. TDR is accessible in supervisor mode as debug c ontrol register 0x07 using th[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-19 28 EDL W2 Da ta enable bit: Data longword. Entire processor’s local data bus . 27 EDWL2 Data enable bit: Low er data word. 26 ED WU2 Data enable bit: Upper data word. 25 EDLL 2 Data enable bit: Lower lo wer data byte. Low-order b yte of the low-order [...]

MCF548x Refere nce Manual, Rev . 3 8-20 F reescale Semiconductor 8.4.7 Pr ogram Counter Breakpoint and Mask Registers (PBR n , PBMR) Each PC breakpoint register (PBR, PBR1, PBR2, PBR3) defines an instruction a ddress for use as part of the trigger . These registers’ conten ts are compared with th e processor ’ s program counter register when th[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-21 Figure 8-12 shows PBMR. PBMR is accessible in supervis or mode as debug control register 0x09 using the WDEBUG instruction and via the BDM port using the WDMREG command. T able 8-14 describes PBMR fields. 8.4.8 Address Breakpoint Regi ster s (ABLR/ABLR1[...]

MCF548x Refere nce Manual, Rev . 3 8-22 F reescale Semiconductor T able 8-15 describes ABLR and ABLR1 fields. T able 8-16 describes ABHR and ABHR1 fields . 8.4.9 Data Breakpoint and Mask Re gisters (DBR/DBR1, DBMR/DBMR1) The data breakpoint registers (DBR/DBR1, Figure 8-14 ), specify data patterns us ed as part of the trigger into debug mode. DBR n[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-23 T able 8-17 describes DBR n fields. DBMR and DBMR1 are ac cessible in supervisor mode as debug c ontrol register 0x0F and 0x1F , using the WDEBUG instruction and via the BDM port using the WDMREG command. T able 8-18 describes DBMR n fields. 31 30 29 28[...]

MCF548x Refere nce Manual, Rev . 3 8-24 F reescale Semiconductor DBRs support both aligned a nd misaligned references. T able 8-19 shows relationships between processor address, access size, and locati on within the 32-bit data bus. 8.4.10 PC Breakpoint ASID Register (PB ASID) Each PC breakpoint register (PBR, PBR1, PBR2, or PBR3) specifies an inst[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-25 8.4.11 Extended T rigger Definition Register (XTDR) The XTDR configures the operati on of the hardware breakpoint l ogic that corresponds with the ABHR1/ABLR1/AA TR1 and DBR1/DBMR1 registers within the debug module and, in conjunction with the TDR and i[...]

MCF548x Refere nce Manual, Rev . 3 8-26 F reescale Semiconductor T able 8-21 describes XTDR fields. T able 8-21. XTDR Fi eld Descriptions Bits Name Description 31–30 — Reser ved, should be cleared. 29 EBL 2 Enab le breakpoint lev el. If set, EBL2 is the global enab le f or the breakpoint trigg er; that is, if TDR[EBL2] or XTDR[EBL2] is set, a b[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-27 8.4.11.1 Resu lting Set of P oss ible T rigger Combinations The resulting set of possible breakpoint trigger combinations consist of the following options where || denotes logical OR, && denotes logical AND, and {} denotes an optional additional[...]

MCF548x Refere nce Manual, Rev . 3 8-28 F reescale Semiconductor then if (PC_breakpoint || Address1_breakpoint{&& Data1_break point}) if (Address1_breakpoint {&& Data1_breakpoint}) then if (PC_breakpoint || Address_breakpoint{&& Data_breakpo int}) In this example, PC_breakpoint is the logica l summation of the PBR/PBMR, PBR1[...]

Bac kgro und Deb ug Mode ( BDM) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-29 4. The assertion of the BKP T input is treated as a pseudo-in terrupt; that is, asserting BKP T creates a pending halt, which is postponed until the processor core samples for halts/interrupts. The processor samples for these conditions once during the [...]

MCF548x Refere nce Manual, Rev . 3 8-30 F reescale Semiconductor 8.5.2 BDM Serial Interface When the CPU is halted and PSTDDA T A reflects th e halt status, the development system can send unrestricted commands to the debug module. The de bug module implements a s ynchronous protocol using two inputs (DSCLK and DSI) and one output (DSO), wh ere DSO[...]

Bac kgro und Deb ug Mode ( BDM) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-31 . T able 8-22 describes receive BDM packet fields. 8.5.2.2 Transmit P a c ket Format The basic transmit packet, Figure 8-20 , consists of 16 data bits and 1 control bit. T able 8-23 describes transmit BDM packet fields. 8.5.3 BDM Command Set T able 8-24[...]

MCF548x Refere nce Manual, Rev . 3 8-32 F reescale Semiconductor Unassigned command opcodes are re served by Freescale. All unused command formats within any revision level perform a NOP and return the illegal command response . T able 8-24. BDM Command Summary Command Mnemonic De scription CPU State 1 1 General command effect and/or requirements o[...]

Bac kgro und Deb ug Mode ( BDM) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-33 8.5.3.1 ColdFire BDM Command Format All ColdFire Family BDM commands include a 16-bit operation word followed by an optional set of one or more extension words, as shown in Figure 8-21 . T able 8-25 describes BDM fields. 8.5.3.1.1 Extension W ords as Re[...]

MCF548x Refere nce Manual, Rev . 3 8-34 F reescale Semiconductor sends to the debug module; the bo ttom half indicates the debug m odule’ s response to the previous development system commands. Command and resu lt transactions overlap to minimize latency . Figure 8-22. Command Sequence Diagr am The sequence is as follows: • In cycle 1, the deve[...]

Bac kgro und Deb ug Mode ( BDM) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-35 8.5.3.3 Command Set Descriptions The following sections describe the commands summarized in T able 8-24 . NO TE The BDM status bit (S) is 0 for nor mally completed commands. S = 1 for illegal commands, not-ready responses , and transfers with bus-errors[...]

MCF548x Refere nce Manual, Rev . 3 8-36 F reescale Semiconductor Command Format: Command Sequence Figure 8-26. WAREG / WDREG Command Seque nce Operand Data Longword data is wri tten into the specified address or data register . The data is supplied most-significant word first. Result Data Command complete status is i ndicated by returning 0xFFFF (w[...]

Bac kgro und Deb ug Mode ( BDM) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-37 Command Sequence: Figure 8-28. READ Command Seque nce Operand Data The only operand is the longw ord address of the requested location. 15 12 11 8 7 4 3 0 Byte Command 0x1 0x9 0x0 0x0 A[31:16] A[15:0] R e s u l t XXXXXXXX D [ 7 : 0 ] W o rd Command 0x1 [...]

MCF548x Refere nce Manual, Rev . 3 8-38 F reescale Semiconductor Result Data W ord results return 16 bits of data; l ongword results return 32. Bytes are returned in the LSB of a word result, the upper byte is undefined. 0x0001 (S = 1) is returned if a bus error occurs. 8.5.3.3.4 Write Memor y Location ( WRITE ) W rite data to the memory location s[...]

Bac kgro und Deb ug Mode ( BDM) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-39 Command Sequence: Figure 8-30. WRITE Command Se quence Operand Data This two-operand instruction require s a longword absolute a ddress that specifies a location to which the data op erand is to be written. Byte data is sent as a 16-bit word, justified [...]

MCF548x Refere nce Manual, Rev . 3 8-40 F reescale Semiconductor NO TE DUMP does not check for a valid address; it is a valid command only when preceded by NOP , READ , or another DUMP command. Otherwis e, an illegal command response is returned. NOP can be used for intercommand padding without corrupting the address pointer . The size field is exa[...]

Bac kgro und Deb ug Mode ( BDM) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-41 Result Data: Requested data is re turned as either a word or longword. Byte data is returned in the least-significant byte of a word result. W ord results return 16 bits of significant data; longword results return 32 bits. A valu e of 0x0001 (with S se[...]

MCF548x Refere nce Manual, Rev . 3 8-42 F reescale Semiconductor Command Sequence: Figure 8-34 . FILL Command Sequence Operand Data: A single opera nd is data to be writte n to the memory location. Byte data is sent as a 16-bit word, justified in the least-si gnificant byte; 16- and 32-bit operands are sent as 16 and 32 bits, respectively . Result [...]

Bac kgro und Deb ug Mode ( BDM) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-43 Result Data: The command-complete response ( 0xFFFF) is returned during the next shift operation. 8.5.3.3.8 N o Operation ( NOP ) NOP performs no operation and may be us ed as a null command where required. Command Formats: Command Sequence: Figure 8-38[...]

MCF548x Refere nce Manual, Rev . 3 8-44 F reescale Semiconductor Command Sequence: Figure 8-40. SYNC _ PC Command Sequence Operand Data: None Result Data: Command complete status (0xFFFF) is returned when the register write is complete. 8.5.3.3.10 Force T ransfer Ac knowledge ( FORCE _ TA ) DEBUG_D logic implements the new FORCE _ TA serial BDM com[...]

Bac kgro und Deb ug Mode ( BDM) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-45 Figure 8-42. FORC E _ TA Command Sequence Operand Data: None Result Data: The command complete response, 0xFFF F (with the status bit cleared), is returned during the next shift operation. This response indicates the FORCE _ TA command was processed cor[...]

MCF548x Refere nce Manual, Rev . 3 8-46 F reescale Semiconductor T able 8-26. ColdFire CPU Control Register Map Name CPU Space (Rc) Register Name Memory Management Contr ol Registers CA CR 0x002 Cache control regi ster ASID 0x003 Address space identi fier A CR0–ACR3 0x004–0x007 Access control registers 0–3 MMUBAR 0x008 MMU base address regist[...]

Bac kgro und Deb ug Mode ( BDM) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-47 8.5.3.3.12 BDM Accesses of the Stack P ointer Regi sters (A7: SSP and USP) The V ersion 4 ColdFire core supports two unique stack pointer (A7) registers: th e supervisor stack pointer (SSP) and the user stack pointer (USP). The hardware implementation o[...]

MCF548x Refere nce Manual, Rev . 3 8-48 F reescale Semiconductor Likewise, to write an accumulator register , the following BDM sequence is needed: BdmWriteACCx ( rcreg macsr; // read current macsr contents & save wcreg #0,macsr; // disa ble all rounding modes wcreg #data,ACCx; // write the desired accumulator wcreg #saved_data,macsr; // restor[...]

Bac kgro und Deb ug Mode ( BDM) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-49 Command Sequence: Figure 8-46. WCREG Command Sequence Operand Data: This instruction re quires two longword operands. The first selects the register to which the operand data is to be wri tten; the second contains the data. Result Data: Successful write[...]

MCF548x Refere nce Manual, Rev . 3 8-50 F reescale Semiconductor T able 8-27 shows the definition of DRc encoding. Command Sequence: Figure 8-48. RDMR E G Command Sequence Operand Data: None Result Data: The contents of th e selected debug register are retu rned as a longword value. The data is returned most-significant word first. 8.5.3.3.17 Write[...]

Real-Tim e Debu g Support MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-51 Figure 8-50. WDMREG Command Sequence Operand Data: Longword data is written into the specified debug register . The data is supplied most-significant word first. Result Data: Command complete st atus (0xFFFF) is returned when register write is complete. 8.6 R[...]

MCF548x Refere nce Manual, Rev . 3 8-52 F reescale Semiconductor BDM instructions use the appropriate registers to lo ad and configure breakpoints. As the system operates, a breakpoint trigger generates the response defined in TDR. PC breakpoints are treated in a precise manner: ex ception recognition and processing are initiated before the excepti[...]

Real-Tim e Debu g Support MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-53 4. It executes an R TE instruction when the excep tion handler finishes. During the processing of the R TE, FS1 is reloaded from the syst em stack. If this bit is set, the process or sets th e emulator mode state and resumes execution of the original de bug i[...]

MCF548x Refere nce Manual, Rev . 3 8-54 F reescale Semiconductor • Read/write control registers For BDM commands that access memory , the debug m odule requests the processor ’ s local bus. The processor responds by stalling the in struction fetch pipeli ne and waiting for cu rrent bus activity to complete before freeing the local bus for the d[...]

Debug C Definition of PSTD D A T A Outputs MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-55 andi.l #<data>,Dx PSTDDA T A = 0x1 asl.l {Dy ,#<data>},Dx PSTDD A T A = 0x1 asr .l {Dy ,#<d ata>},Dx PSTDD A T A = 0x1 bcc.{b ,w ,l} if taken, then PS TDD A T A = 0x5, else PSTDD A T A = 0 x1 bchg.{b ,l} #<data> ,<e[...]

MCF548x Refere nce Manual, Rev . 3 8-56 F reescale Semiconductor extb .l Dx PSTDD A T A = 0x1 illegal PSTDD A T A = 0x1 1 jmp <ea>y PSTDD A T A = 0x5, {[0x9AB], target address} 2 jsr <ea>y PSTDD A T A = 0x5, {[0x9AB], target address},{0x B , destination o perand} 2 lea.l <ea>y ,Ax PSTDD A T A = 0x1 link.w A y ,# <displacement&g[...]

Debug C Definition of PSTD D A T A Outputs MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-57 ori.l #<data>,Dx PSTDD A T A = 0x1 pea.l <ea>y PSTDD A T A = 0x1,{0xB, destination operand} pulse PSTDD A T A = 0x4 rems.l <ea>y ,Dw:Dx PSTDD A T A = 0x1,{0xB, source operand} remu.l <ea>y ,Dw:Dx PSTDD A T A = 0x1,{0xB[...]

MCF548x Refere nce Manual, Rev . 3 8-58 F reescale Semiconductor T able 8-31 shows the PSTDDA T A specification for multiply-a ccumulate instructions. 1 During nor mal exception processing, the PSTDD A T A output is driven to a 0xC indicating the exception processing state. The e xcep tion stack write operands, as w ell as the ve ctor read an d tar[...]

Debug C Definition of PSTD D A T A Outputs MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-59 T able 8-32 shows the PSTDDA T A specificat ion for floating-point instruct ions; note that <ea>y includes FPy , Dy , A y , and <mem>y addressing modes. The optional operand captur e and display applies only to the <mem>y ad[...]

MCF548x Refere nce Manual, Rev . 3 8-60 F reescale Semiconductor Depending on the size of any extern al memory operand specified by the f<op>.fmt field, the data marker is defined as shown in T able 8-33 . 8.7.2 Supervisor Instruction Set The supervisor instruction set has c omplete access to the user mode instructi ons plus the opcodes shown[...]

ColdFire Debug History MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-61 The move-to-SR and R TE instruct ions include an optional PSTDDA T A = 0x3 value, indicating an entry into user mode. Additionally , if the execution of a R T E instruction returns the pr ocessor to emulator mode, a multiple-cycle status of 0xD is signaled. Simi[...]

MCF548x Refere nce Manual, Rev . 3 8-62 F reescale Semiconductor The data_breakpoint can be included as an optional part of an address breakpoint. The ColdFire debug architectu re was created to provide this set of functionality without requiring the traditional connection to the exte rnal system bus. Rather , the func tionality is provided using o[...]

Freescale-Recommended BDM Pinout MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 8-63 Additionally , the execution of the debug interrupt service routine is fo rced to be interrupt-inhibited by the processor hardware. While in this service routine, ther e is an optional capability to map all instruction and operand references into a sep[...]

MCF548x Refere nce Manual, Rev . 3 8-64 F reescale Semiconductor Figure 8-51. Recommended BDM Connector 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 Developer reserved 1 GND GND RESET VDD_IO 2 GND PSTDDATA6 PSTDDATA4 PSTDDATA2 PSTDDATA0 Freescale reserved GND VDD_CPU BKPT DSCLK Developer reserved 1 DSI DSO PSTDDATA7 PSTDDATA[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor i Part II System Integration Unit Part II describes the system integrat ion unit, which provides overall cont rol of the bus and serves as the interface between the ColdFire core processor complex and internal pe ripheral devices. It includes a general description of the SIU and i ndividua[...]

MCF548x Refere nce Manual, Rev . 3 ii F reescale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 9-1 Chapter 9 System Integration Unit (SIU) 9.1 Intr oduction The system integration unit (SIU) of the MCF548 x family integrates several timer functions required by most embedded systems. The SIU contains the following components: • Slice timers • W atchdog timer • General purpose t[...]

MCF548x Refere nce Manual, Rev . 3 9-2 F reescale Semiconductor 9.3.1 Module Base Address Register (MB AR) The supervisor -level MBAR, Figure 9-1 , specifies the base address a nd allowable access types for all internal peripherals. It is writte n with a MOVEC instruction using th e CPU address 0xC0F (refer to the ColdFir e Family Pr ogrammer ’ s[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 9-3 9.3.1.1 System Breakpoint Control Register (SBCR) The System Breakpoint Control Regi ster allows for discrete contro l over functionality of the BKP T signal. The assertion of the BKP T signal can be programmed to halt the core, DMA, and DSPI or any comb[...]

MCF548x Refere nce Manual, Rev . 3 9-4 F reescale Semiconductor 9.3.1.2 SEC Sequential Access C ontr ol Register (SECSA CR) This register is used to contro l bus accesses to the SEC module. If a sequential accesses to the SEC are enabled, then da ta will be buf fe red to create a single 64-bit access to the SEC instead of splitting up the transfer [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 9-5 9.3.1.3 Reset Status Register (RSR) RSR allows the software, pa rticularly the reset except ion service routine, to know what type of reset has been asserted. When a reset signal is asserted, the associ ated status bit is set, and it maintains its va lue[...]

MCF548x Refere nce Manual, Rev . 3 9-6 F reescale Semiconductor T able 9-5. JT A GID Field Descriptions Bits Name Description 31–0 JTAGID The JT A G Identification Numbe r Register is a read only r egister which conta ins the JT AG ID number f or the MCF548x. Its value is hard co ded and cannot be modified. V a lues f or the MCF548x are the follo[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 10-1 Chapter 10 Internal Cloc ks and Bus Ar chitecture 10.1 Intr oduction This chapter describes the clocking and internal buses of the MCF548 x and discusses the main functional blocks controlling the XL bus and the XL bus arbiter . 10.1.1 Block Diagram Figure 10-1 shows a top-level block[...]

MCF548x Refere nce Manual, Rev . 3 10-2 F reescale Semiconductor 10.1.2 Clocking Overvie w The MCF548 x requires a clock generated ex ternally to be input to the CLKIN signal. The MCF548 x uses this clock as the reference clock for the internal P LL. The internal PLL then generates the clocks needed by the CPU core and integrated peripherals. The e[...]

Introduction MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 10-3 • CommBus — The data transfer interface betw een the multichannel DMA and e ach peripheral function. 10.1.4 XL Bus Features Features of the XL bus and its inte gration modules include the following: • 32-bit physical address • 64-bit data bus width • Split-trans[...]

MCF548x Refere nce Manual, Rev . 3 10-4 F reescale Semiconductor Figure 10-3. Ad dress and Data T enures The following outlines the basic f unctions of each of the phases: • Address tenure: — Arbitration: During arbitration, a ddress bus arbitration signals are used to gain mastership of the address bus. — T ransfer: After mastership is obt a[...]

PLL MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 10-5 10.2 PLL 10.2.1 PLL Memory Map/Register Descriptions 10.2.2 System PLL Contr ol Register (SPCR) The system PLL control register ( SPCR) defines the clock enables used to control cloc ks to a se t of peripherals. Unused peripherals ca n have their clock stopped, reduci ng power con[...]

MCF548x Refere nce Manual, Rev . 3 10-6 F reescale Semiconductor 10.3 XL Bus Arbiter The XL bus arbiter handles bus arbitration between XL bus masters. 10.3.1 Features The arbiter features are as follows: • Eight priority levels • Priority levels may be change d dynamically by XL bus masters • XL bus arbitration support for eight masters • [...]

XL Bus Arbiter MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 10-7 algorithm (LRU). Once a requesting master is identified as having pr iority and is granted the bus, that master will be continue to be granted the bus if: 1. It is requesting the bus. The request must occur immediately after the requi red 1 clock de-assertion after a qu[...]

MCF548x Refere nce Manual, Rev . 3 10-8 F reescale Semiconductor 10.3.2.3 W atchdog Functions 10.3.2.3.1 Timer Functions There are three watchdog timers: addr ess tenure time out, data tenure time out, and bus activity time out. Each has a programmable timer count and can be disable d. A timer time-out will se t a status bit and trigger an interrup[...]

XL Bus Arbiter MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 10-9 10.3.3.1 Arbiter Configu ration Register (XARB_CFG) The arbiter configuration register is used to enable watchdog functions and arbiter protocol functions. 0x258 Arbiter Addre ss Timeout XARB_ADR T O R/W 0x25C Arbiter Data Timeout XARB_D A TT O R/W 0x260 Arbiter Bus Tim[...]

MCF548x Refere nce Manual, Rev . 3 10-10 F re escale Semiconductor 10.3.3.2 Arbiter V ersio n Register (XARB_VER) 4 — Reser ved, should be cleared. 3 BA Bus Activity Time-out Enable. If enabled, the ar biter will set the Bus Activi ty Time-out Status bit (XARB_SR[BA]) when the Bus Activity Time-out is reached. Bus Acti vity Time-out is derived fr[...]

XL Bus Arbiter MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 10-11 10.3.3.3 Arbiter Status Register (XARB_SR) The arbiter status regist er indicates the state of watchdog functions. When a monitored condition occurs, the respective bit is set to 1. The bit will stay set until the bit is cleared by writin g a 1 into that bit. Even if t[...]

MCF548x Refere nce Manual, Rev . 3 10-12 F re escale Semiconductor to determine the state of the arbiter . It is possibl e that multiple conditions exist that would cause an interrupt. Disabling an interrupt by writ ing a 0 to a bit in this register w ill not clear the status bit in the arbiter status register . 31 30 29 28 27 26 25 24 23 22 21 20 [...]

XL Bus Arbiter MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 10-13 10.3.3.5 Arbiter Address Capt ure Register (XARB_ADRCAP) The arbiter address capture register will capture the address for a tenure that has an addr ess time-out, data time-out, or there is a tr ansfer error acknowledge from another source. This valu e is held until un[...]

MCF548x Refere nce Manual, Rev . 3 10-14 F re escale Semiconductor 10.3.3.7 Arbiter Address T enure Time Out Register (XARB_ADRT O) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0000000000000000 W R e s e t 0000000000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R 000000 T S I Z [ 0 : 2 ] — T B S T T T [ 0 : 4 ] W R e s e t 0000000000000000 Reg A[...]

XL Bus Arbiter MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 10-15 10.3.3.8 Arbiter Data T enure Time Out Register (XARB_D A TT O) T able 10-11. XARB_ ADRT O Field Description s Bits Name Description 31–28 — Reser ved, should be cleared. 27–0 ADRT O Upper 28-bits of the Address time-out c ounter value. This field is prepended to[...]

MCF548x Refere nce Manual, Rev . 3 10-16 F re escale Semiconductor 10.3.3.9 Arbiter Bus Activity Time Out Register (XARB_BUST O) 10.3.3.10 Arbiter Master Priority Enable Register (XARB_PRIEN) The arbiter master priority enable register determines whet her the arbiter uses th e hardwired or software programmable priority for a master . The default i[...]

XL Bus Arbiter MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 10-17 When enabled, the software programmable value in th e arbiter master priority register (XARB_PRI) is used as the priority for the master . When disable d, the master ’ s priority is determined as follows: 10.3.3.11 Arbiter Master Prio rity Register (XARB_PRI) The mas[...]

MCF548x Refere nce Manual, Rev . 3 10-18 F re escale Semiconductor T able 10-16. XARB_PRI Field Des criptions Bits Name Description 31–15 — Reser ved, should be cleared. 14–12 M3P Maste r 3 Prior ity 11 — Reser ved, should be cleared. 10–8 M2P M aster 2 Prior ity 7–3 — Reser v ed, should be cleared. 2–0 M0P Master 0 Prior ity[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 11-1 Chapter 11 General Purpose Timer s (GPT) 11.1 Intr oduction This chapter describes th e operation of the MCF548 x general purpose timers. 11.1.1 Overview The MCF548 x has four general-purpose timers ( GP T[0:3] ) that are configurable for the following functions: • Input capture •[...]

MCF548x Refere nce Manual, Rev . 3 11-2 F reescale Semiconductor 6. W atchdog T imer—This is a special CPU timer mode, available only on GP T0. The user must enable the watchdog timer mode, which is not active upon reset. The terminal count value is programmable. If the counter is allowed to expi re, a full reset occurs. T o prevent the watchdog [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 11-3 11.3.1 GPT Enable and Mode Select Register (GMS n ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R OCPW 0 0 OCT 0 0 ICT W R e s e t 0000000000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RW D E N 00 CE 0 SC OD IEN 0 0 GPIO 0 TMS W R e s e t 000000000000[...]

MCF548x Refere nce Manual, Rev . 3 11-4 F reescale Semiconductor 15 WD EN W atchdog enable. Enab les watchdog operation. A timer expiration causes an inter nal MCF548 x reset. W a tchdog operation requires the TMS field be set f or inter nal timer mode and the CE bit to be set. In this mode the OCPW byte field operates as a watchdog reset field. Wr[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 11-5 11.3.2 GPT Counter Input Register (GCIR n ) 8 IEN Inte rrupt enable. Enables interrupt generation to the CPU for all modes ( IC, OC , PWM, and Inter nal Timer ) . IEN is not required for watchdog expir ation to create a reset. 0 Interrupt disabled 1 Int[...]

MCF548x Refere nce Manual, Rev . 3 11-6 F reescale Semiconductor 11.3.3 GPT PWM Configur ation Register (GPWM n ) T able 11- 3. GCIR n Field Descriptions Bits Name Description 31–16 PRE Prescaler . Prescale amount applied to internal counter (in clocks). Note that in addition to other enable bits and field settings, the PRE field must be written [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 11-7 11.3.4 GPT Status Register (GSR n ) 7–1 — Reser v ed. Should be cleared. 0 LOAD Bit forces immediate period update. Bit auto cl ea rs itself. A ne w perio d begins immediately with th e current count and width settings. If LOAD = 0, ne w co unt or w[...]

MCF548x Refere nce Manual, Rev . 3 11-8 F reescale Semiconductor 11.4 Functional Description 11.4.1 Timer Configuration Method Use the following method to configure each timer: 1. Determine the mode select field ( GMS n [TMS] ) value for the desired operation. 2. Program any other registers associated with this mode. 3. Program interrupt enable as [...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 12-1 Chapter 12 Slice Timer s (SL T) 12.1 Intr oduction This chapter explains the operation of the MCF548 x slice timers. 12.1.1 Overview T wo slice timers are included to provide shorter term pe riodic interrupts—SL T0 and SL T1. Each timer consists of a 32-bit counter with no prescale.[...]

MCF548x Refere nce Manual, Rev . 3 12-2 F reescale Semiconductor 12.2.1 SL T T erminal Count Register (STCNT n ) 12.2.2 SL T Control Register (SCR n ) 31 30 29 28 27 26 25 24 23 22 2 1 20 19 18 17 16 RT C W R e s e t 000000000 0000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RT C W R e s e t 000000000 0000000 Reg Addr MBAR + 0x900 (STCNT0), + 0x910 (S[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 12-3 12.2.3 SL T T imer Co unt Register (SCNT n ) T able 12-3. SCR n Field Descriptions Bits Name Description 31–27 — Reser ved, should be cleared. 26 RUN Run or wait mode 0 Timer counter e xpires, but then waits until the timer is cleared (either by wr [...]

MCF548x Refere nce Manual, Rev . 3 12-4 F reescale Semiconductor 12.2.4 SL T Status Register (SSR n ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 000000 B E S T 0000000 0 W R e s e t 0000000000 000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R 000 00000000000 00 W R e s e t 0000000000 000000 Reg Addr MBAR + 0x90C (SSR0 ), + 0x91C (SSR1) Figure 12-4[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 13-1 Chapter 13 Interrupt Contr oller 13.1 Intr oduction This section details the f unctionality for the MCF548 x interrupt controller . The general features of the interrupt controller include: • 63 interrupt sources, or ganized as: — 56 fully-programmabl e interrupt sources — 7 fix[...]

MCF548x Refere nce Manual, Rev . 3 13-2 F reescale Semiconductor and status register data, along with the 32-bit program counter value of the instruction that was interrupted (see Section 3.8.1, “Exception St ack Frame Definition,” for more information on the stack frame format). After the exception stack frame is stored in memory , the process[...]

Introduction MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 13-3 8 fully-programmable interrupt sour ces are mapped into a single interr upt level. The “fixed” interrupt source is hardwired to the given level and represents the mid-point of the priority within the level. For the fully-programmable interrupt sources, the 3-bit level[...]

MCF548x Refere nce Manual, Rev . 3 13-4 F reescale Semiconductor explicitly cleared in the interrupt service routine. This design provi des unique vector capability for all interrupt requests, regardless of the “complexity” of the peripheral device. V ector number 64 is unused. 13.2 Memory Map/Register Descriptions The register programming mode[...]

Memory Map/Regis ter Descriptions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 13-5 13.2.1 Register Descriptions 13.2.1.1 Interrupt Pending Register s (IPRH, IPRL) The IPRH and IPRL registers, Figure 13-1 and Figure 13-2 , are each 32 bits in si ze and provide a bit map for each interrupt request to indicate if there is an active req[...]

MCF548x Refere nce Manual, Rev . 3 13-6 F reescale Semiconductor The IPR is a read-only register , so any attempted writ e to this register is ignor ed. Bit 0 is not implemented and reads as a zero. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R INT[63:48] W R e s e t 0000000000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R INT[47:32] W R e s e t 0[...]

Memory Map/Regis ter Descriptions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 13-7 13.2.1.2 Interrupt Mask Reg ister (IMRH, IMRL) The IMRH and IMRL registers are each 32 bits in size and provide a bit map for ea ch interrupt to allow the request to be disabled (1 = di sable the request, 0 = enable the reque st). The IMR is se t to a[...]

MCF548x Refere nce Manual, Rev . 3 13-8 F reescale Semiconductor 13.2.1.3 Interrupt Force Re gister s (INTFRCH, INTFRCL) The INTFRCH and INTFRCL registers ar e each 32 bits in size and provi de a mechanism to allow software generation of interrupts for each po ssible source for functional or de bug purposes. The system design may reserve one or mor[...]

Memory Map/Regis ter Descriptions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 13-9 . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R INTFRC[63:48] W R e s e t 0000000000000000 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 R INTFRC[47:32] W R e s e t 0000000000000000 Reg Addr MBAR + 0x710 Figure 13-5. Interrupt For ce Register High (INTFR[...]

MCF548x Refere nce Manual, Rev . 3 13-10 F re escale Semiconductor 13.2.1.4 Interrupt Request L evel Register (IRLR) This 7-bit register is upda ted each machine cycle a nd represents the current interrupt requests for each interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc. 13.2.1.5 Interrupt Acknowledge Level and Priority [...]

Memory Map/Regis ter Descriptions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 13-11 13.2.1.6 Interrupt Cont r ol Register s 1–63 (ICR n ) Each ICR n specifies the interrupt level (1–7) and th e priority within th e level (0–7). All ICR n registers can be read, but only ICR8 to ICR63 ca n be written. It is software’ s respons[...]

MCF548x Refere nce Manual, Rev . 3 13-12 F re escale Semiconductor 13.2.1.6.1 Interrupt Sources T able 13-12 lists the interrupt sources fo r each interrupt request line T able 13-12. I nterrupt Sour ce Assignments Sourc e Module Flag Source Description Flag Clearing Mechan ism 1 EPORT EPF1 Edge por t flag 1 Write ‘ 1’ to EPFR[EPF1] 2 EPF2 Edge[...]

Memory Map/Regis ter Descriptions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 13-13 13.2.1.7 Software and Level n IA CK Registers (SWIA CKR, L1IA CK–L7IA CK) The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed via a processor-generated interrupt acknowledge cycle during exception processing. I[...]

MCF548x Refere nce Manual, Rev . 3 13-14 F re escale Semiconductor determines the highest pr iority within the level, and then re sponds with the unique vector number corresponding to that specific interrupt source. The vector number is suppl ied as the data for the byte-sized IACK read cycle. In addition to pr oviding the vector number , the inter[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 14-1 Chapter 14 Edge P or t Module (EPORT) 14.1 Intr oduction The edge port module (EPOR T) has se ven external interrupt pins, IRQ [7:1]. Each pin can be configured individually as a level-sensitive inte rrupt pin, an edge-detecting interrupt pin (rising edge , falling edge, or both), or [...]

MCF548x Refere nce Manual, Rev . 3 14-2 F reescale Semiconductor NO TE The GPIO functionality of the external interrupt pins is controlled by the EPOR T module. However , some extern al interrupt signals are muxed with other functions. In this case, the pin’ s IRQ functionality must be enabled in the GPIO module’ s pin assignment regist er in o[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 14-3 14.3.2.1 EPORT Pin Assignm ent Register (EPP AR) 14.3.2.2 EPORT Data Dir ection Register (EPDDR) 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R EPP A7 EPP A6 EPP A5 EPP A4 EPP A3 EPP A2 EPP A1 0 0 W R e s e t 0000000000000000 Reg Addr MBAR + 0xF00 Figure 14-2. EP[...]

MCF548x Refere nce Manual, Rev . 3 14-4 F reescale Semiconductor 14.3.2.3 Edg e P ort Interrupt Enable Register (EPIER) 14.3.2.4 Edg e P ort Data Reg ister (EPDR) T able 14-3. EPDDR Field Descriptions Bits Name Description 7–1 EPDD n Setting any bit in the EPDDR configures the corr esponding pin as an output. Clear ing any bit in EPDDR configures[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 14-5 14.3.2.5 Edg e P or t Pin Data Register (EPPDR) 14.3.2.6 Edg e P ort Flag Register (EPFR) T able 14-5. EPDR Field Descriptions Bits Name Description 7–1 EPDx Edg e por t data bits. Data written to EPDR is stored in an inter nal register ; if any pin o[...]

MCF548x Refere nce Manual, Rev . 3 14-6 F reescale Semiconductor T able 14-7. EPFR Field Descript ions Bits Name Description 7–1 EPF n Edge por t flag bits. When an EPOR T pin is configured for edge triggering, its corresponding read/write bit in EPFR indicates th at the selected edge has been detected. Reset clears EPF7–EPF1. Bits in this regi[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-1 Chapter 15 GPIO 15.1 Intr oduction Many of the MCF548 x pins whose primary functio n is to serve as the exte rnal interface to off-chip resources may also be used for general-purpose digi tal I/O (GPIO) acc ess and for one or two secondary functions. When used for GPIO purposes, the p[...]

MCF548x Refere nce Manual, Rev . 3 15-2 F reescale Semiconductor Figure 15-1. MCF548 x GPIO Module Block Di agram 15.1.1 Overview The MCF548 x GPIO module controls the c onfiguration and use for the following external GPIO ports (register types in parentheses): • ColdFire bus (FlexBus) accesses (FBCTL, FBCS) DACK [1:0] / PDMA[3: 2] FBCS [5:1] / P[...]

External Pin Description MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-3 • External DMA request and acknowledge (DMA) • PCI bus access (PCIGNT, PCIREQ) • Ethernet data and control (FEC0H , FEC0L, FEC1H, FEC1L, FECI2C) •I 2 C serial control (FECI2C) • DMA serial peripheral interface (DSPI) • Programmable serial cont rol [...]

MCF548x Refere nce Manual, Rev . 3 15-4 F reescale Semiconductor DAC K 0 PDMA2 T OUT0 — DMA acknowledge 0 / P or t DMA2 / GP timer output 0 DREQ1 PDMA1 TIN1 IRQ1 DMA request 1 / P or t D MA1 / GP timer input 1 / Interru pt 1 DREQ0 PDMA0 TIN0 — DMA request 0 / P or t DMA0 / GP timer input 0 Fast Ethernet Controller 0 FEC0TXCLK PFEC0H7 — — Et[...]

External Pin Description MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-5 FEC1MDC — SCL CANTX0 Ethernet Controller 1 manag ement data clock / I 2 C serial clock / Fle xCAN 0 transmit data I 2 C Serial Control SDA PFECI2C1 — — I 2 C serial data / P or t FECI2C1 SCL PFECI2C0 — — I 2 C serial clock / P or t FECI2C0 External I[...]

MCF548x Refere nce Manual, Rev . 3 15-6 F reescale Semiconductor Refer to the signals chapter of the MCF548 x chip specification for more de tailed descriptions of these signals. The function of most of th e pins (primary function, GPIO, etc. ) is determined by the GPIO module pin assignment registers. PSC1R TS PPSC1PSC06 PSC1FSYNC — PSC1 request[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-7 It should be noted from T able 15-1 that there are several cases wher e a function is mapped to more than one pin. While it is possibl e to enable the function on more than one pin simultaneously , this type of programming should be avoided for input fu[...]

MCF548x Refere nce Manual, Rev . 3 15-8 F reescale Semiconductor 15.3.2 Register Descriptions 15.3.2.1 P or t x Output Data Registers (PODR_ x ) The PODR registers stor e the data to be driv en on the corresponding port x pins when the pins are configured for general purpose output. 0xA08 PODR_FECI2C PODR_PCIBG PODR_PCIBR Reser ved 3 S/U 0xA0C PODR[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-9 Most PODR_ x registers have full 8-bit implementations, as shown in Figure 15-2 . The remaining PODR_ x registers use fewer than eight bi ts. These registers are shown in Figure 15-3 , Figure 15-4 , Figure 15-5 , and Figure 15-6 . The PODR_ x registers [...]

MCF548x Refere nce Manual, Rev . 3 15-10 F re escale Semiconductor 15.3.2.1.3 5-Bit PODR_ x Registers The 5-bit PODR_ x registers are the output data registers for PPCIBG n (PODR_PCIBG) and PPCIBR n (PODR_PCIBR). Figure 15-4 displays the 5-bit PODR_ x registers. 15.3.2.1.4 4-Bit PODR_ x Registers The 4-bit PODR_ x registers are the output data regi[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-11 15.3.2.1.5 FBCS Regi ster (PODR_FBCS) The 5-bit PODR_FBCS register is the output data register for PFBCS n (PODR_FBCS). Figure 15-6 displays the 5-bit PODR_FBCS register . 15.3.2.2 P or t x Data Direction Registers (PDDR_ x ) The PDDR registers control[...]

MCF548x Refere nce Manual, Rev . 3 15-12 F re escale Semiconductor Most PDDR_ x registers have a full 8-bi t implementation, as shown in Figure 15-7 . The remaining PDDR_ x registers use fewer than eight bits . Their bit definitions are shown in Figure 15-8 , Figure 15-9 , Figure 15-10 , and Figure 15-1 1 . The PDDR_ x registers are read/write. At [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-13 15.3.2.2.3 5-Bit PDDR_ x Registers The 5-bit PDDR_ x registers are the data di rection registers for PPCIBG n (PDDR_PCIBG) and PPCIBR n (PDDR_PCIBR). Figure 15-9 displays the 5-bit PDDR_ x registers. 15.3.2.2.4 4-Bit PDDR_ x Registers The 4-bit PDDR_ x[...]

MCF548x Refere nce Manual, Rev . 3 15-14 F re escale Semiconductor 15.3.2.2.5 FBCS Regi ster (PDDR_FBCS) The 5-bit PDDR_FBCS register is for data direction of PFBCS n . Figure 15-1 1 displays the 5-bit PDDR_FBCS register . 15.3.2.3 P or t x Pin Data/Set Data Registers (PPDSDR_ x ) The PPDSDR registers reflect the current pin states and control the [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-15 Most PPDSDR_ x registers have a full 8-bi t implementation, as shown in Figure 15-12 . The remaining PPDSDR_ x registers use fewer than eight bits . Their bit definitions are shown in Figure 15-13 , Figure 15-14 , Figure 15-15 , and Figure 15-16 . The [...]

MCF548x Refere nce Manual, Rev . 3 15-16 F re escale Semiconductor 15.3.2.3.3 5-Bit PPDSDR_ x Registers The 5-bit PPDSDR_ x registers are the pi n data and set data registers for PPCIBG n (PPDSDR_PCIBG) and PPCIBR n (PPDSDR_PCIBR). Figure 15-14 displays the 5-bit PPDSDR_ x registers. 76543210 R 0 PPDx6 PPDx5 PPDx4 PPDx3 PPDx2 PPDx1 PPDx0 W PSDx6 PS[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-17 15.3.2.3.4 4-Bit PPDSDR_ x Registers The 4-bit PPDSDR_ x registers are the pin data a nd set data registers for PDMA n (PPDSDR_DMA) and PFECI2C n (PPDSDR_FECI2C). Figure 15-15 displays the 4-bit PPDS DR_DMA and PPDSDR_FECI2C registers. 15.3.2.3.5 FBCS [...]

MCF548x Refere nce Manual, Rev . 3 15-18 F re escale Semiconductor 15.3.2.4 P or t x Clear Output Data Registers (PCLRR_ x ) W riting 0s to a PCLRR_ x register clears the corresponding bits in the PODR_ x register . Wr iting 1s has no effect. Reading the PCLRR_ x register returns 0s. Most PCLRR_ x registers have a full 8-bi t implementation, as sho[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-19 15.3.2.4.1 7-Bit PCLRR_ x Register The 7-bit PCLRR _ DSPI register is the clear output data register for PDSPI n . Figure 15-18 displays the 7-bit PCLRR _ DSPI register . 15.3.2.4.2 5-Bit PCLRR_ x Registers The 5-bit PCLRR_ x registers are the pin data[...]

MCF548x Refere nce Manual, Rev . 3 15-20 F re escale Semiconductor 15.3.2.4.3 4-Bit PCLRR_ x Registers The 4-bit PCLRR_ x registers are the clear out put data registers for PDMA n (PCLRR_DMA) and PFECI2C n (PCLRR_FECI2C). Figure 15-20 displays the 4-bit PCLRR_ x registers. 15.3.2.4.4 5-Bit PCLRR _ FBCS Registers The 5-bit PCLRR_FBCS regi ster is th[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-21 15.3.2.5 P or t x Pin Assignment Registers (P AR_ x ) The P AR_ x registers select the signal function th at will be driven on the physical pin. 15.3.2.5.1 FlexBus Contr ol Pin A ssignment Register (P AR_FBCTL) The FlexBus control pin assignment (P AR_[...]

MCF548x Refere nce Manual, Rev . 3 15-22 F re escale Semiconductor 15.3.2.6 FlexBus Chip Select Pin Assignment Register (P AR_FBCS) The P AR_FBCS register controls the function of the FlexBus chip select signal pins. The P AR_FBCS register is read/write. 12 P AR_BWE2 The P A R_BWE bit configures the BE2 /BWE2 pin for its primary function or general[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-23 15.3.2.7 DMA Pin Assig nment Register (P AR_DMA ) The P AR_DMA register controls the function of the four MCF548 x DMA pins. The P AR_DMA register is read/write 15.3.2.8 FEC/I2C/IRQ Pin Assig n ment Register (P AR_FECI2CIRQ) The P AR_FECI2CIRQ register[...]

MCF548x Refere nce Manual, Rev . 3 15-24 F re escale Semiconductor 1 5 1 41 3 1 2 1 1 1 0 9876543210 RP A R _ E07 PA R _ E0MII PA R _ E0MDIO PA R _ E0MDC PA R _ E17 PA R _ E1MII P AR_E1MDIO P AR_E1MDC 0 0 P AR_ SD A PA R _ SCL PA R _ IRQ6 PA R _ IRQ5 W R e s e t 00 0 0 001111000011 Reg Addr MBAR + 0xA44 (P AR_FECI2CIRQ) Figure 15-25. FEC/I2C/IRQ Pi[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-25 15.3.2.9 PCI Grant Pin Assignm ent Register (P AR_PCIBG) The P AR_PCIBG register controls the functions of the PCI grant pins. Th e P A R_PCIBG register is read/write. 3 P AR_ SD A SD A Pin Assignment. Configures th e SD A pin for its primar y function[...]

MCF548x Refere nce Manual, Rev . 3 15-26 F re escale Semiconductor 15.3.2.10 PCI Request Pin Assi gnment Register (P AR_PCIBR) The P AR_PCIBR controls the functions of the PC I request pins. The P AR_PCIBR is read/write. 5–4 P AR_ PCIBG2 PCIBG2 pin assignment. Confi gures the PCIBG2 pin for one of its pr imar y functions or GPIO. 0X PCIBG2 pin co[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-27 15.3.2.11 PSC3 Pin Assignm ent Register (P AR_PSC3) The P AR_PSC3 register controls th e functions of the PSC3 pins. The P AR_PSC3 register is read/write. 3–2 PAR_PCIBR1 PCIBR1 Pin Assignment. Configu res the PCIBR1 pin for one of its primar y functi[...]

MCF548x Refere nce Manual, Rev . 3 15-28 F re escale Semiconductor 15.3.2.12 PSC2 Pin Assignm ent Register (P AR_PSC2) The P AR_PSC2 register controls th e functions of the PSC2 pins. The P AR_PSC2 register is read/write. 15.3.2.13 PSC1 Pin Assignm ent Register (P AR_PSC1) The P AR_PSC1 register controls th e functions of the PSC1 pins. The P AR_PS[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-29 15.3.2.14 PSC0 Pin Assignm ent Register (P AR_PSC0) The P AR_PSC0 register controls th e functions of the PSC0 pins. The P AR_PSC0 register is read/write. 76543210 R P AR_CTS1 P AR_R TS1 P AR_RXD1 P AR_TXD1 0 0 W R e s e t 00000000 Reg Addr MBAR + 0xA4[...]

MCF548x Refere nce Manual, Rev . 3 15-30 F re escale Semiconductor 15.3.2.15 DSPI Pin Assignment Register (P AR_DSPI) The P AR_DSPI register contro ls the functions of MCF548 x DSPI pins. The P A R_DSPI register is read/write. T able 15-33. P AR_PCS0 Descriptions Bits Name Description 7–6 PAR_ CTS0 PSC0CTS pin assignment. Con figures the PSC0CTS [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-31 15.3.2.16 General Purpose Timer Pin Assignment Register (P AR_TIMER) The P AR_TIMER register contro ls the functions of MCF548 x general purpose timer pins. The P AR_TIMER register is read/write. 11–10 P AR_CS3 DSPICS3 pin assignment. Configures the [...]

MCF548x Refere nce Manual, Rev . 3 15-32 F re escale Semiconductor NO TE Explicit pin function assignment cap ability for the TIN1, T OUT1, TIN0, and TOUT0 pins is not needed in th e GPIO module since these pins only have the primary timer functions and general pu rpose I/O. Switching between the primary timer functions a nd GPIO is handled by the [...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 15-33 (PPDSDR_x) to monitor and control the stat e of its pins. Data written to a PODR_ x register is stored and then driven to the corresponding port x pins configured as outputs. Reading a PODR_ x register returns the current state of the register regardless of th[...]

MCF548x Refere nce Manual, Rev . 3 15-34 F re escale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor i Part III On-Chip Integration Part III describes on-chip integration for the MCF548 x device. It includes descriptions of the system SRAM, SDRAM controller , PCI, Fl exBus interface, FlexCAN, SEC cryptography accelerator , and JT AG . Contents Part III contains the following chapters: •[...]

MCF548x Refere nce Manual, Rev . 3 ii F reescale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 16-1 Chapter 16 32-Kb yte System SRAM 16.1 Intr oduction This chapter explains the operation of the MCF548 x 32-Kbyte system SRAM. 16.1.1 Block Diagram The system SRAM is organized as f our 8-Kbyte banks, each or ganized as 2048 × 32-bits. The four banks occupy a contiguous block of memor[...]

MCF548x Refere nce Manual, Rev . 3 16-2 F reescale Semiconductor The system SRAM contents always reside at MBAR + 0x0001 0000; ther efore, it can be relocated by changing the MBAR contents. 16.1.2 Features The 32-Kbyte system SRAM is intende d primarily as a fast scratch me mory and data buf fer for DMA and SEC processing, and as memory ac cessed t[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 16-3 16.2.1 System SRAM Config uration Register (SSCR) This register is used to define the base address of the system SRAM and whether to interleave the banks. Each field is described in T able 16-2 . 0x1_FFCC T ransf er Count Conf igu ration Register - DMA [...]

MCF548x Refere nce Manual, Rev . 3 16-4 F reescale Semiconductor 16.2.2 T ransfer Count Config uration Register (TCCR) This register is used to confi gure the allocated maximum transfer count for each bank for the following masters: the ColdFire core, DMA, SEC, or PCI. This occurs as they access memory through the shared system bus. The DMA and the[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 16-5 16.2.3 T ransfer Count Configu rat ion Register—DMA Read Channel (TCCRDR) This register is used to config ure the allocated maximum transfer count for each bank for the DMA read channel as it accesses SRAM directly , without going through the system b[...]

MCF548x Refere nce Manual, Rev . 3 16-6 F reescale Semiconductor 16.2.4 T ransfer Count Configu rat ion Register—DMA Write Channel (TCCRD W) This register is used to configure the allocated ma ximum transfer count for each bank of the DMA write channel as it accesses SRAM directly , without going through the system bus. Each field is described in[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 16-7 16.2.5 T ransfer Count Configu r ation Register—SEC (TCCRSEC) This register is used to configur e the allocated maximum transfer c ount for each bank for the SEC as it accesses SRAM directly , without going through the system bus. Each field is descri[...]

MCF548x Refere nce Manual, Rev . 3 16-8 F reescale Semiconductor 16.3 Functional Description The system SRAM decodes the addre sses for all four banks to determin e wh ich master is trying to access which bank. The system SRAM modul e provides a bus arbitr ation mechanism for gr anting access of each bank to each master . All masters si mply reques[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-1 Chapter 17 Flex Bus 17.1 Intr oduction This chapter describes d ata transfer operations, error conditi ons, and reset operations. It describes transfers initiated by the MCF548 x and includes detailed timing diagrams showing the interaction of signals in supported bus operations. NO T[...]

MCF548x Refere nce Manual, Rev . 3 17-2 F reescale Semiconductor 17.2 Byte Lanes Figure 17-1 shows the byte lanes that extern al memory should be connected to and the sequential transfers if a longword is transferred for three port sizes. Fo r example, an 8-bit memory should be connected to AD[31:24] (BE /BWE0 ). A longword transfer take s four tra[...]

External Signals MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-3 Figure 17-2 . Multiple xed FlexBu s Implementat ion 17.4 External Signals This section describes the external signals th at are involved in data transfer operations. T able 17-1 summarizes the MCF548 x FlexBus signals. T able 17-1. Fle xBus Signal Summary Signal Name [...]

MCF548x Refere nce Manual, Rev . 3 17-4 F reescale Semiconductor 17.4.1 Chip-Select (FBCS [5:0]) The chip-select signal indicates whic h device is being selected. A partic ular chip-select asserts when the transfer address is within the device ’ s address space as defined in the ba se and mask addre ss registers, see Section 17.5.2, “Chip-Selec[...]

External Signals MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-5 For aligned transfers larger than the port size, TSIZ[1:0] behaves as follows: • If bursting is used, TSIZ[1:0] is driven to the size of transfer . • If bursting is inhibited, TSIZ[1:0] first shows the si ze of the entire transfer and then shows the port size. For[...]

MCF548x Refere nce Manual, Rev . 3 17-6 F reescale Semiconductor 17.5 Chip-Select Operation Each chip-select has a dedicated set of the foll owing registers for conf iguration and control: • Chip-select address registers (C SARn) control the base address space of the chip-select. See Section 17.5.2.1, “Chip-Select Addre ss Registers (CSAR0–CS[...]

Chip-Select Operation MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-7 17.5.2 Chip-Select Register s The following tables describe in detail the registers and bit meanings for confi guring chip-select operation. The chip-select controller register map is accessed re lative to the memory base address register (MBAR). T able 17-6 show[...]

MCF548x Refere nce Manual, Rev . 3 17-8 F reescale Semiconductor 1 The access column indicates whether the corresponding regist er allows both read/wr ite functionality (R/W), read-only functionality (R), or wr ite-only function ality (W). A read access to a write-only reg ister returns zeros . A write a ccess to a read-only register has no effect.[...]

Chip-Select Operation MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-9 17.5.2.2 Chip-Select Mask Register s (CSMR0–CSMR5) CSMR n , Figure 17-4 , are used to specify the address mask and allowable access types for the respective chip-selects. T able 17-8 describes CSMR fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 7 16 R BAM [...]

MCF548x Refere nce Manual, Rev . 3 17-10 F re escale Semiconductor 17.5.2.3 Chip-Select Control Registers (CSCR0–CSCR5) Each CSCR n , Figure 17-5 , controls the auto acknowledge, addre ss setup and hold times, port size, burst capability , and activation of each chip-select. Note that to supp ort the global chip-select, FBCS0 , the CSCR0 reset va[...]

Chip-Select Operation MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-11 19–18 RDAH Read Address Hold or (Deselect). This field controls th e address and attribute hold time after the ter mination during a read cycle that hits in the chip-select address space. The hold time only applies at the end of a transf er . Therefore , a bur[...]

MCF548x Refere nce Manual, Rev . 3 17-12 F re escale Semiconductor 17.6 Functional Description 17.6.1 Data T ransfer Operation Data transfers between the MCF548 x and other devices involve the following signals: • Address/data bus (AD[31:0]) • Control signals (ALE and T A) •F B C S n •O E •B E /BWE [3:0] • Attribute signals (R/W , TBST [...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-13 Figure 17-6. Connections for External Memory P ort Sizes 17.6.3 Address/Data Bus Multiple xing The MCF548 x FlexBus uses a 32-bit wide multiplexed addr ess and data bus (AD[31: 0]). The full 32-bit address will always be driv en on the first clock of a bus cyc[...]

MCF548x Refere nce Manual, Rev . 3 17-14 F re escale Semiconductor 4. FBCS n is negated at the fourth rising clock edge. This last clock of the bus cycle uses what would be an idle clock between cycles to provide hol d time for address, attr ibutes, and write data. 17.6.4.1 Data T ransfer Cyc le States The data transfer ope ration in the MCF548 x i[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-15 17.6.5 Fle xBus Timing Examples 17.6.5.1 Basic Read Bus C yc le During a read cycle, the MCF548 x receives data from memory or from a peripheral device. Figure 17-8 is a read cycle flowchart. NO TE Throughout this chapter AD[ X :0] is used to indicate an addre[...]

MCF548x Refere nce Manual, Rev . 3 17-16 F re escale Semiconductor Figure 17-9. Ba sic Read Bus Cyc le 17.6.5.2 Basic Write Bus C yc le During a write cycle, the MCF548 x sends data to memory or to a peripheral device. The write cycle flowchart is shown in Figure 17-10 . NO TE Throughout this chapter AD[ X :0] is used to indicate an address bus tha[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-17 The write cycle timing diagram is shown in Figure 17-1 1 . Figure 17-11. Basic Wri te Bus Cycle 17.6.5.3 Bus Cycle Multiple xing This section shows timing diagrams for various port size scenarios. Figure 17-12 illustrates the basic word read transfer to a 16-b[...]

MCF548x Refere nce Manual, Rev . 3 17-18 F re escale Semiconductor Figure 17-12. Single W ord Read T ransfer with Muxed 32- A / 16-D or Non-Mu xed 16-A / 16 -D Figure 17-13 shows the similar configuration for a write transfer . The data is driven from the second clock on AD[31:16]. Figure 17-13. Si ngle W ord Write T ransfer with Muxed 32 -A / 16-D[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-19 Figure 17-14 illustrates the basic byte read transfer to an 8-bit device with no wait s tates. The address is driven on the full AD[31:0] bus in the first clock. The MCF548 x tristates AD[31:24] on the second clock and continues to drive address on AD [23:0] t[...]

MCF548x Refere nce Manual, Rev . 3 17-20 F re escale Semiconductor Figure 17-15. Si ngle Byte Write T ransfer with Muxed 32-A / 8-D or Non-Mux ed 24-A / 8-D Figure 17-16 depicts a longword read through a 32-bit device. Notice that when the device port size is 32 bits, the only mode the bus supports is multiplexing address and data lines. Figure 17-[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-21 Figure 17-17 illustrates the longword write to a 32-bit device. Figure 17-17. Longw ord Write T ransfer with Muxed 32-A / 32-D 17.6.5.4 Timing V ariations The MCF548 x has several features that can be used to change the timing ch aracteristics of a bas ic read[...]

MCF548x Refere nce Manual, Rev . 3 17-22 F re escale Semiconductor Figure 17-18. Basi c Read Bus Cyc le (No W ait States) Figure 17-19. Basic Write Bus Cyc le (No W ait States) If wait states are used, then the S1 state will repeat continuous ly until either the internal T A is asserted by the chip select auto-acknowl edge unit or the external T A [...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-23 Figure 17-20 . Read Bus Cyc le (One W ait State) Figure 17-21. Write Bus Cyc le (One W ait State) 17.6.5.4.2 A ddress Setup and Hold The timing of the assertio n and negation of the chip selects, byte selects, and output enable can be programmed on a chip sele[...]

MCF548x Refere nce Manual, Rev . 3 17-24 F re escale Semiconductor Figure 17-22 . Read Bus Cycle with T wo Clock Address Setup (No W ait St ates) Figure 17-23. Wri te Bus Cycl e with T wo Cloc k Addres s Setup (No W ait States) In addition to address set up, there is also a programma ble address hold option for ea ch chip select. Address and attrib[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-25 Figure 17-24. Re ad Cycl e with T wo Clock Address Hold (No W ait States) Figure 17-25. Write Cyc le with T wo Cloc k Address Hold (No W ait States) Figure 17-26 shows a bus cycle that uses addres s setup, wait states, and address hold. CLK AD[ X :0] AD[31: Y [...]

MCF548x Refere nce Manual, Rev . 3 17-26 F re escale Semiconductor Figure 17-26. Write Cyc l e with T wo Cloc k Address Setup and T wo Cl ock Hold (One W ait State) 17.6.6 Burst Cyc les The MCF548 x can be programmed to in itiate burst cycles if its transfer size exceeds the size of the port it is transferring to. The initia tion of a burst cycle i[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-27 NO TE Line-sized transfers requested by the core or cache are broken up into four individual longword transfers, but the DMA can request line -sized transfers when the read line or combine wr ite flags are set. See Section 24.4.9, “Line Buffers,” for more [...]

MCF548x Refere nce Manual, Rev . 3 17-28 F re escale Semiconductor Figure 17-28. Lo ngwor d Write Burst to 8-Bit P or t 3-1-1-1 (No W ait States) Figure 17-29 shows a longword read through an 8-bit device with burst inhibited. Th e transfer results in four individual transfers. Notice that the transfer size is driven at l ongword (2’b00) during t[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-29 Figure 17-30 shows a longword write through an 8-bit device with burst inhi bited. The transfer results in four individual transfers. Notice that the transfer size is driven at l ongword (2’b00) during the first transfer and at byte (2’b01) during the next[...]

MCF548x Refere nce Manual, Rev . 3 17-30 F re escale Semiconductor Figure 17-31 illustrates a write burst trans fer with one wait state. Figure 17-32. Longw ord Write Burst to 8-Bit P o rt 4-2-2-2 (One W ait State) If address setup and hold are used, only the first and last beat of the burst cycle w ill be af fected as shown in Figure 17-33 . Figur[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 17-31 Figure 17-34. Longw or d Write Burst to 8-Bit P or t 4-1-1-1 (Address Setup and Hold) 17.6.7 Misaligned Operands Because operands, unlike opc odes, can reside at any byte boundary , th ey are allowed to be misaligned. A byte operand is properly aligned at any [...]

MCF548x Refere nce Manual, Rev . 3 17-32 F re escale Semiconductor Figure 17-36. Examp le of a Misaligne d W ord T ransfer (32-Bit P or t) 17.6.8 Bus Error s The MCF548 x has no bus monitor . If the auto-acknowledge feature is not enabled for the address that generates the error , the bus cycle can be terminated by asserting T A or by using the sof[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-1 Chapter 18 SDRAM Contr oller (SDRAMC) 18.1 Intr oduction This chapter describes configurat ion and operation of the synchrono us DRAM (SDRAM) controller . It begins with a general overview a nd includes a description of signals involved in SDRAM operations. The remainder of the chapte[...]

MCF548x Refere nce Manual, Rev . 3 18-2 F reescale Semiconductor 18.2.3 Block Diagram Figure 18-1. SDRAM Contr oller Block Diagram 18.3 External Signal Description 18.3.1 SDRAM Data Bus (SDD A T A[31:0]) SDDA T A[31:0] is the bidirectional, non-multiplexed data bus used for SDRAM accesses. Data is sampled by the MCF548 x on the rising edge of SDCLK[...]

External Signal Description MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-3 18.3.4 SDRAM Row Ad dress Str o be (RAS ) This output is the SDRAM s ynchronous row address strobe. 18.3.5 SDRAM Column Address Str obe (CAS ) This output is the SDRAM sync hronous column address strobe. 18.3.6 SDRAM Chip Selects (SDCS [3:0]) These signals [...]

MCF548x Refere nce Manual, Rev . 3 18-4 F reescale Semiconductor 18.3.12 SDRAM Cloc k Enable (SDCKE) This output is the SDRAM clock enable. SDCKE nega tes to put the SDRAM into low-power , self-refresh mode. 18.3.13 SDR SDRAM Da ta Str obe (SDRDQS) This is connected to SDDQS inputs. It is used in SDR mode only . 18.3.14 SDRAM Memory Supply (SD V DD[...]

Interface Recommendations MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-5 All memory devices of a si ngle chip select block must have the same configuration and row/col address width; however , this is not necessa ry between different bl ocks. If mixing dif feren t memory organizations in diff erent blocks, the following guidelines[...]

MCF548x Refere nce Manual, Rev . 3 18-6 F reescale Semiconductor 18.4.2 SDRAM SD R Connections Figure 18-2 shows a block diagram of the connections between the MCF548 x and SDR SDRAM components. SDR design requires sp ecial timing consideration for th e SDDQS[3:0] signals. For reads from DDR SDRAMs, the memory will drive the DQS pins so that th e d[...]

Interface Recommendations MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-7 Figure 18-3. MCF548 x Connections to DDR SDRAM 18.4.4 SDRAM DDR DIMM Connections There is a JEDEC standard for a 100-pin DDR DIMM with a 32-bit wide data bus. This DIMM standard was designed specifically to support 32-bit processors. The MCF548 x can support [...]

MCF548x Refere nce Manual, Rev . 3 18-8 F reescale Semiconductor Figure 18-4. MCF548 x Connections to 100-pin DDR SDRAM DIMM 18.4.5 DDR SDRAM La y o ut Considerations Due to the critical timing for DDR SDRAM, there are a number of consid erations that should be taken into account during PCB layout: • Minimize overall trace lengths. • Each DQS, [...]

SDRAM Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-9 18.4.5.1 T ermination Example Figure 18-5 shows the recommended termination circuitry for DDR SDRAM signals. Figure 18-5. MCF548 x DDR SDRAM T ermination Circuit 18.5 SDRAM Overview 18.5.1 SDRAM Commands When an internal bus master accesses SDRAM addr ess space, the mem[...]

MCF548x Refere nce Manual, Rev . 3 18-10 F re escale Semiconductor Many commands require a delay befo re the next command may be issued; sometimes the delay depends on the type of the next command. These delay requirements are manage d by the values programmed in the memory controller configurat ion registers (SDCFG1, SDCFG2). 18.5.1.1 Row and Bank[...]

SDRAM Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-11 issue a P ALL command to close the active row . Then the SDRAMC issu es ACTV to activate the necessary row and bank for the new access, followed finally by the WRITE command. The P ALL and ACTV commands (if ne cessary) can sometimes be issued in parallel with an on-goi[...]

MCF548x Refere nce Manual, Rev . 3 18-12 F re escale Semiconductor 18.5.1.5.1 Mode Register Definition Figure 18-6 shows the mode register defi nition. Note that this is the SDRAM’ s mode register not the SDRAMC’ s mode/extended mode register (SDMR) defined in Section 18.7.3, “SDRAM Mode/Extended Mode Register (SDMR) .” 18.5.1.5.2 E xtended[...]

SDRAM Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-13 18.5.1.6 Auto Refresh Command (REF) The memory controller issues auto refresh commands according to the SDCR[RC] value. Each time the programmed refresh interval elapses, the memor y controller is sues a P ALL command followed by a REF command. If a memory access is in[...]

MCF548x Refere nce Manual, Rev . 3 18-14 F re escale Semiconductor 18.5.2.1 SDR Initialization SDR initialization requires the following s teps: 1. After reset is deactivated, pause for the amount of time indicated in the SDRAM specification. Usually 100 µ s or 200 µ s. 2. Initialize the SDRAM drive strength (SDRAMDS) and SDRAM chip select config[...]

Functional Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-15 8. Issue a second P ALL command. Initialize the SDRAM control regi ster (SDCR) with SDCR[IP ALL] set. The SDCR[REF , and IREF] b its should remain clea red for this step. 9. Refresh the SDRAM. The SDRAM spec should indicate a number of refresh cycles to be perform[...]

MCF548x Refere nce Manual, Rev . 3 18-16 F re escale Semiconductor The SDRAM controller supports a ll possible XLB transfer sizes. SDRAMs are “burst only” devices; unnecessary beats on the memory bus are masked (write) or discarded (read). The SDRAMC will perform line bur sts (32 byte) for all SDRAM access. This requires two beats of 16 bytes o[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-17 18.7.1 SDRAM Drive Strength Register (SDRAMDS) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0000 0000 0 0 0 0 W R e s e t 0 0 0 0 0000 0000 0 0 0 0 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7654 3 2 1 0 R0 0 0 0 0 0 SB_E SB_C SB_A SB_ S SB_D W R e s e t[...]

MCF548x Refere nce Manual, Rev . 3 18-18 F re escale Semiconductor 18.7.2 SDRAM Chip Select Co nfiguration Registers (CS n CFG) Any chip select can be enabled or disabled, independe nt of others. Any chip se lect can be allocated any size of address space from 1 Mbyte to 4 Gbyte, independent of others . Any chip select address space can begin at an[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-19 CS3CFG = 94000019 = 64M @ 0x9400 0000-0x97FF FFFF CS4CFG = 8000001b = 256M @ 0x8000 0000-0x8FFF FFFF CS5CFG = 00000000 = disable This gives 400 Mbyte total memory , at 0x8000 0000-0x98FF FFFF 18.7.3 SDRAM Mode/Extended Mode Register (SDMR) The SDMR, sh[...]

MCF548x Refere nce Manual, Rev . 3 18-20 F re escale Semiconductor 18.7.4 SDRAM Contr o l Register (SDCR) The SDCR, shown in Figure 18-1 1 , controls SDRAMC operating mode s including the refresh count and address line muxing. 31 30 29 28 27 26 25 24 23 22 21 20 1 9 18 17 16 RM O D E _EN CKE DDR REF 0 0 MUX AP DRIV E RCNT W Reset Uninitialized 1 5 [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-21 18.7.5 SDRA M Configuratio n Register 1 (S DCFG1) The 32-bit read/write SDRAM configur ation regis ter 1 (SDCFG1) stores delay values necessary between specific SDRAM commands. Du ring initialization, software loads values to the register according to [...]

MCF548x Refere nce Manual, Rev . 3 18-22 F re escale Semiconductor The minimum values of certain fields can be dif ferent for SDR and DDR SDRAM , even if the data sheet timing is the same, because: • In SDR mode, the memory controller counts the delay in SDCLK • In DDR mode, the memory contro ller counts the delay in SDCLK × 2 SDCLK—memory c[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-23 18.7.6 SDRA M Configuratio n Register 2 (S DCFG2) The 32-bit read/write configuratio n register 2 stores delay values necessary between specific SDRAM commands. During initialization, soft ware loads values to the register acco rding to the SDRAM infor[...]

MCF548x Refere nce Manual, Rev . 3 18-24 F re escale Semiconductor 18.8 SDRAM Example This example interfaces two 16M × 16-bit × 4 bank DDR SDRAM components to an MCF548 x operating at a 120 MHz SDCLK frequency . T able 18-14 lists design specifications for this example. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R BRD2PRE BWT2RW BRD2WT BL W[...]

SDRAM Example MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-25 18.8.1 SDRAM Signal Drive Strength Settings The SDRAMDS should be pr ogrammed as shown in Figure 18-14 . The settings assume the normal drive strength for 2.5V drive, 7.6m A, is suf ficient for th e loading in the system. This configuration results in a value of SDRAMDS[...]

MCF548x Refere nce Manual, Rev . 3 18-26 F re escale Semiconductor This configuration results in a valu e of SDRAMDS = 0x0000_0019, as described in T able 18-16 . 18.8.3 SDRAM Configuration 1 Register Settings The SDCFG1 register should be programmed as shown in Figure 18-16 . This configuration results in a valu e of SDCFG1 = 0x7362_2830, as descr[...]

SDRAM Example MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-27 18.8.4 SDRAM Configuration 2 Register Settings The SDCFG2 register should be programmed as shown in Figure 18-17 . This configuration results in a valu e of SDCFG2 = 0x4677_0000, as described in T able 18-18 . 18.8.5 SDRAM Contr ol Register Settings and P ALL command Th[...]

MCF548x Refere nce Manual, Rev . 3 18-28 F re escale Semiconductor This configuration results in a valu e of SDCR = 0xE10D_0002, as described in T able 18-19 . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field MODE _EN CKE DDR REF — MUX AP DRIVE RCNT Setting 1110_0001_0 000_1101 (he x) E 1 0 D 1 5 1 4 1 3 1 2 1 1 1 0 987 6 543210 Field — DQ[...]

SDRAM Example MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-29 18.8.6 Set the Extended Mode R egister The SDMR should be pr ogrammed as shown in Figure 18-19 . This step enables the DDR memory’ s DLL. This configuration results in a valu e of SDMR = 0x4001_0000, as described in T able 18-20 . 18.8.7 Set the Mode Register and Rese[...]

MCF548x Refere nce Manual, Rev . 3 18-30 F re escale Semiconductor 18.8.8 Issue a P ALL command The SDCR should be pr ogrammed as shown in Figure 18-21 . This will issue a second P ALL command to the memory . The same SDCR value calculated in Section 18.8.5, “SDRAM Control Register Settings and P ALL command ” is used (0xE10D_0002). This config[...]

SDRAM Example MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-31 18.8.9 P erform T wo Refresh Cyc les The SDCR should be progr ammed as shown in Figure 18-22 . Along with the base settings for the SDCR the MODE_EN and IREF bits are set to issue an REF co mmand to the SDRAM and enable writing of the mode register . The memory used in [...]

MCF548x Refere nce Manual, Rev . 3 18-32 F re escale Semiconductor 18.8.10 Clear the Reset DLL Bit in the Mode Register The SDMR should be programmed as shown in Figure 18-20 . This step programs th e mode register and enables normal operation o f the DLL by clearing the “reset DLL” option. This configuration results in a valu e of SDMR = 0x008[...]

SDRAM Example MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-33 18.8.11 Enable A utomatic Refr esh and Lock Mode Register The SDCR should be progr ammed as shown in Figure 18-24 . Along with the base settings for the SDCR the REF bit is set to enable auto matic refreshing of the memory . In addition, the MODE_EN bit is cleared to di[...]

MCF548x Refere nce Manual, Rev . 3 18-34 F re escale Semiconductor 18.8.12 Initialization Code The following assembly code ini tializes the DDR SDRAM using the re gister values determined above. Basic Configuration and Initialization: move.l #0x000002AA, d0//Initialize SDRAMDS move.l d0, SDRAMDS move.l #0x00000019, d0//Initialize SDCS0 move.l d0, C[...]

SDRAM Example MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 18-35 move.l #0x008D0000, d0//Write LMR and clear reset DLL move.l d0, SDMR Enable Auto Refresh and Lock SDMR: move.l #0x710D0F00, d0//Enable auto refresh and clear MODE_EN move.l d0, SDCR[...]

MCF548x Refere nce Manual, Rev . 3 18-36 F re escale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-1 Chapter 19 PCI Bus Contr oller 19.1 Intr oduction This chapter details the operation of the PCI bus controller for the MCF548 x device. The PCI Bus Arbiter is detailed in Chapter 20, “PCI Bus Arbiter Module.” 19.1.1 Block Diagram Figure 19- 1. PCI Block Diagram 19.1.2 Overview The[...]

MCF548x Refere nce Manual, Rev . 3 19-2 F reescale Semiconductor • Compatible with PCI 2.2 specification • PCI initiator and target operation • Fully synchronous design • 32-bit PCI address bus • PCI 2.2 T ype 0 configuration space header • Supports the PCI 16/8 clock rule • PCI master multichannel DMA or CPU access to PCI bus • Ide[...]

External Signal Description MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-3 19.2.3 Device Select (PCIDEVSEL) The PCIDEVSEL signal is asserted active low when the PCI c ontroller decodes that it is the target of a PCI transaction from the address presente d on the PCI bus during the address phase. 19.2.4 Frame (PCIFRAME ) The PCIFRA[...]

MCF548x Refere nce Manual, Rev . 3 19-4 F reescale Semiconductor 19.2.13 T arget Ready (PCITRD Y ) The PCITRDY signal is asserted active low by the currently a ddressed tar get to indicate that it is ready to complete the current data phas e. 19.3 Memory Map/Register Definition The MCF548 x has several sets of registers th at control and report sta[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-5 MBAR + 0xB68 PCITBATR1 32 Target Base Address Transla tion Register 1 R/W MBAR + 0xB6C PCITCR 32 Target Control Register R/W MBAR + 0xB70 PCIIW0BTAR 32 Initiator Window 0 Base/Tran slation Address Register R/W MBAR + 0xB74 PCIIW1BTAR 32 Initiator Window[...]

MCF548x Refere nce Manual, Rev . 3 19-6 F reescale Semiconductor 19.3.1 PCI T ype 0 Conf iguration Registers The PCI controller supplies a type 0 PCI configuration space header. These registers are accessible as an offset from MBAR or through exte rnally mastered PC I c onfiguration cycles. PCI Dword Reserved space (0x10–0x3F) can be accessed onl[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-7 19.3.1.1 Device ID/V endor ID Regist er (PCIIDR)—PCI Dwor d Addr 0 19.3.1.2 PCI Status/Command Regist er (PCISCR)—PCI Dwor d Addr 1 31 30 29 28 27 26 25 24 23 2 2 21 20 19 18 17 16 RD e v i c e I D W R e s e t 010110 00000001 10 1 5 1 4 1 3 1 2 1 1 [...]

MCF548x Refere nce Manual, Rev . 3 19-8 F reescale Semiconductor T able 19-4. PCI SCR Field Descripti ons Bits Name Desc ription 31 PE P arity error d etected. This bit is set when a pari ty error is detected, ev en if the PCISCR[PER] is cleared. This bit is cleared b y a PCI conf iguration cycle writing a ‘1’ to the bit. Writing ‘0’ has no[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-9 19.3.1.3 Revision ID/Cla ss Code Register (PCICCRIR)—PCI Dwor d 3 6 PER Parity error response. This bit controls the device’s response to parity errors. 0 The device sets its P ar ity Error status bit (bit 31 ) in the e vent of a parity error, b ut [...]

MCF548x Refere nce Manual, Rev . 3 19-10 F re escale Semiconductor 19.3.1.4 Configuration 1 Reg ister (PCICR1)—PCI Dwor d 3 T able 19-5. PCICCRIR Field Des criptions Bits Name Description 31–8 Class Code This field is read-only a nd represents the PCI Class Code assigned to proc essor . Its value is: 0x06 8000 . (Other bridge de vice). 7–0 Re[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-11 19.3.1.5 Base Address Register 0 (PCIB AR0)—PCI Dw or d 4 31 30 29 28 27 26 25 24 23 2 2 21 20 19 18 17 16 R BAR 0 0 0 W R e s e t 00000000000 00000 1 5 1 4 1 3 1 2 1 1 1 0 98765432 10 R 000 000000000 P R E F R A N G E I O / M # W R e s e t 000000000[...]

MCF548x Refere nce Manual, Rev . 3 19-12 F re escale Semiconductor 19.3.1.6 Base Address Register 1 (PCIB AR1)—PCI Dw or d 5 19.3.1.7 CardBus CIS P ointer Re gister PCICCPR—PCI Dwor d A This optional register contains the pointer to the Card Information Structure (CIS) for the CardBus card. All 32 bits of the register are pr ogrammable by the s[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-13 All 32 bits of the register are pr ogrammable by the slave bus. From the PCI bus, this regi ster can only be read, not written. The reset value is 0x0000_0000 and is accessible at a ddress MBAR + 0xB2C. 19.3.1.9 Expansion ROM Base Address PCIERB AR—P[...]

MCF548x Refere nce Manual, Rev . 3 19-14 F re escale Semiconductor registers are accessed primarily internally as offsets of MBAR, but can also be accessed by an external PCI master if PCI base and tar get base address re gisters are configured to access the space. See Section 19.5.2, “Address Maps,” on configuring address windows. 19.3.2.1 Glo[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-15 19.3.2.2 T arget Base Address T ranslation Register 0 (PC ITB A TR0) 13 PEE Parity error interr upt enable. This bit enables CPU Interrupt generation when the PCI P ar ity Error signal, PCIPERR , is sampled asser ted. When enabled and PCIPERR asser ts,[...]

MCF548x Refere nce Manual, Rev . 3 19-16 F re escale Semiconductor 19.3.2.3 T arget Base Address T ranslation Register 1 (PC ITB A TR1) 19.3.2.4 T arget Control Register (PCITCR) 31 30 29 28 27 26 25 24 23 22 2 1 20 19 18 17 16 R Base Address T ranslation 1 00000000000 00 0 W R e s e t 00000000000 00000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R 000000 0[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-17 19.3.2.5 Initiator Window 0 Base/T ranslation Address Register (PCIIW0BT AR) T able 19-13. PCITCR Field Des criptions Bit s Name Description 31–25 — Reser ved, should be cleared. 24 LD Latency rule disable. This control bit applies on ly when MCF54[...]

MCF548x Refere nce Manual, Rev . 3 19-18 F re escale Semiconductor 19.3.2.6 Initiator Window 1 Base/T ranslation Address Register (PCIIW1BT AR) The field descriptions for this regi ster are the same as for PCIIW0BT AR, except that they apply to W indow 1. T able 19-14. PCIIW0BT AR Field Descriptions Bit s Name Des cription 31–24 Window 0 Base Add[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-19 19.3.2.7 Initiator Window 2 Base/T ranslation Address Register (PCIIW2BT AR) The field descriptions for this regi ster are the same as for PCIIW0BT AR, except that they apply to W indow 2. 19.3.2.8 Initiator Window Confi guration Register (PCIIWCR) 31 [...]

MCF548x Refere nce Manual, Rev . 3 19-20 F re escale Semiconductor 19.3.2.9 Initiator Control Register (PCIICR) T able 19- 15. PCIIWCR Field Description s Bit s Name Description 31–28 — Reser ved, should be cleared. 27–24 Window 0 Control[3:0] Bit[3]—IO/M#. 0 Windo w is mapped to PCI memor y . 1 Windo w is mapped to PCI I/O. Bit[2:1]—PCI [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-21 19.3.2.10 Initiator Status Register (PCIISR) T able 19-16. PCII CR Field Descript ions Bit s Name Description 31–27 — Reser ved, should be cleared. 26 REE Retr y error enable. This bit enables CPU Interr upt generation in the case of Retr y Error t[...]

MCF548x Refere nce Manual, Rev . 3 19-22 F re escale Semiconductor 19.3.2.11 Configuration Ad dress Register (PCICAR) T able 19-17. PCIISR Field Descriptions Bit s Name Description 31–27 — Reserved, should b e cleared. 26 RE Retry error. This flag is set when the controller ARTR Y’ s a read o n XL bus when retr y-termina ted by the PCI target[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-23 19.3.3 Comm unication Subsystem Interface Register s The communication subsystem/multic hannel DMA interface ha s separate control registers for transmit and receive operations. 19.3.3.1 Comm Bus FIFO T ransmit Interface PCI Tx is controlled by 14 32-b[...]

MCF548x Refere nce Manual, Rev . 3 19-24 F re escale Semiconductor 19.3.3.1.2 Tx Star t Addre ss Register (PCITSAR) T able 19-19. PCITPSR Field Des criptions Bit s Name Description 31 –18 Pac ket_Siz e P ack et_Siz e [15:2]. The P acket _Size fi eld indicates the n umber of b ytes for the tr ansmit contr oller to send ov er PCI. Only bits [15:2] [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-25 19.3.3.1.3 Tx T ransaction C ontrol Register (PCITTCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0000 P C I _ c m d M a x _ R e t r i e s W R e s e t 0000011100000000 1 5 1 4 1 3 1 2 1 1 1 0 98765432 10 R 00000 M a x _ B e a t s 000 W 000 D I W[...]

MCF548x Refere nce Manual, Rev . 3 19-26 F re escale Semiconductor 19.3.3.1.4 Tx Enables Register (PCITER) 31 30 29 28 27 26 2 5 24 23 22 21 2 0 19 18 17 16 R RC RF 0 CM BE 0 0 ME 0 0 FEE SE RE T AE IAE NE W R e s e t 000000 0000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R 0 000000000000000 W R e s e t 000000 0000000000 Reg Addr MBAR + 0x840C Figure[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-27 19.3.3.1.5 Tx Ne xt Address Register (PCITNAR) 21 FEE FIFO error enable. User writes this bit high to enable CPU Interrupt generation in the case of FIFO error ter mination of a pack et transmission. It ma y be desirable to mask CPU interrupts in the c[...]

MCF548x Refere nce Manual, Rev . 3 19-28 F re escale Semiconductor 19.3.3.1.6 Tx Last W ord Register (PCITL WR) 19.3.3.1.7 Tx Done Counts Register (PCITDCR) T able 19-23. PCITNAR Field Descriptions Bit s Name De scription 31–0 Next_Address This status regi ster contains the ne xt (unwritten) PCI address and is updated at th e successful completio[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-29 19.3.3.1.8 Tx Status Register (PCITSR) T able 19-25. PCITDCR Field Descriptions Bit s Name Description 31–16 Bytes_Done This status register indicates the number of bytes tran smitted since the start of a packet. It is updated at the end of each succ[...]

MCF548x Refere nce Manual, Rev . 3 19-30 F re escale Semiconductor NO TE Registers MBAR + 0x8 420 through MBAR + 0x843C are reserved for future use. Accesses to these register s will result in undefined behavior . 23 BE3 Bus error type 3. This bit is set whenever a sla v e bus transaction attempts to write to a Read-Only register. This flag bit is [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-31 19.3.3.1.9 Tx FIFO Data Register (PCITFDR) + 19.3.3.1.10 Tx FIFO St atus Register (PCITFSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R FIFO_Data_W ord W R e s e t 000 0000000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R FIFO_Data_W ord W R e s e t[...]

MCF548x Refere nce Manual, Rev . 3 19-32 F re escale Semiconductor 19.3.3.1.11 Tx FIFO Cont r ol Register (PCITFCR) T able 19-28 . PCITFSR Field Descript ions Bit s Na me Description 31 IP Illegal P ointer. An address outside the FIFO c ontrolle r’ s memor y range has been wr itten to one of the user visib le pointers. This bit will cause the FIF[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-33 19.3.3.1.12 Tx FIFO Al arm Register (PCITF AR) T able 19-29. PCITFCR Field Descriptions Bit s Name Description 31–30 — Reser ved, should be cleared . 29 WFR Wr ite frame. When this bit is set, the FIFO controller assu mes next data transmitted is E[...]

MCF548x Refere nce Manual, Rev . 3 19-34 F re escale Semiconductor 19.3.3.1.13 Tx FIFO Read P o inter Register (PCITFRPR) T able 19-30. PCITF AR Field Descriptions Bit s Name Description 31– 12 — Reser ved, should be cleared. 11– 7 Alar m Bits 11-7 are h ardwired low . 6–0 Bits 6-0 are programmable to control a 128-b y te FIFO . User wr ite[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-35 19.3.3.1.14 Tx FIFO Write P ointer Register (PCITFWPR) This marks the end of the PCI Comm Bu s FIFO T ransmit Interface description. 19.3.3.2 Comm Bus FIFO Receive Interface PCI Rx is controlled by 13 32-bit registers. These regi sters are located at a[...]

MCF548x Refere nce Manual, Rev . 3 19-36 F re escale Semiconductor 19.3.3.2.1 R x P acket Si ze Register (PCIRPSR) 19.3.3.2.2 Rx Star t Addr ess Register (PCIRSAR) 31 30 29 28 27 26 25 24 23 22 2 1 20 19 18 17 16 R P ack e t_Size[15:2] P ack et _Size [1:0] W R e s e t 0000000000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R 0000000000000000 W R e s e [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-37 19.3.3.2.3 R x T ransaction C ontrol Register (PCIR TCR) T able 19-34. PCI RSAR Field Descr iptions Bit s Name Description 31 –0 Star t_Add The user wr ites this register with the de si red star ting address for the current pac ket. This is the addre[...]

MCF548x Refere nce Manual, Rev . 3 19-38 F re escale Semiconductor 19.3.3.2.4 R x Enables Register (PCIRER) 12 FB Full burst. This is the full b urst bit an d it supersedes the Max_Beats setting. Since Max_Beats provides suppor t f or up to 8-beat bursts , the Full burst bit should not be set f or packets siz es of 8-beats or less. In Full b urst m[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-39 T able 19-36. PCIRER Field Descriptions Bit s Name Description 31 RC Reset controller. User writes this bit high to pu t Receive Controller in a reset state. Note that other register bits are not affected. This Reset i s intended for recovery from an e[...]

MCF548x Refere nce Manual, Rev . 3 19-40 F re escale Semiconductor 19.3.3.2.5 Rx Next Addr ess Register (PCIRNAR) 17 IAE Initiator abort enable . User writes this bit high to enable CPU Interrup t generation in the case of i ni- tiator abort error termination of a packet transmis sion. It may be desirabl e to mask CPU interrupts in the case that Mu[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-41 19.3.3.2.6 R x Done Count s Register (PCIRDCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Bytes_Done W R e s e t 0 0000 0000 0 0 0 00 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Packet s_ Do ne W R e s e t 0 0000 0000 0 0 0 00 0 0 Reg Addr MBAR [...]

MCF548x Refere nce Manual, Rev . 3 19-42 F re escale Semiconductor 19.3.3.2.7 R x Status Register (PCIRSR) 31 30 29 28 27 26 25 2 4 23 22 21 20 19 18 1 7 16 R 0 0 0 0 0 0 0 NT BE3 BE2 BE1 FE SE RE T A IA W rwc 1 rwc 1 rwc 1 rwc 1 rwc 1 rwc 1 rwc 1 rwc 1 rwc 1 R e s e t 0 0000000000000 00 1 5 1 4 1 3 1 2 1 1 1 0 98765 43210 R 0 0000000000000 00 W R [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-43 NO TE Registers 0x84A0 through 0x84BC are rese rved for future use. Accesses to these registers will resu lt in undefined behavior . 19.3.3.2.8 R x FIFO Data Register (PCIRFDR) 18 RE Retry Error .This bit is set if Max_Retr ies is set to a finite v alu[...]

MCF548x Refere nce Manual, Rev . 3 19-44 F re escale Semiconductor 19.3.3.2.9 R x FIFO Stat us Register (PCIRFSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R I P T X W 000000 F A E R X W U F O F F R F u l l A l a r m E m p t y Wr w c 1 rwc 1 rwc 1 rwc 1 rwc 1 rwc 1 R e s e t 0000000000000001 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R 00000000000000[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-45 19.3.3.2.10 Rx FIFO Cont rol Register (PCIRFCR) 17 Alar m The FIFO is at or above the Alar m “watermark ”, as se t by the user according to the Alarm and Control registers settings. This is not a sticky bit or error indication. 16 Empty The FIFO is[...]

MCF548x Refere nce Manual, Rev . 3 19-46 F re escale Semiconductor 19.3.3.2.11 Rx FIFO Ala rm Register (PCIRF AR) 19 OF_MASK Overflow mask. When this bit is set, the FIFO controller masks th e Status Register ’ s OF bit from generating an error . 18 TXW_MASK T ransmit wait condition ma sk. When this bit is set, the FIFO cont roller masks the Stat[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-47 19.3.3.2.12 Rx FIFO Read P o inter Register (PCIRFRPR) 19.3.3.2.13 Rx FIFO Write P o inter Register (PCIRFWPR) 31 30 29 28 27 26 2 5 24 23 22 21 2 0 19 18 17 16 R 0 000000000000000 W R e s e t 000000 0000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R 0 00[...]

MCF548x Refere nce Manual, Rev . 3 19-48 F re escale Semiconductor 19.4 Functional Description The MCF548 x PCI module provides both master and ta rget PCI bus interfaces as shown in Figure 19-1 . The internal master , or initiator , interface is accessible by any XL bus ma ster , such as the processor core, and also provides a DMA interfa ce throu[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-49 19.4.1.2 Basic T ransfer Contr ol The basic PCI bus transfer mechanism is a burst. A bur st is composed of an address phase followed by one or more data phases. Fundamental ly , all PCI data transfers are co ntrolled by three signals PCIFRAME, PCIIRDY , and PC[...]

MCF548x Refere nce Manual, Rev . 3 19-50 F re escale Semiconductor command driven on the PCICXBE bus. In cycle 2, the AD bus is in a turnaround cycle because of the read on a muxed bus. The byte enables, which are active low , are driven onto the PCICXBE bus in this clock. Any combination of byte enables ca n be asserted (none may be asse rted). A [...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-51 Figure 19-48. PCI Write T erminated b y T arget 19.4.1.4 PCI Bus C ommands PCI supports a number of differen t commands. These commands are presented by the initiator on the PCICXBE[3:0] lines during the address phase of a PCI transaction. T able 19- 47. PCI B[...]

MCF548x Refere nce Manual, Rev . 3 19-52 F re escale Semiconductor Though MCF548 x supports many PCI commands as an initiator , the communication subsystem initiator interface is intended to use PCI memory read and memory write commands. 19.4.1.5 Addressing PCI defines three physical address spaces: PCI memory space, PCI I/O space, and PCI configur[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-53 As an initiator , the MCF548 x supports both linear incrementing and cache wrap mode. For memory transactions, when an XL bus burst transaction is wrapped, the cache wrap mode is automatically generated. For zero-word-ali gned bursts and single-beat transactio[...]

MCF548x Refere nce Manual, Rev . 3 19-54 F re escale Semiconductor tells the community of devices on the PCI bus that the bridge that “owns” the PCI bus has already performed the bus number comparis on and verified that the reque st tar gets a device on its bus. Figure 19-49 shows the contents of the AD bus during the address phase of the T ype[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-55 its secondary bus as a T ype 0 confi guration access, decoding the device number to select one of the IDSEL lines. If the bus number is not equal to its secondary bus, but is with in the range of buses that are subordinate to the bridge, the bridge claims an d[...]

MCF548x Refere nce Manual, Rev . 3 19-56 F re escale Semiconductor Figure 19-52. Initiat or Arbitration Bloc k Diagram 19.4.2.1 Priority Scheme The PCI initiator arbiter uses the following fixed priority scheme: 1. XL bus initiator 2. Comm bus transmit (Tx) 3. Comm bus receive (Rx) (lowest) 19.4.3 Configuration Interface The PCI bus protocol requir[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-57 The particular type of PCI transa ction generated is determined by th e PCI configurati on bits associated with the address window (PCIIWCR). For example, the user might se t one window to do PCI memory read multiple accesses, one window fo r PCI I/O accesses,[...]

MCF548x Refere nce Manual, Rev . 3 19-58 F re escale Semiconductor request to the PCI bus comes in, the data transfer is delayed until all previous writes to the PCI bus are completed. Only when the write buf fer is empt y can burst data from the XL bus be posted. 19.4.4.1 Endian T ranslation The PCI bus is inherently li ttle endian in its byte or [...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-59 000 100 OP4 OP5 OP6 OP7 — — — — 00 000 0 OP7 OP6 OP5 OP4 001 100 — OP4 OP5 OP6 OP7 — — — 000 0001 OP6 OP5 OP4 — 100 1110 ——— OP7 010 100 — — OP4 OP5 OP6 OP7 — — 000 0011 OP5 OP4 — — 100 1100 — — OP7 OP6 011 100 — — ?[...]

MCF548x Refere nce Manual, Rev . 3 19-60 F re escale Semiconductor 19.4.4.2 Configuration M echanism In order to support both T ype 0 and T ype 1 configuration transactions, the MCF548 x provides the 32 bit configuration address register (PCI CAR). The register specifies the ta rget PCI bus, device, function, and configuration register to be access[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-61 The MCF548 x can issue PCI configur ation transactions to itself. A T ype 0 configurati on initiated by the MCF548 x can access its own confi guration space by asserting its IDSEL input signal. NO TE Asserting IDSEL is th e only way the MCF548 x can clear its [...]

MCF548x Refere nce Manual, Rev . 3 19-62 F re escale Semiconductor 19.4.4.2.2 T ype 1 Conf iguration T ranslation For T ype 1 translations, the 30 high- order bits of the configuration a ddress register are copied without modification onto the AD[31:2] signals during the address phase. The AD[ 1:0] signals are driven to 0b01 during the address phas[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-63 assigned by the PCI SIG S t eering Committee. The current list of defined encodings are provided in T able 19-51 . 19.4.4.5 T ransactio n T ermination If the PCI cycle Master Aborts, th e interface will return 0xFFFF FFFF as read data, but complete without err[...]

MCF548x Refere nce Manual, Rev . 3 19-64 F re escale Semiconductor Upon detection of a PCI address phase, the PCI controller decode s the address an d bus command to determine if the transaction is for local memory (BAR0 or BAR1 hit). If th e transaction falls within MCF548 x PCI space (memory only), the PCI Controller tar get interface asserts DEV[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-65 T able 19-53. Ali gned PCI to XL Bus T ransfers PCI Bus XL Bus BE[3: 0] AD[2:0] 31:24 23:16 15:8 7:0 A[29:31] Data Bus Byte Lanes 01234567 1110 000 OP3 000 OP3 1101 000 OP3 0 01 OP3 1011 000 OP3 010 OP3 0111 000 OP3 011 OP3 1110 100 OP3 100 OP3 1101 100 OP3 10[...]

MCF548x Refere nce Manual, Rev . 3 19-66 F re escale Semiconductor 19.4.5.4 T arget Abor t A target abort will occur if the PC I address falls within a base address window (BAR0 or BAR1) that has not been enabled. See Section 19.3.2.2, “T arget Base Address T ran slation Register 0 (PCITBA TR0),” and Section 19.3.2.3, “T arget Base Address T [...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-67 on the XL bus will have 100% band width available to th em during PCI multicha nnel DMA activities. In general, this block will be used by functions in the multichannel DMA API. The communication subsystem initiator interface consis ts of Receive and T ransmit[...]

MCF548x Refere nce Manual, Rev . 3 19-68 F re escale Semiconductor 19.4.6.3 Data T ranslation The PCI bus is inherently little endian in its byte ordering. The comm bus however is big endian. T able 19-55 shows the byte lane mapping betw een the two buses. Because th is interface only allows 32-bit accesses, there is only one entry. 19.4.6.4 Initia[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-69 If Continuous mode is active, basic operation is still straight forward. A Restart is achieved by writing the Packet_Size register to a non-zero value (just as before). When a Restart occurs, the Bytes_Done counter is cleared to begin counting for the current [...]

MCF548x Refere nce Manual, Rev . 3 19-70 F re escale Semiconductor 19.4.6.9 Bus Error s Because bus errors are partic ular to the module register set and that register set includes both transmit and receive controller and FIFO settings, the bus error stat us bits and Bus error Enab le bit(s) are duplicated in the T ransmit and Receive register grou[...]

Application Information MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-71 read and write requests from an XL bus master and decodes them to dif ferent address ranges resulting in the generation of memory , I/O, c onfiguration, interrupt acknowledge and special cycles on the PCI bus. The window registers are defined in Section 19.3.2[...]

MCF548x Refere nce Manual, Rev . 3 19-72 F re escale Semiconductor 19.5.2.1 Address T ranslation 19.5.2.1.1 Inbound Address T ranslation The MCF548 x -as-target occupies two memo ry target address windows on the PCI bus. The location is determined by the values programmed to BAR0 a nd BAR1 of the PCI T ype 00h configuration space. These inbound mem[...]

Application Information MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-73 Figure 19-54. Inbound Ad dress Map 19.5.2.1.2 O utbound Ad dress T ranslation Figure 19-55 shows an example of XL Bus Initiator W indow configurations . Overlapping the inbound memory window (MCF548 x Memory) and the outbound translati on window is not support[...]

MCF548x Refere nce Manual, Rev . 3 19-74 F re escale Semiconductor Figure 19-55. Outbound Ad dress Map 19.5.2.1.3 B ase Address Register Overview T able 19-58 shows the available acces sibility for all PCI associated ba se address and translation address registers in the MCF548 x . T able 19-58. Addres s Register Accessi bility Base Address Regist [...]

XL Bus Ar bitra tion Pr iority MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 19-75 19.6 XL Bus Arbitration Priority T o prevent XL bus arbitration liv elock, the PCI controll er should have the sa me or higher XL bus arbitration priority as other XL bus masters that access PCI space. If the XL bus arbiter master priority register (PRI[...]

MCF548x Refere nce Manual, Rev . 3 19-76 F re escale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 20-1 Chapter 20 PCI Bus Arbiter Module 20.1 Intr oduction This chapter describes the MCF548 x PCI bus arbiter module, includi ng timing for request and grant handshaking, the arbitration process, and the registers in the PCI bus arbiter programing model. It also provides arbitration exam p[...]

MCF548x Refere nce Manual, Rev . 3 20-2 F reescale Semiconductor 20.1.3 Features • Direct support for up to five external PCI bus masters • Fair arbitration scheme • Hidden bus arbitration • Bus parking • Master time-out • Interface with 33 MHz and 66 MHz PCI 20.2 External Signal Description This section defines the PCI arbiter and corr[...]

Regist er Defini tion MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 20-3 20.2.5 External Bus Grant/ Request Output (PCIBG0 /PCIREQOUT ) The PCIBG0 signal is asserted to external master device 0 to give it cont rol of the PCI bus. When the PCI arbiter module is disa bled, the signal opera tes as the PCIREQOUT output. It is asserted whe[...]

MCF548x Refere nce Manual, Rev . 3 20-4 F reescale Semiconductor T able 20-2. P A CR Field Descriptions Bit s Name Description 31 DS Disable bit f or the inter nal PCI arbite r . 0 Enab le the PCI arbiter . 1 Disable the on-chip arbiter and u se GNT0 f or the MCF548 x PCI request output and REQ0 fo r its grant input. 30–22 — Reser ved, should b[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 20-5 20.3.2 PCI Arbiter Status Register (P ASR) 20.4 Functional Description 20.4.1 External PCI Requests An external PCI master may tar get the MCF548 x or external slaves . The re quest/grant handshake always precedes any PCI bus operation. Th e PCI arbiter must se[...]

MCF548x Refere nce Manual, Rev . 3 20-6 F reescale Semiconductor 20.4.2 Arbitration 20.4.2.1 Hidden Bus Arbitration PCI bus arbitration can take place while the currentl y granted device is perf orming a bus transaction if another master is requesti ng access to the bus. As long as the bus is active, the arbite r can deassert GNT to one master and [...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 20-7 Figure 20-4. PCI Arbitration Init ial State 20.4.2.3 Arbitration Latency W orst case arbitration latency: ar bitration latency is th e number of clock cycles from a master ’ s REQ assertion to PCI bus idle state AND its GNT assertion. In a lightly loaded syst[...]

MCF548x Refere nce Manual, Rev . 3 20-8 F reescale Semiconductor Figure 20-5. Alternating Priority Device 0 and device 1 assert REQ while the bus is parked with device 2. Because the PCI bus is idle, the arbiter deasserts GNT to the parked master (devi ce 2) and a cycle later , grants access to device 0. Device 0’ s transaction begins when PCIFRA[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 20-9 Figure 20-6. Higher Priority Override The arbiter again dea sserts device 2’ s GNT on clock 2, but devi ce 2 initiates a tran saction in the same cycle. As long as the PCI bus is idle and GNT is asserted, a master can begin a transaction on the next cycle. (A[...]

MCF548x Refere nce Manual, Rev . 3 20-10 F re escale Semiconductor considered “broken” and subseq uent requests are acknowledged. Th is “never -mind” scenario is detrimental to system performance, however , and is not a recommended implementation. 20.5 Reset Reset capability is provided by the MCF548 x system reset. This signal re sets both[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-1 Chapter 21 FlexCAN 21.1 Intr oduction The FlexCAN module is a communication controller implementing the controller area network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control systems. It is a high speed (1 Mbps), short di stance, prio[...]

MCF548x Refere nce Manual, Rev . 3 21-2 F reescale Semiconductor Figure 21-2. Fle xCAN Message Buffer Ar chitect ure 21.1.2 The CAN System A typical CAN system is shown below in Figure 21-3 . Figure 21-3. T ypical CAN System Each CAN station is conn ected physically to the CAN bus through a transceiver . The tr ansceiver provides the transmit drive[...]

Introduction MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-3 bus. It can also provide protection against damage to the Flex CAN caused by a defective CAN bus or defective stations. 21.1.3 Features Following are the main feat ures of the FlexCAN module: • Full implementation of the CAN pr otocol specification version 2.0B — Stan[...]

MCF548x Refere nce Manual, Rev . 3 21-4 F reescale Semiconductor • The prescaler is disabled, thus halting all CAN bus communication. • The FlexCAN ignores its Rx pins an d drives its Tx pins as recessive. • The FlexCAN loses synchronization with the CAN bus, and the NOTRDY and FRZACK bits in CANMCR are set. • The CPU is allowed to read and[...]

External Signals MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-5 21.2 External Signals The FlexCAN module has two I/O si gnals connected to the extern al MPU pins: CA NTX and CANRX. Note that the general purpos e I/O (GPIO) must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 15, “GPIO”[...]

MCF548x Refere nce Manual, Rev . 3 21-6 F reescale Semiconductor 21.3.2 Register Descriptions This section describes the regi sters in the FlexCAN module. NO TE The FlexCAN has no hard-wired prot ection against invalid bit/field programming within its regi sters. Specifically , no protection is provided if the programming does not meet CAN protocol[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-7 T able 21-2. CANMCR Field Descr iptions Bits Name Description 31 MDIS Module di sable . This bit controls whether Fle x CAN is enabled or not. When disabled, FlexCAN shuts down the Fle xCAN cloc ks. This is the only bit in CANMCR not aff ected by soft r[...]

MCF548x Refere nce Manual, Rev . 3 21-8 F reescale Semiconductor 21.3.2.2 FlexCAN Contr o l Register (CANCTRL) CANCTRL is defined for specific FlexCAN control feat ures related to the CAN bus, such as bit-rate, programmable sampling point within an Rx bit, l oop back mode, listen-onl y mode, bus of f recovery behavior , and interrupt enabling (for [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-9 T able 21-3. C ANCTRL Fiel d Descriptions Bits Name Description 31–24 PRESDIV Prescaler division factor . This 8-bit field defi nes the ratio between the system cloc k frequency and the ser ial clock (S cloc k) frequency . The S cloc k period defines [...]

MCF548x Refere nce Manual, Rev . 3 21-10 F re escale Semiconductor 21.3.2.3 FlexCAN Timer Register (TIMER) This register represents a 16-bit fr ee running counter that can be read and written to by the CPU. The timer starts from 0x0000 after reset, counts linearly to 0xFFFF , and wraps around. The timer is clocked by the FlexCA N bit-clock (which d[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-11 The timer value is captured at the beginning of the identifie r (ID) field of a ny frame on the CAN bus. This captured value is written in to the TIMEST AMP entry in a message buf fer after a successful reception or transmission of a message. W riting [...]

MCF548x Refere nce Manual, Rev . 3 21-12 F re escale Semiconductor 21.3.2.4.1 FlexCAN Rx Global Mask Register (RXGMASK) The Rx global mask bits are applied to al l Rx identifiers, excluding Rx buf fers 14 – 15 that have their specific Rx mask registers. Access to this register is unrestr icted. Rx_Msg in 2 1 1 1 1 1 1 1 1 0 0 1 0 2 2 Rx_Msg in 3 [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-13 21.3.2.4.2 FlexCAN Rx 14 M ask Register (RX14MASK) The RX14MASK register has the same structure as the Rx global mask register and is used to mask message buffer 14. Access to this register is unrestricted. 21.3.2.4.3 FlexCAN Rx 15 M ask Register (RX15[...]

MCF548x Refere nce Manual, Rev . 3 21-14 F re escale Semiconductor 21.3.2.5 FlexCAN Error Counter Register (ERRCNT) This register has two 8-bit fields reflecting the value of two FlexCAN er ror counters: transmit error counter (TXECTR) and receive error counter (RXECTR). The rules for increasing and decreasing these counters are described in the CA[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-15 to zero and counts in a manner where the internal counter counts 1 1 such bits, then wraps around while incrementing the TXECTR. When TXECTR reaches the value of 128, the FL TCONF field in the error and status register is updated to be error -ac tive, [...]

MCF548x Refere nce Manual, Rev . 3 21-16 F re escale Semiconductor T able 21-8 describes the ERRST A T fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0000000000000000 W R e s e t 0000000000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RB I T E R R A C K ERR CRC ERR FRM ERR STF ERR TX WRN RX WRN IDLE TXRX FL T CONF 0B O F F INT ERR INT 0 W R [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-17 21.3.2.7 Interrupt Mask Reg ister (IMASK) IMASK contains one interrupt mask bit per buffer . It enables the CPU to determine which buf fer will generate an interrupt after a succes sful transmission/reception (that is , when the corresponding IFLAG bit[...]

MCF548x Refere nce Manual, Rev . 3 21-18 F re escale Semiconductor T able 21-10 describes the IMASK fields. 21.3.2.8 Interrupt Flag Register (IFLA G) IFLAG contains one interr upt flag bit per buf fer . Each succe ssful transmission/reception sets the corresponding IFLAG bit and, if th e corresponding IMASK bit is set, will generate an interrupt. T[...]

Functional Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-19 21.4 Functional Overview The FlexCAN module is flexible in that each one of its 16 message buf fers (MBs) can be assigned either as a transmit buffer or a receive buf fer . Each MB, which is up to 8 bytes long, is also assigned an interrupt flag bit that indicates[...]

MCF548x Refere nce Manual, Rev . 3 21-20 F re escale Semiconductor 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 0x0 CODE SRR IDE R TR LENGTH TIME ST AMP 0x4 Standard ID [28:18] Extende d ID [17:0] 0x8 Da ta Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 0xC Data Byte 4 Data Byte 5 Data Byte 6 Data B[...]

Functional Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-21 28–0 ID [28:18] Standard frame identifier : In standard frame format, o nly the 11 most significant bits (28 to 18 ) are used for frame identification in both receive and transmit cases. The 18 least significant bits are ignored. ID [17:0) Extended frame identif[...]

MCF548x Refere nce Manual, Rev . 3 21-22 F re escale Semiconductor 21.4.2 Message Buffer Memor y Map The message buffer memory map starts at an of fset of 0x80 from the FlexCAN’ s base address (0xA000 or 0xA800). The 256-byte message buf fer space is full y used by the 16 message buf fer structures. T able 21-15. Mes sage Buffe r Code f or Tx Buf[...]

Functional Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-23 Figure 21-13. FlexCAN Mess age Buff er Memory Map 21.4.3 T ransmit Process The CPU prepares or changes an MB for transmission by ex ecuting the following steps: 1. W riting the control/status word to hold Tx MB inactive (CODE = 0b1000). 2. W riting the ID word. 3.[...]

MCF548x Refere nce Manual, Rev . 3 21-24 F re escale Semiconductor Once the arbitration process is complete and ther e is a “winner” MB for transmission, the frame is transferred to the serial message buf fer (SMB) for tra nsmission (move out). While transmitting, the FlexCAN tran smits up to 8 data bytes, even if the DLC is bigger in value. At[...]

Functional Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-25 was captured at the beginning of th e ID field on the CAN bus ) is written into the TIMEST AMP field in the MB, the ID field, data field (8 bytes at most) and the LENG TH fi eld are stored, the CODE field is updated and a status flag is se t in the IFLAG regis ter[...]

MCF548x Refere nce Manual, Rev . 3 21-26 F re escale Semiconductor lost. T wo or more receive MBs that hold a matching ID to a received fr ame do not assure reception in the FlexCAN if the user has deactivated the matc hing MB after FlexCAN has scanned the second. 21.4.6.1 Serial Messag e Buffer s (SMB s) T o allow double buffering of mess ages, th[...]

Functional Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-27 • There is a point in time until which the deactivati on of a Tx MB causes it not to be transmitted (end of move-out). After this point, it is transmitted bu t no interrupt is issued and the CODE field is not updated. 21.4.6.4 Locking and Releasing Message Buffe[...]

MCF548x Refere nce Manual, Rev . 3 21-28 F re escale Semiconductor When transmitting a remote frame , the user initiali zes a message buf fer as a transmit message buffe r with the R TR bit set to one. Once this remote frame is transmitted successf ully , the transmit message buffer automatically becomes a receive me ssage buf fer , with the same I[...]

Functional Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-29 • SYNC_SEG: This segment has a fixed length of one time quantum. Signal e dges are expected to happen within this section. • T ime Segment 1: This segment includes the Propa gation Segment and the Phase Segment 1 of the CAN standard. It can be programmed by se[...]

MCF548x Refere nce Manual, Rev . 3 21-30 F re escale Semiconductor If PSEG2 equals two, then the FlexCAN transmits one time quantum late relative to the scheduled sync segment. • If the prescaler and bit timing control fields are pr ogrammed to values that res ult in fewer than ten system clock periods per CAN bit time and the CAN bus loading is [...]

FlexCAN Initialization Sequenc e MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 21-31 • If the RXECTR increases to a value greater than 127, it is no longer incremented, even if more errors are detected while being a receiver . At the next successful message reception, the counter is set to a value between 1 19 and 127, in or der to [...]

MCF548x Refere nce Manual, Rev . 3 21-32 F re escale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-1 Chapter 22 Integrated Security Engine (SEC) This chapter provides an overview of the MCF548 x security encryption controller (SEC). NO TE Purchasing any of the MCF548 x devices with security requires government export control regulation. 22.1 Features The SEC is designed to offl oad c[...]

MCF548x Refere nce Manual, Rev . 3 22-2 F reescale Semiconductor define the cryptographic function to be performed and the location of the data. The SEC’ s bus-mastering capability permits the host processor to set up a crypt o-channel with a few regist er writes, then the SEC can perform reads and writes on system memory to fetch data packet des[...]

Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-3 22.4.2 SEC Contr oller Unit The SEC controller unit manages on-chip resources, including the in dividual execution units (EUs), FIFOs, the bus interface, and the internal buses that connect all the various modules. The controller receives service requests from the bus interfa[...]

MCF548x Refere nce Manual, Rev . 3 22-4 F reescale Semiconductor 4. W ait for EU to complete processing. 5. Upon completion, unload results and context and wr ite them to external me mory as indicated by the data packet descriptor . 6. If multiple services requested, go back to step 2. 7. Reset the appropriate EU if it is dynamically assigned. Note[...]

Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-5 Figure 22-2. DES Encryption Process In addition, the DEU module can co mpute T riple-DES. T riple-DES is an extension to the DES algorithm whereby every 64-bit input block is processed three times. A diag ram of T riple-DES is shown in Figure 22-3 . Figure 22-3. T riple-DES E[...]

MCF548x Refere nce Manual, Rev . 3 22-6 F reescale Semiconductor Figure 22-4. RC4 Encryption Pr ocess 22.4.4.3 Adv anced Encryption St andar d Execution Unit (AESU) The AESU is used to accelerate bulk data encrypt ion/decryption in compliance with the advanced encryption standard algorithm (AESA) Rinjdael. The AESU executes on 128 bit blocks with a[...]

Overview MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-7 • The MDEU also supports HMAC com putations, as specified in RFC 2104. W ith any hash algorithm, the larger message is mapped onto a smalle r output space, th erefore collisions are potential, albeit not probable. The 160-bit hash value is a suff icie ntly large space such [...]

MCF548x Refere nce Manual, Rev . 3 22-8 F reescale Semiconductor 22.4.4.5 Random N umber Generator (RNG) The RNG is a digital integrated circuit capable of generating 32-bi t random numbers. It is designed to comply with FIPS 140-1 standards fo r randomness and non-determinism. Because many cryptographic algorithms use random numbers as a source fo[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-9 0x21008 SIMRH SEC Interr upt Mask Register High p . 22-14 0x2100C SIMRL SEC Interr upt Mask Register Low p . 22-14 0x21010 SISRH SEC Interrupt Status Register High p . 22-14 0x21014 SISRL SEC Interrupt Status Register Low p . 22-14 0x21018 SICRH SEC Int[...]

MCF548x Refere nce Manual, Rev . 3 22-10 F re escale Semiconductor 22.6 Contr oller The controller within the SEC core is responsible fo r overseeing the operations of the EUs, the interface to the host processor , and the manage ment of the crypto-channels. The c ontroller interfaces to the host via the bus interface and to the channels and EUs vi[...]

Controller MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-11 22.6.1 EU Access Assignment of an EU function to a ch annel is done either st atically or dynamically . In the case of static assignment, an EU is assigned to a channel via th e EU Assignment Control Re gister (EUACR). Once an EU is statically assigned to a channel, it wil[...]

MCF548x Refere nce Manual, Rev . 3 22-12 F re escale Semiconductor T able 22-4 describes the EUACRH and EUACRL fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field — RNG — — Reset 1111 0000 1111 0000 R/W R R/W R R 1 5 1 4 1 3 1 2 1 1 1 0 98765432 10 Field — MDEU — AFEU Reset 1111 0000 1111 0000 R/W R R/W R R/W Reg Addr MBAR + 0x2[...]

Controller MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-13 22.6.4.2 EU Assignment Status Registers (EU ASRH and EU ASRL) The EUASR registers, shown in Figure 22-9 and Figure 22-10 , are used to check the assignment status (static or dynamic) of an EU to a particular crypto -channel. When an EU is already assigned, it is inaccessib[...]

MCF548x Refere nce Manual, Rev . 3 22-14 F re escale Semiconductor 22.6.4.3 SEC Interrupt Mask Registers (SIMRH and SIMRL) The SEC generates a single interru pt output from all possible interr upt sources. These sources can be masked by the SIMR registers. If unmasked, the interrupt source value, when active, is captured into the SEC interrupt stat[...]

Controller MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-15 I 31 30 29 28 27 26 25 24 23 22 21 20 1 9 18 17 1 6 Field CHA_1 CHA_0 AERR — Definition ERR DN ERR DN Reset 0x0000 R/W W 1 5 1 4 1 3 1 2 1 1 1 0 987654 3210 Field — Definition Reset 0x0000 R/W W Reg Addr MBAR + 0x21008 (SIMRH), 0x 21010 (SISRH), 0x21018 (SIC RH) Figure[...]

MCF548x Refere nce Manual, Rev . 3 22-16 F re escale Semiconductor 22.6.4.6 SEC ID Register (SIDR) The read-only SEC ID register , displayed in Figure 22-13 , contains a 32-bit value that uniquely identifies the version of the SEC. The value of this register is always 0x0900_0000. 31 30 29 28 27 26 25 24 23 22 21 20 1 9 18 17 1 6 Field — RNG — [...]

Controller MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-17 22.6.4.7 SEC Master Control Register (SMCR) The SEC master control register (SMCR), shown in Figure 22-14 , controls certain functions in the controller and provides a means fo r software to reset the SEC. 31 30 29 28 27 26 25 24 23 22 2 1 20 19 18 17 16 RV e r s i o n W R[...]

MCF548x Refere nce Manual, Rev . 3 22-18 F re escale Semiconductor 22.6.4.8 Master Error Address Register (MEAR) This register saves the address of the transaction whose data phase wa s terminated with a TEA or Master Parity Error . A T ransfer Error Acknowledge (TEA ) signal indicates a fatal er ror has occurred during the data phase of a bu s tra[...]

Channels MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-19 store the ciphered data the EU outputs. Through a series of requests to the controller , the crypto-channel decodes the contents of the descriptor s to perform the following functions: • Request assignment of one or more of the several EUs for the exclusive use of the chan[...]

MCF548x Refere nce Manual, Rev . 3 22-20 F re escale Semiconductor 31 30 29 28 27 26 25 24 23 22 2 1 20 19 18 17 16 R 00000000000 00000 W R e s e t 000000000 0000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 00000 B U R S T _ S I Z E 000 W E N E N T C D I E R S T W R e s e t 000000000 0000000 Reg Addr MBAR + 0x2200C (CCCR0), 0x2300C (CCCR1) Figure 22[...]

Channels MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-21 T able 22-12 defines the burst size according to the value displayed in the BURST_SIZE field. 22.7.1.2 Cr ypto-Channel P ointe r Status Registers (CCPSRH n and CCPSRL n ) These registers contain status fields and counters which provide the user with status information regard[...]

MCF548x Refere nce Manual, Rev . 3 22-22 F re escale Semiconductor 31 30 29 28 27 26 25 24 23 2 2 21 20 19 18 17 16 R 000000000000000 0 W R e s e t 000000000 0000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R 00000000 S T A T E W R e s e t 000000000 0000000 Reg Addr MBAR + 0x22010 (CCPSRH0), 0x23010 (CCPSRH1) Figure 22-17. Crypto-Chan nel P ointer Status[...]

Channels MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-23 T able 22-14. CCPSRL n Field Descriptions Bits Name Description 31–27 — Reser ved, set to z ero 26 ST A T Cr ypto-Channel Static Mode Enable. The ST A T bit is set when descr iptor processing is initiated and the EUs indicate d in the descriptor header registe r are alre[...]

MCF548x Refere nce Manual, Rev . 3 22-24 F re escale Semiconductor 18 SRD Secondar y EU reset done. Reflects the state o f the reset done signal from the assigned secondar y EU . 0 The assigned secondary EU reset done sign al is inactiv e. 1 The assigned secondary EU reset done sign al is active indicating its reset sequence has completed and it is[...]

Channels MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-25 T able 22-15 shows the values of crypto-channel states. 8 EUERR EU error . An EU assigned to this channel ha s generated an error interrupt. This erro r ma y also be reflected in the controller’ s SISR. The EUERR bi t can only be cleared by first clearing the error source [...]

MCF548x Refere nce Manual, Rev . 3 22-26 F re escale Semiconductor 0x12 Wr ite mode secondar y 0x13 Wr ite datasize primar y 0x14 Delay rng do ne 0x15 Wr ite datasize secondary multi EU in 0x16 T rans request read multi EU in 0x17 Delay primar y secondar y done 0x18 T rans request re ad 0x19 Write key siz e 0x1A Wr ite EU go 0x1B De la y primar y d[...]

Channels MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-27 22.7.1.3 Cr ypto-Channel Current Descriptor P oin ter Register (CDPR n ) The CDPR, shown in Figure 22-19 , contains the address of the da ta packet descriptor which the crypto-channel is currently processing. This register , along with the P AIR_P TR in the CCPSR, can be use[...]

MCF548x Refere nce Manual, Rev . 3 22-28 F re escale Semiconductor T able 22-17 describes the FR n fields. 22.7.1.5 Data Pac ket Descrip tor Buffer (CDBUF n ) This bank of eight register s stores the header , follow ed by length/pointer pairs, followed by a next data packet descriptor pointer . These registers fully describe the serv ice the SEC is[...]

ARC Four Execution Unit (AFEU) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-29 hardware reset, software reset, or module initialization, which performs proper initialization of the S-Box. T o determine when this is co mplete, observe the RD bit in the AFEU status register . Figure 22-21. AFEU Reset Contr ol Register (AFRCR) T able[...]

MCF548x Refere nce Manual, Rev . 3 22-30 F re escale Semiconductor Figure 22-22. AFEU St atus Register ( AFSR) T able 22-19 describes AFEU stat us register fields. 31 30 29 28 27 26 25 24 23 2 2 21 20 19 18 17 16 R 00 H A L T I F W O F R I E I D R D 000 00000 W R e s e t 000000000 0000000 1 5 1 4 1 3 1 2 1 1 1 0 987654 3210 R 00000 0000000000 0 W R[...]

ARC Four Execution Unit (AFEU) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-31 22.8.4 AFEU Interrupt St atus Register (AFISR) The interrupt status register , seen in Figure 22-23 , tracks the state of possible errors, if those errors are not masked via the AFEU interrupt mask register . Figure 22-23. AFEU Interrupt Status Re giste[...]

MCF548x Refere nce Manual, Rev . 3 22-32 F re escale Semiconductor 22.8.5 AFEU Interrupt M ask Register (AFIMR) The interrupt mask register , shown in Figure 22-24 , controls the result of det ected errors. For a given error , if the corresponding bit in th is register is set, the e rror is disabled ; no error interrupt occurs and the interrupt sta[...]

ARC Four Execution Unit (AFEU) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-33 Figure 22-24. AFEU Interrupt Mask Regi ster (AFIMR) T able 22-21 describes AFEU interrupt mask register fields. 31 30 29 28 27 26 25 24 23 2 2 21 20 19 18 17 16 R ME AE OFE IFE 0 IFO OFU 0 0 0 0 IE ERE CE KSE DSE W R e s e t 000000000 0000000 1 5 1 4 1 [...]

MCF548x Refere nce Manual, Rev . 3 22-34 F re escale Semiconductor 22.9 Data Encryption Standard Execution Units (DEU) This section contains details a bout the Data Encryptio n S tandard Execution Units (DEU), including detailed register map, modes of operation, status and c ontrol registers, and FIFOs. 22.9.1 DEU Register Map The registers used in[...]

Data Encryption Standard Execution Units (DEU) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-35 Figure 22-25. DEU Reset Control Register (DRCR) T able 22-22 describes DEU reset control register fields. 22.9.3 DEU Status Register (DSR) This status register , displayed in Figure 22-26 , contains 6 bits which refl ect the state of DEU[...]

MCF548x Refere nce Manual, Rev . 3 22-36 F re escale Semiconductor Figure 22-2 6. DEU Status Regist er (DSR) T able 22-23 describes the DEU status register ’ s bit settings. 31 30 29 28 27 26 25 24 23 2 2 21 20 19 18 17 16 R 00 H A L T I F W O F R I E I D R D 0000000 W R e s e t 000000000 0000000 1 5 1 4 1 3 1 2 1 1 1 0 987654 3210 R 00000 000000[...]

Data Encryption Standard Execution Units (DEU) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-37 22.9.4 DEU Interrupt Status Register (DISR) The DEU interrupt status register , shown in Figure 22-27 , tracks the state of possibl e errors, if those errors are not masked, via the DEU interrupt mask register . Figure 22-27. DEU Interru[...]

MCF548x Refere nce Manual, Rev . 3 22-38 F re escale Semiconductor 29 OFE Output FIFO error . The DEU output FIFO was detected non-empty upon wr ite of DEU data size register . 0 No error detected 1 Output FIFO non-empty error 28 IFE Input FIFO error . The DEU input FIFO was de tected non-empty upon generation of DONE interr upt. 0 No error detecte[...]

Data Encryption Standard Execution Units (DEU) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-39 22.9.5 DEU Interrupt Mask Register (DIMR) The interrupt mask register contro ls the result of detected errors . For a given erro r (as defined in Section 22.9.4, “DEU Interrupt St atus Register (DISR) ”), if the corresponding bit in [...]

MCF548x Refere nce Manual, Rev . 3 22-40 F re escale Semiconductor 22.10 Message Digest Execution Unit (MDEU) This section contains details about the message di gest execution unit (MDEU), including register details. 22.10.1 MDEU Register Map The registers used in the MDEU are documented prim arily for debug and tar get mode operations. If the requ[...]

Message Digest Execution Unit (MDEU) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-41 22.10.2 MDEU Reset Contr ol Register (MDRCR) This register , shown in Figure 22-29 , allows three levels reset of just the MDEU, as defi ned by the three self-clearing bits. Figure 22-29. MDEU Reset Contr ol Register (MDRCR) T able 22-26 describes[...]

MCF548x Refere nce Manual, Rev . 3 22-42 F re escale Semiconductor Figure 22-30. MDEU St atus Register ( MDSR) T able 22-27 describes MDEU status register fields. 31 30 29 28 27 26 25 24 23 2 2 21 20 19 18 17 16 R 00 H A L T I F W 0 I E I D R D 00000 000 W R e s e t 000000000 0000000 1 5 1 4 1 3 1 2 1 1 1 0 987654 3210 R 00000 0000000000 0 W R e s [...]

Message Digest Execution Unit (MDEU) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-43 22.10.4 MDEU Interr upt Status Register (MDI SR) The interrupt status regist er tracks the state of possible errors, if those errors are not masked, via the MDEU interrupt mask register . The definition of each bit in the in te rrupt status regi s[...]

MCF548x Refere nce Manual, Rev . 3 22-44 F re escale Semiconductor 22.10.5 MDEU Interrupt Mask Register (MDIMR) The MDEU interrupt mask register , shown in Figure 22-32 , controls the result of detected errors. For a given error , if the corresponding bit in this register is set, then the error is disabled; no error interrupt occurs and the interru[...]

Message Digest Execution Unit (MDEU) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-45 Figure 22-32. MDEU Interrupt Mask Re gister (MDIMR) T able 22-28 describes MDEU interrupt mask register fields. 31 30 29 28 27 26 25 24 23 2 2 21 20 19 18 17 16 R M E A E 0 00 I F O 00000 I E E R E C E K S E D S E W R e s e t 000000000 0000000 1 5[...]

MCF548x Refere nce Manual, Rev . 3 22-46 F re escale Semiconductor 22.11 RNG Executi on Unit (RNG) The RNG is an execution unit capable of generating 32- bit random numbers. It is designed to comply with the FIPS-140 standard for randomness and non-determinism. A linear feedback shift register (LSFR) and cellular automata shift register (CASR) are [...]

RNG Execution Unit (RNG) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-47 22.11.3 RNG Status Register (RNGSR) This RNG status register , Figure 22-34 , contains 4 bits which reflect the state of the RNG internal signals. The RNG status register is read-only . W riting to this lo cation will result in an a ddress error being reflect[...]

MCF548x Refere nce Manual, Rev . 3 22-48 F re escale Semiconductor 22.11.4 RNG Interrupt Status Register (RNGISR) The RNG interrupt status register tr acks the state of possible errors, if those errors are not masked, via the RNG interrupt mask register . The de finition of each bit in the interr upt status register is shown in Figure 22-35 . Figur[...]

RNG Execution Unit (RNG) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-49 T able 22-32 describes RNG interrupt status register fields. 22.11.5 RNG Interrupt Mask Register (RNGIMR) The RNG interrupt mask register c ontrols the result of detected e rrors. For a given error , if the corresponding bit in this regi ster is set, then the[...]

MCF548x Refere nce Manual, Rev . 3 22-50 F re escale Semiconductor 22.12 Adv anced Encr yption St andar d Execution Units (AESU) This section contains details about the Advanced Encryption St andard Execution Units (AESU), including detailed register map, modes of ope ration, status and control registers. 22.12.1 AESU Register Map The registers use[...]

Adv anced Encryptio n Standard Execution Units (AESU) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-51 Figure 22-36. AESU Re set Contr ol Register (AESRCR) T able 22-34 describes AESU reset c ontrol register fields. 22.12.3 AESU Status Register (AESSR) The AESU status register is a read- only register that reflect s the state of si[...]

MCF548x Refere nce Manual, Rev . 3 22-52 F re escale Semiconductor Figure 22-37. AESU Status Register (AESSR) T able 22-35 describes AESU stat us register fields. 31 30 29 28 27 26 25 24 23 2 2 21 20 19 18 17 16 R 00 H A L T I F W O F R I E I D R D 000 00000 W R e s e t 000000000 0000000 1 5 1 4 1 3 1 2 1 1 1 0 987654 3210 R 00000 0000000000 0 W R [...]

Adv anced Encryptio n Standard Execution Units (AESU) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-53 22.12.4 AESU Interrupt Status Register (AESISR) The AESU interrupt status register tracks the state of possible errors, if those errors are not masked, via the AESU interrupt mask register . Th e definition of each bit in the inte[...]

MCF548x Refere nce Manual, Rev . 3 22-54 F re escale Semiconductor 22.12.5 AESU Interrupt M ask Register (AESIMR) The AESU interrupt mask register , shown in Figure 22-39 , controls the result of detected errors. For a given error , if the corresponding bit in this register is set, then the erro r is ignored; no error interrupt occurs 29 OFE Output[...]

Adv anced Encryptio n Standard Execution Units (AESU) MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-55 and the interrupt status register is not updated to reflect th e error . If the corresponding bit is not set, then upon detection of an error , the interr upt status register is updated to re flect the error , causing assertion of[...]

MCF548x Refere nce Manual, Rev . 3 22-56 F re escale Semiconductor 22.13 Descriptor s As an IPSec accelerator , the SEC has been targeted fo r ease of use and integrat ion with existing systems and software. As such, all crypt ographic functions are accessible thr ough data packet descriptors. In addition, some multi-function descriptor s have been[...]

Descri ptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-57 Figure 22-40. Data P a c ket Descriptor Format 22.13.1.1 Descriptor Header Descriptors are created by the host to guide the SEC through required crypto-graphic operations. The descriptor header defines the opera tions to be performed, mode for e ach operation, and intern[...]

MCF548x Refere nce Manual, Rev . 3 22-58 F re escale Semiconductor T able 22- 38. Header Bit Definitions Bits Name Description 31–28 PEUSEL Primar y ex ecu tion unit select. Programs the channel to select a pr imary EU of a given type. A “No primar y EU selecte d” or a reser ved v alue in this field w ill generate an unrecognized heade r erro[...]

Descri ptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-59 T able 22-39 shows the permissible values for the descript or TYPE field in the descriptor header . See Section 22.13.3, “Descriptor T ype Formats ” for more information on the data length and pointer pairs required for each descriptor type. 1 ST Snoop type. Selects [...]

MCF548x Refere nce Manual, Rev . 3 22-60 F re escale Semiconductor 22.13.1.2 Descriptor Length and P ointer Fields The length and pointer fields represent one of seven da ta length/pointer pairs. E ach pair defines a block of data in system memory . The length field gives the length of the bloc k in bytes. The maximum allowable number of bytes is 3[...]

Descri ptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-61 22.13.1.3 Null Fields On occasion, a descriptor field may not be applicable to the requested service. W ith seven length/pointer pairs, it is possible that not all descri ptor fields will be required to load the required keys, context, and data. (Some operations do not r[...]

MCF548x Refere nce Manual, Rev . 3 22-62 F re escale Semiconductor Figure 22-45. Chain of Descriptor s 22.13.3 Descriptor T ype Formats The SEC accepts 12 fixed format descriptors. The descri ptor TYPE field in the de scriptor header informs the crypto-channel of the ordering of the inputs and outputs defined by the length/pointer pairs in the desc[...]

Descri ptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-63 T able 22-44 shows how the length/pointer pa irs should be used with the va rious descriptor types to load keys, context, and data into the EUs, and how the requi red outputs should be unloaded. NO TE Some of the inputs and outputs will be optional depending on the exact[...]

MCF548x Refere nce Manual, Rev . 3 22-64 F re escale Semiconductor 22.13.4 Descriptor Classes The SEC has two general classes of descriptors: dynamic, which refers to a continually changing usage model, and static, which refers to a relativ ely unchanging usage of the SEC resources. 22.13.4.1 Dynamic Descriptor s In a typical networking en vironmen[...]

Descri ptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-65 22.13.4.2 Static Descriptor s Recall that the SEC has five executi on units and two crypto-channels. Th e EUs can be s tatically assigned or dedicated to a par ticular crypto-channel. Certain co mbinations of EUs can be stati cally assigned to the same crypto-channel to [...]

MCF548x Refere nce Manual, Rev . 3 22-66 F re escale Semiconductor The middle (and multiple subsequent) descriptors contains length/pointer pairs to the remaining data to be permuted. T a ble 22-47 shows the format for a TYPE 0001 data packet descriptor that encrypts or decrypts a block of data. Since the context an d keys were loaded into the EU b[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-67 Because the key and context are unchanging over multiple pa ckets (or descriptors), th e series of short reads and writes required to set-up a nd tear down a session are avoide d. This savings, along with the crypto-channel having dedicated execu[...]

MCF548x Refere nce Manual, Rev . 3 22-68 F re escale Semiconductor The AFEU mode bits do not control cryptographic modes, only operational modes. Therefore, the AFEU only uses actual descriptors, i.e. th ere is not a representative format that is used with multiple header values. 22.14.1.1 Dynamicall y Assigned AFEU T able 22-50 shows the descripto[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-69 T able 22-51 shows the descriptor format to load a previously generated c ontext into the AFEU. Then the input data is ciphered and the context is unloaded. 22.14.1.2 Staticall y Assigned AFEU S tatically assigning the AFEU to a pa rticular crypt[...]

MCF548x Refere nce Manual, Rev . 3 22-70 F re escale Semiconductor T able 22-53 shows the descriptor format to load a previously generated context into the AFEU. PTR_1 P ointer (not used) NULL LEN_2 IV Length NULL PTR_2 IV Po inter NULL LEN_3 K ey Length Number of bytes in ke y (5–16 b ytes) PTR_3 Ke y P ointer Address of ke y to be written into [...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-71 T able 22-54 shows the descriptor format fo r the middle descriptor to perf orm the cipher on a block of data using a context or key that was loaded into the AFEU using either the first descriptors. T able 22-55 shows the descriptor format fo r t[...]

MCF548x Refere nce Manual, Rev . 3 22-72 F re escale Semiconductor 22.14.2 DEU Mode Options an d Data P ac ket Descriptor s Figure 22-47 shows the DEU options that ar e programmable via the PMODE fiel d in the descriptor header . T able 22-56 describes DEU mode register fields. LEN_3 Ke y L ength NULL PTR_3 Ke y P ointer N ULL LEN_4 Data In Length [...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-73 22.14.2.1 Dynamicall y Assigned DEU For IPSec processing, it is envisione d that the SEC will need to proce ss small packets of data associated with many different contexts. This descriptor type is de signed to optimize syst em throughput in a ca[...]

MCF548x Refere nce Manual, Rev . 3 22-74 F re escale Semiconductor 22.14.2.2 Staticall y Assigned DEU When statically assigned, it can be assumed that no ot her crypto-channel will ac cess the DEU in between descriptors. Therefore, in this usage mode, the context remains with in the DEU. The DEU is programmed with the particular mode of operation a[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-75 T able 22-61 shows the middle descriptor that performs a cipher on data using the key and optional context (IV) that were loaded into the DEU by the first descriptor . T able 22-62 lists the specific descriptors that use the format shown in T abl[...]

MCF548x Refere nce Manual, Rev . 3 22-76 F re escale Semiconductor T able 22-63 shows the final descriptor that performs a cipher on data us ing the key and optional context (IV) that were loaded into the DEU by a previous descriptor , then optionally unloads the context. T able 22-64 lists the specific descriptors that use the format shown in T ab[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-77 22.14.3 MDEU Mode Options an d Data P acket Descriptors The MDEU mode options, shown in Figure 22-48 , contains 8 bits which are used to program the MDEU. The mode options are cleared when the MDEU is reset or re- initialize d. Setting a reserv e[...]

MCF548x Refere nce Manual, Rev . 3 22-78 F re escale Semiconductor The MDEU implements hardware accelerated ha shing of data using MD5, SHA-160, or SHA-256. Because it supports several different hashing algorithms, there are four representa tive descriptor formats supporting more different ac tual descriptors. The only variation between the actual [...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-79 (outbound) or compare the hash gene rated by the SEC with the hash wh ich was received with the packet (inbound). If the hashes match, the packet integrity check passes. T able 22-68 lists several different descriptor s that use the format shown [...]

MCF548x Refere nce Manual, Rev . 3 22-80 F re escale Semiconductor T able 22-70 lists several different descriptor s that use the format shown in T able 22-69 . T able 22-71 shows the middle descriptor fo r a statically assigned MDEU. T able 22- 69. First Descripto r for a Statically Assigned M DEU Field Name V alue/T ype Description Header see T a[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-81 T able 22-72 lists several different descriptors that use the middle descript or format shown in T able 22-71 . NO TE For the middle descriptor the HMAC bit should alwa ys be cleared, even if HMAC is the desired final value. Th erefor the table b[...]

MCF548x Refere nce Manual, Rev . 3 22-82 F re escale Semiconductor T able 22-74 lists several different descri ptors that use the final MDEU descriptor format shown in T able 22-73 . 22.14.4 RNG Data P acket Descriptor s There is one RNG-specific data pack et descriptor . It causes a read of the RNG’ s output FIFO and then writes the specified nu[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-83 22.14.5 AESU Mode Options and Data P ac ket Descriptors The AESU mode register contains three bits which are us ed to program the AE SU. The mode register is cleared when the AESU is reset or re -initialized. Setting a rese rved mode bit will gen[...]

MCF548x Refere nce Manual, Rev . 3 22-84 F re escale Semiconductor 22.14.5.1 Dynamicall y Assigned AESU T able 22-77 shows a descriptor for a dynamically assigned AESU. The descriptor loads a key into the AESU, performs the cipher on data, and writes the result and optional context (IV) to memory . 5 FM F inal MA C. Processes final message block an[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-85 T able 22-78 lists several different descriptor s that use the format shown in T able 22-77 . 22.14.5.2 Staticall y Assigned AESU T able 22-69 shows the first descriptor fo r a statically assigned AESU. PTR_6 IV Out P ointer Add ress where output[...]

MCF548x Refere nce Manual, Rev . 3 22-86 F re escale Semiconductor T able 22-80 lists several different descriptor s that use the format shown in T able 22-79 . T able 22-81 shows the middle descriptor fo r a statically assigned AESU. T able 22-82 lists several different descriptors that use the middle descript or format shown in T able 22-81 . PTR[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-87 T able 22-83 shows the final descriptor fo r a statically assigned AESU. T able 22-84 lists several different descriptors that use the middle descript or format shown in T able 22-83 . T able 22-82 . T y pical Header V a lues for Using Middle Sta[...]

MCF548x Refere nce Manual, Rev . 3 22-88 F re escale Semiconductor 22.14.5.3 AESU-CCM Mode Descriptor The SEC supports single pass, single desc riptor AES-CCM proc essing for generic authenticate-and-encrypt block cipher . T able 22-85 shows a the descriptor fo rmat used for AES-CCM in encryption mode. The descriptor load s a key and context (IV) i[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-89 T able 22-87 shows the format used for the context output for AES-CCM. T able 22-88 shows a the descriptor format used for AES-CCM in encrypti on mode. The descriptor loads a key and context (IV) into the AESU, performs the cipher on data, and wr[...]

MCF548x Refere nce Manual, Rev . 3 22-90 F re escale Semiconductor T able 22-89 shows the format used for the context input for AES-CCM. T able 22-87 shows the format used for the context output for AES-CCM. 22.14.6 Multi-Function Data P acket Descriptor s The SEC supports a li mited subset of mul ti-function descriptors. In part icular , the SEC s[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-91 such that the same data read into the DEU, AESU, or AFEU modules can be si multaneously directed to the MDEU module. 22.14.6.1 Snooping As shown in Figure 22-41 , the ST bit in the descriptor header controls the type of snooping which must occur [...]

MCF548x Refere nce Manual, Rev . 3 22-92 F re escale Semiconductor DEU/AESU and MDEU only r eading the portion that matches the st arting address and byte length in the length/pointer fields corresponding to their data of interest. Ciphertext is brought into the DEU/AESU input FIFO , with the MDEU in-snoopi ng the portion of the data it has been to[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-93 T able 22-93 lists typical AESU/HMAC multi-f unction descriptor header values. T able 22-94 shows the representative descriptor used for multi-function encryption such as outbound IPSec ESP . The descriptor header encodes to select the DEU or AES[...]

MCF548x Refere nce Manual, Rev . 3 22-94 F re escale Semiconductor copy the last 8 bytes of the ciphertex t to the Security Association Databa se Entry for this particular session before transmitting the packet. T able 22-95 lists typical DEU/HMAC multi-f unction descriptor header values. T able 22-94. Descriptor f or Dynamic Multi-Function Encrypt[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-95 T able 22-96 lists typical AESU/HMAC multi-f unction descriptor header values. 22.14.6.3 Static Multi-Function Descriptor Formats This example is designed to contra st the dynamic desc riptors shown in Section 22.14.6.2, “Dynamic Multi-Function[...]

MCF548x Refere nce Manual, Rev . 3 22-96 F re escale Semiconductor T able 22-98 lists typical DEU/HMAC multi- function descriptor header valu es for the first descriptor . T able 22-97. Firs t Descriptor f or Stat ic Multi-Function Encryption/Decryption Field Name V al ue/T ype Des cription Header Ta b l e 2 2 - 9 8 Header commo n to se v eral desc[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-97 T able 22-99 lists typical AESU/HMAC multi-f unction descriptor header values. 0x20339920 CBC Single DES E ncrypt SHA256 Y es No 0x20239A22 CBC Single DES Decryp t MD5 Y es No 0x20339A20 CBC Single DES Encr ypt MD5 Y es No 0x20239822 CBC Single D[...]

MCF548x Refere nce Manual, Rev . 3 22-98 F re escale Semiconductor T able 22-100 shows the representative descri ptor format for the middle descri ptors in a statically assigned multi-function operation descriptor chain. The middle descriptor header encodes to select the DEU or AESU as the primary EU, and the MD EU for the secondary EU . Because al[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-99 T able 22-102 lists typical AESU/HMAC multi-f unction descriptor header values. 0x20138220 ECB Single DES Encr ypt MD5 No No 0x20038022 ECB Single DES Decr ypt SHA No No 0x20138020 ECB Single DES Encr ypt SHA No No 0x20438122 ECB T riple DES Decr[...]

MCF548x Refere nce Manual, Rev . 3 22-100 F reescale Semico nductor T able 22-103 shows the representative descriptor format fo r the final descriptor in a statically assig ned multi-function operation descriptor ch ain. The final descriptor header encodes to select th e DEU or AESU as the primary EU, and the MDEU for the secondary EU. Because the [...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-101 T able 22-104 lists typical DEU/HMAC multi- function descriptor header valu es for the first descriptor . LEN_4 IV Length NULL PTR_4 IV P ointer NULL LEN_5 Data In Length B ytes of input data PTR_5 Data In Pointer Address of cipher text to be de[...]

MCF548x Refere nce Manual, Rev . 3 22-102 F reescale Semico nductor T able 22-105 lists typical AESU/HMAC multi-f unction descriptor header values. 22.14.6.4 SSLv3.1/TLS 1.0 Pr ocessing Descriptors The SEC is capable of assisting in SSL record layer processing, how ever for SSL v3.0 and earlier , this support is limited to acceleration of the encry[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-103 performs the HMAC function first, then attaches the HMAC (which is variable size) to the end of the payload data. The payload data, HMAC, and any padding added after the HMAC are then encrypted. Parallel encryption and authentication of TLS “r[...]

MCF548x Refere nce Manual, Rev . 3 22-104 F reescale Semico nductor T able 22-107 lists several different desc riptor header values that can be used for the outbound TLS descriptor one shown in T able 22-106 . The second descriptor , shown in T able 22-108 , performs the encryption of the record, HMAC, pad length, and any padding generated to disgu[...]

EU Specific Data Pac k et Descriptors MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 22-105 The primary EU is the AFEU, with it s mode bits set to cause the AFEU to load the key and initialize the AFEU S-box for data permutation. Th e descriptor does not designate a secondary EU, so the setting of the snoop type bit is ignored. At the [...]

MCF548x Refere nce Manual, Rev . 3 22-106 F reescale Semico nductor T able 22-1 11 lists several dif ferent desc riptor header values that can be used for the outbound TLS descriptor 1 shown in T able 22-1 10 . At the conclusion of inbound TLS descriptor 2, the crypto-channel ha s calculated the HMAC, placed it in memory , and has reset and releas [...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 23-1 Chapter 23 IEEE 1149.1 T est Access P or t (JT A G) 23.1 Intr oduction The Joint T est Action Group, or JT AG , is a dedicated us er -accessible test logic, that complies with the IEEE 1 149.1 standard for boundary-scan testability , to help with system diag nostic and manufacturing t[...]

MCF548x Refere nce Manual, Rev . 3 23-2 F reescale Semiconductor 23.1.2 Features The basic features of the JT AG module are the following: • Performs boundary-scan operations to te st circuit board electrical continuity • Bypasses instruction to reduce the sh ift register path to a single cell • Sets chip output pins to safety stat es while e[...]

External Signal Description MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 23-3 When one module is selected, the inpu ts into the other module are disabled or forced to a known logic level as shown in T able 23-3 , in order to disable the corresponding module. NO TE The MTMOD0 does not support dynami c switching between JT AG and BDM m[...]

MCF548x Refere nce Manual, Rev . 3 23-4 F reescale Semiconductor 23.2.1.5 T est Reset/Developm ent Serial Cloc k (TRST /DSCLK ) The TRST pin is an active low asynchronous reset input with an internal pull-up resistor that forces the T AP controller to the test-logic-reset state. The DSCLK pin clocks the serial communication port to the debug m odul[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 23-5 23.3.2.3 Bypass Register The bypass register is a single-bit shift register path from TDI to TDO when the BYP ASS instruction is selected. 23.3.2.4 JT A G_CFM_CLKDIV Register The JT AG_CFM_CLKDIV register is a 7-bit clock divider for the CFM that is use[...]

MCF548x Refere nce Manual, Rev . 3 23-6 F reescale Semiconductor 23.3.2.6 Boundar y Scan Register The boundary scan register is connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD instruction is selected. It captures input pin data, forces fi xed values on output pins, and selects a logic value and direct ion for bidirectional pins or h[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 23-7 Figure 23-3. T AP Contr oller State Ma chine Flo w 23.4.3 JT A G Instructions T able 23-5 describes public and private instructions. F T able 2 3-5. JT A G Instruction s Instructio n IR[5:0] Instruction Summary EXTEST 000000 Selects boundar y scan registe r whi[...]

MCF548x Refere nce Manual, Rev . 3 23-8 F reescale Semiconductor 23.4.3.1 External T est Instruction (EXTEST) The EXTEST instruction selects the boundary scan register . It forces al l output pins and bidirectional pins configured as outputs to the values preloaded with the SAMPLE/PRELOAD instruction and held in the boundary scan update regist ers.[...]

Initialization/Applicatio n Information MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 23-9 23.4.3.4 ENABLE_TEST _CTRL Instruction The ENABLE_TEST_CTRL instruction selects a 3-bit shift register (TEST_CTRL) for connection as a shift path between the TDI and TDO pin. When the user transitio ns th e T AP controller to the UPDA TE_DR stat[...]

MCF548x Refere nce Manual, Rev . 3 23-10 F re escale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor i Part IV Communications Subsystem Part IV contains chapters that discuss the operation and configur ation of the communications I/O subsystem including the MCF548 x multichannel DMA, communications timer , PSC, FEC, DSPI, and USB2, and I 2 C. Contents Part IV contains the following chapte[...]

MCF548x Refere nce Manual, Rev . 3 ii F reescale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-1 Chapter 24 Multichannel DMA 24.1 Intr oduction The MCF548 x ’ s direct memory access contro ller (DMA) module provides a flexible and efficient means to move blocks of data within the system. The multichannel DMA cont roller reduces the workload on the microprocessor , allowing it t[...]

MCF548x Refere nce Manual, Rev . 3 24-2 F reescale Semiconductor 24.1.2 Overview The DMA controller processes microc ode tasks that are stored in memory . A task is a sequence of instructions, referred to as descriptors , that specifies a series of data movements or manipulations. The DMA controller steps through the desc riptors and executes the s[...]

External Signals MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-3 24.2 External Signals 24.2.1 DREQ [1:0] These active-low inputs provide extern al requests from peripherals need ing DMA service. When asserted, the device is requesting se rvice. Depending on the operatin g mode, either the level of the signal is sampled at the risin[...]

MCF548x Refere nce Manual, Rev . 3 24-4 F reescale Semiconductor 24.3.1.3 V ariable T able Each task has a private 48-longword va riable table. T ypically , each vari able table must be aligned to a 256-byte boundary , though some may be aligned to a 128-byte boundary if the task uses 32 or less variables. 24.3.1.4 Function D escriptor T able Funct[...]

Memory Map/Regist er Definitions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-5 Figure 24-2. DMA Pr ogrammer-Maintai ned Memory Model 24.3.3 DMA Registers 24.3.3.1 DMA Register Map T able 24-1 shows the memory map of the DMA module. T able 24- 1. DMA Memo ry Map Address (MB AR +) Name Byte0 Byte1 Byte2 Byte3 Acces s 0x8000 T ask B[...]

MCF548x Refere nce Manual, Rev . 3 24-6 F reescale Semiconductor 24.3.3.2 T ask Base Addr ess Register (T askB AR) Note that there is a 512-byte alignment restriction on the T askBAR. 0x8018 DMA Interrupt Mask Regi ster DIMR R/W 0x801C T ask Con trol Register TCR0 TCR1 R/W 0x8020 T ask Control Register TCR2 TCR3 R/W 0x8024 T ask Control Register TC[...]

Memory Map/Regist er Definitions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-7 24.3.3.3 Current P ointer (CP) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R T ask Base Address W Reset Uninitialized 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R T ask Base Address W Reset Uninitialized Reg Addr MBAR + 0x8000 Figure 24-3. T ask Base Addre[...]

MCF548x Refere nce Manual, Rev . 3 24-8 F reescale Semiconductor 24.3.3.4 End P ointer (EP) 24.3.3.5 V ariable P ointer (VP) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Descriptor P ointer W Reset Uninitialized 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R Descriptor P ointer W Reset Uninitialized Reg Addr MBAR + 0x8008 Figure 24-5. End P ointer Regis[...]

Memory Map/Regist er Definitions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-9 24.3.3.6 PTD Control (PTD) The priority task decode control register is used to configure dif ferent opera ting modes of this DMA module. The P TD is also used to enable/disable new functionality desi gned into the module after the first release of the[...]

MCF548x Refere nce Manual, Rev . 3 24-10 F re escale Semiconductor 24.3.3.7 DMA Interrupt Pending (DIPR) 24.3.3.8 DMA Interrupt Mask Reg ister (DIMR) 31 30 29 28 27 26 25 24 23 22 21 2 0 19 18 17 16 R 0000000000000000 W R e s e t 0000000 000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R T ASK 15 T ASK 14 T ASK 13 TA S K 12 T ASK 11 T ASK 10 T ASK 9 T [...]

Memory Map/Regist er Definitions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-11 24.3.3.9 T ask Control Register s (TCR n ) Each of the sixteen tasks has an associated task c ontrol register . Only one re gister is shown. At system reset, all bits are initialized to logic zeros. T able 24-8. DIMR Field Descriptions Bits Name Descr[...]

MCF548x Refere nce Manual, Rev . 3 24-12 F re escale Semiconductor 24.3.3.10 Priority Registers (PRIOR n ) When the P TD Control register bit 15 is set to a logic one, the first 16 Priority Registers are used to set the associated priority level of the corresponding task. Th e last 16 Priority register s are unused in this case. When P TD[PCTL15] i[...]

Memory Map/Regist er Definitions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-13 24.3.3.11 Initiator Mux Control Register (IMCR) The DMA supports up to 32 simultan eous DMA request sources, or in itiators. For sy stems where the number of initiators can ex ceed 32, it is possible to mux them such that there is user control of whic[...]

MCF548x Refere nce Manual, Rev . 3 24-14 F re escale Semiconductor 24.3.3.12 T ask Siz e Registers (TSKSZ[0:1]) Each of the 16 tasks can be program med to use specific source and des tination sizes contained in a task size register instead of a specific type encoded in a DRD. The ADS module uses the task size register information to determine the s[...]

Memory Map/Regist er Definitions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 T ASK0 T ASK1 T ASK2 T ASK3 R SRCSZ DSTSZ SRCSZ DSTSZ SRCSZ DSTSZ SRCSZ DSTSZ W R e s e t 00000 00000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 T ASK4 T ASK5 T ASK6 T ASK7 R SRCSZ DSTSZ SRCSZ DSTSZ SRCSZ [...]

MCF548x Refere nce Manual, Rev . 3 24-16 F re escale Semiconductor 24.3.3.13 Debug Comparator Registers (DBGCOMP n ) 24.3.3.14 Debug Contr ol (DBGCTL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Comparator V alue W R e s e t 0000000000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R Comparator V alue W R e s e t 0000000000000000 Reg Addr MBAR + 0x[...]

Memory Map/Regist er Definitions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-17 T able 24-14 below shows the encodings for th e comparator 1 type bits. These bits are set to 000 at reset signifying an uninitialized state. T able 24-13. Deb ug Contr ol Field Descriptio ns Bits Name Description 31–16 Block T asks Specify for each[...]

MCF548x Refere nce Manual, Rev . 3 24-18 F re escale Semiconductor T able 24-15 below shows the encodings for the bits. Thes e bits are set to 101 at reset signifying an uninitialized state. 24.3.3.15 Debug Status (DBGST A T) T able 24-15. Comparator 2 T ype Bit Encodings Encodings Comparator 2 T ype 000 uninitialized 001 wr ite address 010 read ad[...]

Memory Map/Regist er Definitions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-19 24.3.3.16 PTD Debug Register s The P TD Debug register allows access to internal read- only P TD status registers. A different internal status register can be viewed by writing to the register . That register will stay selected until a different value[...]

MCF548x Refere nce Manual, Rev . 3 24-20 F re escale Semiconductor 24.3.4 External Reques t Module Registers The following section shows the registers containe d within the multichannel DMA exte rnal request module. Details are given regard ing register mapping, programming notes, bit definitions, and operating modes. 24.3.4.1 External Request Modu[...]

Memory Map/Regist er Definitions MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-21 24.3.4.3 External Request Addre ss Mask Register (EREQMASK) This register contains an address mask value used for the compare tha t determines a hit for the external acknowledge signal. A 0 indica tes a compare and a 1 is a do not care. This address m[...]

MCF548x Refere nce Manual, Rev . 3 24-22 F re escale Semiconductor 24.4 Functional Description The DMA controller processes microc ode tasks that are stored in memory . A task is a sequence of instructions, referred to as descriptors , that specifies a series of data movements or manipulations. The DMA controller steps through the desc riptors and [...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-23 The details of creating task code is beyond the scope of this documen t. An API containing pregenerated task code is provided and described in the “Multichannel DMA API User ’ s Guide”. 24.4.2 Descriptors The DMA controller interpre ts a seri es of descr[...]

MCF548x Refere nce Manual, Rev . 3 24-24 F re escale Semiconductor 24.4.5 Prioritization The multichannel DMA has two basic prioritization schemes to decide which task should run when more than one is enabled and its initiator is asserte d. These are initiator priority and task priority . When in initiator priority mode, the task with the highe st [...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-25 function descriptor table. Each data routing descriptor can us e the contents of the f unction descriptor table to perform diff erent operations. The LURC is programmed to perform its operations on 32-bit operands. The opera tions can be categorized into four [...]

MCF548x Refere nce Manual, Rev . 3 24-26 F re escale Semiconductor 24.4.9 Line Buffer s The multichannel DMA makes use of li ne buf fers in its interface to the XL bus to combine writes and to prefetch reads to increase performance. Each line buf fer is 32 bytes in depth. The buffer interface has two queues, one for prefetched reads, and another fo[...]

Program ming Model MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-27 24.4.10 T ermination of Loop While executing an inner loop, there are two ways to terminate that loop: 1. Loop-termination conditions have been met. A loop is allowed one termination condition. For example, this could be a byte count for a number of taps in a filte[...]

MCF548x Refere nce Manual, Rev . 3 24-28 F re escale Semiconductor 4. Priority registers - These will typically only be set during initia lization, but can be changed during operation if desired. 5. Initiator Mux Control register - This will t ypically be set up during c onfiguration and will be dependent on what modules of the chip which the syste[...]

Program ming Model MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-29 The base address for contex t save space is used to save variables and values being used by the MDE and ADS. For each task, an area needs to be set aside for all relevant data to be saved until the task is called again. Figure 24-23. T ask Descriptor T able Format [...]

MCF548x Refere nce Manual, Rev . 3 24-30 F re escale Semiconductor 24.6 Timing Diagrams The following timing diagrams show the th ree modes of external request operation. 24.6.1 Le vel-T riggered Requests Figure 24-24 shows the timing for level-triggered external requests. For level-triggered requests, the internal DMA request will assert when DREQ[...]

Timing Diagrams MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 24-31 D ACK to assert (clock 5). The next falling edge of DREQ occurs during clock 8, causing the internal request to assert on the rising edge of clock 9. Figure 24-25. Edge-T riggered External Request Timing 24.6.3 Pipelined Requests Figure 24-26 shows the timing for pipe[...]

MCF548x Refere nce Manual, Rev . 3 24-32 F re escale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 25-1 Chapter 25 Comm Timer Module (CTM) 25.1 Intr oduction This chapter contains a detailed description of the Comm T imer Module (CTM). 25.1.1 Block Diagrams The following section presents three block di agrams showing the CTM in greater detail. Figure 25-1 is a high level block diagram o[...]

MCF548x Refere nce Manual, Rev . 3 25-2 F reescale Semiconductor Figure 25-2. Fixed Time r Channel Conceptual Bloc k Diagram Figure 25-3. V a riable Timer Chan nel Co nceptual Bloc k Diagram 25.1.2 Overview The CTM module provide s two functions for the communications co mplex. First, it can be configured to run as a baud clock generator for th e c[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 25-3 The fixed timer channel provides th e user with two modes, a programmable baud cl ock generator mode or a fixed period task initiator mode. • In baud clock generator mode the fixed timer channel outputs a cInitiator signal that is free running. • In[...]

MCF548x Refere nce Manual, Rev . 3 25-4 F reescale Semiconductor 25.2.2 Register Descriptions 25.2.2.1 Comm Timer Config uration Register (CTCR n )—Fixed Timer Channel This register provides programming options for e ach fixed timer channel. These channels can be programmed to be in in itiator mode or in baud clock generator mode. T able 25-2. Ti[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 25-5 25.2.2.2 Comm Timer Config uration Register (CTCR n )—V ariable Timer Channel This register provides programming opt ions for each variable time r cha nnel. These channels can also be programmed as a baud clock generator or initiator . T able 25-3. CT[...]

MCF548x Refere nce Manual, Rev . 3 25-6 F reescale Semiconductor NO TE The initiator mode is dif ferent from that of a fixed channel in that the period is variable . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R0 00 SM P C T C R V W R e s e t 0000110111111111 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RC R V W R e s e t 1111111111111111 Reg Addr MBAR +[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 25-7 25.3 Functional Description 25.3.1 V ariable Timer in Baud Cloc k Generator M ode In baud clock generator mode, the f unctionality is the same for both fixe d and variable ti mer channels. The only difference is the variable time r channel has a 24-bit referenc[...]

MCF548x Refere nce Manual, Rev . 3 25-8 F reescale Semiconductor is deasserted, and the percent counter stops c ounting and retains a valu e of 0x3. As before the cInitiator signal remains asserted because the percent counter has not timed out. At the rising edge of the clock in cycle 13 the cAcknowledge signal is asserted for the third time, and t[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 25-9 At the rising edge of th e clock in cycle 8, the cAcknowledge signal is asserted. At that point the percent counter begins to count. At the rising edge of clock 10, cAcknowledge is deasserted a nd the counter reaches the high time value. As a result of the coun[...]

MCF548x Refere nce Manual, Rev . 3 25-10 F re escale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-1 Chapter 26 Pr ogrammable Serial Contr oller (PSC) 26.1 Intr oduction This chapter describes the MCF548 x programmable serial controller (PSC). 26.1.1 Block Diagram A block diagram of the PSC /IrDA module is shown in Figure 26-1 below . Figure 26- 1. PSC/IrD A Block Diagram 26.1.2 Over[...]

MCF548x Refere nce Manual, Rev . 3 26-2 F reescale Semiconductor • Backward compatible with the MC68681 — 5,6,7,8 bits data plus parity — Odd, even, none, or force parity — S top bit width programmabl e in 1/16 bit increments — Parity , framing, and overrun error detection — Automatic PSC n CTS and PSC n RT S modem control signals • I[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-3 26.2.4 PSC n TXD PSC n TXD are the transmitter serial data outputs for the PSC modules. The output is held high (mark condition) when the transmitte r is disabled, idle, or in the local loopback mode. The PSC n TXD signals can be programmed to be driven[...]

MCF548x Refere nce Manual, Rev . 3 26-4 F reescale Semiconductor 0x860C 0x870C 0x880C 0x890C PSC Receive Buff er PSCRB R PSC T ransmit Buff er PSCTB W 0x8610 0x8710 0x8810 0x8910 PSC Input P o r t Change Register PS CIPCR — R PSC A u xiliar y Control Register PSCACR —W 0x8614 0x8714 0x8814 0x8914 PSC Interrupt Status Reg ister PSCISR — R PSC [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-5 26.3.3 Register Descriptions This section gives detailed descriptions of the user accessible registers a nd bits within the module. In cases where the operation mode affects the functionality of the control regist er , the operation in each mode is desc[...]

MCF548x Refere nce Manual, Rev . 3 26-6 F reescale Semiconductor 26.3.3.2 Mode Register 2 (PSCM R2 n ) PSCMR2 controls some of the module configuration. It is acc essed when the mode re gister pointer points to PSCMR2, which occurs after any access to PSCMR1. Access to PSC MR2 does not change the pointer . The pointer is set to the mode regi ster 1[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-7 76543210 M o d e R CM TXRTS TXCTS SB U ART W RC M T X R T S T X C T S 0000 S I R W RC M 000000 A l l o t h e r m o d e s W R e s e t 00000000 Reg Addr MBAR + 0x8600 (PSC0); 0x8700 (PSC1); 0x8800 (PSC2); 0x8900 (PSC3 ) Figure 26-3. PSC Mod e Register 2 ([...]

MCF548x Refere nce Manual, Rev . 3 26-8 F reescale Semiconductor 26.3.3.3 Status Register (PSCSR n ) The PSCSR register indicates the status of the characters in the FIFO and the status of the transmitter and receiver . 4 TXCTS T ransmitter clear-to-send (UAR T and SIR modes). If both TxCTS and TxR T S are enabled, TxCTS controls the operati on of [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-9 T able 26-5. PSCSR n Field Descriptions Bits Name De scription 15 RB_NEOF For U ART and SIR modes, this field signifies a received break. 0 No break receiv ed. 1 Break received. F or modem mode, this field is reserved. In MIR and FIR mode, this bit sign[...]

MCF548x Refere nce Manual, Rev . 3 26-10 F re escale Semiconductor 26.3.3.4 Clock Select Register (PSCCSR n ) The comm timers (CTMs) or the PSC’ s timer (see Section 26.3.3.1 1, “Counter Ti mer Registers (PSCCTURn, PSCCTLRn) ” for more information) can be used to generate the baud rate for UAR T and SIR modes. The PSCCSR sele cts which clock [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-11 The upper 4 bits set the receiver and the lower 4 bits set th e transmitter clock source. T o use the system bus clock for both the tran smitter and receiver , program the PSCCSR with 0xDD. It is possible to program the transmitter and the receiver wit[...]

MCF548x Refere nce Manual, Rev . 3 26-12 F re escale Semiconductor T able 26-7. PSCCR n Field Descriptions Bits V alue Command Description 7 — Reserved, should be cleared. 6–4 MISC Field (Th is field selects a single command.) 000 N O C OMMAND — 001 R ESET M ODE R EGISTER P OINTER Causes th e mode reg ister poi nter to po int to PS CMR1 n . 0[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-13 3–2 TXC Field (This field selects a single command) 00 N O A CTION T AKEN The transmitter stays in its current mode. 01 T RANSMITTER E NAB LE This command enables operation of the transmitte r . If the transmitter is alre ady enabled, this command ha[...]

MCF548x Refere nce Manual, Rev . 3 26-14 F re escale Semiconductor 26.3.3.6 Receiver Buffer (PSCRB n ) and T ransmitter Buffer (PSCTB n ) Data is read from the Rx FIFO by reading from the read-onl y PSCRBn registers. Data is written to the Tx FIFO by writing to the write-only PSCTBn registers. Figure 26-9 shows the registers for UAR T , Modem 8, SI[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-15 Figure 26-10 shows the modem 16 register . Figure 26-1 1 shows the AC97 mode register . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RR B R B WT B T B R e s e t 0 0 0 0 000 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RR B R B WT B T B R [...]

MCF548x Refere nce Manual, Rev . 3 26-16 F re escale Semiconductor T able 26-8 shows the fields for Modem 8, SIR, MIR, and FIR modes. T able 26-9 shows the fields for Modem 16 mode. T able 26-10 shows the fields for AC 97 mode. 31 30 2 9 28 27 26 25 24 23 22 21 20 19 18 17 1 6 R RB[19:4] WT B [ 1 9 : 4 ] R e s e t 000 0 00 0 0 0 0 0 0 0 0 0 0 15 14[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-17 26.3.3.7 Input P or t Chang e Register (PSCIPCR n ) PSCIPCR n shows the current state and the change-o f-state for the modem control input port. 11 SOF Start of frame . 1 RB/TB contains the first sample in t he fram e. This is also known as the T AG sl[...]

MCF548x Refere nce Manual, Rev . 3 26-18 F re escale Semiconductor 26.3.3.8 A uxiliary Control Register (PSCA C R n ) PSCACR controls the handshake of the transmitter/receiver . 26.3.3.9 Interrupt Status Register (PSCISR n ) PSCISR provides status for all potenti al interrupt sources. The contents of these registers are masked by the PSCIMR registe[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-19 26.3.3.10 Interrupt Mask Register (PSCIMR n ) The PSCIMR selects the corresponding bi ts in the PSCISR that cause an in terrupt. If one of the bits in the PSCISR is set and the corres ponding bit in the PSCIMR is also set, the internal interrupt output[...]

MCF548x Refere nce Manual, Rev . 3 26-20 F re escale Semiconductor 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode RI P C 0 0 0 0 0 R XRD Y_ FU TXRD Y DEOF ERR 0 0 0 0 0 0 MI R / FIR W RI P C 0 0 0 0 0 R XRD Y_FU TXRD Y 0E R R 0 0 0 0 0 0 Modem W RI P C 0 0 0 0 DB RXRD Y_FU TXRD Y 0E R R 0 0 0 0 0 0 UA RT W RI P C 0 0 0 0 DB RXRD Y_FU TXRD Y DEOF ERR 0 [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-21 26.3.3.11 Counter Timer Registers (PSCCTUR n , PSCCTLR n ) These registers hold the upper and lower bytes of the preload value to be used by the PSC timer in order to provide a given baud rate. 26.3.3.12 Input P or t (PSCIP n ) The PSCIP shows the curr[...]

MCF548x Refere nce Manual, Rev . 3 26-22 F re escale Semiconductor 26.3.3.13 Output P or t Bit Set (PSCOPSET n ) Output ports are asserted by writing to this register . 26.3.3.14 Output P or t Bit Reset (PSCOPR ESET n ) Output ports are negated by writing to this register . RES 5–1 — Reser ved, should be cleared. 0 CTS Current state of the PSCn[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-23 26.3.3.15 PSC/IrD A Control Register (PSCSICR n ) This register sets th e main operation mode. NO TE When the operating mode change occurs, all receiver , transm itter , and error statuses are reset and the receive r and transmitter are disabled. T abl[...]

MCF548x Refere nce Manual, Rev . 3 26-24 F re escale Semiconductor 26.3.3.16 Infrared Contro l Register 1 (PSCIRCR1 n ) This register controls the configuration in IrDA mode. 26.3.3.17 Infrared Contro l Register 2 (PSCIRCR2 n ) This register sets some reque sts to the transmitter or the TxFIFO. T able 26-22. PSCI RCR1 n Field Descriptions Bits Name[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-25 26.3.3.18 Infrared SIR Divi de Register (PSCIRSDR n ) 26.3.3.19 Infrared MIR Divide Register (PSCIRMDR n ) This register sets the baud rate in MIR mode. 1 ABOR T In most mo des this bit is reser ved. In MIR and FIR mode, this bit signifies abor t outpu[...]

MCF548x Refere nce Manual, Rev . 3 26-26 F re escale Semiconductor 26.3.3.20 Infrared FIR Divide Register (PSCIRFDR n ) This register sets the baud rate in FIR mode. T able 26-25. PSCI RMDR n Field Descr iptions Bits Name Description 7 FREQ Applies only in MIR mode; in all ot her modes, this field is reser ved. In MIR mode, this bit signifies 0.576[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-27 26.3.3.21 Rx and Tx FIFO Co unter Register (PSCRFCNT n , PSCTFCNT n ) This register applies to all modes. 26.3.3.22 Rx and Tx FIFO Data Register (PSCRFDR n , PSCTFDR n ) These registers provide access to the internal Rx and Tx FIFOs. T able 26-27. PSCI[...]

MCF548x Refere nce Manual, Rev . 3 26-28 F re escale Semiconductor Reads from the PSCRFDR n register return received data from the Rx FIFO. In addition, this register provides the possibility to fill the Rx FI FO for software development/debug purposes. W rites to the PSCTFDR n register write data into the Tx FIFO. In addition, this register provid[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-29 T able 26-30. PSCRFSR n and PSCTFSR n Field Descriptions Bits Name Description 15 IP Il legal pointer . This bit signifi es an illegal pointer condition in the FIFO controller . A 1 in this bit will cause a FIFO error condition in the PSCISR. This bit [...]

MCF548x Refere nce Manual, Rev . 3 26-30 F re escale Semiconductor 26.3.3.24 Rx and Tx FIFO Control Register (PSCRFCR n , PSCTFCR n ) The FIFO control registers provide pr ogrammability of FIFO behaviors, including last transfer granularity and frame operation. Last tran sfer granularity allows the user to control when the FIFO controller stops req[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-31 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 WFR TIMER FRMEN GR IP_ MSK F AE_ MSK RXW _MSK UF_ MSK OF_ MSK TXW_ MSK 0 0 W R e s e t 0 00 0 0 001000 00000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RC N T R W R e s e t 0 00 0 0 001000 00000 Reg Addr[...]

MCF548x Refere nce Manual, Rev . 3 26-32 F re escale Semiconductor 26.3.3.25 Rx and Tx FIFO Alarm Register (PSCRF AR n , PSCTF AR n ) 26.3.3.26 Rx and Tx FIFO Read P ointer (PSCRFRP n , PSCTFRP n ) The read pointer is a FIFO-maintaine d pointer that points to the next FI FO location to be read. The physical address of this FIFO location is ac tuall[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-33 provided through a port to the FIFO controller . The read pointer can be both read and wr itten. This ability facilitates the debug of the FIFO controller and peripheral drivers. 26.3.3.27 Rx and Tx FIFO Write P ointer (PSCRFWP n , PSCTFWP n ) The writ[...]

MCF548x Refere nce Manual, Rev . 3 26-34 F re escale Semiconductor there are no safeguards to prevent retransmitting data which has been overwritten. When FRMEN in the PSCRFCR and PSCTFCR is cleared, then this pointer has no meaning. The last read frame pointer is reset to zero, and non-functional bits of this pointer will always remain zero. 26.3.[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-35 26.4 Functional Description This section provides a complete f unctional description of the module. 26.4.1 U ART Mode The universal asynchronous receiver and transmitter (UAR T) is comm only used to send low speed data between devices. The term asynchronous is[...]

MCF548x Refere nce Manual, Rev . 3 26-36 F re escale Semiconductor Figure 26-28. Modem Co ntr ol and T ransmitter If PSCnR TS is programmed to be RxR TS, the PSCnR TS output is automatically asserted and negated by the receiver . The PSCnR TS is assert ed when the receiver is ready and the number in the RxFIFO is less than the threshold, and PSCnR [...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-37 A/D bit is set or as a data charac ter if the A/D bit is cleared. The pol arity of the A/D bit is sele cted by programming bit 2 of PSCMR1. PSCMR1 should be pr ogrammed before enabling the transmitter and loading the corresponding data bits into the transmit b[...]

MCF548x Refere nce Manual, Rev . 3 26-38 F re escale Semiconductor Figure 26-30. W avef orm of Modem8 Mode The transmitter starts to transmit the fir st bit at the rising edge of the PSCFS YNC or one clock after the rising edge of the PSCFSY NC, according to the value in the DTS1 bit in the control register PSCSICR. The SHDIR bit in the PSCSICR con[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-39 Figure 26-31. W avef orm of Modem16 Mode The function of this mode is the same as 8-bit mode m mode except that the transmit/receive data length is 16 bit. 26.4.5 A C97 Mode Figure 26-32 shows the waveform in AC97 modem mode. Figure 26-32. W avefo rm of A C97 [...]

MCF548x Refere nce Manual, Rev . 3 26-40 F re escale Semiconductor 26.4.5.1 T ransmitter The transmitter starts to tran smit th e first bit at the one clock after th e rising edge of the frame sync. The first slot, slot #0, is 16 bits wide while the other slot, from slot #1 to slot #12, is 20 bits wide. Because the transmit order is the MSB first, [...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-41 Leaving low power mode ca n be done via either a warm or cold reset ( Figure 26-34 ). The CPU performs a warm reset by writing a 1 to the A WR bit of SICR register for a minimum of 1 us. The A WR bit forces a 1 on PSCnR TS, which is used as the frame sync out [...]

MCF548x Refere nce Manual, Rev . 3 26-42 F re escale Semiconductor The ST A represents the start of the frame and the ST O represents the e nd of the frame. Both of ST A and ST O are defined as 01 1 1 1 1 10 in binary format. In the transmitted data and FCS, a 0 is inserted after 5 consecutive 1s. The FCS is a 16-bit CRC defined as: Eqn. 26-3 26.4.[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-43 . 26.4.9 PSC FIFO System The receive FIFO stack consists of the FIFO and a r eceiver shift register connected to the RxD. Data is assembled in the receiver shift regi ster and loaded into the FIFO at the location pointed to by the FIFO write pointer . Reading [...]

MCF548x Refere nce Manual, Rev . 3 26-44 F re escale Semiconductor are unaffected, and PSCSR n [ERR] sets when th e r eceiver detects the start bit of the new overrunning character . T o support flow control, the receiver can be programmed to automati cally negate and asse rt R TS. In which case, the receiver automatica lly negates R TS when a vali[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-45 NO TE In AC97, the number of data bytes are four times the number of time slot samples in the FIFO. Becau se, each 20-bit sample uses an entire 32-bit longword in the FIFO. For the Rx FIFO, the value can be be tween 0 and 7 bytes only . Therefore, the interrup[...]

MCF548x Refere nce Manual, Rev . 3 26-46 F re escale Semiconductor 26.4.10 Looping Modes The UAR T can be configured to operate in various looping modes as shown in Figure 26-42 . These modes are useful for local and remote sy stem diagnostic functions, and can be used in mode m mode and IrDA mode as well as UAR T mode. The modes are described in t[...]

Resets MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-47 is ignored, the TxD is held marki ng, and the receiver is clocked by th e transmitter clock. The transmitter must be enabled, but the receiver need not be enabled. 26.4.10.3 Remote Loopbac k Mode In this mode, the channel automatically transmits received data on the TxD out pu[...]

MCF548x Refere nce Manual, Rev . 3 26-48 F re escale Semiconductor 26.6 Interrupts This section describes interrupts originated by this module. 26.6.1 Description of Interrupt Operation 26.6.1.1 Processor Interrupt This is the interrupt to the processor. There are five conditions to assert this interrupt: • The IPC interrupt condition is met if t[...]

Software En vironment MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-49 26.7.2 Configuration 26.7.2.1 U ART Mode The following is a sample ini tialization sequence for UAR T mode. T able 26-41. Sample Ini tialization Sequence for U ART Mode Step No. Register V alue Details Meaning 1 PSCSICR 08 RxDCD =1 D CD input effects receiv er S[...]

MCF548x Refere nce Manual, Rev . 3 26-50 F re escale Semiconductor 26.7.2.2 Modem8 Mode Applying the clock to the PSCBCLK input and programming the control registers are required to initialize in modem8 mode. The following table desc ribes a sample initialization sequence. 9 PSCRFCR 0F WRITE T AG = 00 Not EOF FRMEN=1 Enable frame mode GR[2:0]=100 G[...]

Software En vironment MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-51 26.7.2.3 Modem16 Mode The configuration sequence in modem16 mode is almost the same as in m odem8 mode except that the first write value to the SIM[2:0] in PSCSICR should be 3’b010. 26.7.2.4 A C97 Mo de Applying a 12.288 MHz clock to the PSCBCLK input and prog[...]

MCF548x Refere nce Manual, Rev . 3 26-52 F re escale Semiconductor 26.7.2.5 SIR Mode Here is a sample configur ation sequence in SIR mode. 6 PSCRF AR 00F0 ALARM[8 :0]=0F0 Request is asser t ed if # of data >= 240 7 PSCTF AR 00F0 ALARM[8 :0]=0F0 Request is asser ted if # of empty >= 240 8 PSCCR 05 TC=01 Enable tr ansmitter RC=01 Enable receive[...]

Software En vironment MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-53 26.7.2.6 MIR Mode Applying clock to the PSCBCLK input and programming the c ontrol registers are re quired to initialize in MIR mode. Here is a sample sequence when the input frequenc y of PSCBCLK is 18.432 MHz. (1.152 MHz x 16). 8 PSCMR2 07 CM[1:0]=00 Norma l m[...]

MCF548x Refere nce Manual, Rev . 3 26-54 F re escale Semiconductor 26.7.2.7 FIR Mode Applying the clock to the PSCBCLK input and programming the control registers are required to initialize in FIR mode. Here is a sample se quence when the input frequency of PSCBCLK is 64 MHz. S teps 3 to 1 1 are the same as in MIR mode. 4 PSCMR1 73 RxIRQ=1 receiver[...]

Software En vironment MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 26-55 26.7.3 Pr ogramming In any mode, after the configuration sequence, enabli ng the transmitter and writ ing data to the transmit buffer s ends serial data via the PSCnTXD port. Enabling the receiver makes the r eceiver ready and if there is incoming data to PSC n [...]

MCF548x Refere nce Manual, Rev . 3 26-56 F re escale Semiconductor After initialization and after enabli ng the receiver , the receiver is rea dy to receive data. While receiving serial data, the recei ver will eliminate ST A and STO, and these fl ags are not written into the FIFO. After receiving enough data, PSC asserts request /interrupt to prom[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-1 Chapter 27 DMA Serial P eripheral Interface (DSPI) This chapter describes the use of the DMA seri al peripheral interface (DSPI) implemented on the MCF548 x processor . 27.1 Overview The DMA serial peripheral interf ace (DSPI) block provides a synchr onous serial bus for communication[...]

MCF548x Refere nce Manual, Rev . 3 27-2 F reescale Semiconductor 27.3 Bloc k Diagram Figure 27-1 shows a DSPI with external queues in system RAM. Figure 27-1. DSPI wi th Queues and DMA 27.4 Modes of Operation The DSPI has two modes of operation: master and slave. The two modes ar e entered by host software writing to a register. 27.4.1 Master Mode [...]

Signal Description MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-3 27.5 Signal Description 27.5.1 Overview T able 27-1 lists the DSPI signals. 27.5.2 Detailed Signal Descriptions 27.5.2.1 DSPI Peripheral Chip Select/Sla ve Select (DSPICS0/SS ) In master mode, the DSPICS0 signal is a peripheral chip se lect output that select s whic[...]

MCF548x Refere nce Manual, Rev . 3 27-4 F reescale Semiconductor 27.5.2.4 DSPI Serial Input (DSPISIN) DSPISIN is a serial data input signal. 27.5.2.5 DSPI Serial Output (DSPISOUT) DSPISOUT is a serial data output signal. 27.5.2.6 DSPI Serial Clock (DSPISCK) DSPISCK is a synchronous serial co mmunication clock signal . In master mode, the DSPI gener[...]

Memory Map and Regi ster s MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-5 27.6.1 DSPI Module Config uration Register (DMCR) The DMCR contains bits which configure various at tributes associated with DSPI operation. The HAL T bit can be changed at any time but will only take ef fect on the next frame boundary. Only the HAL T bit in[...]

MCF548x Refere nce Manual, Rev . 3 27-6 F reescale Semiconductor 25 PCSSE P eriph eral chip select strobe enable . Selects between the DSPICS5 and PCSS functions. See Section 27.7.3.5, “P er ipheral Chip Select Strobe Enable (PCSS) ” f or more information. 0 DSPICS5/PCSS is used as the DSPICS5 signal 1 DSPICS5/PCSS is used as PCSS peripheral st[...]

Memory Map and Regi ster s MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-7 27.6.2 DSPI T ransfer Count R egister (DTCR) The DTCR contains a counter that indicates the num ber of SPI transfers made. The transfer counter is intended to assist in queue manageme nt. The user must not write to th e DTCR while the DSPI is in the running [...]

MCF548x Refere nce Manual, Rev . 3 27-8 F reescale Semiconductor an SPI master , t he DT FR[CT AS] field in the comm and portion of the Tx FIFO entry selects which of the DCT AR registers is used. In slave mode, a subset of the bitfie lds in only the DCT AR0 regist ers are used to set the slave transfer attributes. See the individual bit desc ripti[...]

Memory Map and Regi ster s MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-9 21–20 P ASC After DSPISCK delay prescaler . The P ASC field selects the prescaler value f or the dela y between the last edge of DSPISCK and the negatio n of DSPICS . This field is only used in master mode. 00 1 clock DSPISCK to DSPICS negation prescaler 0[...]

MCF548x Refere nce Manual, Rev . 3 27-10 F re escale Semiconductor 7–4 DT Dela y after transf er scaler . The DT field selects the delay after transf er scaler. This field is only used in master mode. The delay after transf er is the time between the negation of the DSPICS signal at the end of a frame and the asser tion of DSPICS at the beg innin[...]

Memory Map and Regi ster s MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-11 27.6.4 DSPI Status Register (DSR) The DSR contains status and flag bi ts. The bits reflect the status of the DSPI and indicate the occurrence of events that can generate interr upt or DMA requests. Software can cl ear flag bits in the DSR by writing a ‘1?[...]

MCF548x Refere nce Manual, Rev . 3 27-12 F re escale Semiconductor T able 27-9. DSR Field Descriptions Bits Name Description 31 TCF T ransfer complete flag. The TCF bit in dicates that all bits in a frame hav e been shifted out. The TCF bit is set at the end of the frame transf er. The TCF bit remains set until cleared by soft ware . 0 Transfer not[...]

Memory Map and Regi ster s MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-13 27.6.5 DSPI DMA/Interrupt Requ est Select Register (DIRSR) The DIRSR serves two purposes. It enables flag bits in the DSR to generate DMA requests or interrupt requests. The DIRSR also selects th e type of request to be generate d. See the individual bit de[...]

MCF548x Refere nce Manual, Rev . 3 27-14 F re escale Semiconductor DIRSR Field Descriptions Bits Name Description 31 TCFE T ransfer complete flag interrupt enable. The TCFE bit enab les TCF flag in the DSR to generate an interrupt request. 0 TCF interrupts are disab led 1 TCF interrupts are enab led 30–29 — Reser ved, should be cleared. 28 EOQF[...]

Memory Map and Regi ster s MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-15 27.6.6 DSPI Tx FIFO Register (DTFR) The DTFR provides a means to write to the Tx FIFO. SPI commands and data written to this register are transferred to the Tx FIFO. See Section 27.7.2.4, “Tx FIFO Buffering Mechanism ” for more information. 8- or 16-bit[...]

MCF548x Refere nce Manual, Rev . 3 27-16 F re escale Semiconductor 27.6.7 DSPI Rx FIFO Register (DRFR) The DRFR provides a means to read the Rx FIFO. See Section 27.7.2.5, “Rx FIFO Buffering Mechanism ” for a description of the Rx FIFO op erations. 8- or 16-bit re ad accesses to the DRFR will read from the Rx FIFO and update the counter and poi[...]

Memory Map and Regi ster s MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-17 27.6.8 DSPI Tx FIFO Deb ug Register s 0–3 (DTFDR n ) The DTFDR n registers provide visibility into the Tx FIFO for debugging purposes. Each register is an entry in the Tx FIFO. The regi sters are read-only and cannot be modified. Reading the DTFDR n regis[...]

MCF548x Refere nce Manual, Rev . 3 27-18 F re escale Semiconductor 27.7 Functional Description The DMA serial peripheral interf ace (DSPI) block provides a synchr onous serial bus for communication between an MCU and an external peripheral device. The DSPI supports up to eight queued SPI transfers at once (four transmit and four rece ive) in the DS[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-19 Figure 27-11. SPI Seria l Pro tocol Overvie w The DSPI has four peripheral chip select signals that are used to se lect which of the sl aves to communicate with: DSPICS5, DSPICS3, DSPICS1, and DSPICS0. The transfer rate and delay sett ings are described in sec[...]

MCF548x Refere nce Manual, Rev . 3 27-20 F re escale Semiconductor S tate transitions from running to st opped occur on the next fr ame boundary if a transfer is in progress, or on the next system clock cycle if no transfers are in progress. 27.7.2 Serial P eripheral Interface (SPI) The SPI transfers data serially usi ng a shift register and a sele[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-21 for successful communication with an SPI master. These SPI slave mode transfer attributes are set in the DCT AR0. 27.7.2.3 FIFO Disable Operation The FIFO disable mechanisms allo w SPI transfers without using the Tx FIFO or Rx FIFO. The DSPI operates as a doub[...]

MCF548x Refere nce Manual, Rev . 3 27-22 F re escale Semiconductor 27.7.2.5 Rx FIFO Buffering Mechanism The Rx FIFO functions as a buf fer for data received on the DSPISIN signa l. The Rx FIFO holds from 1 to 16 received SPI data frames. SPI data is added to the Rx FIFO at the completion of a transfer when the received data in the shift register is[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-23 27.7.3.1 Baud Rate Generator The baud rate is the frequency of the DSPI serial communication cl ock (DSPISCK). The system clock f sys is divided by a prescaler (PBR) and scaler (BR) to produce DSPISCK. The PBR and BR fields in the DCT AR n registers select the[...]

MCF548x Refere nce Manual, Rev . 3 27-24 F re escale Semiconductor Eqn. 27-7 T able 27-18 shows an example of how to co mpute the delay after transfer . 27.7.3.5 Peripheral Chip Sel ect Str obe Enable (PCSS ) The PCSS signal provides a delay to allow the DSPICS n signals to settle afte r transitioning, thereby avoiding glitches. When the DSPI is in[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-25 27.7.4 T ransfer Formats The SPI serial communication is c ontrolled by the serial communications clock (DSPISCK) signal and the DSPICS n signals. The DSPISCK signal provi ded by the master de vice synchronizes shifting and sampling of the data on the DSPISIN [...]

MCF548x Refere nce Manual, Rev . 3 27-26 F re escale Semiconductor Figure 27-15. DSPI T ransfer Timing Diagram (MTFE = 0, CPHA = 0 , FMSZ = 8) The master initiates the transfer by placing its first data bit on the DSPISOUT pin and asserting the appropriate peripheral chip select signals to the slave de vice. The slave responds by placing its first [...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-27 Figure 27-16. DSPI T ransfer Timing Diagram (MTFE = 0, CPHA = 1 , FMSZ = 8) The master initiates the tr ansfer by asserting the CS n signal to the slave. Af ter the t CSC delay has elapsed, the master generates the first DS PISCK edge and, at the same time , p[...]

MCF548x Refere nce Manual, Rev . 3 27-28 F re escale Semiconductor Figure 27-17. DSPI Modifi ed T ransfer Format (MTF E = 1, CPHA = 0, Fsck = Fsys/4) 27.7.4.4 Modified SPI T ransfer Format (MTFE = 1, CPHA = 1) Figure 27-18 shows the modified transfer format for CPHA = 1. Only the condition where CPOL = 0 is described. At the start of a tr ansfer th[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-29 be visible on the master D SPISCK pin during the sampling of the last bit. The DSPISCK to CS delay must be greater or equal to half of the DSPISCK period. Figure 27-1 8. DSPI Modified T ransfer F ormat (MTFE = 1, CPHA = 1, Fsck = Fsys/4) 27.7.4.5 Continuous Se[...]

MCF548x Refere nce Manual, Rev . 3 27-30 F re escale Semiconductor (t DT ) is not inserted between the transfers. Figure 27-20 shows the timing diagram for two 4-bit transfers with CPHA = 1 and CONT = 1. Figure 27-20. Example of Continuou s T ransfer (CPHA = 1, CONT = 1) Switching DCT AR n registers between frames wh ile using continuous selecti on[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-31 Figure 27-21. Contin uous DSPI SCK Timing Dia gram (CSCK = 0) If DTFR[CONT] is set, DSPICS n remains asserted between th e transfers when the DSPICS n signal for the next transfer is the same as for the current transfer. Figure 27-22 shows timing diagram for c[...]

MCF548x Refere nce Manual, Rev . 3 27-32 F re escale Semiconductor Each condition has a flag bit in the Section 27.6.4, “DSPI Status Register (DSR) ” and a request enable bit in the Section 27.6.5, “DSPI DMA/Interrupt Re quest Select Re gister (DIRSR) .” The Tx FIFO fill flag (TFFF) and Rx FIFO drain flag (RFDF) generate inte rrupt requests[...]

Initialization and Ap plication Information MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-33 27.8 Initialization and Application Inf ormation 27.8.1 How to Change Queues This section presents an example of how to change queues for the DSPI. The queues are not part of the DSPI, but the DSPI includes features in support of queue mana[...]

MCF548x Refere nce Manual, Rev . 3 27-34 F re escale Semiconductor 27.8.3 Dela y Settings T able 27-23 shows the values for the delay a fter transfer (t DT ) and CS to DSPISCK delay (t CSC ) that can be generated based on the pres caler values and the scaler values set in the DCT AR n registers. The values calculated assume a 100MHz system frequenc[...]

Initialization and Ap plication Information MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 27-35 27.8.4 Calculation of FIFO P ointer Addresses The user has complete visibility of the Tx and Rx FIFO contents th rough the FIFO registers, and valid entries can be identified through a memory mapped pointer and a me mory mapped counter for [...]

MCF548x Refere nce Manual, Rev . 3 27-36 F re escale Semiconductor Figure 27-23. Tx FIFO P ointers and Counter 27.8.4.1 Address Calculation for the First-in Entry and Last-in Entry in the Tx FIFO The memory address of the first-in entry in the Tx FIFO is computed by the following equation: First-in entry address = Tx FIFO base + 4*(TXP TR) The memo[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 28-1 Chapter 28 I 2 C Interface 28.1 Intr oduction This chapter describes the I 2 C™ module, including I 2 C protocol, clock synchronization, and I 2 C programming model registers. It also pr ovides extensive programming examples. 28.1.1 Block Diagram A block diagram of the I 2 C module [...]

MCF548x Refere nce Manual, Rev . 3 28-2 F reescale Semiconductor 28.1.2 I 2 C Overview I 2 C is a two-wire, bidi rectional serial bus which provides a simple, efficien t method of data exchange between devices. This two-wire bus minimi zes the interconnection between the devices. The interface is designed to operate up to 100 kbps wi th maximum bus[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 28-3 28.3 Memory Map/Register Definition 28.3.1 I 2 C Register Map . 28.3.2 Register Descriptions There are five regist ers used in the I 2 C interfa ce with the interrupt control register . The internal configuration of these re gisters is discussed in the [...]

MCF548x Refere nce Manual, Rev . 3 28-4 F reescale Semiconductor 28.3.2.2 I 2 C Frequency Divider Register (I2FDR) The I2FDR, shown in Figure 28-3 , provides a programmable pr escaler to configure the I 2 C clock for bit-rate selection. 76543210 R0 0 I C W R e s e t 00000000 Reg Addr MBAR + 0x8F04 Figure 28-3. I 2 C Frequency Divide r Register (I2F[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 28-5 28.3.2.3 I 2 C Control Register (I2CR) The I2CR is used to enable the I 2 C module and the I 2 C interrupt. It also contains bits that govern operation as a slave or a master . 28.3.2.4 I 2 C Status Register (I2SR) This I2SR contains bits that indi cate[...]

MCF548x Refere nce Manual, Rev . 3 28-6 F reescale Semiconductor 76543210 R I CF IAAS IBB IAL 0 SRW IIF RXAK W R e s e t 10000001 Reg Addr MBAR + 0x8F0C Figure 28-5. I 2 C Status Register (I2SR) T able 28-6. I2SR Field Descr iptions Bits Name Description 7 ICF Data transferring bit. While one byte of data is transf erred, ICF is cleared. 0 T ransfe[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 28-7 28.3.2.5 I 2 C Data I/O Registe r (I2DR) While in master -receive mode , reading the I2DR allows a read to o ccur and initiates th e next data byte to be received. In slave mode, the sa me function is available once the I 2 C has received its slave addr[...]

MCF548x Refere nce Manual, Rev . 3 28-8 F reescale Semiconductor 28.4 Functional Description The I 2 C has a simple bidirectional 2-wire bus for ef ficient inter -IC cont rol. The two wires, serial data address line (SDA) and serial clock line (SCL), carry in formation betw een the MCF548 x and other devices connected to the bus. Each device, inclu[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 28-9 Normally , a standard communication is composed of f our parts: ST AR T signal, slave address transmission, data transfer , and STOP signal. The parts of a communication are de scribed briefly in the following sections and illustrated in Figure 28-8 . 28.4.1 ST[...]

MCF548x Refere nce Manual, Rev . 3 28-10 F re escale Semiconductor Data can be changed only while SCL is low and must be held stable while SCL is high, as Figure 28-8 shows. SCL is pulsed once for each da ta bit, with the msb being sent first. The receiving device must acknowledge each byte by pulling SDA low at the ninth clock; therefore, a data b[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 28-11 28.4.6 Repeated Star t A repeated ST AR T signal is a ST AR T signal generated without first generating a ST OP signal to terminate the communication. This is used by th e master to communicate with anot her slave or with the same slave in a diff erent mode wi[...]

MCF548x Refere nce Manual, Rev . 3 28-12 F re escale Semiconductor Devices with shorter low periods enter a high wait state dur ing this time (see Figure 28-13 ). When all devices concerned have counted of f their low period, the s ynchronized clock SCL li ne is released and pulled high. There is then no differen ce between the device cloc ks and t[...]

Initialization Sequence MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 28-13 2. Update the I2ADR to define it as a slave device (give it a slave address) 3. Set I2CR[IEN] to enable the I 2 C interface system 4. Modify the I2CR to select master/slave m ode, transmit/receive mode , or interrupt enable NO TE If I2SR[IBB] is set when the I[...]

MCF548x Refere nce Manual, Rev . 3 28-14 F re escale Semiconductor /* Wait for I2SR.IBB (bus busy) to b e set */ while ( !(MCF5_I2C_I2SR & MCF_I2C_I2 SR_BB) ); 28.5.2 P ost-T ransfer Software Response T ransmission or reception of a byte w ill set the data transferring bit (I CF) to 1, which indicates one byte of communication is finishe d. The[...]

Initialization Sequence MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 28-15 28.5.3 Generation of ST OP A data transfer ends with a STOP signal generated by the ‘master ’ devi ce. A master transmitter can simply generate a STOP signal after all the d ata has been transmitted. For a master receiver to termin ate a data transfer , it[...]

MCF548x Refere nce Manual, Rev . 3 28-16 F re escale Semiconductor /* Generate STOP by clearing I2CR.MS TA */ MCF_I2C_I2CR = 0x80; } /*Store received data and release SD A */ rx_buffer[i] = MCF_I2C_I2DR; } 28.5.4 Generation of Repeated ST ART At the end of a data transfer , if the master still wants to communicate on the bus , it can generate anoth[...]

Initialization Sequence MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 28-17 /* Set I2CR.MTX to put the module in transit mode */ MCF_I2C_I2CR |= MCF_I2C_I2CR_MTX; /* Send the contents of tx_buffer un til NACK is detected */ i = 0; while (1) { /*Put TX data into I2DR */ MCF_I2C_I2DR = tx_buffer[i]; /*Wait for transfer to complete */ wh[...]

MCF548x Refere nce Manual, Rev . 3 28-18 F re escale Semiconductor /* Receive data from master device a nd store in rx-buffer */ for(i=0; i<rx_byte_count; i++) { /* Wait for transfer to complete */ while (!(MCF_I2C_I2SR & MCF_I2C_I2SR _IIF) ); /* Clear IIF bit */ MCF_I2C_I2SR &= 0xFD; /* Store received data and release S DA */ rx_buffer[[...]

Initialization Sequence MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 28-19 Figure 28-14. Flow-Chart of T ypical I 2 C Interrupt Rou tine Clear IIF Tx/Rx ? Second Last Byte to be Read ? Clear IAL Last Byte to be Read ? Switch to Rx Mode Dummy Rea d from I2DR Set TXAK=1 Generate ST OP Signal Generate ST OP Signal Read Data from I2DR an[...]

MCF548x Refere nce Manual, Rev . 3 28-20 F re escale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-1 Chapter 29 USB 2.0 De vice Contr oller 29.1 Intr oduction This chapter provides an overview of th e USB 2.0 device controller module of the x MCF548 x . Connection examples and circuit board layout considerations are also provided. The USB Specification, Revision 2.0 is a recommended [...]

MCF548x Refere nce Manual, Rev . 3 29-2 F reescale Semiconductor 29.1.3 Block Diagram A block diagram of the complete USB 2.0 Device controller module is shown in Figure 29-1 . Figure 29-1. USB 2.0 De vice Controller Block Di agram 29.1.3.1 Controller and Synchr onization This block handles all of the detail s of managing the USB prot ocol and pres[...]

Introduction MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-3 29.1.3.3 FIFO Controller The FIFO controller implements th e data FIFOs in such a way that they can communicate with the ColdFire core or with the multichannel DMA. There are two physical RAMs that are shared by all of the FIFO controllers. For maximum pe rformance, the t[...]

MCF548x Refere nce Manual, Rev . 3 29-4 F reescale Semiconductor 29.1.3.5.4 USBCLKIN Input pin for the 12-MHz USB crystal circuit. 29.1.3.5.5 USBCLK OUT Output pin for the 12-MHz USB crystal circuit. 29.2 Memory Map/Register Definition This section contains a deta iled description of each regist er and its specific function. 29.2.1 USB Memory Map T[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-5 0xB088 USB PID e rror counter register , USB framing error counter register PIDECNT FRMECNT 0xB08C USB transmitted pack et counter register USB counter overflow register Reserved TXPCNT CNT O VR — 0xB090– 0xB0FF Reser ved Endpoint Conte xt Register [...]

MCF548x Refere nce Manual, Rev . 3 29-6 F reescale Semiconductor 0xB164 EP2 OUT interface number register , EP2 OUT status register EP2OUTIFR EP2OUTSR — — 0xB168 Reser ved 0xB16C EP2 OUT Sync F rame Register EP2OUTSFR 0xB170– 0xB177 Reser ved 0xB178 EP2 IN attri b ute control register , EP2 IN max pack et size register — EP2INA CR EP2INMPSR[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-7 0xB1D0– 0xB1D7 Reser ved 0xB1D8 EP4 IN attribute control register , EP4 IN max pack et size register — EP4INA CR EP4INMPSR 0xB1DC EP4 IN interface number register , EP4 IN status register EP4INIFR EP4INSR — — 0xB1E0– 0xB1E7 Reser ved 0xB1E8 EP[...]

MCF548x Refere nce Manual, Rev . 3 29-8 F reescale Semiconductor 0xB23C EP6 IN interf ace number register , EP6 IN status register EP6INIFR EP6INSR — — 0xB240– 0xB244 Reser ved 0xB248 EP6 IN sync frame register EP6INSFR 0xB24C– 0xB3FF Reser ved USB Request, Control, and Status Register s 0xB400 USB status register USBSR 0xB404 USB control r[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-9 29.2.2 USB Request, Contr o l, and Status Registers The following registers provide an ap plication interface to th e request, control, and status functionality of the USB 2.0 device controller . 29.2.2.1 USB Status Register (USBSR ) The USBSR reports t[...]

MCF548x Refere nce Manual, Rev . 3 29-10 F re escale Semiconductor 29.2.2.2 USB Control Register (USBCR) The USBCR configures f eatures of the module. 6–4 — Reser v ed, should be cleared. 3–0 ISOERREP Isochrono us error endpoint. This is the endpoint number f or the isochronous OUT endpoint that has experienced a PID sequencing e rror and cau[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-11 T able 29-3. USBCR Field Descr iptions Bits Name Description 31–6 — Reser ved, should be cleared. 5 RAMSPLIT RAM split. The endpoint FIFO RAM can be con figured for maximum fle xibility o r f or maximum performance. The individual FIFO base and dep[...]

MCF548x Refere nce Manual, Rev . 3 29-12 F re escale Semiconductor 29.2.2.3 USB Descripto r RAM Control Register (DRAMCR) 1 APPLOCK Application Loc k. This bit should be asserted to ensure the indivisibility of read-modify-write (RMW) operations on cer tain USB 2.0 device registers. Ma ny register bits can be written to by the user software and the[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-13 29.2.2.4 USB Descripto r RAM Data Register (DRAMDR) The DRAMDR allows user access to the USB descriptor memory . T able 29-4. DRAMCR Field Descr iptions Bits Name Description 31 ST ART Star t. This bit initiates the GET_DESCRI PT OR ha ndler . Before s[...]

MCF548x Refere nce Manual, Rev . 3 29-14 F re escale Semiconductor 29.2.2.5 USB Interrupt Status Register (USBISR) The USBISR maintains the status of interrupt conditions pertaini ng to USB functions. An interrupt, once set, remains se t until cleared by writi ng a 1 to the correspondi ng bit. Interrupts do not clear automatically if the event that[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-15 29.2.2.6 USB Interrupt Mask Reg ister (USBIMR) Setting a bit in the USBIMR masks the corresponding interrupt in the USBISR. 5 RSTST OP Reset stop. This indicates the end of reset signalling on the USB. 0 Reset signalling has n ot stopped. Does not impl[...]

MCF548x Refere nce Manual, Rev . 3 29-16 F re escale Semiconductor 29.2.2.7 USB Applicatio n Interrupt Status Register (USBAISR) The USBAISR contains information re garding the source of a USB interrupt event. Interrupt sources may be masked in the USBAIMR. The a pplication must clear al l interru pt bits when necessary as they do not clear automat[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-17 29.2.2.8 USB Applicatio n Interrupt Mask Register (USBAIMR) The USBAIMR allows the application to mask interrupt sources within the USB module. The format of this register is identical to that of the USBAISR. A logic 1 in any of the defined bit positio[...]

MCF548x Refere nce Manual, Rev . 3 29-18 F re escale Semiconductor 29.2.2.9 Endpoint Info Register (EPINFO) The EPINFO contains the currently active endpoint index. Th e contents of this re gister are updated each time a token is received by the USB device controller . 76543210 R EPST ALLEN CTRO VFLEN ACK EN TRANSEREN EPHAL TEN OUTEN INEN SETUPEN W[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-19 29.2.2.10 USB Configurat ion V alue Register (CFGR) 29.2.2.11 USB Configurat ion Attribute Register (CFGAR) The CFGAR contains attributes of the current configuration. 76543210 R 0 0 0 0 EPNUM EPDIR W R e s e t 00000000 Reg Addr MBAR + 0xB003 Figure 29[...]

MCF548x Refere nce Manual, Rev . 3 29-20 F re escale Semiconductor 29.2.2.12 USB Device Speed Register (SPEEDR) The SPEEDR contains the current US B operating speed of the USB module. It is updated by the USB 2.0 device controller when a USB reset, suspend, or resume process completes. 76543210 R 1 R M T W K E U P 100000 W R e s e t 100000 00 Reg A[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-21 29.2.2.13 USB Frame Number Register (FR MNUMR) 29.2.2.14 USB Endpoint T ransaction Number Register (EPTNR) The EP TNR is used for high-spee d, high-bandwidth, isochronous IN endpoints only . It contains the number of transactions required by th e endpo[...]

MCF548x Refere nce Manual, Rev . 3 29-22 F re escale Semiconductor 29.2.2.15 USB Application In terf ace Update Register (IFUR) The IFUR is used by the USB applic ation to perform a high- speed update of the al ternate setting of a specified interface. It cannot be addressed as 8 bits. When application software writes to this register , a parallel [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-23 29.2.3 USB Counter Registers The USB module contains a number of registers that keep statistics on the number of packets that have been received and tran smitted along with th e number of errors. 29.2.3.1 USB Pac ket Passed Count Register (PPCNT) 1 5 1[...]

MCF548x Refere nce Manual, Rev . 3 29-24 F re escale Semiconductor 29.2.3.2 USB Dropped P acket Counter Register (DPCNT) 29.2.3.3 USB CRC Error C ounter Register (CRCECNT) 29.2.3.4 USB Bitstu ffing Err or Counter Register (BSECNT) 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R DPCNT W R e s e t 0000000000000000 Reg Addr MBAR + 0xB082 Figure 29-19. USB Dr opp[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-25 29.2.3.5 USB PID Error Count er Register (PIDECNT) 29.2.3.6 USB Framing Error Counter Register (FRMECNT) T able 29-21. BSECNT Fi eld Descriptions Bits Name Description 15–0 BSECNT Bitstuffing error coun ter . This register counts the occurrences of b[...]

MCF548x Refere nce Manual, Rev . 3 29-26 F re escale Semiconductor 29.2.3.7 USB T ransmitted P ac ket Counter Register (TXPCNT) 29.2.3.8 USB Counter Over flow Register (CNT O VR) The CNTOVR tracks overflow of each of the counter re gisters described above. When a counter overflow occurs, the appropriate bit in this register is set, and the USBAISR[[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-27 29.2.4 Endpoint Context Register s The endpoint registers are used to configure each of the individual endpoints. Some of the registers come in pairs: an IN register and an OUT register . The curre nt direction of the endpoint determines which of the t[...]

MCF548x Refere nce Manual, Rev . 3 29-28 F re escale Semiconductor 29.2.4.2 Endpoint n Max Pac ket Size Register (EP0MPSR, EP n OUTMPSR, EP n INMPSR) The endpoint max packet size registers contain the maximu m packet size that this endpoint, in its current configuration, is capable of transmitting or receiving. These registers should be updated by [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-29 29.2.4.3 Endpoint n Interface Number Register (EP0IFR , EP n OUTIFR, EP n INIFR) These registers identify which inte rface each particular endpoi nt is a memb er of. They should be updated by the USB application before en abling the USB device for the [...]

MCF548x Refere nce Manual, Rev . 3 29-30 F re escale Semiconductor 29.2.4.4 Endpoint n Status R egister (EP0SR, EP n OUTSR, EP n INSR) The endpoint status register contains the status for the specified endpoint. The AC TIVE bit of this register must be set before doing any transaction on this endpoint. 76543210 RI F N U M W R e s e t 00000000 Reg A[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-31 29.2.4.5 bmRequest T ype Register (BMRTR) The BMR TR records the bmRequestT ype fiel d of a SETUP transaction on Endpoint 0. 5 TXZERO T ransmit a zero byte pac k et. This bit should only be set by the application and cleared by the USB module. 0 NOP (d[...]

MCF548x Refere nce Manual, Rev . 3 29-32 F re escale Semiconductor 29.2.4.6 bRequest T ype Register (BRTR) The BR TR records the bRequest field of a SETUP transaction on Endpoint 0. 29.2.4.7 wV alue Register (WV ALUER) The WV ALUER records the wV alue field of a SETUP transaction on Endpoint 0. T able 29-30. BMR TR Field Des criptions Bits Name Des[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-33 29.2.4.8 wIndex Register (WINDEXR) The WINDEXR records the wIndex field of a SETUP transaction on Endpoint 0. 29.2.4.9 wLength R egister (WLENGTHR) The WLENG THR records the wLength fiel d of a SETUP transaction on Endpoint 0. . 29.2.4.10 Endpoint n Sy[...]

MCF548x Refere nce Manual, Rev . 3 29-34 F re escale Semiconductor When the host directs a SYNCH_FRAM E control read query at this re gister ’ s endpoint, the contents of this register are returned to the host. FRMNUM may range from 0x000 through 0x7FF . 29.2.5 USB Endpoint FIFO Registers These registers are used to configure and ac cess the FIFO[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-35 29.2.5.2 USB Endpoint n Interrupt Status Register (EP n ISR) The EP n ISR monitors the status of a specific endpoint and generates a CPU interrupt each time a monitored event occurs. An interrupt, once set, remains se t until cleared by writi ng a 1 to[...]

MCF548x Refere nce Manual, Rev . 3 29-36 F re escale Semiconductor If a register write oc curs at the same time a n in terrupt is received, the interr upt takes precedence over the write. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0000 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Uninitialized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0000 0 0 0 F U E M T [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-37 29.2.5.3 USB Endpoint n Interrupt Mask Register (EP n IMR) The EP n IMR allows software to ma sk individual in terrupts for each endpoint by masking the corresponding bits in the EPISR. W r iting a 1 to a bit in this register masks th e corresponding i[...]

MCF548x Refere nce Manual, Rev . 3 29-38 F re escale Semiconductor 29.2.5.4 USB Endpoint n FIFO RAM Configuration Register (EP n FRCFGR) The EP n FRCFGR allows the software to allocate the total FIFO RAM space among the individual endpoint FIFOs. Note that care should be taken to ensure that no two active endpoints are allocated to the same memory [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-39 29.2.5.5 USB Endpoint n FIFO Data Register (EP n FDR) The EP n FDR is the main interface por t for the FIFO. Data that is to be buf fered in the FIFO, or has been buffered in the FIFO, is accessed th rough this register . Th e register can access data [...]

MCF548x Refere nce Manual, Rev . 3 29-40 F re escale Semiconductor 29.2.5.6 USB Endpoint n FIFO Status Register (EP n FSR) T able 29-40. EP n FDR Field Descriptions Bits Name Description 31–0 TXDA T A This is the transmit FIFO write data 31–0 RXDA T A Th is is the receiv e FIFO read data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R IP TXW [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-41 23 F AE F rame accept error . This bit indicates a frame accept error in th e FIFO controller and will asser t in two scenari os. 1) The user has over-written data in a transmit FIFO for a pa ck e t (frame) that needs to be retr ied. 2) The use r has r[...]

MCF548x Refere nce Manual, Rev . 3 29-42 F re escale Semiconductor 29.2.5.7 USB Endpoint n FIFO Contr ol Register (EP n FCR) 31 30 29 28 27 2 6 25 24 23 22 21 20 19 18 17 16 RS H A D 0 W F R T M R F R M G R I P MSK FA E MSK RXW MSK UF MSK OF MSK TXW MSK 00 W R e s e t 0 U n i n . 0 0 0001001001 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R COUNTER W [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-43 26-24 GR Gr anularity . The functionality of this fiel d depe nds on the direction of the FIFO. The direction, type, and pack e t size are defined in the EPnST A T registers. For T ransmitter (IN): These bits control the h igh “watermar k ” point a[...]

MCF548x Refere nce Manual, Rev . 3 29-44 F re escale Semiconductor 29.2.5.8 USB Endpoint n FIFO Alarm Register (EP n F AR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0000 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Uninitialized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0000 A L R M P W R e s e t U n i n i t i a l i z e d 0000000000 0 0 Reg Addr MBAR + 0x[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-45 29.2.5.9 USB Endpoint n FIFO Read P ointer (EP n FRP) 29.2.5.10 USB Endpoint n FIFO Write P ointer (EP n FWP) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0000 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Uninitialized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0[...]

MCF548x Refere nce Manual, Rev . 3 29-46 F re escale Semiconductor 29.2.5.11 USB Endpoint n Last Read Frame P ointer (EP n LRFP) T able 29-45. EP n FWP F ield Descriptions Bits Name Description 31–12 — Reser ved, should be cleared. 11–0 WP Write p ointer . This v alue is maintained by the FIFO hardware and is not nor mally wr itten. Writing t[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-47 29.2.5.12 USB Endpoint n Last Write Frame P ointer (EP n LW F P ) 29.3 Functional Description 29.3.1 Interrupts Please see Chapter 13, “Interrupt Controller,” for information on the USB interrupts. 29.4 Software Interface This section provides information [...]

MCF548x Refere nce Manual, Rev . 3 29-48 F re escale Semiconductor At power-up time, the USB module contains no configuration info rmation. The USB module does not know how many endpoints it has availabl e or how to find th e descriptors. Initia lization for the device consists of downloading this inform ation to the appropriate memories and config[...]

Software Interface MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-49 Download of the descriptor data consists of the following steps: 1. V erify that the USBCR [RAMEN] bit is clear . This ensures that the datapath to the descriptor RAM is open to the application. 2. W rite the starting address of th e descriptors into the DADR fi el[...]

MCF548x Refere nce Manual, Rev . 3 29-50 F re escale Semiconductor 29.4.1.4 FIFO Siz es FIFO sizes must be program med to match the traf fic sent across the USB. The EP n FRCFGR along with the USBCR[RAMSPLIT] bit allow software to specify the memory configuration that is to be used at any given time. In most cases, all endpoints s hould be disabled[...]

Software Interface MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-51 29.4.3.1 USB Pac kets Data moves across the USB in units called packets. Packets range in size from 0 to 1024 bytes, and depending on the transfer mode, the pack et size is restricted to a small se t of values. Control packet sizes are limited to 8, 16, 3 2, or 64 [...]

MCF548x Refere nce Manual, Rev . 3 29-52 F re escale Semiconductor 2. On receiving EOF interrupt, prepare to read a comp lete packet of data. Cl ear the EOF interrupt so that software will receive not ification of the next frame. 3. Read the EP n FDR to read in the next piece of data. 4. Read the EP n FSR to get the end of frame status bits. If the[...]

Software Interface MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-53 further requests from the host. This guarantees that data from two di f ferent transfers will never get intermixed within the FIFO. NO TE The DMA extensions do not define a zer o length frame. Thus, it is necessary to have the CPU monitor the EOT inte rrupts and us[...]

MCF548x Refere nce Manual, Rev . 3 29-54 F re escale Semiconductor 4. Handle the request appropriately . If a data transf er is implied by the command, set up and perform the data transfer . Be careful not to send back more bytes to the USB host than were requested in the wLength field of the SETUP packet. The US B device controller hardware does n[...]

Software Interface MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 29-55 29.4.3.8 Isochronous Operations Isochronous operations are a special case of USB traffic. Instead of guaranteeing delivery with unbounded latency , isochronous traffic flows over the bus at a guaranteed rate with no error checking. 29.4.3.8.1 Isochronous T ransfer [...]

MCF548x Refere nce Manual, Rev . 3 29-56 F re escale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-1 Chapter 30 F ast Ethernet Controller (FEC) 30.1 Intr oduction This Fast Ethernet Controller (F EC) chapter provides a functional bloc k diagram, a feature-set overview , and transceiver conne ction information for both th e 10 and 100 Mbps MII (Media Independent Interface), as well as[...]

MCF548x Refere nce Manual, Rev . 3 30-2 F reescale Semiconductor Figure 30-1. FEC Block Dia gram 30.1.3 Overview The Fast Ethernet Controller is designed to support both 10 and 100 Mbps Et hernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports thre[...]

Introduction MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-3 30.1.4 Features The FEC incorporates the following features: • Support for three different Et hernet physical interfaces: — 100-Mbps IEEE 802.3 MII — 10-Mbps IEEE 802.3 MII — 10-Mbps 7-wire interface • IEEE 802.3 full duplex flow control • Programmable max fra[...]

MCF548x Refere nce Manual, Rev . 3 30-4 F reescale Semiconductor transceiver via this interface in the following sections: Section 30.4.3, “Network Interface Options ,” Section 30.4.13, “MII Data Frame ,” and Section 30.4.14, “MII Management Frame Structure .” 30.1.5.2.2 10 Mpbs 7-Wire Interface Operation The FEC supports a 7-wire inter[...]

External Signals MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-5 30.2.5 T ransmit Error (E n TXER) Assertion of this output signal for one or more clock cycles while E n TXEN is asserted shall cause the PHY to transmit one or more illegal symbols. Asserting EnTXER has no affect when opera ting at 10 Mbps or when E n TXEN is de-asse[...]

MCF548x Refere nce Manual, Rev . 3 30-6 F reescale Semiconductor . A false carrier condition occurs if the PHY detects a bad start-of-s tream delimiter . This condition is signaled to the MII by asserting E n RXER and placing 1 1 10 on E n RXD. E n RXDV must also be de-asserted. The vali d encodings of E n RXDV , E n RXER and E n RXD[3:0] are shown[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-7 30.3.2 Detailed Memory Map (Contr ol/Status Registers) T able 30-5 shows the FEC register memory map with each register address, name, and a brief description. T able 30-5. F EC Register Memo ry Map MBAR Offset for FEC0 MB AR Offset for FEC1 Name Byte 0[...]

MCF548x Refere nce Manual, Rev . 3 30-8 F reescale Semiconductor 30.3.3 MIB Block Counter s Memory Map T able 30-6 defines the MIB Counters memo ry map which defines the locat ions in the MIB RAM space where hardware maintained count ers reside. These fall in the 0x9200–0 x93FF address of fset range for FEC0 and the 0x9A00–0x9BFF address offset[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-9 which are supported do not require MIB counters. Counters for tr ansmit and receive full duplex flow control frames are included as well. T able 30-6. MIB Count ers Memory Map MB AR Offset for FE C0 MB AR Offset for FE C1 Mnemonic Description 0x9200 0x9[...]

MCF548x Refere nce Manual, Rev . 3 30-10 F re escale Semiconductor 30.3.3.1 Ethernet Interrupt Event Reg ister (EIR) When an event occurs that sets a bit in the EIR, an interrupt will be genera ted if the corresponding bit in the interrupt mask register (EIMR) is also set. The bit in the EIR is clear ed if a one is written to that bit position; wri[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-11 Interrupts resulting from errors/p roblems detected in th e network or transcei ver are HBERR, BABR, BABT , LC, and RL. Interrupts result ing from internal errors are HB ERR, XFUN, XFERR, and RF ERR. Some of the error interr upts are independently coun[...]

MCF548x Refere nce Manual, Rev . 3 30-12 F re escale Semiconductor 30.3.3.2 Interrupt Mask Reg ister (EIMR) The EIMR controls which possible interrupt events are a llowed to generate actual interrupts. All implemented bits in this CSR are read/write. This register is cleared upon a hardware reset. If the corresponding bits in both the EIR and EIMR [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-13 30.3.3.3 Ethernet Control Register (ECR) ECR is a read/write user register , though both fields in this register may be altered by hardware as well. The ECR is used to enable/disable the FEC. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R HBERR BABR[...]

MCF548x Refere nce Manual, Rev . 3 30-14 F re escale Semiconductor 30.3.3.4 MII Manag ement Frame Register (MMFR) The MMFR is accessed by the user and does not reset to a defined value. The MMFR register is used to communicate with the attached M II compatible PHY devices, providing read/write acc ess to their MII registers. Performing a write to t[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-15 T o perform a read or write operation on the MII Ma nagement Interface, the MMFR register must be written by the user . T o generate a va lid read or write management frame, the ST field must be written with a 01 pattern, and the T A field must be writ[...]

MCF548x Refere nce Manual, Rev . 3 30-16 F re escale Semiconductor The MII_SPEED field must be progr ammed with a value to provide an EMDC frequency of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII sp ecification. The MII_ SPEED must be set to a non-zero value in order to source a read or write management frame. After the ma[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-17 30.3.3.6 MIB Control Register (MIBC) The MIBC is a read/write register used to provide control of and to observe the state of the MIB block. This register is accessed by user so ftware if there is a need to disable the MIB block operation. For example,[...]

MCF548x Refere nce Manual, Rev . 3 30-18 F re escale Semiconductor 30.3.3.8 Receive Hash Register (RHR) This read only register provides address recognition information from the receive block about the frame currently being received. 31 30 29 28 27 26 25 24 23 2 2 21 20 19 18 17 16 R 00000 M A X _ F L W R e s e t 0000010111 1 0 1 1 1 0 1 5 1 4 1 3 [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-19 30.3.3.9 T ransmit C ontr ol Register (TCR) The TCR is read/write and is writte n by the user to configure the transm it block. This regist er is cleared at system reset. Bits 2 and 1 should be modified only when ECR[ETHER_EN] is cleared. 31 30 29 28 2[...]

MCF548x Refere nce Manual, Rev . 3 30-20 F re escale Semiconductor 30.3.3.10 Physical Ad dress Low Register (P ALR) The P ALR is written by the user . This register contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit address used in the address recogni tion process to compare with the DA (Destina tion Address) field of receive frames with an i[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-21 30.3.3.11 Physical Ad dre ss High Register (P AHR) The P AHR is written by the user . Th is register contains the upper 16 bi ts (bytes 4 and 5) of the 48-bit address used in the address rec ognition process to compare with th e DA (destination address[...]

MCF548x Refere nce Manual, Rev . 3 30-22 F re escale Semiconductor 30.3.3.12 Opcode/P ause Duration Register (OPD) The OPD is read/write accessible. This register contains the 16-bit opcode and 16- bit pause duration fields used in transmission of a P AUSE frame. The OPCODE field is a c onstant value, 0x0001. When another node detects a P AUSE fram[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-23 30.3.3.14 Individual Address Lower Register (IALR) The IALR register is writ ten by the user . This register contains the lower 32 bi ts of the 64-bit individual address hash table used in the addr ess recognition process to check for possible match wi[...]

MCF548x Refere nce Manual, Rev . 3 30-24 F re escale Semiconductor 30.3.3.15 Group Ad dress U pper Register (GA UR) The GAUR is written by the user . This register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Th is register must be initialized by the user . [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-25 30.3.3.17 FEC T r ansmit FIFO W atermark Register (FECTFWR ) The FECTFWR is a 32-bit read/write register programmed by the user to control the amount of data required in the transmit FIFO before transmission of a frame can begin. This allows the user t[...]

MCF548x Refere nce Manual, Rev . 3 30-26 F re escale Semiconductor 30.3.3.18 FEC Receive FIFO Data Register (FECRFDR) This is the main interface port for the FIFO. Data that is to be buf fered in the FIFO or that has been buffered in the FIFO is accessed through this register . It can be accessed by byte, word, or longword. It is recommended to ali[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-27 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R IP 0 0 0 FRM F AE RXW UF OF FRM RD Y FU ALARM EMT W w1c w1c w1c w1c w1c R e s e t 000000 00000000 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 000000 00000000 0 0 W R e s e t 000000 00000000 0 0 Reg Addr[...]

MCF548x Refere nce Manual, Rev . 3 30-28 F re escale Semiconductor 30.3.3.20 FEC Receive FIFO Control Register (FECRFCR) The FIFO receive control register provides programmability of FIFO behaviors, including last transfer granularity and frame operation. Last transfer granularity allows th e user to control when the FIFO controller stops requestin[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-29 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 000 T I M E R F R M EN GR IP_ MSK FA E _ MSK RXW_ MSK UF_ MSK OF_ MSK 10 0 W R e s e t 000 0 0 0 0 1 0 010 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R COUNTER W R e s e t 000 0 0 0 0 0 0 000 0 0 0 0[...]

MCF548x Refere nce Manual, Rev . 3 30-30 F re escale Semiconductor 30.3.3.21 FEC Receive FIFO Last Read Frame P ointer Register (FECRLRFP) The last read frame pointer (LRFP) is a FIFO-maintained pointer that indicates the location of the next byte after the last frame that has been completely rea d. If no frames have been read out of the FIFO, the [...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-31 in-between the read and write point ers) into framed and unframed data . Data between the L WFP and write pointer constitutes an incomplete frame, while data between the r ead pointer and the L WFP has been received as whole frames. When FECRF CR[FRMEN[...]

MCF548x Refere nce Manual, Rev . 3 30-32 F re escale Semiconductor 30.3.3.24 FEC Receive FIFO Read P ointer Register (FECRFRP) The read pointer is a FIFO maintain ed pointer which points to the next FIFO location to be read. The read pointer can be both read and written. This ability facilitates the debug of the FIFO controller and peripheral drive[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-33 30.3.3.25 FEC Receive FIFO Write P ointer Register (FECRFWP) The write pointer is a FIFO maintain ed pointer which points to the next FIFO location to be wr itten. The write pointer can be both read and written. This ability fa cilitates the debug of t[...]

MCF548x Refere nce Manual, Rev . 3 30-34 F re escale Semiconductor 30.3.3.27 FEC T r ansmit FIFO Status Register (FECTFSR) The FIFO transmit status register contains bits which provide inform ation about the status of the FIFO controller . Some of the bits of this re gister are used to generate DMA requests. 31 30 29 28 27 26 25 24 23 22 21 20 19 1[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-35 T able 30-34. FECTFSR F ield Descriptions Bits Name De scriptions 31 IP Ill egal pointer . This bit signifies an illegal pointe r condition in the FIFO controller. F or e xample, if a value larger than the FIFO controller’ s memor y range is wri tten[...]

MCF548x Refere nce Manual, Rev . 3 30-36 F re escale Semiconductor 30.3.3.28 FEC T r ansmit FIFO Control Register (FECTFCR) The FIFO transmit control register provides programmability of FIFO behaviors, including last transfer granularity and frame operation. Last transfer granularity allows th e user to control when the FIFO controller stops reque[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-37 30.3.3.29 FEC T ransmit F IFO Last Read Frame P o inter Register (FECTLRFP) The last read frame pointer (LRFP) is a FIFO-maintained pointer that indicates the location of the next byte after the last frame that has been completely rea d. If no frames h[...]

MCF548x Refere nce Manual, Rev . 3 30-38 F re escale Semiconductor 30.3.3.30 FEC T r ansmit FIFO Last Writ e Frame P ointer Register (FECTL WFP) The last read frame pointer (L WFP) is a FIFO-maintained pointer that indicates the lo cation of the next byte after the last frame that has b een completely written. If no frames have been written into th[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-39 30.3.3.31 FEC T ransmit F IFO Alarm Register (FECTF AR) This pointer provides low level alar m information to the user and the comm bus interface. A low level alarm reports lack of data. The alar m register defines the alarm thres hold for the number o[...]

MCF548x Refere nce Manual, Rev . 3 30-40 F re escale Semiconductor 30.3.3.32 FEC T r ansmit FIFO Read P ointer Register (FECTFRP) The read pointer is a FIFO maintain ed pointer which points to the next FIFO location to be read. The read pointer can be both read and written. This ability facilitates the debug of the FIFO controller and peripheral dr[...]

Memory Map/Regist er Definition MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-41 30.3.3.34 FEC FIFO Reset Register (F ECFRST) The FIFO’ s within the FEC module have independent cont rollers. This register pr ovides the user the ability to reset FIFOs via hardware or software. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0000[...]

MCF548x Refere nce Manual, Rev . 3 30-42 F re escale Semiconductor 30.3.3.35 FEC CRC and T r ansmit Frame Contr ol W ord Register (FECCTCWR) The FEC can be sent a control word (32-bit) with additional instructions on how to transmit the current frame. This control word ins tructs the FEC to ap pend or not append a CRC va lue to the f rame being tra[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-43 30.4 Functional Description This section describes the operation of the FEC, beginning with the ha rdware and software initia lization sequence, then the software (Ethernet driver) interface for transmitti ng and receiving frames. Following the software initia[...]

MCF548x Refere nce Manual, Rev . 3 30-44 F re escale Semiconductor 30.4.2 Frame Contr ol/Status W ords In the FEC, transmit frame contro l words and receive frame s tatus words are appe nded to frame data in the FIFO. These words use the format shown below . 30.4.2.1 Receive Frame Status W or d (RFSW) Figure 30-39 defines the format for the receive[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-45 30.4.2.2 T ransmit Frame Con tr ol W ord (TFCW) Figure 30-40 shows the format of the transmit frame control word. 20 NO Receiv e Nonoctet Aligned F rame. Written by the FEC . A frame that conta ined a number of bits not divisible by 8 was receiv ed, an d the C[...]

MCF548x Refere nce Manual, Rev . 3 30-46 F re escale Semiconductor 30.4.3 Netw ork Interface Options The FEC supports both an MII interf ace for 10/100 Mbps Ethernet and a 7-wire serial interface for 10 Mbps Ethernet. The interface mode is selected by the RCR[ MII_MODE] bit. In MII mode (RCR[MII_MODE] = 1), the followi ng 12 signals are defined by [...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-47 When the transmit FIFO fills to the watermark (defined by FECTFWR) or a complete (small) frame is placed in the FIFO, the FEC tr ansmit logic will assert E n TXEN and start transm itting the preamble (P A) sequence, the start f rame delimiter (SFD), and then t[...]

MCF548x Refere nce Manual, Rev . 3 30-48 F re escale Semiconductor During reception, the Ethernet controll er checks for various error condi tions and once the entire frame is written into the FIFO, a 32-bit fram e status word (RFSW) is written into the FIFO. This receive fr ame status word contains the M, BC, MC, LG , NO, CR, OF and TR status bits[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-49 Figure 30-41. Eth ernet Address Reco gnition—Receiv e Bloc k Decisions 30.4.7 Hash Algorithm The hash table algorithm used in th e group and individual hash filterin g operates as follows. The 48-bit destination address is mappe d into one of 64 bits, wh ich[...]

MCF548x Refere nce Manual, Rev . 3 30-50 F re escale Semiconductor The hash table registers must be initialized by the user . The CRC32 polynomial to use in computing the hash is: Eqn. 30-1 A table of example destination addresses and corresponding hash values is included below for reference. T able 30-49 . Destination Address to 6-Bit Ha sh 48-bit[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-51 59:FF:FF:FF:FF:FF 0x1C 28 79:FF:FF:FF:FF:FF 0x1D 29 29:FF:FF:FF:FF:FF 0x1E 30 19:FF:FF:FF:F F:FF 0x1F 31 D1:FF:FF: FF:FF:FF 0x20 32 F1:FF:FF :FF:FF:FF 0x21 33 B1:FF:FF:FF:FF:F F 0x22 34 91:FF:FF:FF:FF:F F 0x23 35 11:FF:FF:FF:FF:F F 0x24 36 31:FF:FF:FF:FF:F F 0[...]

MCF548x Refere nce Manual, Rev . 3 30-52 F re escale Semiconductor 30.4.8 Full Duplex Flow Contr ol Full-duplex flow control allows the user to transmit pause frames and to detect receiv ed pause frames. Upon detection of a pause frame, MAC data frame transmission st ops for a given pause duration. T o enable pause frame detection, the FEC must ope[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-53 The user must specify the desired pause duration in the OPD register . Note that when the transmitter is paused due to receive r/microcontroller pause frame detection, trans mit flow control pause (TCR[TFC_P AUSE]) still may be asse rted and will cause the tra[...]

MCF548x Refere nce Manual, Rev . 3 30-54 F re escale Semiconductor transmit side and/or limit the size of the frames to prevent transmit FIFO underr un and receive FIFO overflow . For external loopback set RCR[LOOP] = 0, RCR[DR T] = 0 and configure the ex ternal transceiver for loopback. 30.4.12 Ethernet Err or-Handling Pr ocedure The Ethernet cont[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-55 30.4.12.2 Reception Error s 30.4.12.2.1 Overrun Error If the receive block has data to put into the receive FIFO a nd the receive FIFO is fu ll, the FEC sets the OV bit in the receiv e frame status word (RFSW). A ll s ubsequent data in the fram e will be disca[...]

MCF548x Refere nce Manual, Rev . 3 30-56 F re escale Semiconductor The data portion of the frame consists of N octets which corresponds to 2N nibbles being transmitted. The order of each nibble is defined in the figure below . Figure 30-42. MII Nibble/Oct et to Octet/Nibble Ma pping The End-of-Frame delimiter is indicated by th e de-assertion of th[...]

Functional Descriptio n MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 30-57 4 A uto-Negotiation (AN) Advertisement E 5 AN Link P ar t ner Ability E 6 AN Expansion E 7 AN Ne xt P a ge T ransmit E 8-15 Reser ved E 16-31 V end or Specific E T able 30-52. MII Management Register Set (Cont inued) Register Addr . Registe r Name Basic/Extend[...]

MCF548x Refere nce Manual, Rev . 3 30-58 F re escale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor i Part V Mechanical Part V provides mechanical de scriptions of the MCF548 x . Contents • Chapter 31, “Mechanical Data,” provides a functional pin listing and package diagram for the MCF548 x .[...]

MCF548x Refere nce Manual, Rev . 3 ii F reescale Semiconductor[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 31-1 Chapter 31 Mechanical Data This chapter contains drawings showing the pinout, packaging, and me chanical characteristics of the MCF548 x . See the website http://www .freescale.com/coldfire for any updated information. 31.1 P acka ge The MCF548 x is assembled in a 388 -pin, thermally [...]

MCF548x Refere nce Manual, Rev . 3 31-2 F reescale Semiconductor A22 PSTDD A T A3 — — — R14 VSS — — — A23 PSTDD A T A7 — — — R15 VSS — — — A24 PCIBR0 PPCIBR0 TIN0 — R16 VSS — — — A25 PCIBR2 PPCIBR2 TIN2 — R23 IVDD — — — A26 1 E1RXD1 PFEC1L5 — — R2 4 PCIAD24 — FBADDR24 — B1 SD VDD — — — R25 PCIAD[...]

Pinout MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 31-3 C1 SD VDD — — — V3 AD4 — — — C2 CAS — —— V 4I V D D — — — C3 VSS — — — V23 DSPICS3 PDSPI5 TOUT3 CANTX1 C4 SDD A T A17 — — — V24 PCIBG1 PPCIBG1 T OUT1 — C5 SDD A T A19 — — — V25 PCIAD31 — FBADDR31 — C6 SD VDD — — — V26 PCIAD3[...]

MCF548x Refere nce Manual, Rev . 3 31-4 F reescale Semiconductor D6 VSS — — — AB2 AD15 — — — D7 SD ADDR2 — — — AB3 EVDD — — — D8 SD ADDR6 — — — AB4 VSS — — — D9 VSS — — — AB23 PSC3R TS PPSC3PSC26 PSC3FSYNC — D10 SD ADDR10 — — — AB24 D A CK0 PDMA2 TOUT0 — D11 IVDD — — — AB25 PSC1TXD PPSC1PSC0[...]

Pinout MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 31-5 F3 SD VDD — —— A C 2 5 D A C K 1 PDMA3 TOUT1 — F4 VSS — — — AC26 PSC2TXD PPSC3PSC20 — — F23 PCIP AR — —— A D 1 A D 1 6 — — — F24 PCISERR — —— A D 2 A D 2 1 — — — F25 PCIFRM — —— A D 3 A D 2 3 — — — F26 PCICXBE3 — —— A [...]

MCF548x Refere nce Manual, Rev . 3 31-6 F reescale Semiconductor K2 SDD A T A0 — — — AE4 AD27 — — — K3 SDD A T A1 — — — AE5 R/W PFBCTL2 TBST — K4 SDD A T A11 — — — AE6 OE PF BCTL3 — — K23 PCIAD0 — FBADDR0 — AE7 BE/BWE0 PFBCTL4 FBADDR0 — K24 PCIAD6 — FBADDR6 — AE8 1 E1RXER PFEC1L0 — — K25 PCIAD8 — FBADDR[...]

Pinout MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 31-7 M23 VSS — — — AF9 E0TXCLK PFEC0H7 — — M24 EVDD — — — AF10 E0MDIO PFECI2C3 — — M25 PCIAD12 — FBADDR12 — AF11 E0RXD3 PFEC0L3 — — M26 PCIAD13 — FBADDR13 — AF12 E0RXD2 PFEC0L2 — — N1 SDCLK0 — — — AF13 E0RXD1 PFEC0L1 — — N2 SDCLK0 — ?[...]

MCF548x Refere nce Manual, Rev . 3 31-8 F reescale Semiconductor 31.3 Mechanical Dia grams 31.3.1 MCF5485/5484 Mec hanical Diagram Figure 31-1 – Figure 31-4 show the pinout for the each qua drant of the MC F5485/MCF5484 388 PBGA package. Figure 31-1 shows the pinout for the upper left quadrant. Figure 31-1. MCF5 485/5484 Upper Le ft Quadrant Pino[...]

Mechanical Diagrams MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 31-9 Figure 31-2 shows the pinout for the upper right quadran t of the MCF5485/MCF5484 pinout for the 388 PBGA package. Figure 31-2. MCF5 485/5484 Upper Right Quadrant Pi nout (388 PBGA) 14 15 16 17 18 19 20 21 22 23 24 25 26 A IRQ5 DSI/TDI TCK CLKIN MTMOD 1 PLL VDD RST[...]

MCF548x Refere nce Manual, Rev . 3 31-10 F re escale Semiconductor Figure 31-3 shows the pinout for the lo wer left quadrant of the MC F5485/MCF5484 pinout for the 388 PBGA package. Figure 31-3. MCF5485/5484 Lo wer Le ft Quadrant Pinout (388 PBGA) 123456789 1 0 1 1 1 2 1 3 P SDCS1 SDCS2 SD VDD IVDD VSS VSS VSS R FBCS5 SDCS3 EVDD VSS VSS VSS VSS T F[...]

Mechanical Diagrams MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 31-11 Figure 31-4 shows the pinout for the lo wer left quadrant of the MC F5485/MCF5484 pinout for the 388 PBGA package. Figure 31-4. MCF5485/5484 Lo wer Ri ght Quadrant Pinout (38 8 PBGA) 14 15 16 17 18 19 20 21 2 2 23 24 25 26 P VSS VSS VSS PCIAD 19 PCIAD 20 PCIAD 18 [...]

MCF548x Refere nce Manual, Rev . 3 31-12 F re escale Semiconductor 31.3.2 MCF5483/5482 Mec hanical Diagram Figure 31-5 – Figure 31-8 show the pinout for the each qua drant of the MC F5483/MCF5482 388 PBGA package. Figure 31-5 shows the pinout for the upper left quadrant. Figure 31-5. MCF5 483/5482 Upper Le ft Quadrant Pinout (388 PBGA) 123456789 [...]

Mechanical Diagrams MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 31-13 Figure 31-6 shows the pinout for the upper right quadran t of the MCF5483/MCF5482 pinout for the 388 PBGA package. Figure 31-6. MCF5 483/5482 Upper Right Quadrant Pi nout (388 PBGA) 14 15 16 17 18 19 20 21 22 23 24 25 26 A IRQ5 DSI/TDI TCK CLKIN MTMOD 1 PLL VDD RS[...]

MCF548x Refere nce Manual, Rev . 3 31-14 F re escale Semiconductor Figure 31-7 shows the pinout for the lo wer left quadrant of the MC F5483/MCF5482 pinout for the 388 PBGA package. Figure 31-7. MCF5483/5482 Lo wer Le ft Quadrant Pinout (388 PBGA) 123456789 1 0 1 1 1 2 1 3 P SDCS1 SDCS2 SD VDD IVDD VSS VSS VSS R FBCS5 SDCS3 EVDD VSS VSS VSS VSS T F[...]

Mechanical Diagrams MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 31-15 Figure 31-8 shows the pinout for the lo wer left quadrant of the MC F5483/MCF5482 pinout for the 388 PBGA package. Figure 31-8. MCF5483/5482 Lo wer Ri ght Quadrant Pinout (38 8 PBGA) 14 15 16 17 18 19 20 21 2 2 23 24 25 26 P VSS VSS VSS PCIAD 19 PCIAD 20 PCIAD 18 [...]

MCF548x Refere nce Manual, Rev . 3 31-16 F re escale Semiconductor 31.4 MCF5481/5480 Mechanical Dia gram Figure 31-9 – Figure 31-12 show the pinout for the each qua drant of the MCF5481/MCF5480 388 PBGA package. Figure 31-9 shows the pinout for the upper left quadrant. Figure 31-9. MCF5 481/5480 Upper Le ft Quadrant Pinout (388 PBGA) 123456789 1 [...]

MCF5481/5480 Mechanical Diagram MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 31-17 Figure 31-10 shows the pinout for the uppe r right quadrant of the MC F5481/MCF5480 pinout for the 388 PBGA package. Figure 31-10. MCF5481/5480 Upper Rig ht Quadrant Pinout (388 PBGA) 14 15 16 17 18 19 20 21 22 23 24 25 26 A IRQ5 DSI/TDI TCK CLKIN MTMO[...]

MCF548x Refere nce Manual, Rev . 3 31-18 F re escale Semiconductor Figure 31-1 1 shows the pinout for the lo wer left quadrant of the MC F5481/MCF5480 pinout for the 388 PBGA package. Figure 31-11. MCF5 481/5480 Lo wer Left Quadrant Pinout (388 PBGA) 123456789 1 0 1 1 1 2 1 3 P SDCS1 SDCS2 SD VDD IVDD VSS VSS VSS R FBCS5 SDCS3 EVDD VSS VSS VSS VSS [...]

MCF5481/5480 Mechanical Diagram MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor 31-19 Figure 31-12 shows the pinout for the lower left quadr ant of the MCF5481/MCF5480 pinout for the 388 PBGA package. Figure 31-1 2. MCF5485/5484 Lowe r Ri ght Quadrant Pinout (388 PBGA) 14 15 16 17 18 19 20 21 2 2 23 24 25 26 P VSS VSS VSS PCIAD 19 PCIAD[...]

MCF548x Refere nce Manual, Rev . 3 31-20 F re escale Semiconductor 31.5 Mechanicals 388-pin PBGA P ackage Outline 31.6 Case Dra wing Figure 31-13 shows the MCF548 x case drawing. Figure 31-13. 3 88-pin BGA Case Out line[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor A-1 Appendix A MCF548 x Memory Map Ta b l e A - 1 lists an overview of the memory map for the on-chip modules. T able A-1. MCF54 8 x Module Memo ry Map Overvie w Addr ess Name (abbreviation) Description MBAR + 0x0000 – 0x00FF SIU SIU ov ervi ew registers MBAR + 0x0100 – 0x01FF SDRAMC S[...]

MCF548x Refere nce Manual, Rev . 3 A-2 F reescale Semiconductor MBAR + 0x8000 – 0x80FF DMA Multi-Channel DMA registers MBAR + 0x8100 – 0x83FF Reser ved — MBAR + 0x8400 – 0x84FF SCPCI Mul ti-Channel DMA PCI registers MBAR + 0x8500 – 0x85FF Reser ved — MBAR + 0x8600 – 0x86FF PSC0 Programmab le Serial Controller registers MBAR + 0x8700 ?[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor A-3 NO TE Read and write accesses to reserved MBAR spaces will re sult in undefined behavior that may result in a non-terminated bus cycle. This applies to the reserved locations between modules and the reserved locations within valid module address ranges. MBAR + 0x1_FF00 – 0x1_FFFF SRA[...]

MCF548x Refere nce Manual, Rev . 3 A-4 F reescale Semiconductor[...]

Index MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor Inde x-1 A Acknowledge error (ACKERR) 21-16 Addressing modes 3-18 Associated functions 15-3 B BDM, see debug Bit error (BITERR) 21-16 Bus off interrupt (BOFFINT) 21-17 Bus, see FlexBus 17-1 Byte lanes 17-2 C Cache cache-inhibited accesses 7-13 initialization 7-30 interaction with SRA[...]

MCF548x Refere nce Manual, Rev . 3 Inde x-2 F reescale Semico nductor configuration/status (CSR) 8-1 1 data breakpoint/mask (DBR, DBMR) 8-2 2 extended trigger definition (XTDR) 8-25 PC breakpoint ASID (PBASID) 8-24 PC breakpoint ASID control (PBAC) 8-1 4 program counter breakpoint/mask (PBR n , PBMR) 8-20 trigger definition (TDR) 8-17 signals 8-2 t[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor Inde x-3 port interrupt enable (EPIER) 14-4 Error counters 21-30 Ethernet address recognition 30-48 collision handling 30-53 errors handling 30-54 reception CRC 30-55 frame length 30-55 non-octet 30-55 overrun 30-55 truncatio n 30-55 transmission attempts limit expired 30 -54 heartbeat 30-[...]

MCF548x Refere nce Manual, Rev . 3 Inde x-4 F reescale Semico nductor structure 21-19 time stamp 21-28 transmit codes 21- 22 error status flag (TXW ARN) 21-16 priority 21-24 operation 21-19–21-3 1 bit timing con figuration 21-29 debug mode 21-3 listen-only mode 21-4 receive process 21-24 registers control (CANCTRL) 21-8 error and status (EST A T)[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor Inde x-5 repeated start 28-1 1 signals SCL 28-2 SDA 28-2 ST AR T 28-9 STOP 28-9 Instruction s architecture additions 3-19 branch acceleration 3-4 debug 8-54 , 8-60 EMAC execution timing 4-1 1 summary 4-1 1 execution timing 3-27 branch 3-33 EMAC 3-34 FPU 3-35 miscellaneous 3-32 MOVE 3-28 on[...]

MCF548x Refere nce Manual, Rev . 3 Inde x-6 F reescale Semico nductor Mechanical data case drawing 31-20 diagram 31-8 pinout 31-1 Memory maps debug 8-10 DMA 24-3 DSPI 27-4 EMAC 4-5 EPOR T 14-2 Ethernet control and status registers 30-7 MIB block counters 30-8 FlexCAN 21-5 I 2 C 28-3 interrupt controller 13-4 JT AG 23-4 MMU 5-1 1 PCI controller 19-4[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor Inde x-7 initiator window 2 base/translatio n address (PCIIW2BT AR) 19-19 initiator window confi guration (PCIIWCR) 19-19 revision ID/class code (PCICCRIR) 19-9 Rx done counts (PCIRDCR) 19-41 Rx enable (PCIRER) 19-38 Rx FIFO alarm (PCIRF AR) 19-46 Rx FIFO control (PCIRFCR) 19-45 Rx FIFO da[...]

MCF548x Refere nce Manual, Rev . 3 Inde x-8 F reescale Semico nductor R RAMBAR 3-13 Registers cache access control (ACR n ) 3-13, 5-5, 5 -6, 7-22 configuration (CACR) 3-13 control (CACR) 5-5, 7-19 core address (A n )3 - 9 condition code (CCR) 3-9 data (D n )3 - 9 module base address (MBAR) 3-13 RAM base address (RAMBAR) 3-13 status (SR) 3-12 user s[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor Inde x-9 PCI grant pin assignment (P AR_PC IBG) 15-25 PCI request pin assignm ent (P AR_PCIBR) 15-26 port clear output data (PCLRR_ x ) 15-18–15-20 port x data direction (PDDR_ x ) 15-1 1–15 -14 port x output data (PODR_ x ) 15-8–15-11 port x pin assignment (P AR_ x )1 5 - 2 1 port x[...]

MCF548x Refere nce Manual, Rev . 3 Index-10 F re escale Semiconductor infrared FIR divide (PSCIRFDR n )2 6 - 2 6 infrared MIR divide (PSCIRMDR n )2 6 - 2 5 infrared SIR divide (PSCIRSDR n )2 6 - 2 5 input port (PSCIP) 26-21 input port (PSC IP n ) 26-21 input port change (PSCIPCR n ) 26-17 interrupt mask (PS CIMR n )2 6 - 1 9 interrupt status (PSCIS[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor Index-11 USB application interface update (IFU R) 29-22 application interrupt mask (USBAIMR) 29-17 application interrupt status (USBIASR) 29-16 bitstuffing error counter (BSECNT) 29 -24 bmrequest type (BMR TR) 2 9-31 brequest type (BR TR) 29-32 configuration attribute (CFGAR) 29-19 configu[...]

MCF548x Refere nce Manual, Rev . 3 Index-12 F re escale Semiconductor execution units access 22-1 1 AESU 22-6, 22-83 AFEU 22-5, 22-67 DEU 22-4, 22-72 MDEU 22-6, 22-77 multifunction data packet descripto rs 22-90 multiple assignment 22-1 1 RNG 22-8, 22-8 2 memory map 22-8 registers AESU interrupt mask (AESIMR) 22-54 AESU interrupt status (AESISR) 22[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor Index-13 transfer burst (TBST ) 2-1 7, 17-4 transfer size (TSIZ n ) 2-17, 17-4 transfer start (TS ) 2 -17, 17-4 FlexCAN receive (CANRX0, CANRX1) 2-27 transmit (CANTX0, CANTX1) 2-27 general-purpose timers inputs (TIN n )2 - 2 9 outputs (TOUT n )2 - 2 9 GPIO 15-3–15-7 I 2 C SCL 28-2 SDA 28[...]

MCF548x Refere nce Manual, Rev . 3 Index-14 F re escale Semiconductor write data byte mask (SDDM n )2 - 1 9 write data byte mask (SDDM n ) 18-3 write enable (SDWE ) 2-19, 18-3 test mode (MTMOD n )2 - 3 0 timers GP T TIN n 11 - 2 USB differential data 29-3 differential data (USBD+, USBD–) 2-26 USBCLKIN 2-26, 29-4 USBCLKOUT 2-26, 2 9-4 USBRBIAS 2-2[...]

MCF548x Refere nce Manual, Rev . 3 F reescale Semiconductor Index-15 device speed (SPEEDR) 29-20 dropped packet counter (DPCNT ) 29-24 endpoint info (EPINFO) 29-18 endpoint n attribut e control 29-27 endpoint n FIFO alarm (EP n F AR) 29-44 endpoint n FIFO contro l (EP n FCR) 29-4 2 endpoint n FIFO data (EP n FDR) 29-39 endpoint n FIFO RAM configura[...]

MCF548x Refere nce Manual, Rev . 3 Index-16 F re escale Semiconductor[...]

Ov er vie w Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMA C) Memor y Management Unit (MMU) Floating-P oint Unit (FPU) Deb ug Suppor t System Integr ation Unit (SIU) Local Memor y Edge P or t Module (EPOR T) Inde x Interrupt Controller (INTC) 20 General Pur pose I/O (GPIO) 14 13 15 PCI Bus Arbiter (PCIARB) 2 3 5 6 7 8 9 4 [...]

Ov er view Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMA C) Memor y Management Unit (MMU) Floating-P oint Unit (FPU) Deb ug Suppor t System Integr ation Unit (SIU) Local Memor y Edge P or t Module (EPOR T) Inde x Interrupt Controller (INTC) 20 General Pur pose I/O (GPIO) 14 13 15 PCI Bus Arbiter (PCIARB) 2 3 5 6 7 8 9 4 G[...]