Fujitsu FR30 Bedienungsanleitung

FUJITSU SEMICONDUCT OR CONTROLLER MANU AL FR30 32-Bit Microcontroller MB91F109 Hardware Manual CM71-10106- 1E[...]

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FUJITSU LIM ITED FR30 32-Bit Microcontroller MB91F109 Hardware Manual[...]

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i PREFACE ■ Objectives and Intended Reader The MB91F109 has been de veloped as one of the " 32-bit sing le-chip mi crocon troller FR30 series" products tha t use new RISC architec ture CPUs as their core s. It has op timal specific ations for e mbedding applicat ions that require hi gh CPU pro cessing p ower. This manu al explains the f[...]

ii ■ Organization of This Manual This manu al consis ts of 16 c hapters and an appendi x. Chapter 1 Overv iew Chapter 1 provi des ba sic gen eral informat ion on the MB91F1 09, incl uding i ts char acteri stics, a block diagram, a nd functio n overvie w. Chapter 2 CPU Chapter 2 p rovides basi c informa tion on the FR se ries CPU core fun ctions i[...]

iii Chapter 14 PW M Timer Chapter 14 provides a n overview o f the PWM ti mer, explai ns the regis ter configur ation and function s, and ope rations of the PW M timer. Chapter 15 DMAC Chapter 15 provide s an ov erview of t he DMA C, explains the reg ister conf iguration a nd function s, and ope rations of the DMAC . Chapter 16 Flash M emory Chapte[...]

iv ©1999 FUJI TSU LIMITED P rinted in Japa n 1. The cont ents of this doc ument are sub ject to change w ithout noti ce. Customers a re advi sed to consult with F UJITSU sales rep resentatives b efore orderi ng. 2. The i nformat ion and c ircuit diagram s in th is docu ment are prese nted as examp les of se miconductor devic e applicati ons, and a[...]

v How to Read This Manual ■ Description Format of this Manual Major te rms used i n this ma nual are ex plained below: Term Meaning I-BUS 16-bit wide bus used for internal ins tructions . Since the FR seri es uses an inter nal Harvar d archite cture, indep endent buses are u sed for instruc tions and data. A bu s conve rter is conn ected t o the [...]

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vii CONTEN TS CHAPTER 1 OVERVIEW ............. ................... ......... .............. ................... ......... ......... ....... 1 1.1 MB91F109 Ch aracteristics ................. .................... ................... ............. ................... ........... ............... .. 2 1.2 General Block Diagram of M B91F109 .............[...]

viii 3.9 Gear Function . ................... ............. .................... ................... ................... ............. ....... ...................... 87 3.10 Standby M ode (Low Pow er Consumpti on Mechanis m) ......... ................... ............. .................... ......... 90 3.10.1 Stop State .. ................... .......[...]

ix 4.17.17 Hy per DRAM Interfa ce: Read ............... ................... ................... .................... ............. ....... .......... 1 88 4.17.18 Hy per DRAM Interfa ce: Write .. ................... ............. ................... .................... ................... ........... 189 4.17.19 Hy per DRAM Interfa ce ..... ......[...]

x 10.5 Serial Sta tus Register (S SR) .... ................... .................... ............ .................... ................... ....... ....... 253 10.6 UART Operation .......... ...... ....... ...... ....... ...... ....... ...... ....... ...... ...... ............. ....... ...... ....... . ..... ............. . 2 55 10.7 Asynchronou s (S[...]

xi 15.5 Descriptor Registe r in RAM ................ ....... ...... ............. ...... ....... ...... ....... ...... ....... ...... ....... .. ........... .... 332 15.6 DMAC Transfer M odes .... ................... ............. ................... .................... ................... ......... ........... .... 335 15.7 Output of Tran sfer Re[...]

xii FIGURES Figure 1.2-1 Gene ral Block Diagram of MB91F10 9 ............ ............. ................... .................... ................. ....... 6 Figure 1.3-1 Outsid e Dimensions of FPT-100P-M 06 .......... ................... ............. .................... .................. ...... 7 Figure 1.3-2 Outsid e Dimensions of FPT-100P-M 05[...]

xiii Figure 3.15 -1 Example of PLL Clock S etting .. ............. ................... .................... ................... .................... .... 1 08 Figure 3.15 -2 Clock Syste m Reference Diag ram ........ ................... .................... ............. ................... ........... 109 Figure 4.1-1 Bus Interface Registers ......[...]

xiv Figure 4.17 -12 Example 5 of Wr ite Cycle Tim ing Chart ................. ................... ............. ................... ............. . 169 Figure 4.17 -13 Example of Read and Write C ombinatio n Cycle Timing Chart .................... .................... ....... 170 Figure 4.17 -14 Example of Au tomatic Wai t Cycle Timing Ch art .....[...]

xv Figure 7.1-1 Delay ed Interrup t Module Regis te r ............... ...... ...... ....... ...... ....... ...... ....... ...... ....... ...... .. ..... .... 220 Figure 7.1-2 Del ayed Interrup t Module Blo ck Diagram ........... ................... ............. .................... ............. .... 220 Figure 8.1-1 Int errupt Controller R egiste[...]

xvi Figure 14.1 0-1 One-Shot Operation Ti ming Chart (Trigg er Restart Disabl ed) ........ .................... ................... . 318 Figure 14.1 0-2 One-Shot Operation Ti ming Chart (Trigg er Restart Ena bled) .. ............. ................... .............. 3 18 Figure 14.1 1-1 Causes of In terrupts and Their Timin g (PWM Output : Normal P[...]

xvii TABLES Table 1.4 -1 FBGA Pa ckage Pin Names ............. ............. ................... ................... .................... ................... 13 Table 1.5 -1 Pin Functio ns (1/5) ...... .................... ................... ................... ............. ................... .............. ...... 14 Table 1.5 -2 Pin Functio ns [...]

xviii Table 8.3 -1 Correspondence s between t he Interrupt Lev el Setting B its and Interrupt Levels ............ ....... 229 Table 8.5 -1 Relationships among Inte rrupt Causes, Numbers, an d Levels (1/2) ..... ................... ............. . 2 31 Table 8.5 -2 Relationships among Inte rrupt Causes, Numbers, an d Levels (2/2) ..... .............[...]

xix Table A-4 I/O M ap (4/6) .. .................... ............. ................... ................... .................... ........... ........ ........... 3 75 Table A-5 I/O M ap (5/6) .. .................... ............. ................... ................... .................... ........... ........ ........... 3 76 Table A-6 I/O M ap ...[...]

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1 CHAPTER 1 OVERVIEW This chapter pr o vides basic g eneral inf ormation on the MB91F109, inc luding its characteristics, bloc k diagram, and fu nction o verview . 1.1 MB91 F109 Chara cteristi cs 1.2 Ge ne ral Bl ock Diagr am of MB9 1F109 1.3 Outsid e Dim ensio ns 1.4 Pin Arr ange ment D iagra m s 1.5 Pi n Functio ns 1.6 I/O Circuit Format 1.7 Me m[...]

2 CHAPTER 1 OVE RVIEW 1.1 MB91F109 Characteristi cs The MB91F109 is a standar d single-chip micr ocontroller using a 32-bit RISC CPU (FR30 se ries) as its cor e . It contai ns v arious I/ O resources and bus control mechanisms for embedd ed contr ol applications that require high-speed CPU processing. This micr ocontroller contains 254-kilobyte fla[...]

3 1.1 MB 91F109 Chara cterist ics • Automati c wait cy cle: An y number of cycles ( 0 to 7) can be set for each ar ea. • Unuse d data and address term inals c an be used as I/O por ts. • Suppor t for little e ndian mod e (selecti ng one of a reas 1 to 5) ❍ DRAM interface • 2-bank independe nt control ( areas 4 an d 5) • Double CA S DRAM[...]

4 CHAPTER 1 OVE RVIEW convers ion • Starting: Selectable from software, e xternal trigg er, and internal timer ❍ Reload timer • 16- bit time r: Thre e channe ls • Internal clock: 2 -clock cy cle resoluti on. Selec table fr om 2-, 8-, a nd 32-frequ ency div ision mode ❍ Other interval timers • 16- bit time r: Th ree chan nel s (U-T ime r[...]

5 1.1 MB 91F109 Chara cterist ics ■ A vailable T ypes MB91V10 6 MB91106 MB91F109 IROM - 63 Kbyte - IRAM 64 Kb yte - - CROM - 64 Kbyte 254 Kb yte CRAM 64 K by te - 2 Kby te R A M 2 K b y t e2 K b y t e2 K b y t e I$ - - - Others - - -[...]

6 CHAPTER 1 OVE RVIEW 1.2 General Block Diag ram of MB91F109 Figure 1.2.1 is a general MB91F109 bloc k diagram. ■ General Block Dia gram of MB91F109 Figure 1.2-1 General B loc k Diagram of MB91F109 Notes: • Terminal s are rep resented by the function (some te rminals a re actua lly mult iplexed). • When RE ALOS is u sed, per form time m anage[...]

7 1.3 Outside Dimensions 1.3 Outsid e Dimensions Figures 1.3.1 to 1.3 .3 sho w the outside dimensi o ns of th e MB91F109 . ■ Outside Dimensions (QFP-100) Figure 1.3-1 Outside Dimensions of FPT -100P-M06 : * QFP100-P-1420-4 (F PT -100P -M06 ) (FPT -100P-M06) 1994 FUJITSU LIMITED F100008-3C-2 "A" 0.10(.004) 0.53(.021)MAX 0.18(.007)MAX Det[...]

8 CHAPTER 1 OVE RVIEW ■ Outside Dimensions (LQFP-100) Figure 1.3-2 Outside Dimensions of FPT -100P-M05 * QFP100-P-1414-1 (FPT -100P-M05 ) (FPT -100P-M05) C 1995 FUJITSU LIMITED F100007S-2C-3 Details of "B" par t 16.00 0.20(.630 .008)SQ 14.00 0.10(.551 .004)SQ 0.50(.0197)TYP .007 -.001 +.003 -0.03 +0.08 0.18 INDEX 0.10(.004) 0.08(.003) M[...]

9 1.3 Outside Dimensions ■ Outside Dimensions (FBGA -112) Figure 1.3-3 Outside Dimens ions of BGA-112P-M01 0.80 mm 11 10.00 × 10.00 mm 1.45 mm MAX 0.45 (BGA-112P -M01) (BGA-112P-M01) C 1998 FUJITSU LIMITED B112001S-2C-2 10.00 0.10(.394 .004)SQ .049 -.004 +.008 -0.10 +0.20 1.25 (Mounting height) 0.38 0.10(.015 .004) (Stand off) 0.10(.004) C0.80(.[...]

10 CHAPTER 1 OVE RVIEW 1.4 Pin Arrangement Diagram s Figures 1.4.1 to 1.4 .3 sho w the pin arra ngements of the MB91F109 . ■ Pin Arrangements (QFP-10 0) Figure 1.4-1 QFP -100 Pin A rrangements 80 78 79 77 76 75 73 74 72 71 70 68 69 67 66 65 63 64 62 61 60 58 59 57 56 55 53 54 52 51 96 97 98 99 100 91 92 93 94 95 86 87 88 89 90 81 82 83 84 85 26 2[...]

11 1.4 Pin Arra ngement Diagrams ■ Pin Arrang ements (LQFP -100) Figure 1.4-2 LQFP-100 Pin Arrangements P20/D16 P85/WR1X P84/WR0X P83/RDX P82/BRQ P81/BGRNTX P80/RDY MD2 MD1 MD0 VSS RSTX VCC NMIX PA0/CS0X PA1/CS1X PA2/CS2X EOP1/PA3/CS3X PA4/CS4X PA5/CS5X PA6/CLK VCC PB7/DW1X DACK2/PB6/CS1H DREQ2/PB5/CS1L A08/P50 A09/P51 A10/P52 A11/P53 A12/P54 A13[...]

12 CHAPTER 1 OVE RVIEW ■ Pin Arrang ements (FBGA-112) Figure 1.4-3 FBG A-112 Pin Arrang ements Table 1.4.1 shows the cross-re ferences o f the FBGA package pi n names. L K J H G F E D C B A 1 2 3 4 5 6 7 8 10 9 11 TOP VIEW INDEX[...]

13 1.4 Pin Ar rangement Diagrams T able 1.4-1 F BGA Pac kag e Pin Names BALL-No. PIN-NAME BALL-No. PIN-NAME BALL-No. PIN-NAM E A1 A2 A3 A4 A5 N.C RAS1 / PB4/ EOP2 CS0L/ PB1 INT1/ PE1 X1 D6 D7 D8 D9 D10 VCC DREQ0/ PE4 OCPA0/ PF 7/ ATGX AN2 AVRH H9 H10 H11 J1 J2 A14/ P 56 A13/ P 55 N.C. RDX/ P83 WR0X/ P8 4 A6 A7 A8 A9 A10 INT3/ SC2/ PE 3 DACK1/ PE7 S[...]

14 CHAPTER 1 OVE RVIEW 1.5 Pin Function s T ables 1. 5.1 to 1.5.5 list s the M B91F109 pin f unctions. The number s shown in the tables has nothing to do with the pack age pin number s. Since pins have diff erent pin numbers among QFP , LQFP , an d FBGA, see Section 1.4, "Pin Arrangement Dia grams." ■ Pin Functions T able 1.5-1 Pin Func[...]

15 1.5 Pin Functions 33 34 35 36 37 38 39 40 A16/P6 0 A17/P6 1 A18/P6 2 A19/P6 3 A20/P6 4 A21/P6 5 A22/P6 6 A23/P6 7 F Bits 16 to 23 of ex ternal addr ess bus. When the se pins are not used for the ad dress b us, they ca n be u sed as general-pu rpose I /O ports ( P60 to P67) . T able 1.5-1 Pin Functions (1 /5) NO. Pin name I/O c ircuit for mat Fun[...]

16 CHAPTER 1 OVE RVIEW 47 WR1X/P8 5 F Note: WR1X is Hi-Z whil e it is in res et state. When it is used as a 16-bit bu s, attach a pull-u p resistor to the outs ide. [P84 or P85] Whe n WR0X or W R1X is no t used, the pin c an be use d as a gen eral-purpos e I/O por t. 48 49 50 CS0X/PA 0 CS1X/PA 1 CS2X/PA 2 F Chip Sel ect 0 outp ut (Low ac tive) Chip[...]

17 1.5 Pin Functions T able 1.5-3 Pin Functions (3 /5) NO. Pin name I/O c ircuit for mat Function 55 56 57 58 59 60 61 62 RAS0/PB0 CS0L/PB1 CS0H/PB2 DW0X /PB 3 RAS1/ PB4/E OP2 CS1L/PB5/DREQ2 CS1H /PB6/ DACK2 DW1X /PB 7 F RAS outp ut of DRAM ba nk 0 CASL out put of DRAM b ank 0 CASH outp ut of DRAM b ank 0 WE output of DRA M bank 0 (Lo w active) RAS[...]

18 CHAPTER 1 OVE RVIEW 73 INT2/SC1/PE2 F [INT2] In put of extern al interrupt req uest. This input is used from time to tim e while th e corresp onding ex ternal inte rrupt is e nabled. Therefore, i t is need ed to stop output by other function s excep t when suc h output i s performe d intent ionally. [SC1] UAR T1 clock I/O . Clock out put can be [...]

19 1.5 Pin Functions 78 DACK1/PE 7 F [DACK1 ] Output o f DMAC external transfer request acceptan ce (ch 1). This function is valid when the ou tput of DMAC transfer requ est acceptan ce is en abled . [PE7] G eneral-pur pose I/O po rt. This function is valid wh en the outpu t of DMA C transfe r request acceptan ce or DA CK1 ou tput is disa bled. 79 [...]

20 CHAPTER 1 O VERVIEW 83 SO1/TRG 3/PF4 F [SO1 ] UART1 data outp ut. This fun ction is v alid when UAR T1 da ta outpu t is ena ble d. [TRG3] Ex ternal trigge r input of PW M timer . This function is valid wh en PF4 a nd UART1 dat a output is dis abled. [PF4] Gen eral-p urpose I/O port. This function is valid wh en UART1 data out put is disa bled. T[...]

21 1.5 Pin Functions Note: An I/O p ort and resourc e I/O are mu ltipl exed, as shown l ike xxx x/Px x, at mos t pins l isted above. If the port c onflicts with res ource outpu t at this typ e of pin, th e resource outpu t is given p riority. 92 AVR H - Referenc e voltage of A/D co nverter (hi gh potent ial side). A lways turn the pin on or off whi[...]

22 CHAPTER 1 O VERVIEW 1.6 I/O Circuit Format T ables 1. 6.1 and 1.6.2 sh ow s I/O cir cuit f ormats. ■ I/O Cir cuit Fo rmat T able 1.6- 1 I/O circuit format (1/2) Classification Circuit format Remarks A • For 50 MHz • Oscill ation feedb ack tra nsistor: About 1 M Ω • Standb y co ntr ol B • CMOS le vel hys teresis i nput • No sta ndby[...]

23 1.6 I/O Circuit Format D • CMOS le vel h ysteresi s input • No standby contro l T able 1.6- 1 I/O circuit format (1/2) Classification Circuit format Remarks CMOS Diffused resistor P-channel transistor N-channel transistor Digital input T able 1.6- 2 I/O circuit format (1/2) Classifi cation Circuit format Remarks E • CMOS level o utput • [...]

24 CHAPTER 1 OVE RVIEW 1.7 Memory Address Space The logical address space of the FR series consists of 4 gigab y tes (2 32 ad dresses) and the CPU a ccesses them li nearly . ■ Memory map Figure 1. 7.1 shows the memor y addre ss space o f the MB91F1 09. Figure 1.7-1 M B91F109 Memor y Map Note: The CPU ca n acces s no extern al areas i n single -ch[...]

25 1.7 Memory Address Spa ce ❍ Direct address ing area The followi ng area in th e addres s space is used for I/O. This area i s called the direct addres sing are a. The address es in this area can be direct ly specifi ed for ins tructio n operand s. The direc t address ing area va ries depen ding on the size of access ed data as follows : • By[...]

26 CHAPTER 1 OVE RVIEW 1.8 Handling of Devices This section pro vides notes on using devices. ■ Device Handling ❍ Latchup pre vention If volta ge hi gher than Vcc or lower th an V ss is ap plied to a CMOS IC inp ut or o utput pin or if voltage exce eding the r ating is a pplied b etwe en Vcc and V ss, latch up may be c ause d. La tchup rapidly [...]

27 1.8 Handling of Devices Figure 1.8-2 Example of Using an External Cloc k (P ossible at 12.5 MHz or Lo wer) ❍ Connection of po wer pins (Vcc and Vss) When two or mor e Vcc or Vss pins are used, the devi ce is des igned so that th e pins, w hich should b e at the s ame potenti al, are connecte d to one an other ins ide the d evice to pr event a [...]

28 CHAPTER 1 OVE RVIEW ❍ Initialization by power -on r eset Devices contain registe rs that a re initi alized only by power -on re set. To ini tialize these regist ers, turn th e power of f and turn it on agai n to execute power-on r esetting. ❍ Recovery from sleep or stopped state To reco ver from the sl eep or stopped state that has been en t[...]

29 CHAPTER 2 CPU This chapter pro vides basic inf ormation on the FR series CPU core funct ions including the ar chitecture, specifications, and instructions. 2.1 CPU Architecture 2.2 Inte rnal Architect ure 2.3 Progr ammin g Mode l 2.4 Da ta Structure 2.5 Word Align ment 2.6 Memory Map 2.7 Instru ction Overview 2.8 EIT ( Exceptio n, Inter rupt, an[...]

30 CHAPTER 2 CPU 2.1 CPU Architecture The FR30 CPU is a high perf ormance core that uses the RISC arc hitect ure an d suppor t s ad vanced functional instructions geared to embedding applications. ■ Char acteri stics o f CPU Arc hitec ture ❍ RISC architecture • Basic i nstru ct ion: One instru ction p er cycle ❍ 32-bit a r chitecture • 32[...]

31 2.2 Internal Architecture 2.2 Internal Architecture The FR CPU uses the Har var d arc hitecture in wh ich the instruction b us and data b us are independent of each other . The "32 bits <--> 16 bits" b us con verter is connected to the data b us (D-B US) to implement th e inte rface be tween the CPU a nd peripher al resour ces. T[...]

32 CHAPTER 2 CPU Figure 2.2-2 Instruction Pipeline Inst ruct ions ar e always ex ecut ed in or der. That is, in struction A that is put int o the pi peline before i nstruc tion B alw ays rea ches the write bac k stage before in structi on B. Instructi ons are normall y executed at a rate of on e instruction pe r cycle. However, a load/s tore instru[...]

33 2.3 Programming Model 2.3 Programming Model This section explains the CPU registers that ar e essential f or programming. The CPU registers are classified into the f ollowing tw o groups: • G eneral-purpose regi ster s • Special register s ■ Gener al- Purp ose R egi sters Figure 2. 3.1 shows the confi guration of g eneral-pur pose r egiste[...]

34 CHAPTER 2 CPU Figure 2.3-2 Configuration of special registers SCR CCR ILM PC PS TBR RP SSP USP MDH MDL 32 bits Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiplication/division result register[...]

35 2.3 Programming Model 2.3.1 General-Pu rpose Registers Register s R0 to R15 are general-purpose regis ter s. They are used as accum ulators f or v arious types of operation or memory access pointers. ■ General-Purpose Registers Figure 2. 3.3 shows the confi guration of g eneral-pur pose r egisters. Figure 2.3-3 Configuration of General-Purpose[...]

36 CHAPTER 2 CPU 2.3.2 Special Register s The special register s are used f o r special purposes. They are the program counter (PC), pr ogram status (PS), tab le base regi ster (TBR ), return point er (RP), system stack pointer (SSP), user stack pointer (USP), and m ultiplication/division result register (MDH/MDL). ■ Special Re gisters Figure 2. [...]

37 2.3 Programming Model ❍ Program status (PS) The program status register holds the progra m s tatus in three parts, CCR, SCR, an d ILM. See Section 2.3.3 fo r more info rmation. The undefin ed bits a re all res erved. Wh en the reg ister is re ad, 0 is a lways read from thes e bits. No data ca n be writt en to this register. ❍ T able ba se re[...]

38 CHAPTER 2 CPU [Division] When ca lculatio n begins , a dividend is stored in the MDL. The resu lt of divi sion by the DIV0S/DIV 0U, DIV1, DIV 2, DIV3 , or DIV4S in structi on is st ored in the MDL and MDH as follows: • MDH: Remai nder • MDL: Quo tient[...]

39 2.3 Programming Model 2.3.3 Pr ogram Status Register (PS) The pr og ram status register holds the pr ogram stat us in three parts, ILM, SCR, and CCR. The undefined bits are all reserved. When the register is r ead, 0 is al ways read fr om these bits. No data can be written to this register . ■ Pr ogram Status Register (PS) The config uration o[...]

40 CHAPTER 2 CPU [bit 3] N: Negative flag This bit ind icates a si gn applic able when the ope ration re sult is as sumed to be an in teger that is rep resente d in two’s c omplement. 0: Ind icates th at the oper ation re sult is a positi ve valu e. 1: Indic ates that t he operati on result is a nega tive val ue. The in itial va lue after resetti[...]

41 2.3 Programming Model [bit 8] T: St ep-trace-trap f lag This flag specifies whether to enable step -trace -trap. 0: Disab les step-t race-tra p. 1: Enabl es step-tr ace-trap. Sett ing the bi t to 1 inhibi ts all us er NMIs and user in terrupts. The flag i s cleared to 0 by resetting. The step- trace-trap function is used by an e mulator. It cann[...]

42 CHAPTER 2 CPU 2.4 Data Structure FR-series data is ma pped as f ollows : • Bit orderi ng: Little endian • Byte or dering: Big endian ■ Bit Or dering The FR se ries uses little endi an for bit or dering. Figure 2. 4.1 shows data mappi ng in bit ordering m ode. Figure 2.4-1 Data M apping in Bit Or d e ring Mode ■ Byte Or deri ng The FR se [...]

43 2.5 Word Alignment 2.5 Word Ali gnment Since instructions and data are acc essed in b y tes, mappi ng ad dress es v a ry depending on instruction length or data width. ■ Program Access A progra m runnin g in the FR series must be p laced at an address consis ting of a multiple of two. Bit 0 o f the program c ounter (P C) is se t to 0 wh en the[...]

44 CHAPTER 2 CPU 2.6 Memory Map This sectio n sho ws an MB91F109 memory map and a me mory map common to the FR series. ■ MB91F1 09 Memor y Map The addre ss space i s 32 bits l ong linea rly. Figure 2. 6.1 shows an MB91F10 9 memory map. Figure 2.6-1 MB91F109 Mem ory Map ❍ Direct address ing area The followin g area in the addre ss space is used [...]

45 2.6 Me mory Ma p ■ Memory Ma p Common to the FR Series The FR series defi nes the followi ng mem ory m ap. This mem ory m ap i s comm on t hroug hout the FR series reg ardless of types (except in s ingle chi p mode). Figure 2. 6.2 shows the memor y map co mmon to the FR series. Figure 2.6-2 Memor y Map Common to the FR Series. <Note> The[...]

46 CHAPTER 2 CPU 2.7 Instruction Overview The FR series suppor ts logical operation, bit manipulation, and dir ect addressing instructions, which are optimi zed for embeddi n g applications, in ad dition to g eneral RISC instructions. Each instruction, whi ch is 16 bits long (some are 32 bits or 48 bits long), shows e x cellent memor y use efficien[...]

47 2.7 Instruction Over vie w ❍ Logical operation and bit manipulation A logic al operation instruc tion can exe cute AND, O R, or EOR logi cal operati on between general -purpose regi sters or be tween a genera l-purpose re gister and mem ory (or I/O ). A bit manipul ation ins truction c an directl y manipu late the c ontents of memory (o r I/O)[...]

48 CHAPTER 2 CPU 2.7.1 Branc h Instructions with Dela y Slots A branc h instruction causes the pr ogram to bran ch a nd e x ecute the i nstruction at the branch destination af ter the instructi on (call ed the dela y slot) plac ed immediat el y afte r the branc h instruction is e xecute d. ■ Branch Instructions w ith Delay Slots The followi ng in[...]

49 2.7 Instruct ion Overvie w ❍ Ri that is re ferenced by the JMP:D @Ri or CALL:D @Ri instruction is not affected even when the instruction in the delay slot updates the Ri. [Example] ❍ RP that is re f erenc ed b y the RET :D instructio n is not affected even when t he instructio n in the dela y slot updates the RP . [Example] ❍ The flag that[...]

50 CHAPTER 2 CPU ■ Restri ctions on Branch Instructi ons with Delay Slots ❍ Instruc tions that can be place d in delay slots An in struction that ca n be exec uted in th e delay s lot must satisfy all of the follow ing cond itions: • One-cy cle inst ructi on • Non-br anch instr uction • Instruc tion whos e operation is not aff ected e ven[...]

51 2.7 Instruction Over vie w 2.7.2 Branch Instructions without Delay Slots Instructions inc luding branch instructions without dela y slots are ex ecuted in order of coding. ■ Branch Instructions Without Delay Slots The instr uctions r epresented as follow s execu te branchin g without de lay slo ts: ■ Theory of Operat ion of Branch Instructio[...]

52 CHAPTER 2 CPU 2.8 EIT (Excepti on, Interrupt, a nd Trap) EIT indicates that the pr ogram being e xecuted is interrupted by an e ven t and another program is e xecuted. EIT is a generic name coined fr om the w ords: e xception, interrupt, and tr ap. An exception is an event that occurs in connection with the conte xt of the current execution. Pro[...]

53 2.8 EIT (Exception, Interrupt, and Trap) ■ Not e on EI T ❍ Delay slot The delay slot of a branch instructi on has res trictions on EIT. See Sec tion 2.7, "Instructi on Overview," for details of the restricti ons.[...]

54 CHAPTER 2 CPU 2.8.1 EIT Interrupt Le vels The EIT interrupt le vels range from 0 to 31, w hich are mana g e d using five bits. ■ Interrupt Levels Table 2.8.1 summar izes the assignment s of the EIT interru pt levels. Operat ion can b e performed on level s 16 to 31. Undefined -instruc tion exce ptions, co proces sor none xistent tr aps, copro [...]

55 2.8 EIT (Exception, Interrupt, and Trap) ■ I Fla g The I flag spec ifies whether to enab le or disable inte rrupts. It is provid ed at bit 4 of PS register CCR. ■ Interrupt Level Mask Register (ILM) ILM is a part of the PS register (bi ts 16 to 20) t hat holds an interru pt level mas k value . Of the inte rrupt requ ests input to the CPU, on[...]

56 CHAPTER 2 CPU 2.8.2 Interr upt Contr ol R egister (ICR) The interrupt contr ol register , which is pr ovided in the interrupt contr oller , is used to set the level f or each interrupt request. The ICR is divided to correspond to indi vidual interrupt causes. The ICR is mapped in the I/O ad dress space and acce ssed fr om the CPU vi a the b us. [...]

57 2.8 EIT (Exception, Interrupt, and Trap) 2.8.3 System Stac k P ointer (SSP) The syste m stac k pointer (SSP) indic ates the s tack us ed to sa ve data f or EIT processing or restore data for returning fr om EIT . ■ Syst em St ac k P ointer (SSP ) The config uration of the syste m stack pointer (S SP) regi ster is sh own below: Value 8 is subt [...]

58 CHAPTER 2 CPU 2.8.4 Interr upt Stac k The interrupt s tac k is the are a indicate d b y the system stac k pointer (SSP). The PC or PS v alue is sa ved to it or restore d fr om it. After an i nterrupt is caused, the PC val ue is store d at the address i ndicated by the SSP an d the PS value is stor e d at the addr e ss "SSP + 4 ." ■ I[...]

59 2.8 EIT (Exception, Interrupt, and Trap) 2.8.5 T able Base Registe r (TBR) The tabl e base register (T BR) indica tes the fir st address of the EIT ve ctor table. ■ Table Base Register (TBR) The config uration of the table base re gister (TB R) is shown below: The addres s obtained by adding the offse t defined for each EIT cause to the TBR is[...]

60 CHAPTER 2 CPU 2.8.6 EIT V ector T able The 1-kilobyte area beginning fr om the address, indicated b y the tab l e base register (TBR), is the EIT ve ctor area . ■ EIT V ector T able The area si ze per vecto r is 4 bytes. The rel ationshi p between a vect or number an d vector addres s is repres ented as f ollows: The two low- order bit s of th[...]

61 2.8 EIT (Exception, Interrupt, and Trap) Table 2.8.3 is the v ector table in the ar chitectu re. Specia l functio ns are as signed to some v ectors . T able 2.8- 3 V ector T able Vector offset (hexadecimal) Vec tor number Explanation Hexadecima l Decimal 3FC 00 0 Reset (*1) 3F8 01 1 Reserved by the syst em 3F4 02 2 Reserved by the syst em 3F0 03[...]

62 CHAPTER 2 CPU 2.8.7 Multiple EIT Pr ocessin g When multiple EIT e vents occur concurrently , the CPU selects one EIT event, accepts it, ex ecut es the EIT sequence, and then detects another EIT e vent. It repeats this operation f or all EIT e vents. When no more acceptab le E IT ev ent is detected, the CPU ex ecutes the i nstruction of t he hand[...]

63 2.8 EIT (Exception, Interrupt, and Trap) Figure 2. 8.2 shows an example o f multi ple EIT proc essing. Figure 2.8-2 Example of Multiple EIT Pr oces sing T able 2.8-5 EI T Handler Execution Order Handler execution order Event 1 Reset (*1) 2 Undefin ed-instru ction ex ception 3 Step-trac e-trap * 2 4 INTE in structio n * 2 5 NMI (for user) 6I N T [...]

64 CHAPTER 2 CPU 2.8.8 EIT Operation This section explains EIT operation. Suppose the transfer sour ce "PC" appearing in the foll owing explanation indicates the address of the instr uction that detect ed an EIT event. "Ne xt inst ruction ad dress" appeari ng in the f ollo wing e xplanati on means the address of the i n s tructi[...]

65 2.8 EIT (Exception, Interrupt, and Trap) [Operation] SSP - 4 --> SSP PS --> (SS P) SSP - 4 --> SSP Next ins tructio n addres s --> (SS P) Interrupt level of accepted request --> ILM "0" -- > S flag (TBR + v ector offs et of acce pted inter rupt reque st) --> PC Before ex ecuting the fir st instructio n of the handl[...]

66 CHAPTER 2 CPU ■ Operation for Step -trace-trap After the T flag in the PS SC R is set to enabl e the step-trace function , a trap occurs every time an instr uction is executed , resulting in a bre ak. A step-tr ac e-t rap is dete ct ed unde r the foll owi ng con di tio ns: • T flag = 1 • Instru ction othe r than a d elaye d branch instru c[...]

67 2.8 EIT (Exception, Interrupt, and Trap) ■ Coprocessor Nonexistent T rap If a coproc essor inst ruction th at attempts to use a cop rocessor that is not installe d is executed, a copro cessor nonex istent trap occur s. [Operation] SSP - 4 --> SSP PS --> (SS P) SSP - 4 --> SSP Next ins tructio n addres s --> (SS P) "0" -- [...]

68 CHAPTER 2 CPU 2.9 Reset Sequence This section explains CPU resetting. ■ Causes of Rese tting The caus es of resett ing are a s follows : • Input f rom an externa l reset pin • Software r eset by mani pulation of th e SRST bit of standby c ontrol regis ter (STCR) • Expir ation of wa tchdog tim er • Power- on rese t ■ Initialization by[...]

69 2.10 Operat ion Mode 2.10 Opera tion Mode T wo operation modes, b us mode and access m ode, are av ailable . The mode pins (MD2, MD1, and MD0) and mode register (MODR) are used to contr ol the operation mode . ■ Operation Mode Two operat ion modes , bus mode and acc ess mode, ar e avail able. ❍ Bus mode In bus mod e, the oper ations of int e[...]

70 CHAPTER 2 CPU ■ Mode Data Data that th e CPU writ es at 0000 07FF H after resetting is called mode data. The mode regist er (MODR) exists at 0000 07FF H . After mode data is set to this register, the CPU oper ates base d on the mo de set to th e register . Mode data c an be writt en to the mode registe r only once a fter resetti ng. The mode s[...]

71 2.10 Operat ion Mode MODR writing RSTX (reset) MD2,1,0 BW1 and BW0 of AMD0 to AMD5 Bus width specification[...]

72 CHAPTER 2 CPU[...]

73 CHAPTER 3 CLOC K GENERATOR AND CON TROLLER This chapter pro vides detailed information on the generation and contr ol of c l oc k pulses that contr ol the MB 91F109. 3.1 Outline of Clock Generator and Contro ller 3.2 Re set Reason Re sister (R SRR) an d Watchdog Cycl e Con trol R egister (WTCR) 3.3 Standby Control Register (STCR) 3.4 DMA Requ es[...]

74 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.1 Outline of Clock Generator and Controller The c loc k g enerator and contr oller are the modules that have the f ollowing functions: • CPU c l ock generation (including the g ear function) • P eripheral cloc k g eneration (inc luding the g ear function) • Reset g eneration and cause retention ?[...]

75 3.1 Outline of Clock Gener ator and Controller ■ Clock Generator and Contr o ller Bloc k Diagram Figure 3. 1.2 is a b lock diagram of the clo ck genera tor and c ontroller. Figure 3.1-2 Block Diagram of the Cloc k Generator and Controller X0 PLL X1 1/2 R | B U S [Gear controller] GCR register CPU gear Peripheral gear PCTR register Oscilla- tio[...]

76 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.2 Reset Reason Resister (R SRR) and Watchd og Cycle Control Register (WTC R) The reset reason register (RSRR) holds the type of the reset event that occurred, and the watchdog cyc le control register (WTCR) specifies the cycle of the watc hdo g timer . ■ Configuration of Reset Re ason Register (RSRR) [...]

77 3.2 Reset Reas on Resister (RSRR) and Watchdog Cycle C ontrol Register (WTCR) [bit 09, 08] WT1, 0 These bits specify t he cycle of the watch dog timer . The bits a nd the cycle s selected by the bits have the relation ships sh own in Table 3. 2.1. These bit s are initial ized when t he entire register is reset. φ is twice as large as X0 when GC[...]

78 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.3 Standby Control R egister (STCR) The standby control r e gister (STCR) is used to control standb y operation and specify the oscilla tion stabilization wait time. ■ Configuration of Standby Contr ol R egister (STCR) The confi guration of standby c ontrol reg ister (STCR) i s shown below: ■ Bit Fun[...]

79 3.3 Standby Control Regis ter (STCR) φ i s twice as larg e as X0 when GCR CHC is 1, and is the cycle of PLL oscil lation freque ncy when CHC is 0. [bit 01, 00] (Reserv ed) These bit s are res erved. The v alue rea d from this bit is un defined. T able 3.3-1 Oscil lation Stabil ization W a it Time Specif ied by OSC1 and OSC0 OSC1 OSC0 Oscillatio[...]

80 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.4 DMA Request Sup pression Registe r (PDRR) The DMA request suppression register (PDRR) is used to temporaril y suppress DMA reque sts to lighten the load t o the CPU. ■ Configuration of the DMA Request Suppress ion Register (PDRR) The configurati on of the DM A request suppression register (P DRR) is[...]

81 3.5 Time base Timer Clea r Register (CTBR) 3.5 Timebase T imer Clear Register (C TBR) The timebase time r c l ear register (CTBR) c lear s the timebase timer to 0 f or initialization. ■ Configuration of the Timebase Timer Clear Register (CTB R) The config uration of the timeb ase time r clear regis ter (CTBR) i s shown b elow: ■ Bit Function[...]

82 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.6 Gear Control Re gister (GCR) The gear control register (GCR) contr ols the g ear functions of the CPU and peripheral clo cks . ■ Configuration of the Gear Control Register (GCR) The confi guration of the gear c ontrol regi ster (GC R) is shown below: ■ Bit Functions of t he Gear Contr ol Register [...]

83 3.6 Gear Control R egister (GCR ) [bit 12] DBLON This bit sp ecifies the cl ock doubler operation mode. This bit is initia lized by resetting. This model do es not su pport the c lock doub ler func tion. [bit 11, 10] PCK1, 0 These bits sp ecify the gear cycl e of peripher als. These bits , and the cycle s selecte d by the bits, ha ve the re lati[...]

84 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER When the clock doubler is set to O N, the CPU gear is fixed r egardle ss of the GCR value a nd therefore t he gear c an also b e set direc tly to th e desired v alue. [Example of programming] [bit 09] Re served bit Always write 1 to th is bit. [bit 08] CHC This bit select s the so urce of the ref erence c[...]

85 3.7 Watchdog Timer Res et Delay Register (WPR) 3.7 Watchd og Timer Reset Delay Re gister (WPR) The watchdog timer reset dela y register (WPR) c lears the flip-flop f or the watchdog timer . This register can be used to dela y watchdog timer resets. ■ Configuration of W atchdog Timer Reset Delay Register (WPR) The config uration of the watch do[...]

86 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.8 PLL Control Register (PCTR) The PLL contr ol register (PCTR) is used to contr ol PLL oscillation. The setting of this register can be changed only when GCR CHC is 1. ■ Configuration of PLL Contr o l Register (PCTR) The PLL con trol reg ister (PCTR) i s used to cont rol PLL o scillation. The s etting[...]

87 3.9 Gear Function 3.9 Gear Functi on The gear function su pplies cloc k pulses by slo wing down the c lock pulse interv als. The function uses tw o independent circuits f or the CPU and peripherals. Data can be transferred between the CPU and peripherals e ven when both cir cuits use different gear ratios. The function also permits a source c lo[...]

88 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example] The output fr om the divi de-by-two freq uency ci rcuit can be selected as the sourc e clock by setting the CHC bit of the gear control register to 1. Setting the CHC bi t to 0 selects the clock having t he same c ycle as th e clock g enerated f rom the osc illation c ircuit. S ince the s ource [...]

89 3.9 Gear Function Figure 3.9-2 Clock Selection Timing Char t ■ Blocks That Use the Peripheral Clock The block s listed b elow use the per ipheral c lock, which c an be set by the gea r function, a s the operati ng clock. Calcula te the opera tion time based on the frequenc y d ivis io n ratio se t to bi ts P CK 0 and PC K1 of the GCR regi ster[...]

90 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.10 S tandby Mode ( Low Power C onsump tion Mechanis m) The standb y mode implies the stop state a nd sleep state. ■ Outline of Stop State In the sto p state, a ll interna l clocks and the op eration of th e oscilla tion circui t are sto pped so a s to minim ize power c onsumpti on. Procee d as follows[...]

91 3.10 Standby Mode (Low Power Consumption Mechanism) *: When S TCR HIZX i s "0", the p revious s tate is he ld. Setti ng HIZX to " 1" puts th e pin to Hi -Z. <Note> Reset: RSTX = "0" SR ST bit o f STCR registe r = "0" W atchdog timer res et Po wer-on reset ■ Mapping Addresses of Programs Use d to Pu[...]

92 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.10.1 Stop State This section pr o vides inf ormation on transition to and returning from the stop state . Figure 3.10.1 sho ws a stop controller b lock dia gram. ■ Stop Contr oller Block Dia gram Figure 3.10-1 Stop Controller Block Diagram ■ T ransition to Stop State ❍ T ransition to the st op sta[...]

93 3.10 Standby Mode (Low Power Consumption Mechanism) [Example of setting the maximum gear sp eed:] ■ Returning fr om the Stop State An inter rupt or r esetting can be used to return fr om the stop state. ❍ Return by wa y of an i nterrupt When the in terrupt enabl e bit, which is one of the pe ripheral fu nctions, is on, a periph eral interrup[...]

94 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER L level application to RSTX pin --> occurrence of internal reset --> restar t of oscillation circuit operation --> wait for oscillation stabilization --> restart of internal peripheral clock supply after stabilization --> restart of interna l DMA clock supply --> restart of internal bus [...]

95 3.10 Standby Mode (Low Power Consumption Mechanism) 3.10.2 Sleep State This section pro vides inform ation on transition to the sleep state and returning fr om the sleep state . Figure 3.10 .2 sho ws a bloc k diagram of the sleep contr oller . ■ Sleep Controller Bloc k Diagram Figure 3.10-2 S leep Controller Block Diagram ■ T ransition to S [...]

96 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example of setting the maximum gear sp eed] ■ Returning fr om the Sleep State An inter rupt or r esetting can be used to return fr om the sleep state. ❍ Return by wa y of an interrupt When the en abl e b it for th e i nte rrup t, wh ic h is on e o f the p eriph er al fun ction s, is o n, a pe ri ph e[...]

97 3.10 Standby Mode (Low Power Consumption Mechanism) reques t occur simu ltaneou sly, the DMA reques t is given p riority. • When tra nsiti on t o the sl eep sta te ha s b een c au sed by a C- bus RA M pr og ra m, d o not use an interrupt, but reset instead to return from the sleep s tate.[...]

98 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.10.3 Standb y Mode State T ransition Figure 3.10.3 is a standb y mode state transition diagram . ■ Standby Mode State T rans ition Figure 3.10- 3 Standby Mode State T ransition (3) (1) (1) (5) (2) (3) (6) (3) (4) (5) (3) (1) End of oscillation stabilization wait time (2) Cancel of reset state (3) Inpu[...]

99 3.11 Watchdog Function 3.11 Watchdog Function The watchdog function detects pr ogram crashes. If A5 H and 5A H are not written to the watchdog reset postpone register within the specified time due to a pr ogram crash, the watc hd og timer issues a watchdog reset request. ■ W atchdog Contr olle r Block Dia gram Figure 3. 11.1 is a watchdog cont[...]

100 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER Figure 3.11-2 W atchdog Timer Operating Timing <Note> • The tim e interval between the f irst A5 H and the nex t 5A H is not specifie d. Watchd og resetting is po stponed only i f the ti me inter val from one 5A H to the ne xt 5A H is withi n the ti me specif ied by the WT bit s and one A5 H is w[...]

101 3.12 Reset Source Hol d Circuit 3.12 Reset Source Hold Circuit The reset sour ce hold cir cuit holds the source of pre vious resetting. Reading the cir cuit cle ars all flags to 0. Once a sour ce flag i s set, it is not c leared unles s the cir cuit is read. ■ Block Diagram of Reset Sour c e Hold Circ uit Figure 3. 12.1 is a block diag ram of[...]

102 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example] <Notes> • When the PO NR bit is 1, ass ume that the co ntents of the other bits are undefined . W hen it is req uired to check re set so urces, place a p ower-on re set chec k instr uction a t the begin ning. • Check instru ctions oth er than the i nstruct ion for pow er-on res et che[...]

103 3.13 DMA Suppressi on 3.13 DMA Suppression If an interrupt with a higher priority occur s during DMA transfer , the FR series interrupts DMA transfer and branc hes to t he corresponding interrupt r outine . This feature rem ains effective as long as an int errupt request continues. When the interrupt cause is c leared, the suppression feature i[...]

104 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example] <Note> Since t he register consist s of four bi ts, the DMA supp ression f unction c annot be u sed for mor e than 15 con curren t inter rupts. Alway s give a DMA task a pri ority th at is at leas t 15 levels highe r than that o f other interrupts . INT-ENTRY LDI:20 #PDRR, R10 LD @R10, R1[...]

105 3.14 Clock Doubler Function 3.14 Clock Doubler F unction As the internal operating frequenc y goes higher , the e xternal bus timing normally becomes more complicat ed. T o pre vent this, the r a tio of the ex ternal b us frequenc y to the internal operating frequency can be adjusted to 1 to 2 (1 : 2). This model does not suppor t th is functio[...]

106 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example] Code as fo llows to use the PL L clock af ter the cloc k doubler function is disable d: [Example] ■ Note on Enabling or Disabling the Clock Doubler Function Enablin g or dis ablin g the clock doubler function ma y caus e a dead cy cle i n the interna l cloc k. A dead cyc le appears as an erro[...]

107 3.14 Clock Doubler Function regist er. (Table 3 .14.1 shows an exam ple for the c ase that a 12.5 MH z oscillat ion is use d.) *1: Fixed to 1/1 regardle ss of se ttings *2: To d isable the c lock do ubler fu nction, s witch the clock t o the divi de-by- two cloc k in adv ance. *3: When the PLL os cillati on frequenc y is c hanged, the clock mus[...]

108 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.15 Examp le of PLL Clock Setting This section pr o vides an e xample of PLL c lock setting and an e xample of the assemb ler source. ■ Example of PLL Clock Setting An exam ple of th e proc edure for switchin g to 25 M Hz operati on using PLL (in the c ase of 1 2.5 MHz oscil lation) is shown be low: F[...]

109 3.15 Example of PLL Clock Setti ng • The peri pheral op erating fre quency mus t not exc eed 25 MHz . • Design s oftware so th at 100 micr oseconds or more ar e allowed u ntil oscil lation stabi lizes after the PL L VC0 restarts. D o not allo w cache o n/off to cau se a wait t ime shortage. ■ Cloc k Syst em Ref ere nce D ia gram Figure 3.[...]

110 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER CHC_1: call VCO_ RUN PLL_S ET_END: ld @R15 +, PS ; pop pr ocesso r status ; *** ******* ******** ******* ***** ******** ******* ******** ***** ** ; VCO Setting ; *** ******* ******** ******* ***** ******** ******* ******** ***** ** VCO_RUN: st R3, @-R15 ; pus h R3 ldi:8 # PCTR _MASK , R3 ; PCTR_MASK =0 0[...]

111 CHAPTER 4 BUS INTERFACE This ch apter e xplains the basic items of the external b us int erface, registe r configuration and functions, b us operations, and b us timing and pr ovides b us operation pr ogram samples. 4.1 Outlin e of Bu s Interface 4.2 Chip Select Area 4.3 Bus Interface 4.4 Ar ea Sele ct Register (ASR ) and Area M ask Registe r ([...]

112 CHAPTER 4 BUS INTERFACE 4.1 Outline of Bus I nterface The bus interfac e controls the interf ace betw een external memo r y and I/O . ■ Features of the Bus Inter face • 25-bit (32 megabyte s) addres s output • 6 indepe ndent ba nks to be set by chi p select fun ction • Capab le of se tting a bank in an opti onal loca tion in at l east 6[...]

113 4.1 Ou tl ine o f Bus Interfac e ■ Bus Interf ace Registers Figure 4. 1.1 shows the bus inter face regis ters. Figure 4.1-1 Bus Interface Regist ers For detai ls on the mod e regist er (MODR), s ee Section 2 .10, "Op eration M ode." 31 -------- 24 23 -------- 16 15 -------- 8 7 -------- 0 (Area Select Reg. 1) (Area Mode Reg. 1) (Are[...]

114 CHAPTER 4 BUS INTERFACE ■ Block Diagram of the Bus Interface Figure 4. 1.2 shows a block di agram of t he bus in terface Figure 4.1-2 Bus Interface Bloc k Diagram 32 32 A-OUT EXTERNAL D ATA B U S MUX write buff er s witch read buff er switch D A T A BLOCK ADDRESS BLOCK +1or+2 EXTERNAL ADDRESS BUS inpage address buff er shifter ASR CS0X-CS5X A[...]

115 4.2 C hip Se lect Area 4.2 Chip Select A rea A total of six types of c hip select area are prepared for the b us interface. ■ Setting Chip Select Areas Each area can be op tionally located in unit s of at l east 64 kiloby tes in a 4 gigab yte a rea usi ng the area select r egisters (ASR1 to AS R5) and a rea mask r egisters (AMR1 to AM R5). If[...]

116 CHAPTER 4 BUS INTERFACE 4.3 Bus Interface The b us interface include the f ollowing: • Usual b us interf ace • DRAM interfac e These interfa ces can onl y be used in the predetermine d area. ■ Chip Se lect Areas and Bus Interfaces Table 4.3.1 s hows the corres pondence between each chip sele ct area and ava ilable in terface func tions . [...]

117 4.3 Bus Inter face ❍ Bus siz e specification A bus wi dth can be option ally sp ecified for each area by re gister s etting. A bus widt h, set by pins MD2, M D1, an d MD0 at r eset time, is speci fied fo r area 0. Af ter writi ng to the mode regist er (MODR), a b us size i s specifie d by the v alue set in the AM D0 register .[...]

118 CHAPTER 4 BUS INTERFACE 4.4 Area Select Register (ASR) and Area Mas k Register (AMR) The area se lect register s (ASR1 to ASR 5) and are a mask regi sters (A MR1 to AMR5) specify t he range of ad dress space f or chi p select are as 1 to 5. ■ Configu ration of A rea Select Register (ASR) and Ar ea Mask Re gister (AM R) The area s elect regi s[...]

119 4.4 Area S elect Regis ter (ASR) an d Area Mask Register (AMR ) The area selec t registe rs (ASR1 to AS R5) and a rea mask registe rs (AMR1 to AMR5) specify the range of address space f or chip select a reas 1 t o 5. ASR1 to ASR5 spe cify the up per 16 b its (A31 to A16) of e ach addres s, and A MR1 to A MR5 mask th e corres ponding a ddress bi[...]

120 CHAPTER 4 BUS INTERFACE Figure 4.4 .1 s how s a map of the ar eas set i n the 64 k il obyte s b y initial v alu es durin g r eset an d a map of the areas s et in Examp les 1 and 2. Figure 4.4-1 Sample Maps of the Chip Selec t Areas 00000000 H 00000000 H 00010000 H 64KB 00020000 H 00030000 H 64KB 64KB 00030000 H 00040000 H 64KB 00040000 H 0FFC00[...]

121 4.5 Area M ode Regist er 0 (AMD0 ) 4.5 Area Mode Register 0 (AMD0) Area mode re gister 0 (AMD0) speci fies the operation mode of chip sele ct area 0 (area other that those specified by ASR1 to ASR5 and AMR1 to AMR5). At reset time, are a 0 is selecte d . ■ Configuration of Area Mode Register 0 (AMD0) Area mo de register 0 (AMD 0) is confi gur[...]

122 CHAPTER 4 BUS INTERFACE <Note> Before wri ting to t he MODR, se t the bus wi dth, equal to that set by the MD2, MD1, and MD0 pins, in BW1 and BW0 of A MD0. The bus wi dth of area 0 is sp ec ifi ed by the MD2, MD1, and MD 0 pins at re se t time . Afte r setti ng the mode r egister ( MODR), the b us width s et in AMD 0 becomes valid. Suppos[...]

123 4.6 Area M ode Register 1 (A MD1) 4.6 Area Mode Reg ister 1 (AMD1) Area mode re gister 1 (AMD1) specifie s the opera tion mode of c hip select area 1 ( area specified by ASR1 and AMR1). ■ Configuration of Area Mode Register 1 (AMD1) Area mo de register 1 (AMD1) is configu red as fo llows: ■ Bit Functions of Area Mode R egister 1 (AMD1) [bit[...]

124 CHAPTER 4 BUS INTERFACE 4.7 Area Mode Register 32 (AMD32) Area mode registe r 32 (AMD 32) contr ols the opera tion mode of chip se lect are a 2 (ar ea specified b y ASR2 and AMR2) a nd ch ip select are a 3 (area s pecified b y ASR3 and AMR 3). These areas are accessed onl y via the usual bus and do not allo w th e use of s pecial DRAM in terfac[...]

125 4.8 Area M ode Register 4 (A MD4) 4.8 Area Mode Reg ister 4 (AMD4) Area mode re gister 4 (AMD4) specifie s the opera tion mode of c hip select area 4 ( area specified by ASR4 and AMR4). Area 4 allows the use of the DRAM interfa ce. ■ Configuration of Area Mode Register 4 (AMD4) Area mo de register 4 (AMD4) is configu red as fo llows: ■ Bit [...]

126 CHAPTER 4 BUS INTERFACE 4.9 Area Mode Register 5 (AMD5) Area mode registe r 5 (A MD5) spe cifies t he b us mode of c hip select ar ea 5 (are a specified by ASR5 and AMR5). Area 5 allows the use of the DRAM interface. ■ Configuration of A rea Mode Register 5 (AMD5) Area mo de register 5 (AMD 5) is confi gured as fo llows: ■ Bit Functions of [...]

127 4.10 DRAM Control Regis ter 4/5 (DMCR4/5 ) 4.10 DRAM Control Re gister 4/5 (DMCR4/5) DRAM con trol registers 4 and 5 (DMCR4 and DMCR5) cont r o l the DRAM interface for areas 4 a nd 5 and ar e valid onl y when the DRME bits of AMD4 and AMD5 are se t to "1" . ■ Configuration of DRAM Control Register 4/5 (DMCR4 /5) DRAM con trol regis[...]

128 CHAPTER 4 BUS INTERFACE [bit 11] Q1W (Q1 wait bit) The Q1W bit sp ecifies wh ether to extend th e Q1cycl e (the "H" inte rval of RA S), spec ified at DRAM acc ess time, b y one cy cle. 0: Does n ot extend Q 1 cycle (initial v alue). 1: Exte nds Q1 cycle. [bit 10] Q4W (Q4 wait bit) The Q4W bit spec ifies wheth er to extend the Q4 cyc l[...]

129 4.10 DRAM Control Regis ter 4/5 (DMCR4/5 ) [bit 4] REFE (REFresh E nable bit) The REFE bi t specifi es whether to perform the c yclic refr esh operati on of the CA S before RAS (CBR) ty pe. When star ting the cyc lic refresh, rega rdless of are as 4 and 5, set the REFE bit of DMCR4 or DMCR 5 to "1" and se t the STR bit of the r efresh[...]

130 CHAPTER 4 BUS INTERFACE 4.11 Refresh Control Regis ter (RFCR) The refresh contr ol regist er (RFCR) controls the CBR (CAS bef ore RAS) refresh operation when t he DRA M interfa ce is used. This register has a 6-bit do wnwar d counter that uses the divide-b y-32 out put of a timebase timer as a c lock sour ce and specifies a refresh interval b y[...]

131 4.11 Refresh Control Re gister (RFCR) [bit 2] STR (STaRt bit) The STR bit controls or starts a nd stops the down ward counter . 0: STOP (initial val ue) 1: START When the STR is set, th e REL value i s loaded into the d ownward coun ter. When th e REFE bit of th e DMCR and the STR bit are set to "1", t he CRB r efresh o peration is pe[...]

132 CHAPTER 4 BUS INTERFACE 4.12 Externa l Pin Control Reg ister 0 (EPCR0) External pin contr ol register 0 (EPCR0) contr ols the output of each signal. When output is permitted, this register outputs a desired timing signal in eac h bus mode . When the input is v alid, it receives an input signal fr om the outside . When output is inhibited or the[...]

133 4.12 E xternal Pin Control Re gister 0 (EPCR0 ) [bit 8] BRE (Bus Request Enabl e bit) The BRE bi t controls the BR Q and BGRNTX signals as des cribed below. When thi s bit is r eset, the B RQ input becomes in valid an d the BGRN TX outpu t is inhibi ted. 0: Validate s BRQ input and in hibit s BGRNTX output (cor respondi ng pins functio n as I/O[...]

134 CHAPTER 4 BUS INTERFACE [bit 0] COE0 (Chip sele ct Output Enable 0) The C0E0 bi t controls the CS0X output. Wh en this bi t is rese t, output is permitt ed. 0: Inhibi ts output. 1: Perm its outpu t (initial value). When the ex terna l bus mode i s used, the C0E0 bit per forms no I/O por t control for the CS 0X pin. Al ways set thi s bit to &quo[...]

135 4.13 E xternal Pin Control Re gister 1 (EPCR1 ) 4.13 External Pi n Control Reg ister 1 (EPCR1) External pin contr ol register 1 (EPCR1) controls address signal output. ■ Configuration of External Pin Control Register 1 (EPCR1) Extern al pin co ntrol regi ster 1 (E PCR1) is c onfigured as follows : ■ Bit Functions of External Pin Control Reg[...]

136 CHAPTER 4 BUS INTERFACE 4.14 DRAM Sig nal Control Registe r (DSCR) The DRAM signal control register (DSCR) control s the output of each DRAM control signal. When the output is inhibited, this register can be used as an I/O port. ■ Configuration of DRAM Signal C ontr ol Register (DSCR) The DRAM s ignal co ntrol regi ster (DSCR) is config ured [...]

137 4.14 DRAM Signal Control Register (DSCR) [bit 3] C0HE The C0HE bi t controls the CS0H ou tput. When this bit is reset, t he output i s inhibited . 0: Inhibi ts output (initial val ue). 1: Per mits out p ut. [bit 2] C0LE The C0LE bi t controls the CS0L o utput. Whe n this bit is reset, the output is inhibited. 0: Inhibi ts output (initial val ue[...]

138 CHAPTER 4 BUS INTERFACE 4.15 Little End ian Register (LER) When b us acces s b y the MB91F1 09 is perf ormed, th e whol e area is usuall y composed of big endians. Ho we ver , setting the little endian register (LER) makes it possib le to handle one of ar eas 1 t o 5 as a little e ndian area . This register is suppor t ed f or all bus modes i n[...]

139 4.16 Relationship between Data Bus Widths and Control Signals 4.16 Relationship between Data Bus Widths and Control Sig nals Data bus control signals (W R0X-WR1 X, CS0H, CS 0L, CS1L, CS1H , D W0X, and D W1X) alwa ys correspond to data b u s b yte locations on a one-to-one basis, regar dless of big and little endians and data b us widths. ■ Re[...]

140 CHAPTER 4 BUS INTERFACE T able 4.16-1 Rela tionship between Data Bus Widths and Contr ol Signals Bus width 16-bit bus width 8-bit bus width Data bus WR 2CA S/1WE 1CAS /2WE WR 2CAS/1W E 1CAS/2 WE D31-D24 WR0X CASL WEL WR0X CA S WE D23-D16 WRIX CA SH WEH[...]

141 4.16 Relationship between Data Bus Widths and Control Signals 4.16.1 Bus Access with Big Endians When externa l b us acce ss is performed for area s not set by the little endi a n regist er (LER), thos e area s are ha ndled as big endians. The FR series usually em plo ys big endians. ■ Data Format The follo wing sho ws th e relation ship bet [...]

142 CHAPTER 4 BUS INTERFACE ❍ Byte access (during e xecution of LDUB and STB instructions) Figure 4.16-5 Relationship betwee n Internal Register and External Data Bus for Byte Access ■ Data Bus Wi dth The follo wing sho ws th e relation ship bet ween the internal register and ex ternal dat a bus fo r each data bus width . ❍ 16-bit bus width F[...]

143 4.16 Relationship between Data Bus Widths and Control Signals ❍ 8-bit bus width Figure 4.16-7 R elationship between Internal Register and External Da ta Bus for 8-bit Bus Width ■ Extern al Bus Access Figure 4.16 -8 and Figure 4.1 6-9 show exter nal bus acc ess (in a 16- bit or 8-bit bus wid th) in words, h alf-words, and bytes . These fi gu[...]

144 CHAPTER 4 BUS INTERFACE ❍ 16-bit bus width Figure 4.16-8 E xternal Bus Acce ss f or 16-bit Bus W idth MSB LSB 00 01 00 01 00 01 10 11 10 11 10 11 16bit 00 01 00 01 00 01 10 11 10 11 10 11 00 01 00 01 00 01 10 11 10 11 10 11 00 01 10 11 00 01 10 11 00 01 10 11 P A1/P A0 : Lower 2 bits of address specified by prog ram Output A1/A0 : Lower 2 bit[...]

145 4.16 Relationship between Data Bus Widths and Control Signals ❍ 8-bit bus width Figure 4.16-9 E xternal Bus Acce ss f or 8-bit Bus Width P A1/P A0 : Lower 2 bits of address specified b y program Output A1/A0 : Lower 2 bits of output address : First byte location of output address : Data byte location f or access 1) to 4) : Bus access count MS[...]

146 CHAPTER 4 BUS INTERFACE ■ Example of Connection to External Devices Figure 4.16-10 E xample of Connection between M B91F109 and Ex ternal Devices MB91F109 WW D31 R D23 R 0 1 D24 X D16 X 0 1 X D15 D08D07 D00 D07 D00 16-bit de vice* 8-bit device* * F or the 16/8-bit de vice, the data bus on the MSB side of the MB91F109 is used. ("0"/&[...]

147 4.16 Relationship between Data Bus Widths and Control Signals 4.16.2 Bus Access with Little Endians When e xternal bus a cc ess is pe rf ormed for a r ea s se t b y the little e ndian regi st er ( LER) , those area s are handled as litt le endians. ■ Outline of Litt le Endians Little end ian bus acce ss by the M B91F109 uses th e bus acces s [...]

148 CHAPTER 4 BUS INTERFACE ❍ Half-wor d acces s (during ex e cution of LDUH and STH instructions) Figure 4.16-12 Relationship between Internal Register and Extern al Data Bus for Half-w or d Access ❍ Byte access (during e xecution of LDUB and STB instructions) Figure 4.16-13 Re lationship between Internal Register and External Data Bus f or By[...]

149 4.16 Relationship between Data Bus Widths and Control Signals ■ Data Bus Wi dth The follo wing sho ws th e relation ship bet ween the internal register a nd exter nal data bus fo r each data bus width : ❍ 16-bit bus width Figure 4.16-14 R elationship between Internal Register and External Da ta Bus for 16-bit Bus Width ❍ 8-bit bus width F[...]

150 CHAPTER 4 BUS INTERFACE ■ Example of Connection to External Devices ❍ 16-bit bus width Figure 4.16-16 Example of Connection between MB91F10 9 and External Devices (16-Bit Bus Width) ❍ 8-bit bus width Figure 4.16- 17 Example of Connection between MB91F10 9 and External Devices ( 8-Bit Bus Width) MB91F109 CSnX CSmX WW D31 R D23 R 0 1 D24 X [...]

151 4.16 Relationship between Data Bus Widths and Control Signals 4.16.3 External Access This secti on lis ts se veral e xternal acce sses. ■ W or d Access Bus width Big endian mode Little endian mode 16-bit b us width 8-bit bu s width Control pin address: '0' '2' D31 D31 AA AA CC WR0X CASL WEL BB BB DD WR1X CASH WEH D16 CC DD[...]

152 CHAPTER 4 BUS INTERFACE ■ Half-W ord Access Bus width Big endian mode Little endian mode 16-bit b us width 8-bit bu s width address: 0 D31 D31 AA WR0X CASL WEL BB WR1X CASH WEH D16 AA BB D00 1) Control pin Internal register Exter nal pin address: 0 D31 D31 BB WR0X CAS0 WEL AA WR1X CAS1 WEH D16 AA BB D00 1) Control pin Internal register Exter [...]

153 4.16 Relationship between Data Bus Widths and Control Signals ■ Byte Ac cess Bus width B ig endian mode Little endian mode 16-bit b us width address: '0' D31 D31 AA WR0X CASL WEL D16 AA D00 1) Control pin Internal register Exter nal pin address: '0' D31 D31 AA WR0X CASL WEL D16 AA D00 1) Control pin Internal register Exter[...]

154 CHAPTER 4 BUS INTERFACE 8-bit bu s width Bus width B ig endian mode Little endian mode address: D31 D31 AA WR0X CAS WE D24 AA D00 '0' 1) Control pin Internal register External pin address: D31 D31 AA WR0X CAS WE D24 AA D00 '0' 1) Control pin Internal register External pin address: D31 D31 BB WR0X CAS WE D24 BB D00 '1&ap[...]

155 4.16 Relationship between Data Bus Widths and Control Signals 4.16.4 DRAM Relatio nships This sect ion e xplains the DRAM relat ionships. ■ DRAM Control Pins Table 4.16 - 2 list s the relati onship between the pin functions a nd bus wi dths used i n the DRAM interfac e. T able 4.16-2 Functions and Bus Widths of DRAM C ontro l Pins Pin name Da[...]

156 CHAPTER 4 BUS INTERFACE ■ Row and Column Addresses The page siz e select bits (PGS3 to PGS0) o f DRAM con trol regi sters 4 and 5 ( DMCR4 and DMCR5) dete rmines whe ther to create DRAM interface ad dresses. When the high-sp eed page mode is used , PGS3 to PGS0 and the data bus width determi ne whether acces s is within a page. When conn ectin[...]

157 4.16 Relationship between Data Bus Widths and Control Signals ❍ 16-bit data bus (using 2 DRAMs) Figure 4.16-19 Ex ample of Connection between MB91F109 and T wo 8-Bit Outpu t DRAMs (16-Bit Data Bus) This LSI COLUMN Address A08 A07 A06 A05 A04 A03 A02 A01 A00 RO W Address A16 A15 A14 A13 A12 A11 A10 A09 A08 External pin A08 A07 A06 A05 A04 A03 [...]

158 CHAPTER 4 BUS INTERFACE ■ Connection Example of DR AM Device • DRAM: 2CA S/1WE, p age size 512, × 16 -bit produc t • Bus wid th: 16 bits • Number o f banks: 2 (areas 4 and 5) Figure 4.16-20 Example of Connection between MB91F109 and T wo 16-Bit Output DRAMs (16-Bit Data Bus) (Area 4 RAS) RAS0 RAS (Area 4 CASL) CSOL UCAS (Area 4 CASH) C[...]

159 4.17 Bus Timi ng 4.17 Bus Timing This section pr o vides b us access timing char ts used in each mode and e xplains bus access ope ration f or the f ollowi ng items : • Usual b us access • Wait cycle • D RAM inte rfaceDRAM interface • D RAM refresh • External b us request ■ Usua l Bus Ac cess The us ual bus interfac e handles r ead [...]

160 CHAPTER 4 BUS INTERFACE ❍ Usual DRAM interfac e The us ual DRAM inte rfac e convert s the CAS cycle to a 2-cl ock cycle by se ttin g t he DSA S an d HYPR bit s o f DM CR4 a nd DCMR5 to "0 ". It h andl es " 5- cloc k cyc le s" as ba si c bus c y cles du ring read and write ope rations. Thi s manual represents these cy cles [...]

161 4.17 Bus Timing • Hyper DR AM inter face: Read • Hyper DR AM inter face: Write • Hyper DR AM inter face ■ DRAM R efresh • CAS befor e RAS (CBR) refr esh • Automatic wait cycle of CBR refresh •S e l f r e f r e s h ■ External Bus Request • Bus co ntrol r elease • Bus co ntrol acqui sition[...]

162 CHAPTER 4 BUS INTERFACE 4.17.1 Basic Read Cycle This sectio n pr ovides a ch art of the basi c read c ycle t iming. ■ Basic Rea d Cycle Timing Chart ❍ Bus width: 16 bits, access: words, CS0 area ac cess Figure 4.17-1 Example of Basic Read Cycle Timing Char t [Explanation of operation] • CLK o utputs ex ternal bu s operat ion cloc ks. When[...]

163 4.17 Bus Timing • Output of CS0 X to CS5X (area chip select) si gnals is asser ted from the beg inning (BA1 ) of bus cy cles; t hat is , at the same time as A24- A00. The CS0 X to CS 5X sig nals are g enerated from de coded outp ut addres ses and r emain un changed u nless t hose addres ses chan ge, thereby changing the chi p select area s se[...]

164 CHAPTER 4 BUS INTERFACE 4.17.2 Basic Write Cycles This se ct ion pro vides a char t of the basic writ e cyc le timing. ■ Basic Wr ite Cycle Timing Char t ❍ Bus width: 8 bits, access: w ords, CS0 a rea access Figure 4.17-2 Example f or Basic Write Cycle Timing [Explanation of operation] • A24 to A00 ( addr ess 24 to address 00) outp ut the[...]

165 4.17 Bus Timing specif ied area s ar e 8 b its wide, D2 3 to D 16 auto matic ally be come I/O p orts, which are s et to High-Z. The above examp le sh ows the case, wh ere D2 3 to D16 and WR 1X ar e used as I/O p orts. If the bus width o f at leas t one o f chip select areas 0 to 5 is set to 16 b its, D23 to D16 a nd WR1X ca nnot be used as I/O [...]

166 CHAPTER 4 BUS INTERFACE 4.17.3 Read Cyc les in Each Mode This section pr o vides read c yc le timing charts in each mode. ■ Read Cycle Timing Char ts ❍ Bus width: 16 bits, acces s: half-w ords Figure 4.17-3 Example 1 of Read Cycle Timing Char t ❍ Bus width: 16 bits, ac cess: bytes Figure 4.17-4 Example 2 of Read Cycle Timing Char t ❍ Bu[...]

167 4.17 Bus Timing ❍ Bus width: 8 bits, acc ess: half-wor ds Figure 4.17-6 Example 4 of Read Cycle Timing Chart ❍ Bus width: 8 bits, acc ess: bytes Figure 4.17-7 Example 5 of Read Cycle Timing Chart BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2 CLK A24 - 00 #0 #1 #2 #3 D31-24 #0 #1 #2 #3 D23-16 RDX BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA CLK A24-00 #0 #1 #2 #3 D31-2[...]

168 CHAPTER 4 BUS INTERFACE 4.17.4 Write Cyc les in Each Mode This section pr o vides write c yc le timing charts in eac h mode. ■ Write Cycle Timing Chart ❍ Bus width: 16 bits, ac cess: wor ds Figure 4.17-8 Example 1 of Write Cycle Timing Chart ❍ Bus width: 16 bits, acces s: half-w ords Figure 4.17-9 Example 2 of Write Cycle Timing Chart ❍[...]

169 4.17 Bus Timing ❍ Bus width: 8 bits, acc ess: half-wor ds Figure 4.17-11 Example 4 of Write Cycle Timing Char t ❍ Bus width: 8 bits, access : bytes Figure 4.17-12 Example 5 of Write Cycle Timing Char t BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2 CLK A24-00 #0 #1 #2 #3 D31-24 #0 #1 #2 #3 D23-16 WR0X WR1X BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA CLK A24-00 #0 #1 #[...]

170 CHAPTER 4 BUS INTERFACE 4.17.5 Read and Write Co mbination Cycles This section pro vides a read and write combination cyc le timing char t. ■ Read and Wr ite Combination Cycle Timing Chart ❍ CS0 area: 1 6-bit bus width, wor d read CS1 area: 8-bit bus width, half-w or d r ead Figure 4.17-13 Example of Rea d and Write Combination Cycle Timing[...]

171 4.17 Bus Timing 4.17.6 A utom atic W ait Cyc les This se ct ion pro vides an autom atic wai t cyc l e timing char t. ■ Au tomatic W ait Cycle Timing Chart ❍ Bus width: 16 bi ts, access: half- w ord read/w rite Figure 4.17-14 Example of Automatic W ait Cycle Timing Chart [Explanation of operation] • When im pl eme nti ng auto mat ic wai t [...]

172 CHAPTER 4 BUS INTERFACE 4.17.7 External W ait Cycles This se ct ion pro vides an externa l wait cycle timing char t. ■ External W ait Cyc le Timing Char t ❍ Bus width: 16 bi ts, access: half- w ords Figure 4.17- 15 Example of External W ait Cy cl e Timing Chart [Explanation of operation] • When i mplementi ng externa l wait c ycles, s et [...]

173 4.17 Bus Timing 4.17.8 Usual DRAM In terface: Read This section pro vides a usual DRAM interface read timing chart. ■ Usual DRAM Int erface: Read Timing C hart ❍ Bus width: 16 bits, access: w o rds, CS4 area access Figure 4.17-16 Example of Usual D RAM Interface Read Ti ming Chart [Explanation of operation] • A24 to A00 ( address 24 to ad[...]

174 CHAPTER 4 BUS INTERFACE edge of CA SL or CA SH for the 2CAS/1WE. For the 1CAS/2 WE, CAS corres ponds to D31 to D16. For the 2CAS/1 WE, CASL correspond s to D31 to D24, and CAS H correspon ds to D23 to D16. In read c ycles, all o f D31 to D 16 are fetche d, irresp ective o f the bus wi dth and wor d, half- word, and byte acces s. Whet her the re[...]

175 4.17 Bus Timing 4.17.9 Usual DRAM In terface: Write This se ct ion pro vides a usua l DRAM inter face wr ite timi ng char t. ■ Usual DRAM Int erface: Wri te Timing Char t ❍ Bus width: 16 bits, access: w o rds, CS4 area access Figure 4.17-17 Ex ample of Usual DRAM Interface Wri te Timing Char t [Explanation of operation] • The outp ut of A[...]

176 CHAPTER 4 BUS INTERFACE In an 8-b it data bus wi dth, write da ta is output from D31 to D24. • RAS is similar t o that at re ad cycles . • CAS is also simi lar to tha t at read c ycles. •W E is a write strobe s ignal to the DRA M. For the 1CAS/2W E, WEL repr esents W E of the upper ad dress si de ("0" of l ower 1 bit) , and WEH [...]

177 4.17 Bus Timing 4.17.10 Usual DRAM R ead Cyc les This section pro vides usual DRAM re ad cyc le timing c ha rt s. ■ Usual DRAM Re ad Cycle Timing Charts ❍ Bus width: 16 bi ts, access: half- w ords Figure 4.17-18 Example 1 of Usual DRAM Read Cycle Timing Char t Q1 Q2 Q3 Q4 Q5 CLK A24-00 X #0 row .adr . #0 col.adr D31-24 #0 D23-16 #1 RAS CAS [...]

178 CHAPTER 4 BUS INTERFACE ❍ Bus width: 16 bits, access: bytes Figure 4.17-19 Example 2 of Usual DRAM Read Cycle Timing Char t ❍ Bus width: 8 bits, access : half-w or ds Figure 4.17-20 Example 3 of Usual DRAM Read Cycle Timing Char t Q1 Q2 Q3 Q4 Q5 Q1 Q2 Q3 Q4 Q5 CLK 1)1CAS/2WE A24-00 X #0 row .adr . #0 col.adr X #1 row .adr . #1 col.adr D31-2[...]

179 4.17 Bus Timing 4.17.11 Usual DRAM Write Cyc les This sect ion pr ovides usual DRAM write cyc le timing char ts. ■ Usual DRAM Wri te Cyc l e Timing Char ts ❍ Bus width: 16 bi ts, access: half- w ords Figure 4.17-21 Example 1 of Usual DRAM Write Cycle Timing Char t Q1 Q2 Q3 Q4 Q5 CLK 1CAS/2WE A24-00 X #0 row .adr . #0 col.adr D31-24 #0 D23-1[...]

180 CHAPTER 4 BUS INTERFACE ❍ Bus width: 16 bits, access: bytes Figure 4.17-22 Example 2 of Usual DRAM Write Cycle Timing Char t ❍ Bus width: 8 bits, access : half-w or ds Figure 4.17-23 Example 3 of Usual DRAM Write Cycle Timing Char t Q1 Q2 Q3 Q4 Q5 Q1 Q2 Q3 Q4 Q5 CLK 1)1CAS/2WE A24-00 X #0 row .adr . #0 col.adr X #1 row .adr. #1 col.adr D31-[...]

181 4.17 Bus Timing 4.17.12 A utomatic W ait Cyc les in Usual DRAM Interfac e This sect ion pr ovides an automatic wait cycle timing chart in t he usual DRAM interface. ■ Au tomatic W ait Cycle Timing Chart in Us ual DRAM Interface ❍ Bus width: 8 bits, access: bytes Figure 4.17-24 Example of Au tomatic W ait Cycle Timing Chart in Us ual DRAM In[...]

182 CHAPTER 4 BUS INTERFACE 4.17.13 DRAM Interface in High -Speed P age Mode This section pro vides DRAM interface ope ration timing char ts in high-speed page mode . ■ DRAM Interface Timing Char ts in High-Speed P age Mode ❍ Read cycle, bus width: 16 bits, a ccess: wor ds Figure 4.17-25 Example 1 of DRA M Interface Timing Char t in High-Speed [...]

183 4.17 Bus Timing [Explanation of operation] • Write control is perf ormed with only the CAS control signals (includ ing CASL and CA SH) while RA S is low ered to "L", and then W E (inc luding W EL and WEH ) is lowered to "L". • Column ad dresse s and outp ut data ar e output in Q4 and Q 5 cycles . ❍ CS area (CS4/CS5) sw[...]

184 CHAPTER 4 BUS INTERFACE ❍ Combination of high-speed page mode and basic b us cyc le Figure 4.17-28 Example 4 of DRA M Interface Timing Char t in High-Speed Pa g e Mode [Explanation of operation] • Even i f the CS area switches and anoth er CS area is accessed , RAS re mains at "L" in high- speed pa ge mode. Q4 Idle CLK A24-00 CS4X[...]

185 4.17 Bus Timing 4.17.14 Single DRAM I nterface: Read This sect ion pr ovides a read timing chart for a single DRAM interfa ce. ■ Single DRAM Interface: Read Timing Char t ❍ Bus width: 16 bi ts, access: words Figure 4.17-29 E xample of Single DRAM Interface Read Timing Char t [Explanation of operation] • Colum n addresse s are ou tput in Q[...]

186 CHAPTER 4 BUS INTERFACE 4.17.15 Single DRAM Interface: Write This sect ion pr ovides a single DRAM interface writ e timing char t. ■ Single DRAM Interface: Write Timing Char t ❍ Bus width: 16 bits, access: wo rds Figure 4.17-30 Example of Single DRAM Interface Write Timing Char t [Explanation of operation] • Column ad dresse s and write d[...]

187 4.17 Bus Timing 4.17.16 Single DRAM I nterface This sect ion pr ovides a single DRAM interface timing char t. ■ Single DRAM I nterface Timing Char t ❍ Combination of single DRAM and basi c bus cyc le , CS switch-o ve r Figure 4.17-31 Example of S ingle DRAM Interface Timing Char t [Explanation of operation] • When a b us cy cle st ar ts f[...]

188 CHAPTER 4 BUS INTERFACE 4.17.17 Hyper DRAM Interfa ce: Read This sect ion pr ovides a h yper DRAM interface timin g chart. ■ Hyper DRAM Interface: Read Timing Char t ❍ Bus width: 16 bits, access: wo rds Figure 4.17-32 E xample of Hyper DRAM Interface Read Timing Cha rt [Explanation of operation] • Colum n addresse s are ou tput in Q4HR cy[...]

189 4.17 Bus Timing 4.17.18 Hyper DRAM In terface: Write This sect ion pr ovides a h yper DRAM interface write timin g chart. ■ Hyper DRAM Interface: Write Timing chart ❍ Bus width: 16 bi ts, access: words Figure 4.17-33 Example of Hyper DRAM Inte rface Write Timing Char t [Explanation of operation] • Column ad dresse s and write data are o u[...]

190 CHAPTER 4 BUS INTERFACE 4.17.19 Hyper DRAM Interface This sect ion pr ovides a h yper DRAM interface timin g chart. ■ Hyper DRAM Interface Timing Char t ❍ Combination of hyper DRAM and basic bus cyc le , CS switch-o ver Figure 4.17-34 Example of Hyper D RAM Interface Timing Char t [Explanation of operation] • When a b us cy cle st ar ts f[...]

191 4.17 Bus Timing 4.17.20 DRAM Refresh This section pro vides DRAM refresh timing char ts. ■ CAS before RAS (CBR) Refresh Figure 4.17-35 Example of CAS bef ore RAS (CBR) Refresh Ti ming Chart [Explanation of operation] • When execu ting CBR refre sh, set the REFE bit of DMC R4 and DMCR5 and the STR bit of the RFCR. • This manual repr esent [...]

192 CHAPTER 4 BUS INTERFACE ■ Au tomatic W ait Cycle of CBR Refresh Figure 4.17-36 Example of Timing Char t of CBR Refres h A utomatic Wait Cyc le [Explanation of operation] • When in serting a CB R refresh auto matic wait c ycle, set the R3 W bit of th e RFCR. ■ Selfre fresh Figure 4.17-37 Example of S elfrefresh Timing Char t [Explanation o[...]

193 4.17 Bus Timing 4.17.21 External Bus R equest This section pr o vides e xternal b us request timing charts. ■ Bus Control Release Figure 4.17-38 Example of Bus Control Release Timing Chart [Explanation of operation] • When per forming bu s arbitrat ion by BR Q and BGRNTX, set th e BRE bit of EPC R0 to "1". • When releas ing bus [...]

194 CHAPTER 4 BUS INTERFACE 4.18 Internal Clo ck Multiplicatio n (Clock Doub ler) The MB91F109 has a c loc k multiplication cir cuit with which the i nside of the CPU operates a t a frequenc y one or tw o times that of t he b us interface. The b us interfac e operates synchr onously with the CLK output pin regardl ess of which c lock is chosen. Whe[...]

195 4.18 Internal Cl ock Multiplication (Clock Doubler ) Figure 4.18-2 Example of Timing fo r 1X Cloc k (BW -16bit, Acc ess-W ord Read) Internal clock Internal instr uction Internal instr uction CLK output External address bus External data bus External RDX Pref etch External fetch (instruction fetch) address data N N D D + 2 D + 2 N + 4 D D + 2 N [...]

196 CHAPTER 4 BUS INTERFACE 4.19 Program Example for Ex ternal Bus Operation This section pr ovides a simple pr ogram example f or external b us operation. ■ Program Specification Examples f or External Bus Operation Regi ster sett ings are a s fo ll ows: ❍ Areas • Area 0 (AMD0): 16 bits, usual bus, autom atic w ait 0 • Area 1 (AMD1): 16 bi[...]

197 4.19 Progra m Example for External B us Operation stb r0,@r1 Write to dscr reg ister init_ amd0 ldi:8 #0x08,r 0 // 16- bit bus, 0 -wait ldi:20 #0x620 ,r1 // amd0 register address s etting stb r0,@r1 // Write to a md0 regi ster init_ amd1 ldi:8 #0x0a,r 0 // 16- bit bus, 2 -wait ldi:20 #0x621 ,r1 // amd1 register address s etting stb r0,@r1 // Wr[...]

198 CHAPTER 4 BUS INTERFACE //Exter nal bus a ccess ldi:20 #0x626 ,r1 // rfcr r egister add ress setti ng sth r0,@r1 // w rit e to rf cr re giste r init_ asr ldi: 32 # 0x 001 300 1,r 0 // asr1 and amr1 re gis ter sett ing valu es ldi:32 #0x 0015001,r 1 // a sr2, amr2 registe r settin g values ldi:32 #0x 0017001,r 2 // a sr3, amr3 registe r settin g[...]

199 4.19 Progra m Example for External B us Operation ldi:32 #0x001 a6b8c, r 6 // CS5 address (with in the pag e) ldi:32 #0x001 a6c00, r 7 // CS5 address (outs ide of the page) bus_acc ld @r 0, r8 // CS1 data word l oad lduh @r 1, r9 // C S2 data hal f word load ld @r2, r 10 // CS4 data word loa d ldub @r 3, r11 // CS4 data byte load st r8, @r4 // [...]

200 CHAPTER 4 BUS INTERFACE[...]

201 CHAPTER 5 I/O POR TS This chapter outlines the I/O por ts and e xplains the register configuration and the requirements f or using external pins as I/ O pins. 5.1 Outlin e of I/O Port s 5.2 Port Da ta Registe r (PDR) 5.3 Data Direction Register (DDR) 5.4 Usin g External Pins as I /O Ports[...]

202 CHAPTER 5 I/O PORTS 5.1 Outline of I/O Ports When a resour ce is not allowed to use the corresponding pin as an I /O , the MB91F109 allo ws the pin to be use d as an I/O port. ■ Basic Block Diagram of I/O P or ts Figure 5. 1-1 show s the bas ic I/O port co nfigurati on. Figure 5.1-1 Basic I/O P o rt Block Diagram ■ I/O P o r t Registers I/O[...]

203 5.2 Port Data Register (PDR) 5.2 Port Data Reg ister (PDR) The port data register s (PDR2 to P DRF) are I/O port I/O data regis ter s. The corresponding data direction registers (DDR2 to DDRF) perf o rm I/O contr ol. ■ Configuration of P or t Data Regis ter (PDR) The port d ata register (PDR) is configure d as follows : 7654 3210 PDR2 Address[...]

204 CHAPTER 5 I/O PORTS 5.3 Data Direction Reg ister (DDR) The data direction registers (DDR2 to DDRF) contr ol the I/O direction of the corresponding I/O ports in bit units. Set 0 to perf orm input contr ol, and set 1 to perform output contr ol. ■ Configuration of Data Direction Re gister (DDR) The data di rection register (DDR) is c onfigured a[...]

205 5.4 Using Exter nal Pins as I/ O Ports 5.4 Using Extern al Pins as I/O Ports T able 5.4-1 lists the rela tionship betwe en the initial v alue f or eac h e xternal pin and the register specifying whether to use the e xternal pin as an I/O por t or control pin. "Single chip: --- " and "Externa l b us: --- " indicated in th e t[...]

206 CHAPTER 5 I/O PORTS 23 P81 P81 EPCR0 (BRE bit) 0: P81 1: BGRNTX BGRNTX 24 P82 P82 EPCR0 (BRE bit) 0: P82 1: BRQ BRQ 25 P8 3 P83 EPCR0 (RDXE bit) 0 : P8 3 1 : RDX RDX T able 5.4- 1 External Bu s Function s to be Se lected (1 /4) Pin No. P in code Initial value Switc h-over register T able 5.4- 2 External Bu s Function s to be Se lected (2 /4) Pi[...]

207 5.4 Using Exter nal Pins as I/ O Ports 4 PB5 PB5/DREQ2 DSCR (C1 LE) 0: PB 5 1: C S1L Pin va lues ar e always input to DESQ2. CS1L DREQ2 5 PB6 PB6 DS CR (C1HE bit) and D ATCR (AKS E2, AKDE2 bi ts) C1HE, AK SE2, AK DE2 000: P B6 100: CS 1H Other: DACK2 CS1H DAC K2 6 PB7 PB7 DSC R(DW1 E) 0: PB 7 1: D W1X DW1X 19 to 21 MD0 to MD2 MD0 to MD 2 - 15 N[...]

208 CHAPTER 5 I/O PORTS 81 P F2 PF2/SC0 (input) PCNL (POE N) 0: PF2 1: OPCA3 SMR (SCKE) 0: pin values ar e input to SC0 during opera tion. 1: SC0 (outp ut) OPCA 3 SC0 82 P F3 PF3/SI1/T RG2 Pin val ues are alwa ys inpu t to SI1 and TRG2 ( during o peration). SI1 TRG2 83 P F4 PF4/TRG3 SMR ( SOE) 0: PF4 1: S01 ( output) Pin val ues are alwa ys input t[...]

209 5.4 Using Exter nal Pins as I/ O Ports T able 5.4-4 Exter nal Bus Functions to be Se lected (4/4) Pin No. P in code Initial value Switch-over register 74 AVSS (AVRL) AVSS (AVRL) - 17 RSTX RSTX - 95 X0 X0 - 94 X1 X1 - 7, 16, 96, 46 Vcc Vcc - 18, 43, 68, 93 Vss V ss -[...]

210 CHAPTER 5 I/O PORTS[...]

211 CHAPTER 6 EXTERNAL INTERR UPT/NMI CONTROLLER This chapter e xplains the general outlines of the external interrupt/NMI contr oller , configuration/functions of registers, and operations of the e xternal interrupt /NMI contro ller . 6.1 Overview o f Externa l Interrupt /NMI Cont roller 6.2 Ena ble Interrupt Request Register (ENI R) 6.3 Exte rnal[...]

212 CHAPTER 6 EXTERNAL INTERRUPT/N MI CONTROLLER 6.1 Overview of External In terrupt/NMI Controller The ex ternal interrupt/NMI co ntr oller is a bl ock that co ntrols an ex ternal interrupt request input to NMIX or INT0 to INT3. The le vels of inter rupt requests to be detected can be selected fr om "H" , "L", and the "ris[...]

213 6.2 Enable Inter rupt Request Register (ENIR ) 6.2 Enable Interrupt Requ est Register (ENIR) The enable interrupt request register (ENIR) is used to mask the output of an e xternal interrupt request. ■ Enable Interrupt Request Register (E NIR) The config uration of the enabl e interrup t request r egister (E NIR) is sh own below: The enable i[...]

214 CHAPTER 6 EXTERNAL INTERRUPT/N MI CONTROLLER 6.3 External Interru pt Request R egister (EIRR) When the e xternal interrupt request register (EIRR) is read, it indic ates that there are external interrupt requests. When it is written, the flip-flops indicating these requests are c leared. ■ External Interrupt Request Register (EIRR) The confi [...]

215 6.4 E xternal Lev el Register (ELVR ) 6.4 External Level R egister (ELVR) The ex ternal le vel register (EL VR) selects the request detection mode . ■ External Level Regis ter (EL VR) The config uration of the exte rnal level regist er (ELVR) is shown be low: The exter nal leve l register ( ELVR) sel ects the request dete ction mod e. Two bit[...]

216 CHAPTER 6 EXTERNAL INTERRUPT/N MI CONTROLLER 6.5 External Inte rrupt Op eration After the external level re gister a nd enable inter rupt reque st registe r are set, the request set in the EL VR register is input to the corresponding pin. This module then issues an interrupt request signal to the interrupt contr oller . ■ External Inter rupt [...]

217 6.6 Ext ernal Interrupt Re quest Levels 6.6 External Interrupt R equest Levels When an edg e is select ed f or the interrupt re quest mode , a pulse widt h of at least three machine cycles (periphe ral clock machine cyc les) is requir ed to detect an edg e . When a l eve l is se lected f or the interrupt reques t mode, an e xternal request that[...]

218 CHAPTER 6 EXTERNAL INTERRUPT/N MI CONTROLLER 6.7 Nonmaskable In terrupt (NMI) Operation NMI is the interrupt with the highest priority among other user i nterrupts. It can onl y be masked during the period fr om immediat el y after a reset to the completion of the ILM setting. ■ NMI Oper ation NMI is ac cepted a s follows: • Norma l sta te:[...]

219 CHAPTER 7 DELAYED INTERRUPT MODULE This chapter pr o vides an overvie w of the dela yed interrupt module and e xplains the register configuration and functions and the operations of the delay ed interrupt module . 7.1 Over view o f Dela yed Int errupt Modul e 7.2 Delayed Interru pt Control Registe r (DICR) 7.3 Op er ation o f Delay ed Inter rup[...]

220 CHAPTER 7 DELAYED INTE RRUPT MODULE 7.1 Overview of De layed Interrupt Modu le The dela yed interrupt module causes an interrupt f or changing a task. Software can use this module to issue or cancel an in terrupt request to the CPU . ■ Delaye d Interrupt Module Register Figure 7. 1-1 show s the d elayed i nterrupt mod ule regi ster. Figure 7.[...]

221 7.2 Delayed Interrupt Control Regis ter (DICR) 7.2 Delayed Interrupt Control Register (DIC R) The dela yed interrupt contr ol register (DICR) is used to contr ol dela yed interrupts. ■ Configuration of th e Delayed Interrupt Control Register (DICR) The co nfigurati on of the de layed in terrupt control re gister (DICR) is s hown below: ■ Bi[...]

222 CHAPTER 7 DELAYED INTE RRUPT MODULE 7.3 Operati on of D ela yed Int errupt Modul e The dela yed interrupt module causes an interrupt f or changing a task. Software can use this module to issue or cancel an in terrupt request to the CPU . ■ Interrupt Number A delay ed interru pt is assi gned to the i nterrupt ha ving the largest interrupt n um[...]

223 CHAPTER 8 INTERRUPT CON TR OLLER This ch apter pr o vides an o verview of the i nterrupt contr oller and ex plains the register configuration and functions and the operations of the interrupt contr oller . The c hapter also ex plains the hold request cancel request function using examples. 8.1 Overview o f Interrupt Con troller 8.2 Interru pt C[...]

224 CHAPTER 8 INTERRUPT CONTROLLER 8.1 Overview o f Interrupt Cont roller The interrupt controller accepts inter rupts and performs arbi tration over them . ■ Interrupt Contr o ller Har dware Configur ation The int errupt con troller c onsists of the foll owing: • ICR register • Interrupt p riority che ck circuit • Interrupt l evel and numb[...]

225 8.1 Ov erview of Interru pt Controll er ■ Interrupt Contr o ller Registers Figure 8. 1-1 shows th e interrup t controlle r registers . Figure 8.1-1 Interr upt Controller Reg isters (1/2) bit7 6543210 Address:00000400 H ICR4 ICR3 ICR2 ICR1 ICR0 Address:00000401 H ICR4 ICR3 ICR2 ICR1 ICR0 Address:00000402 H ICR4 ICR3 ICR2 ICR1 ICR0 Address:0000[...]

226 CHAPTER 8 INTERRUPT CONTROLLER Figure 8.1-2 Interr upt Controller R egisters (2/2) bit7 6543210 Address:00000420 H Address:00000421 H Address:00000422 H Address:00000423 H Address:00000424 H Address:00000425 H Address:00000426 H Address:00000427 H Address:00000428 H Address:00000429 H Address:0000042A H Address:0000042B H Address:0000042C H Add[...]

227 8.2 Interrupt Controller Block Dia gram 8.2 Interrupt Controller B lock Diagram Figure 8.2-1 is an interrupt controller b loc k diagram. ■ Interrupt Contr oller Block Diagram Figure 8.2-1 Block Diagram of the Interrupt Contr o ller INTO OR 5 NMI / LEVEL4 to 0 4 HLDCAN ICR00 RI00 6 / VCT5 to 0 ICR47 RI47 (DLYIRQ) DLYI *1 *2 *3 R-BUS NMI proces[...]

228 CHAPTER 8 INTERRUPT CONTROLLER 8.3 Interrupt Control Register (ICR) One interrupt contr ol register is pro vided f or eac h type of interrupt input and is used to set the interrupt level of the corr esponding interrupt request. ■ Configuration of Interrupt Control Register (ICR) The confi guration of the interr upt control regist er (ICR) is [...]

229 8.3 Interrupt Control Register (ICR ) ICR4 is fi xed to "1 " and cannot be set to " 0". T able 8.3-1 Correspondences between the Interrupt Level Setting Bits and Interrupt Levels ICR4 ICR3 ICR2 IC R1 ICR0 Int errupt level 00000 0 System re serv ed 01110 1 4 01111 1 5 N M I 1 0 0 0 0 16 H ighest le vel t hat can be set 10001 [...]

230 CHAPTER 8 INTERRUPT CONTROLLER 8.4 Hold Request Cance l Request Level Setting Reg ister (HRCL) The HRCL register is used to s et the interrupt level f or issuing a hold request cancel request. ■ Configuration of Hold Request Ca ncel Request Level Setting Register (HRCL) The register configuration of the hold request cancel request/level setti[...]

231 8.5 Priorit y Check 8.5 Priority Check IWhen m ultiple interrupt causes are generated sim ultaneousl y , this module selects one having the highest priority and posts the interrupt level and number of the cause to the CPU . NMI is given the highest priority among the int errupt causes handled b y this module. ■ Prio rity C hec k The crit eria[...]

232 CHAPTER 8 INTERRUPT CONTROLLER DMAC 2 (end, error) 28 1C ICR12 38C H 000 FFF8C H DMAC 3 ( end, error) 29 1D ICR13 388 H 000 FFF88 H DMAC 4 ( end, error) 30 1E ICR14 384 H 000 FFF84 H DMAC 5 ( end, error) 31 1F ICR15 380 H 000FFF80 H DMAC 6 (end, error) 32 20 ICR16 37C H 000 FFF7C H DMAC 7 ( end, error) 33 21 ICR17 378 H 000 FFF78 H A/D 34 22 IC[...]

233 8.5 Priorit y Check ■ Nonmaskable Interrupt (NMI) When NMI o ccurs s imultaneo usly with ot her interr upts, NMI i s alway s selected . ❍ When NMI occurs, the f oll owing types of inf ormation are posted to the CPU: • Interru pt level: 15 (01111 B ) • Interru pt number: 15 (001111 B ) ❍ NMI detection NMI is set or detected by the e xt[...]

234 CHAPTER 8 INTERRUPT CONTROLLER 8.6 Returning fro m the Standby Mode (Stop/Slee p) This module implements the function to return fr om standby mode when an i nterrupt request is issued. ■ Returning fr om Standb y Mode (Stop or Sleep State) When a per ipheral i nterrupt re quest inclu ding NMI occurs, a req uest to re turn from sta ndby mode is[...]

235 8.7 Hold Request Cancel Request 8.7 Hold Req uest Cancel Request For processing a high-priority int errupt while the CPU is i n hold state, cancellation of the hold request must be requested fr om the sour ce f or the hold request. The int errupt level used to determine whether to issue a c ancel request must be set in the HRCL register . ■ C[...]

236 CHAPTER 8 INTERRUPT CONTROLLER 8.8 Example of Using th e Hold Request Cancel Req uest Function (HRCR ) When the CPU is to perform priori ty processing duri ng DMA transfer , the DMA side must cancel the hold request and release the CPU fr om the hold stat e . An e xample of an interrupt occurring f or DMA to cancel the hold request and allo w C[...]

237 8.8 E xample of Using the Hold Request Cancel Request Function (HRCR) ■ Hold Request C ancel Request Sequence ❍ Example of interrupt r outine Figure 8.8-2 Example of Timing f or Hold Request Cancel Request Sequence (Interrupt Level: HRCL > a) The inter rupt le vel cha nges whe n an inte rrupt req uest is i ssued. If the level is hi gher [...]

238 CHAPTER 8 INTERRUPT CONTROLLER Exampl e of in terrupt rou tines The above examp le indic ates tha t a prior ity int errupt i s caused during e xecutio n of inter rupt routine I. In thi s case, i ncrementi ng PDRR at the be ginning of each inte rrupt rou tine and decrem enting it at the exit of eac h routine can als o preven t a hold request fro[...]

239 CHAPTER 9 U-TIMER This ch apter pr ovide s an o verview of the U-TIM ER and e xplains the regi ster configuration and functions and the operations of the U-TIMER. 9.1 Over view of U -TIMER 9.2 U -TIMER Register s 9.3 U-TIME R Oper ation[...]

240 CHAPTER 9 U-TI MER 9.1 Overview of U-TIMER The U-TIMER is a 16-bit timer that generates a U ART baud rate. Combining the chip operating frequency and U-TIMER reload v alue can g enerate a desired baud rate . Since a count underflow causes an i n terrupt, the U-TIMER can also be used as an interval tim er . The MB91F109 contains three c hannels [...]

241 9.2 U-TIMER Registers 9.2 U-TIMER Reg isters The f ollo wing three U-TIMER register s are used: • U-TIME R (UTIM) • Reload register (UTIMR ) • U-TIMER cont r ol register (U TIMC) ■ U-TIMER (UTIM) The UTIM indi cates the ti mer value. Acces s it using a 16-bit tra nsfer in struction. ■ Reload register (UTIMR) The UTIMR sto res the valu[...]

242 CHAPTER 9 U-TI MER In additi on to a nor mal 2(n +1) cycle cl ock, an o dd frequen cy clock can be set for the UAR T. Setting 1 in UCC1 generates 2n+3 cycle clock pulses. [Example of setting] UTIMR = 5, UC C1 = 0 --> G eneration c ycle = 2n+ 2 = 12 cycle s UTIMR = 25, UCC1 = 1 --> Generation cycle = 2n+3 = 53 cycles UTIMR = 60, UCC1 = 0 -[...]

243 9.3 U-TIMER O peration 9.3 U-TIMER Operatio n This section explains how to calculate the U-TIMER baud rate and also explains the cascade m o de . ■ Calculating the Baud Rate The UART uses the under flow flip-flop (f. f. in the figure) of the corresp onding U-TIMER (U - TIMERx --> UARTx, x = 0, 1, 2) as the baud r ate clock source . ❍ Asy[...]

244 CHAPTER 9 U-TI MER[...]

245 CHAPTER 10 UAR T This chapter pr ovides an o ver view of the U AR T and e xplains the register conf iguration, function s and the operations of the U AR T . 10.1 Overview of UART 10.2 Serial Mode Register (SMR) 10.3 Serial Co n trol Register (SCR) 10.4 Serial Input Data Register (SIDR) and S erial Output Dat a Register (SODR) 10.5 S erial St at[...]

246 CHAPTER 10 UART 10.1 Ove rview of UA RT The U ART is a serial I/O port used to implement asynch r on ous (start-stop) comm unicat ion or CLK synchr on ous communication. The MB91F109 contains three U ART c hannels. ■ U ART Characterist ics • Full d uplex doubl e buffer • Suppor t of both as ynch ronous (s tart-stop) and CLK s ynchrono us [...]

247 10.1 Over view of UART ■ U ART Bloc k Diagram Figure 10 .1-2 is a UA RT block diagram. Figure 10.1-2 U ART Bloc k Diagram SC SI SO SIDR SODR MD1 PEN PE MD0 P ORE SBL FRE SMR SCR CL SSR RDRF CS0 A/D TDRE REC SCKE RXE RIE SOE TXE TIE R - BUS Control signal Reception interrupt (to CPU) From U-TIMER External clock Clock selection circuit Receptio[...]

248 CHAPTER 10 UART 10.2 Serial Mod e Register (SMR) The serial mode register (SMR) specifies the U ART operation mode. Set the operation mode while U AR T operation is stopped. Do not write to the register during U ART operation. ■ Configuration of Serial Mode Regi ster (SMR) The confi guration of the seria l mode regi ster (SMR) is shown b elow[...]

249 10.2 Se rial Mode R egister (SMR) [bit 1] SCKE (SCLK E nable) When c ommunic ation is p erformed in CLK synchronou s mod e (mode 2) , this bit speci fies whether t o use the S C pin as a clock in put pin or a clock output p in. Set this bit to "0 " in CLK a synchron ous mode o r external c lock mode. 0: Clock input pin ( initial va lu[...]

250 CHAPTER 10 UART 10.3 Serial Con trol Register (SCR) The serial control register ( SCR) controls t he transfer pr ot ocol used f or serial comm unication. ■ Configuration of Serial Contr ol Register (SSR) The confi guration of the seria l control r egister (S CR) is shown below: ■ Bit Function of Serial Control Register (SSR) [bit 7] P EN (P[...]

251 10.3 Ser ial Control Register (SCR) <Note> Seven- bit data c an be used on ly in no rmal mod e (mode 0) for async hronous (sta rt-stop) communi cation. Use eight- bit data in multipr ocesso r mode (mode 1) or CLK synch ronous communi cation mo de (mode 2). [bit 3] A/D (Address/Data) This bit spec ifies th e data forma t of frames tha t ar[...]

252 CHAPTER 10 UART 10.4 Serial Inp ut Data Register (SIDR) and Serial Output Data Register (SODR) The serial input data register (SIDR) is a data b uffer register f or receiving data, and the serial output data register (SODR) is a data b uffer register f or transmitting data. When 7-bit data is used, bit 7 (D7) i s in v alid. Write to the SODR r [...]

253 10.5 S erial St atus Register (SSR) 10.5 Serial Status Register (SSR ) The serial status register (SSR) consists of flag s that sho w the U ART operating status. ■ Configurati on of Serial S tatus Register ( SSR) The config uration of the seria l status register (S SR) is sh own below: ■ Bit Function of Serial Status Register (SSR) [bit 7] [...]

254 CHAPTER 10 UART [bit 4] RDRF (Receive Da ta Register Full) This bit is an i nterrupt req uest flag in dicating that r eceived data is stored in the SIDR register . The bit is set whe n receiv ed data is loade d to the SIDR register and cl eared automati cally when the r eceived data i s read from th e SIDR regis ter. 0: No rec eived data is sto[...]

255 10.6 UART Opera tion 10.6 UART Operatio n U A R T has the follo wing three operation modes, whic h can be changed b y setting a v a lue in the SMR or SCR register . • Asynchronous (star t-stop) normal mode • Asynchronous (star t-stop) multipr ocessor mode • CLK synchronous mode ■ U ART Operation Modes Table 10.6- 1 summa rizes the UART [...]

256 CHAPTER 10 UART ❍ Extern al cloc k When the external c lock is s elected with "1" set in CS0 , the baud rate is deter mined as follows (f is th e extern al cloc k freque ncy): • Async hronous (sta rt-stop) : f/16 • CL K sync hronous : f f can be u p to 3.125 M Hz.[...]

257 10.7 A synchronous (Start-Stop) Mode 10.7 Asynchronou s (Start-Stop) Mode The U ART handles data of only NRZ (nonreturn-to- z ero) f ormat. Data transfer begins with a start bit (L-level data) f or the specified number of data bits in LSB firs t mode and ends with a stop bit (H -le vel data). When the external cloc k is selected, alwa ys input [...]

258 CHAPTER 10 UART 10.8 CLK Synch ronous Mode The U ART handles onl y dat a of NRZ (nonreturn-to-z ero) f ormat. Figure 10.8-1 shows the relationship between the transmission/reception cloc k and the data. ■ Format of Data T ransferred in CLK Synchronous Mode Figure 10.8-1 Format of Data T ra nsf erred in CLK Synchrono us Mode (Mode 2) When CS0 [...]

259 10.8 CLK Synchronous Mode • SCR regist er •P E N : 0 • P, SBL , A/D: These bits ar e invalid. • CL: 1 • REC: 0 (for in itializati on) • RXE, TXE : At leas t one mus t be set to 1 . •S S R r e g i s t e r • 1 for us ing interr upts or 0 fo r using no interru pt • TIE: 0 ❍ Start of communication Writin g to the SODR regis ter [...]

260 CHAPTER 10 UART 10.9 UART Interrupt Occurrence and F lag Setting T iming The U ART has five fla gs and tw o interrupt causes. The five flags are P E, ORE, FRE, RDRF , and TDRE. One of the tw o interrupt causes is for data reception and the ot her is for data transmi ssion. ■ Interrupt Occurrence and Flags PE indi cates a pa rity er ror, O RE [...]

261 10.9 UART Interrupt Occurre nce and Flag Setting Timing ■ Interrupt Flag Set Timing f o r Data Recepion in Mode 1 When the las t s to p bi t i s dete cte d a fter da ta rec ep tio n/tr an sfe r is c omp le ted, the ORE, FR E, a nd RDRF flags are set t o issue an int errupt req uest t o th e CP U. Since th e l eng th o f da ta i tem s that can[...]

262 CHAPTER 10 UART ■ Interrupt Flag Set Timing f or Data T ransmission in M ode 0, 1, or 2 TDRE is cle ared when data i s written to the S ODR regis ter. Afte r the written da ta is trans ferred to the in ter nal s hift r eg ist er a nd t he S O DR reg ister is r eady t o accept the ne xt item o f writ e data, TDRE is set a gain to is sue an int[...]

263 10.10 Notes on Us ing the UART and Example for U sing the UART 10.10 Notes on Usin g the UART an d Example for Using the UART This section pro vides an example f or use of the U AR T and notes on using the U ART . ■ Notes on Using the U ART Set the co mmunication mod e while UART o peration is stopped. Data transmitted during mo de setting ca[...]

264 CHAPTER 10 UART Figure 10.10-2 Comm unication Flowchart for Mode 1 END Yes No Yes No START (Host CPU) Set "0" in A/D Communication with slave CPU Set transfer mode to 1 Set address data in D0 to D7 to select the slave CPU and set A/D to "1", then transfer one byte Enable the receive operation Is the communication finished? C[...]

265 10.11 Setting Examples of Baud Rates and U-TIMER Reload Values 10.11 Setting Exam ples of Baud Rates and U-TIMER Relo ad Values T ables 10 .11-1 a nd 10.11-2 are sample setti ngs f or baud rates and U-TIMER r eload va l u es . The frequencies in t he ta bles indicate peripheral machine c lock frequencies. UCC1 indicates the value to set in the [...]

266 CHAPTER 10 UART[...]

267 CHAPTER 11 A/D CONVERTER (Suc ces sive approximation type) This ch apter pr ovide s an o verview of the A/D c on ver ter and e xplains the register configuration and functions and the operations of the A/D con ver ter . 11.1 Ove rview of A/D Converter (Successive Appr oximat ion Type) 11.2 Control Status Re gi ster (ADCS) 11.3 Data Register (AD[...]

268 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) 11.1 Ove rview of A/D Con verter (Successive App roximation Type) The A/D con ver ter con verts analog input v oltage to digital v alues. ■ Char acteri stics o f A/ D Con verter • Minimum convers ion time: 5.6 µ s/ch (fo r 25 MH z sy s tem cl oc k) • Built- in sampl e & hold [...]

269 11.1 Overvi ew of A/D Converter (Successive Approximat ion Type) ■ A/D Con ver ter Block Dia gram Figure 11 .1-2 is an A /D conve rter block d iagram. Figure 11.1-2 Block Diagr am of the A/D Converter . AVCC AVR AVSS MPX AN0 AN1 AN2 AN3 ADCR ADCS ATGX R | B U S Input circuit Internal voltage generator Sample & hold circuit Comparator Succ[...]

270 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) 11.2 Con trol Status Register (A DCS) The control status register (ADCS) c ontr o ls the A/D con ver ter a nd displa y s status inf ormation. Do not rewrite the ADCS during A/D con version. Do not use a Read Modify Write (RMW) instruction to access it. ■ Configuration of Control Statu[...]

271 11.2 Contr ol Status Register (ADCS) <Note> Set the bi t to "0" fo r cleari ng it whil e A/D conver sion is s topped. The bit is initial ized to "0" when the r egister is reset. A Read Mo dify Wr ite instr uction r eads "1 " from th is bit. [bit 13] INTE (INTerrupt Ena ble) This bit specifies whether to enabl[...]

272 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) <Notes> The exter nal pin tri gger signa l is detecte d on the falling edge . If the bit s etting is changed to select an external tr igger m ode while t he external trigger in put leve l is low , the A/ D conv erter may start . In timer start mod e, reload timer channel 2 is sele[...]

273 11.2 Contr ol Status Register (ADCS) <Note> A/D conv ersion that is s tarted in continuou s co nversion m ode or c onvert-and -stop mo de continue s until t he BUSY b it stops it. Writin g "0" to t he BUSY b it stops A/D co nversion. "No res tart is enabl ed" in sing le conve rsion, con tinuous conv ersion, or convert-[...]

274 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) If the sam e channel as that se t by ANS2 t o ANS0 i s set, on ly one ch annel is su bjecte d to A/ D conve rsion (s ingle co nversi on mode) . After A/D c onversio n is finished ove r the chann el set by the se bits in cont inuous conver sion or con vert-and-s top mode, the A/D convert[...]

275 11.3 Data Regis ter (ADCR) 11.3 Data Register (AD CR) The data register (ADCR) is used to store a digital va lue that is the con version result. ■ Configuration of Data Regis ter (ADCR) The config uration of the data r egister (AD CR) is s hown below: The value stored in this r egister is upda ted whenev er one cyc le of co nversi on is comp [...]

276 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) 11.4 A/D Co nverter Operation The A/D con ver ter operate s in succes si ve appro ximation m ode and features a 10 -bit resolution. The A/D con ver ter has only one register (1 6 bits) to s t or e the co n version result s. Theref ore, the da ta register (ADCR) is upda ted whenever con [...]

277 11.4 A/D Converter Operation In conti nuous conversi on mode, t he A/D conver ter continu es conv ersion until the BUSY bit is set to "0 ". Writin g "0" to th e BUSY bi t forcibly termin ates A/D conv ersion. Note that forced termi nation interrupts c onversion in prog ress. When co nversion i s forcibl y terminat ed, the d [...]

278 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) 11.5 Con version Data Protection Functi on The A/D con ver ter of the MB91F109 has a con versi on data pr ot ection function that features contin uo us con ver sion using DMA C and securing mu ltiple data items. ■ Con version Data Protection Function The A/D conv erter has on ly one c[...]

279 11.5 Conver sion Data Protection Function Figure 11.5-1 W orkflow of the Data Pr otection Function when DMA T ransfer is Used NO YES YES NO * End DMAC end interrupt routine Set DMAC The workflow for A/D converter termination is omitted. Start of continuous A/D conversion End of one cycle of conversion Store conversion data in data register End [...]

280 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) 11.6 Notes on Using the A/D Converter This section pro vides notes on using the A/D con ver ter ■ Notes on Using the A/D Conv erter ❍ Using an external trigger or int ernal timer to star t the A/D con v erter The A/D star t cause bits STS1 and STS0 of the ADCS r egister spe cify whe[...]

281 CHAPTER 12 16-BIT RELOAD TIMER This ch apter pr ovide s an o verview of the 16-b it reload time r , and e xplains the registe r configuration and functions, and operations of the 16-bit reload timer . 12.1 O v erview o f 16-Bi t Reload Timer 12.2 Cont rol Stat us Regis ter (TMCSR ) 12.3 16-Bit Timer Re gister (TMR) and 1 6-bit Reload Register ([...]

282 CHAPTER 12 16-BIT RELOAD TIMER 12.1 Ove rview of 16-bit Reload Ti mer The 16-bit reload timer consists of a 16-bit decrementing counter , 16-bit reload register , internal count c l ock pulse generation prescaler , and contr ol reg ister . An input cloc k can be selected fr om three types of internal cloc k frequencies (machine cl ock frequency[...]

283 12.1 Over view of 16-bit Reload Timer ■ 16-Bit Reload Timer Block Diagram Figure 12 .1-2 is a 16 -bit reloa d timer b lock diagram . Figure 12.1-2 16-Bit Re load Timer Block Diagram 16 / / 8 RELD / UF OUTE 16 OUTL 2 / OUT INTE GATE CTL. / 2 UF IRQ CSL1 CNTE CSL0 TRG / 2 IN CTL. EXCK PWM(ch.0,ch.1) 3 A/D (ch.2) 2 1 2 3 2 5 MOD2 MOD1 MOD0 / 3 R[...]

284 CHAPTER 12 16-BIT RELOAD TIMER 12.2 Con trol Status Register (T MCSR) The contr ol status register is used to contr ol the 16-bit timer operation mode and interrupts. Set the bits other than UF , CNTE, and TRG again when CNTE is 0. Sim ultaneous writing is enable d. ■ Configuration of Control Status Register (TMCSR) The confi guration of the [...]

285 12.2 C ontrol Status R egister (TM CSR) [bit 3] INTE This is an int errupt en able bit. When the UF bit changes to "1" while th is bit is "1" , an interrupt request is issued . No int errupt reques t is issu ed whil e this bit i s "0". [bit 2] UF This is a ti mer interrup t reques t flag, whi ch is set to "1&q[...]

286 CHAPTER 12 16-BIT RELOAD TIMER 12.3 16-Bi t Timer Register (TMR) and 16-Bit Reload Registe r (TMRLR) The 16-bit timer register (TMR) is used to read the count value of the 16-bit timer . The 16-bit reload register (TMRLR) stores the initial count v alue. ■ 16-Bit Timer Regis ter (TMR) The 16-bit tim er register is used to read the co unt valu[...]

287 12.4 Operation of 16 -Bit Reload Timer 12.4 Operation o f 16-Bit Reload Tim er The 16-bit reload timer perf orms the f ollowing tw o types of operat ion: • Internal cloc k operation • Underflow operation ■ Internal C lock Operation When a fr equency d ivision clo ck of the inter nal clock is used to run the timer, a machine clock frequenc[...]

288 CHAPTER 12 16-BIT RELOAD TIMER Figure 12.4-2 Underf lo w Operation Timing 0000 H (RELD=1) 0000 H FFFF H (RELD=0) -1 -1 -1 Count clock Counter Data loading Underflow setting Underflow set Counter Count clock Reload data[...]

289 12.5 Counter States 12.5 Counter States The states of the counter are determined b y the CNTE bit of the control regist er and the internal W ait signal as f ollo ws: CNTE = "0 ", W ait = "1 ": S top state CNTE = "1 ", W ait = "1": W ait state (sta r t trig g er wait state) CNTE = "1", W ait = &[...]

290 CHAPTER 12 16-BIT RELOAD TIMER[...]

291 CHAPTER 13 BIT SEARCH MOD ULE This chapter pr o vides an overvie w of the bit searc h module . It explains the register configuration, functions, operations, and the sa ve/restore pr ocessing of th e bit searc h module . 13.1 Overview of the Bit S earch Module 13.2 B it Search Module Regist ers 13.3 Bit Search Mod ule Opera tion and S ave/Resto[...]

292 CHAPTER 13 BIT SEARCH MODULE 13.1 Ove rview of the Bit Search Modu le The bit sear ch module searc hes the data written to the input register f or 0, 1, or a c hange point, and returns the detected bit position. ■ Bit Search Module Registers Figure 13 .1-1 sho ws the bit sear ch modul e regist ers. Figu re 13. 1-1 B it Se arc h Modul e Regist[...]

293 13. 2 Bit Sea rch Mo dule Re gist ers 13.2 Bit Search Module R egisters The bit searc h module uses the f ollo wing four register s: • 0-detecti on data register (BSD0) • 1-detecti on data register (BSD1) • Chang e-p oint detection data register (BSDC) • Detection resul t register ( BSRR) ■ 0-De tec tion Dat a Regist er (BSD0 ) The mo[...]

294 CHAPTER 13 BIT SEARCH MODULE ❍ Read Data save d for the inter nal status of the bit s earch module is rea d from this regis ter. When the interr upt handle r uses the bit sear ch modul e, the reg ister is u sed to sa ve the cu rrent statu s and restore i t. Even when data is written to the 0-detectio n or ch ange-point detection data reg iste[...]

295 13.3 Bit Search Module Operation a nd Save/Restore Processing 13.3 Bit Search Module Ope ration and Save/Restore Processing This section e xplains the operations of the bit searc h module f or 0-detection, 1-detection, and change-point detection and also e x plains save and restore pr ocessing. ■ 0-Detect ion The modul e scan s the da ta writ[...]

296 CHAPTER 13 BIT SEARCH MODULE ■ Change-P oint Dete ction The module scans the data writt en to the change- point det ection dat a registe r from bit 30 to LSB while c omparing each bit with the MSB value and returns the position whe re the value d ifferent from the MSB was f irst detec ted. The detecti on resu lt can be obtained b y reading t [...]

297 13.3 Bit Search Module Operation a nd Save/Restore Processing ■ Save/Restore Processing When the internal status o f the bit s earch modul e must be saved a nd restored , such a s when the module i s used in th e interrupt handle r, proceed as follows : 1. Rea d the 1-d etection d ata registe r and sto re the read data. (Sa ve) 2. Us e the bi[...]

298 CHAPTER 13 BIT SEARCH MODULE[...]

299 CHAPTER 14 PWM TIMER This ch apter pr ovide s an o verview of the PWM t imer an d e xplains the regi ster configuration and functions and the operations of the PWM timer . 14.1 Ove rview of PW M Timer 14.2 PWM Timer Blo ck Diagram 14.3 Control Status Re gi ster (PCNH, PCNL) 14.4 PWM Cycle Settin g Register (PCSR) 14.5 PWM Duty Cycle Setting Reg[...]

300 CHAPTER 14 PWM TIMER 14.1 Ove rview of PWM Timer The PWM time r can eff icientl y output accurate PWM wa veforms . The MB91F109 contains f our channels of PWM timer . Each c hannel consists of a 16-bit counter , a 16-bit data register with a cyc le setting b uff er , a 16-b it compare register wi th a duty c ycle setting b uff er , and a pin co[...]

301 14.1 Ov erview of PWM Timer ■ PWM Timer Registers Figure 14 .1-1 show s the PW M timer re gisters. Figure 14.1-1 PWM Timer Registers 15 0 000000DC H R/W 000000DF H R/W 000000E0 H R 000000E2 H W 000000E4 H W 000000E6 H R/W 000000E8 H R 000000EA H W 000000EC H W 000000EE H R/W 000000F0 H R 000000F2 H W 000000F4 H W 000000F6 H R/W 000000F8 H R 0[...]

302 CHAPTER 14 PWM TIMER 14.2 PWM T imer Block Diagram Figure 14.2-1 is a general bloc k diagram of the PWM timer . Figure 14.2-2 is a bloc k diagram of a single PWM timer channel. ■ General Block Dia gram of PWM Timer Figure 14.2-1 Ge neral Bloc k Diagram of PWM Timer PWM0 PWM1 4 PWM2 PWM3 16-bit reload timer ch0 16-bit reload timer ch1 General [...]

303 14.2 PWM Time r Block Diagram ■ Block Diagram of Single PWM Timer Channel Figure 14.2-2 Block Diagram of Single PWM Timer Channel 1/1 cmp 1/4 ck 1/16 1/64 SQ R IRQ PCSR PDUT Prescaler Peripheral clock Load 16-bit decrementing counter Start Borrow PPG mask PWM output Inverse bit TRG input Enable Edge detection Software trigger interrupt select[...]

304 CHAPTER 14 PWM TIMER 14.3 Con trol Status Register (PC NH, PCNL) The contr ol status register (PCNH, PCNL) is used to contr ol the PWM timer or indicate the timer status. Note that the register has a bit that cannot be rewritten during PWM timer operation. ■ Configuration of Contr ol Status Registers ( PCNH, PCNL) The configurati on of the co[...]

305 14.3 Contr ol Status Regist er (PCNH, PC NL) [bit 12] RTRG: Restart enable bit This bit enables o r disable s restart by a softw are trigger o r trigge r input. [bits 11, 10] CKS1, CKS0: Counter c lock select bit These bit s select th e counter clock for th e 16-bit decrementi ng counter. φ: Perip heral ma chine c lock [bit 9] PGMS: PWM output[...]

306 CHAPTER 14 PWM TIMER [bit 5] IREN: Interrupt request enable bit This bit enables o r disable s interrup t requests. [bit 4] IRQF: Interrupt request flag When the interrupt caus e selected by bits 3 and 2 (IRS1 and IRS0) is genera ted while bit 5 (IREN) is set to 1 ( Enable), th is bit is s et to caus e an interr upt request t o the CPU. Thi s E[...]

307 14.3 Contr ol Status Regist er (PCNH, PC NL) Polarity After resetting Duty cy cle matching Counter borrow Normal polarity O utput of L Inve rse polarity O utput of H[...]

308 CHAPTER 14 PWM TIMER 14.4 PWM C ycle Setting Register (PCSR ) The PWM cyc le set ting register (PCSR) is used to set a cyc l e . This register has a b uffer . A borr ow occurr ing in the counter triggers a t ransf er fr om the b uffer . ■ PWM Cycle Setting Register (P CSR) The confi guration of the PWM cycle se tting regist er (PCSR) i s show[...]

309 14. 5 PWM Dut y C ycle Set tin g Re gist er (PDU T) 14.5 PWM Duty Cycle Setting Register (PDUT) The PWM duty cyc le sett ing register (PDUT) is used to set a duty cyc l e . This register has a b uffe r . A bor ro w occurring in the c ounter t rigger s a tran sfer fr om the b uffer . ■ PWM Duty C yc le Setting Register (PDUT) The config uratio[...]

310 CHAPTER 14 PWM TIMER 14.6 PWM T imer Register (PTMR) The PWM timer register (PTMR) is used to read the v alue of the 16-bit decrementing counter . ■ PWM Timer Register (PTMR) The confi guration of the PWM timer regis ter (PTMR) is shown below. Use a 16- bit data ins tructio n to access the cycle setting reg ister. PTMR bit 15 14 13 12 11 10 9[...]

311 14.7 General C ontrol Register 1 (G CN1) 14.7 General Contro l Register 1 (GCN1) The general control register 1 (GCN1) is used to select the sour ce of PWM timer trig g er input. ■ Configuration of General Control Register 1 (GCN1) The config uration of the gener al contro l register 1 (GCN1) is shown bel ow. GCN1 bit 15 14 13 12 11 10 9 8 Ad[...]

312 CHAPTER 14 PWM TIMER ■ Bit Functions of General Control Register 1 (GCN1) [bits 15-12] TSEL 33-30: ch3 trigger input select bits [bits 11-8] TSEL 23-20: ch2 trigger input sele ct bits T able 14.7-1 Selection of Ch3 T rigger Input TSEL33-30 ch3 trigger input 15 14 13 1 2 0 0 0 0 GCN2 EN0 bit 0 0 0 1 GCN2 EN1 bit 0 0 1 0 GCN2 EN2 bi t (Initial [...]

313 14.7 General C ontrol Register 1 (G CN1) [bits 7-4] TSEL 13 -10: ch1 trigger input select bits [bits 3-0] TSEL 03 -00: ch0 trigger input select bits T able 14.7-3 Select ion of Ch1 T rigger Input TSEL13-10 ch1 trigger input 7654 0000 G C N 2 E N 0 b i t 0 0 0 1 GCN2 EN1 bit ( Initial value) 0010 G C N 2 E N 2 b i t 0011 G C N 2 E N 3 b i t 0 1 [...]

314 CHAPTER 14 PWM TIME R 14.8 Gen eral Control Register 2 (GCN 2) The general control regist er 2 (GCN2) is used f or ge nerating a star t trigger b y software . ■ General Control Register 2 (GCN2) The co nfiguration of the gener al contro l register 2 (GCN2) is shown below. When an E N bi t of t his regi s ter is s ele ct ed b y th e ge ner al [...]

315 14.9 PWM Operati on 14.9 PWM Operation PWM operation outputs pulses continuously . ■ PWM Oper ation. Upon detec tion of a s tart trigg er, the PW M timer outputs pu lses conti nuously. The cycle of o utput puls es can be c ontrolled b y changi ng the PCSR v alue, and th e duty rat io can be c ontrolled b y changi ng the PDUT v alue. After wri[...]

316 CHAPTER 14 PWM TIMER ❍ T rigger r estar t disabled Figure 14.9-1 P WM Operation Timing Char t (T r igger Restar t Disabled) ❍ T rigger r estar t disabled Figure 14.9-2 PWM Operation Timi ng Chart (T rigger Res tart Enabled) m n 0 PWM Start trigger A rising edge is detected. A trigger is ignored. T: Count clock cycle m: PCSR value n: PDUT va[...]

317 14.1 0 One- Sho t Ope r ation 14.10 One-Sh ot Operation One-shot operation outputs a single pulse . ■ One-Shot Oper ation Upon detec tion of a tri gger in one-sho t operatio n mode, the PW M timer can o utput a sing le pulse of arbitrar y width. When an e dge is de tected dur ing operati on while restart is enabled, the counte r is relo aded.[...]

318 CHAPTER 14 PWM TIMER ❍ T rigger r estar t disabled Figure 14.10-1 O ne-Shot Operati on Timing Chart (T ri gger Restar t Disabled) ❍ T rigger r estar t enabled Figure 14.10-2 One-Shot Operation Timing Chart (T rigger Res tart Ena bled) m n 0 PWM Start trigger A rising edge is detected. A trigger is ignored. T: Count clock cycle m: PCSR value[...]

319 14.11 Interr upt 14.11 Interrupt Figure 14.11-1 sho ws the causes of interrupts and their timing. ■ Interrupt Figure 14.11-1 Causes of Interrupts and Their Timing (PWM Output: Normal P olarity) 0003 0002 0001 0000 0003 PWM Start trigger Load Clock Count value Interrupt Effective edge Duty cycle matching Counter borrow *: A maximum of 2.5T (T [...]

320 CHAPTER 14 PWM TIMER 14.12 Con stant "L" or C onstant "H" Output from PWM Timer Figure 14.12-1 shows ho w the PWM timer ca n keep output at a lo w level . Figure 14.12- 2 shows ho w the PWM timer can keep output at a high le vel. ■ Constant "L" or Constant "H" Output fr om PWM Timer ❍ Example of keepi[...]

321 14.13 Starting Multiple PW M Timer Cha nnels 14.13 Starting Mu ltiple PWM Timer C hannels General contr ol registers 1 and 2 (GCN1 and GCN2) can be used to start mul tiple PWM timer channels. Selecting a start trigger with the GCN1 re gister ena bles sim ultaneous start of m ultiple channels. This section pr o vides an e xample of starting mult[...]

322 CHAPTER 14 PWM TIMER ■ Starting M ultiple PWM Timer Channels Using the 1 6-Bit Reload Timer In step 3) of the foregoi ng setting procedure , select the 16 -bit reload timer as the start trigg er in GCN1 and then star t the 16-b it reload ti mer instead of GCN2 i n step 5). The PWM timer c an be resta rted at regu lar inte rvals by setting tog[...]

323 CHAPTER 15 DMAC This chapter pr ovides an overview of the DMA C and ex plains the register configuration and functions and the operations of the DMA C. 15.1 Overview of DMAC 15.2 DMAC Pa rameter D escriptor P o inter (DPDP) 15.3 DMAC Control Status Re gi ster (DACSR) 15.4 DMAC Pin Contr ol Re gi ster (DATCR) 15.5 Descriptor Re gister in RAM 15.[...]

324 CHAPTER 15 DMAC 15.1 Ove rview of DMAC The DMA C is a b uilt-in modul e of the M B91F109 that im plements dire ct memory acce ss (DMA ). ■ DMA C Chara cterist ics • Eight c hannels • Three mod es: Sin gle/block t ransfer, bu rst transf er, and c ontinuous transfer • Transfers from the total addr ess area t o the total address area • T[...]

325 15.1 Ove rview of DMAC ■ DMA C Bloc k D ia gr am Figure 15 .1-2 is a DM AC block diagram. Figure 15.1-2 DMA C Bloc k Diagram DPDP DACSR SADR DADR DATCR DACK0-2 EOP0-2 3 3 3 3 8 DRE Q 0-2 5 BLK DEC BLK DMACT INC/DEC Edge/le v el detection circuit Sequencer Inter nal resource transf er request Interrupt request Data buff er Switcher Mode Data b[...]

326 CHAPTER 15 DMAC 15.2 DMAC Param eter Descriptor Poin ter (DPDP) The DMA C parameter descriptor pointer (DPDP) is an internal register of the DMA C and is used to store the fir st address of the DMA C descriptor tab le in RAM. DPDP bit s 6 to 0 are alw a ys 0, and the fir st ad dress of the des criptor that can be se t is 128 b ytes. ■ DMA C P[...]

327 15.3 D MAC Control Status R egister (DACSR) 15.3 DMAC Control Sta tus Register (DACSR) The DMA C contr ol status register (D A CSR) is an inter n al register of the DMA C that specifies control status inf o rmat ion on the entire DMA C. ■ Configuration of DMA C Control Status Register (DA CSR) The config uration of the DMAC c ontrol status re[...]

328 CHAPTER 15 DMAC These bit s are in itialized to "0" by res etting. These bit s can be both read and written, b ut can onl y be set to "0". A Read Mo dify W rite in struction always reads "1" fro m each of t hese b its. [bit 30, 26, 2 2, 18, 14, 10, 6, 2] DEDn (DMA EnD) Each of th ese bits ind icates whe ther DMA tr[...]

329 15.4 DMAC Pin Control Regi ster (DATCR) 15.4 DMAC Pin Contro l Register (DATCR) The DMA C pin control regist er (D A TCR) is an internal register of the DMA C and is used to contr ol the e x ternal transfer request input pins, e xternal transfer request ac kno wledgment output pins, and e xternal transfer end output pins. ■ Configuration of D[...]

330 CHAPTER 15 DMAC ■ Bit Functions of DMA C Pin Contr ol Register (D A TCR) [bit 21,20, 13, 1 2, 5, 4] LSn1, LSn0: Transfer request input detect level sele ct Each of these bit s selec ts the dete ction le vel of the corres ponding external transfe r request input pi n DREQn as sho wn in Table 15.4-1. The value s of thes e bits are u ndefined a [...]

331 15.4 DMAC Pin Control Regi ster (DATCR) [bit 16, 8, 0] EPDEn These bit s spe cifies the time when th e tran sfer end output s ignal is to be gener ated fr om the corresp onding outpu t pin and also specif y whether to enabl e the output function of the corresp onding trans fer end o utput sig nal pin. These bit s are in itialized to "00&qu[...]

332 CHAPTER 15 DMAC 15.5 Descrip tor Register in RAM This descriptor register has the setup inf ormation for the corr esponding channel in DMA transfer m ode . The descrip tor registe r has a 12 -b yte area f or each c hannel that is allocate d to the memor y address spec ified by DPDP . See T able 15.2-1, " Channel descriptor addresses,"[...]

333 15.5 D escriptor Re gister in RAM [bits 5, 4] DCS1, DCS0: Transfer destination address update mode These bit s speci fy the mode in whi ch the tran sfer sour ce or de stination address is upda ted each tim e DMA t ransfer is p erforme d. Table 15.5 -1 list s the ava ilable comb inations of these b its. The unit in which a n addr ess i s inc rem[...]

334 CHAPTER 15 DMAC [bits 1, 0] MOD1, MOD0: Tr ansfer mode Thes e bi ts sp ecify the t ran sfer mod e. The conti nuous tr ansfer mode can be us ed for chann els 0 to 2 only. ■ Secon d W or d of a De scripto r The seco nd word contains th e transfe r sour ce addre ss. The addres s is updated at every transfer ope ration bas ed on the addre ss upda[...]

335 15.6 DMAC Tra nsfer Modes 15.6 DMAC Transfer Mode s The DMA C suppor ts the follo wing three transfer modes: This section explains the operation in these modes. • Single/bloc k transfer mode • Continuous transfer mode • B urst transfer mode ■ Single/Block T ransfer Mode 1. The initiali zation rou tine sets the descr iptor. 2. The progra[...]

336 CHAPTER 15 DMAC ■ Continuous T ransfer Mode 1. The initiali zation r outine s ets the de script or. 2. The program ini tialize s the DMA tr ansfer re quest sou rce. Set the exter nal tran sfer reque st input pi n to the H-lev el or L-l evel dete ction mode. 3. The program sets the target DO En bit of the DACSR to 1. --- This comp letes the se[...]

337 15.6 DMAC Tra nsfer Modes ■ Burst T ransfer Mode 1. The initiali zation rou tine sets the descr iptor. 2. The program in itializes the DMA tr ansfer re quest so urce. To u se the in ternal peri pheral circuit as the trans fer reques t source, en able inte rrupt requ ests and d isable inte rrupts in the ICR of the i nterrupt control ler. 3. Th[...]

338 CHAPTER 15 DMAC 15.7 Ou tput of Transfer Requ est Acknowled gment and Transfer End signa ls Channels 0, 1, and 2 ha ve a function that out puts transfer request ac knowledgment and transfer end si gnals from the corresponding pins. When a transfer request input fr om the pin is received and DMA transfer is perf ormed, the DMA C output s a trans[...]

339 15.8 Notes on DMAC 15.8 Notes on DMAC This section pro vides notes on using the DMA C. ■ Interc hanne l Priority Order Once the DMAC star ts with a DMA tra nsfer reque st from on e channel, DMA transfer r equests from ano ther channel are su spended u ntil the c urrent tra nsfer ends. When th e DMAC detects DMA tra nsfer req uests f rom multi[...]

340 CHAPTER 15 DMAC ❍ PDRR regist er The suppressio n function for a DMA transfer operation specified via the HRCL register i s valid only when an inte rrupt requ est wit h highe r priorit y is act ive. The refore, i f the in terrupt req uest i s cleared by the interrup t handler p rogram, sup pression o f the DMA transfe r operation v ia the HRC[...]

341 15.8 Notes on DMAC itse lf contin ues. ■ External T r ansfer fr om Internal Memor y In block tr ansfer m ode, DMA tran sfer is performed twice for a single DRE Q. In co ntinuous transfe r mode, DMA tr ansfer is perfor med even if DREQ is cancele d. To prev ent this, se lect one of the following counterm easures: • Use DR EQs in edg e detect[...]

342 CHAPTER 15 DMAC 15.9 DMAC T iming Charts This section pro vides the fol lowing DMA C timing char ts: • Timing charts for t he descriptor access bloc k • Timing charts for t he data transfer b l ock • T ran sf er stop timing c harts in continuous transfer mode • T ran sfer termination timing char ts ■ Codes Used in t he Timing Char ts [...]

343 15.9 D MAC Timing Charts 15.9.1 Timing Char ts of the Descriptor Ac cess Block This secti on sho ws timing c har ts of t he descr iptor ac cess b lock. ■ Descript or Access Block ❍ Required pin input mode: level, descriptor address: external ❍ Required pin input mode: level, descriptor address: internal (A) CLK DREQn RDXD WRnX DACK EOP #2[...]

344 CHAPTER 15 DMAC ❍ Required pin input mode: edge , descriptor addr ess: external ❍ Required pin input mode: edge , descriptor address: intern al <Note> The sect ion from when a DREQn is generated to when th e DMAC operation s tarts sho ws the case w her e the DMAC op eratio n star ts firs t. The DMAC o peration may be d elayed b ecause[...]

345 15.9 D MAC Timing Charts 15.9.2 Timing Char ts of Data T ran sfer Bloc k This secti on sho ws timing c har ts of t he data transf er bloc k. ■ Data T ra nsfer Block f or 16-Bit or 8-Bit Data ❍ T ransfe r sour ce area : ext er nal, tran sfer dest ina tion ar ea: ex tern al ❍ T ransfe r sour ce area : ext er nal, tran sfer dest ina tion ar [...]

346 CHAPTER 15 DMAC ❍ T ransfe r sour ce area : inter nal RAM, t ra nsf er dest ination ar ea: e xter nal (A) CLK DREQn Addr pin Data pin RDXD WRnX DACK EOP #2 #2 W D D DDD D D W W D W[...]

347 15.9 D MAC Timing Charts 15.9.3 T ransfer Stop Timing Char ts in Continuous T r ansfer Mode This section sho ws transfer stop timing char ts in contin uous transfer mode. ■ T ransfer Stop in Continuous T ransfer Mode (When Either Address is Unchanged) for 16-Bit or 8-Bit Data ❍ T ransfe r sour ce area : ext er nal, tran sfer dest ina tion a[...]

348 CHAPTER 15 DMAC ■ T ransfer Stop in Continuous T r ansfer Mode (When Both Addresses are Changed) for 16-Bit or 8-Bit Data ❍ T ransfer source area: external, tra nsfer destination ar ea: external ❍ T ransfer source area: external, transfer destination ar ea: internal RAM ❍ T ransfe r sour ce area : inter nal RAM, t ra nsf er dest ination[...]

349 15.9 D MAC Timing Charts 15.9.4 T ransfer T erminatio n Timing Ch ar ts This section sho ws transfer termi nation timing charts. ■ T ransfer T ermination (When Eith er Address is Unchanged.) ❍ Bus width: 16 bits, data length: 8/16 bits ❍ Bus width: 16 bits, data length: 32 bits CLK Addr pin Data pin RDXD WRnX AKSE=1 DACK AKDE=1 EPSE=1 EOP[...]

350 CHAPTER 15 DMAC ■ T ransfer T ermination (When B oth Addresses are Chang ed.) ❍ Bus width: 16 bits, data length: 8/16 bits ❍ Bus width: 16 bits, data length: 32 bits CLK Addr pin Data pin RDXD WRnX AKSE=1 DACK AKDE=1 EPSE=1 EOP EPDE=1 W D D S S W #2L #2L #1H #1H W D D W W #0H #0H S S W D D W #1L #1L #2H #2H W Both are 1 Both are 1 CLK Add[...]

351 CHAPTER 16 FLASH MEMORY This chapter e xplains the flash memory functions and operations. The chapter pr o vides inf ormation on usin g the flash memory from the FR-CPU . For inf ormation on using the flash memory from the R OM writer , ref er to the user’ s guide f or the R OM writer . 16.1 Ou tline 16.2 Bl oc k Diagram of Flash Me mory 16.3[...]

352 CHAPTER 16 FLASH MEMORY 16.1 Ou tline of Flash Memory This de vice type has an internal flash memor y of 25 4 kilob ytes (2 megabits) that enab les to perf orm the f ollowing functions with a single +3 V po wer supply: sim ultaneous erasure of all sect or s, era sure in sect or units, a nd writing in half-w or d (16 bi ts) units via the F R-CPU[...]

353 16.1 O utline of Flash Memory ■ Execution Status of the A utomatic Algorithm When the au tomati c algo rithm is star ted in CPU pr ogrammi ng mode , its op erati on stat us can be checke d with the inte rnal Busy or Rea dy signa l (RDY/BUSYX ). The level of thi s signal ca n be read from t he "RDY" bit of the fl ash memo ry status r[...]

354 CHAPTER 16 FLASH MEMORY 16.2 Block Diagram of Flash Memo ry Figure 16.2-1 is a bloc k diagram of the flash memory . ■ Block Diagram of Flash Memory Figure 16.2-1 Block diagram of the Flash Memory RDY/BUSYX RESETX BYTEX OEX WEX CEX INTE RDYINT RDY WE FA18-0 DI15-0 DO31-0 CD31-0 CA18-0 2Mbit (254K 8/127K 16) Rising edge detection Control signal[...]

355 16.3 Flash Me mory Status Register ( FSTR) 16.3 Flash Memory Status Reg ister (FSTR) The flash memory st atus register (FSTR) indicates the operation status of the flash memory . This register also contr ols interrupts to the CPU and writing to the flash memory . Only the CPU can access this register . Even if a writer is pr ovi ded, it cannot [...]

356 CHAPTER 16 FLASH MEMORY When this bit is "1", writin g data and commands to the flash memory bec omes valid and the automatic algorithm can be started. Howev er, data from flash mem ory is re ad in 16-bit access mod e, during whic h flash memory cannot be used as prog ram memory becau se 32- bit acc ess is in hibite d. When ove rwriti[...]

357 16.4 Sector Configuration of Flash Memory 16.4 Sector Configu ration of Flash Mem ory Figure 16.4-1 s how s the sector conf iguration of the flash memory . T able 16. 4.1 lists the respec tive sect or ad dress es. ■ Sector Configuration of the Flash Memor y Flash me mory addr ess mapp ing for access fr om the FR-C PU is d ifferent fro m the m[...]

358 CHAPTER 16 FLASH MEMORY T able 16.4-1 Sector Addresse s Sector address Address range Corresponding bits Sector capacity SA0 000C0800-1h to 0 00DFFFC-Dh (MSB side 16 bits) bit 3 1 to 16 63 Kbyte SA1 000E0000-1h to 000EFFFC-Dh (MSB side 16 b its) bit 31 to 16 3 2 Kbyte SA2 000F0000- 1h to 000F3FFC- Dh (MSB side 16 bit s) bi t 31 to 16 8 Kbyte SA3[...]

359 16.5 Fl ash Memory Acce ss Modes 16.5 Flash Memory Access Modes The f ollow ing tw o types of access mode are av ailable f or the FR-C PU: • ROM mode: On e w ord (32 bits) can be read in one cyc le , b ut not written. • Programming mode: Access to data with a length in w ords (32 bits) is inhibited b ut writing data with a length in h alf-w[...]

360 CHAPTER 16 FLASH MEMORY For detai ls on the auto matic al gorithm, see Sec tion 16.6, " Starting th e Automati c Algor ithm." ❍ Restrictions Addres s assignm ent and end ians in t his mode differ from those for writing with the RO M writer. This mod e inhibit s reading d ata in wor ds (32 bits) .[...]

361 16.6 S tarting the Aut omatic Algorithm 16.6 Starting the Auto matic Algo rithm For writing data to or erasing data fr om flash memor y , star t the automatic algori thm stored in f lash memory . ■ Comm an d Op erati on At the st art of the autom atic algorit hm, one to six hal f-words (16 bits ) are written. Th is data is called the com ma n[...]

362 CHAPTER 16 FLASH MEMORY ❍ Pr ogram (Write) In CPU programm ing mode, data is basica lly writte n in hal f-word uni ts. The wr ite ope ration i s performed i n four cy cles of bus operation. The comma nd sequence h as two " unlock" cy cles, which are fol lowed by a Writ e Se tup comman d and a wr ite dat a cyc le. Writ ing to me mory[...]

363 16.6 Starting the Automatic Algorithm During th e time-out perio d, any command othe r than Sector Eras e and Temporari ly Stop Erase is reset at r ead time, an d the precedi ng comman d sequenc e is ignored . In the case o f the Temporary Stop Erase comm and, the conten ds of the secto r are erased ag ain and the erase operati on is compl eted[...]

364 CHAPTER 16 FLASH MEMORY 16.7 Execution Status of the Automatic A lgorithm This flash memory has tw o har dware components fo r perf orming a Write or Erase sequence in the automatic algorithm. These components indicate the internal operation status of flash memory and the completion of operations to external components. One is a Read y/Busy sig[...]

365 16.7 Execution Status of the Automatic Algorithm Table 16.7- 1 lists th e possi ble status es of the hardware s equence fl ag. [bit 7] DPOLL (Dat a polling) ❍ A utomatic wri te operation status When a read op eration is performed during execut ion of th e automati c write a lgorithm , flash memory outputs the inv ersion of the la st written d[...]

366 CHAPTER 16 FLASH MEMORY ❍ T empora r y sec tor erase stop status When a r ead operation is performed during tempor ary sector erase stop, fl ash memory outpu ts "1" if t he address indicated b y the addre ss signal is i ncluded in t he sector i n erase state . If the addres s is not in cl ude d i n th e s ec tor i n e ra se st ate, [...]

367 16.7 Execution Status of the Automatic Algorithm Suppose that the data polling and togg le bit fun ctions indi cate that th e erase algorithm i s running . If this flag is "1" in this case, an inter nally control led erase oper ation has started and succeedi ng comma nd entri es are ign ored until the data p olling o r toggle bi t ind[...]

368 CHAPTER 16 FLASH MEMORY[...]

369 APPENDI X The appendices pr o vide mo re details and pr ogramming references concerning the I /O maps, interrupt vectors, pin statuses in CPU states, precautions on using the little endian area, and instructions. A I/O Maps B Interrupt Vectors C. Pi n Stat us for Ea ch CPU S tatus D. No tes on Usin g Littl e End ian Ar eas E. Instructio n[...]

370 APPENDIX A I/O Maps APPENDIX A I/O Maps The ad dresses li sted from T ab le A. 1 to T ab le A.6 are assigned to the regi ster s of the functions for peripherals that are b uilt-in in the MB91F109. ■ How to Read the I/O Maps <Note> The regis ter bit value has one of the follo wing initi al valu es: "1": Initial v alue "1&q[...]

371 APPENDIX A I/ O Maps ■ I-O Ma ps T able A-1 I/O Map (1/6) Address Register Internal resource +0 +1 +2 +3 000000 H PDR3 [R/W] XXXXXXX X P DR2 [R/W] XXXXXXX X - - Port data register 000004 H PDR7 [R/W] -------X PDR6 [R/W] XXXXXXX X P DR5 [R/W] XXXXXX XX PDR4 [R /W] XXXXXX XX 000008 H PDRB [R/W] XXXXXXX X P DRA [R/W] XXXXXXX X - PDR8 [R /W] --XX[...]

372 APPENDIX A I/O Maps 000054 H -- R e s e r v e d 000058 H -- T able A-1 I/O Map (1/6) Address Register Internal resource +0 +1 +2 +3 T able A-2 I/O Map (2/6) Address Register Internal resource +0 +1 +2 +3 00005C H -- R e s e r v e d 000060 H -- 000064 H -- R e s e r v e d 000068 H -- R e s e r v e d 00006C H -- R e s e r v e d 000070 H -- 000074[...]

373 APPENDIX A I/ O Maps 00009C H -- R e s e r v e d 0000A0 H - 0000A4 H - 0000A8 H - 0000AC H - 0000B0 H - 0000B4 H - 0000B8 H - T able A-2 I/O Map (2/6) Address Register Internal resource +0 +1 +2 +3 T able A-3 I/O Map (3/6) Address Register Internal resource +0 +1 +2 +3 0000BC H - Reserve d 0000C0 H - 0000C4 H - 0000C8 H - 0000CC H - 0000D0 H - [...]

374 APPENDIX A I/O Maps 0000DC H GCN1 [R/W] 00110010 00010 000 - GCN2 [R/W] 0000000 0 PWM 0000E0 H P TMR [R] 11111111 11111 111 PCSR [ W] XXXXXXX X XXXXXXXX 0000E4 H P DUT [W ] XXXXXX XX XXXXXXXX P CNH [R/W] 0000000- P C N L [ R / W ] 00000000 0000E8 H P TMR [R] 11111111 11111 111 PCSR [ W] XXXXXXX X XXXXXXXX 0000EC H PDUT [W ] XXXXXX XX XXXXXXXX P[...]

375 APPENDIX A I/ O Maps T able A-4 I/O Map (4/6) Address Register Internal resource +0 +1 +2 +3 000254 H - Reserve d 000258 H - 00025C H - 000260 H - 000264 H - 000268 H - 00026C H - 000270 H - 000274 H - 000278 H to 0002FC H - 000300 H to 0003E3 H - Reserve d 0003E4 H - Reserve d 0003E8 H - Reserve d 0003EC H - 0003F0 H BSD0 [W] XXXXXX XX XXXXXXX[...]

376 APPENDIX A I/O Maps T able A-5 I/O Map (5/6) Address Register Internal resource +0 +1 +2 +3 000400 H ICR00 [R/W] ---11111 ICR01 [R/W] ---1111 1 ICR02 [R/W ] ---111 11 ICR03 [R/W] ---11111 Inte rrupt controlle r 000404 H ICR04 [R/W] ---11111 ICR05 [R/W] ---1111 1 ICR06 [R/W ] ---111 11 ICR07 [R/W] ---11111 000408 H ICR08 [R/W] ---11111 ICR09 [R/[...]

377 APPENDIX A I/ O Maps 000600 H DDR3 [W] 00000000 DDR2 [W] 0000000 0 - - Data direc ti on regi ste r 000604 H DDR7 [W] -------0 DDR6 [W] 0000000 0 DDR5 [W] 00000000 DDR4 [W] 00000000 000608 H DDRB [W] 00000000 DDRA [W] -0000000 - DDR8 [W] --000000 T able A-5 I/O Map (5/6) Address Register Internal resource +0 +1 +2 +3 T able A-6 I/O Map Address R[...]

378 APPENDIX A I/O Maps <Note> Do not exe cute RMW instructi ons for reg isters for wh ich a wr ite-only bi t is se t. Data in ar eas mar ked as "Res erved" or " -" is und efined. RMW inst ruct io ns ( RMW: Re ad Modi fy Wri te) AND Rj, @ Ri OR Rj, @R i EOR Rj, @R i ANDH Rj, @ Ri ORH Rj, @Ri EORH Rj, @Ri ANDB Rj, @Ri ORB R[...]

379 APPENDIX B Inter rupt Vectors APPENDIX B In terrupt V ectors T able B.1 a nd T able B.2 li st the i n terrupt vectors. The interrupt vector tab les list causes f or MB91F109 interrupts toge ther with interrupt vector or interrupt contr ol register assignments. ■ Interrupt V ectors T able B-1 Interr upt V ectors (1/2) Cause for the interrupt I[...]

380 APPENDIX B Interrupt Vectors UART 2 rece ption com pletion 22 16 ICR06 3A4 H 00 0FFFA4 H UART 0 se nd completi on 23 17 ICR07 3A0 H 000FFFA0 H UART 1 se nd completi on 24 18 ICR08 39C H 000FFF9C H UART 2 se nd completi on 25 19 ICR09 398 H 000FFF98 H DMAC 0 ( end, error) 26 1A ICR10 394 H 000FFF94 H DMAC 1 ( end, error) 27 1B ICR11 390 H 000FFF[...]

381 APPENDIX B Inter rupt Vectors Reserved for the syste m 47 2F ICR3 1 34 0 H 000FFF40 H Reserv ed for the s ystem 4 8 30 - 33 C H 000FFF3C H Reserv ed for the s ystem 4 9 31 - 338 H 000FFF38 H Reserv ed for the s ystem 5 0 32 - 334 H 000FFF34 H Reserv ed for the s ystem 5 1 33 - 330 H 000FFF30 H Reserv ed for the s ystem 5 2 34 - 32 C H 000FFF2C [...]

382 APPENDIX B Interrupt Vectors Reference: The area 1 kilobyte after the a ddress ind icated by th e TBR is a vector address fo r EIT. Each v ector is 4 bytes in siz e. The rel ationshi p between the vector number and ve ctor addres s is as fol lows: vctadr = TBR + vctofs =T B R + ( 3 F C H - 4 × vc t) vctadr: V ector a ddress vctofs: Vector offs[...]

383 APPENDIX C Pin Status for Eac h CPU Status APPENDIX C Pin Status for Each CPU Status T able C.1 e xplains the terms used in the pin s tatus list. T able C- 2 to T ab le C- 5 list the pin status for eac h CPU stat us. Note that th e pin status at reset differ s between the external b us mode and single c hip mode . ■ Explanation of T e rms Use[...]

384 APPENDIX C Pin Status for Each CPU Status ■ Pin Statu s f or Eac h CPU Status T able C-2 Pin Status for 16-bit External Bus Length and 2CA1WR Mode Pin name Function During sleep During stop Bus release (BGRNT) Reset time HIZX=0 HIZX=1 P20 to P27 D16-23 Output retained or Hi-Z Output retained or Hi-Z Output Hi-Z/ Input fi xed to 0 Output Hi-Z [...]

385 APPENDIX C Pin Status for Eac h CPU Status PA6 CLK P: Previous status re tained F: CLK outpu t P, F: Previ ous stat us ret ain ed Output Hi-Z/ Input fi xed to 0 CLK Output CLK Output PB0 RAS0 P: Previous status re tained F: Previou s value retain ed Executed when DRAM pin i s set. P: Previous stat us ret ain ed F: Previo us value re tained Duri[...]

386 APPENDIX C Pin Status for Each CPU Status PF4 SO1, TRG3 Prev iou s sta tus retained P revio us st atus retained O utput Hi-Z/ Input fi xed to 0 Previous sta tus retained O utput Hi-Z/ Input allow ed for all pi ns PF5 SI2, OCPA1 PF6 SO2, OCPA2 PF7 OCPA0, ATGX T able C-2 Pin Status for 16-bit External Bus Length and 2CA1WR Mode (Continued) Pin na[...]

387 APPENDIX C Pin Status for Eac h CPU Status T able C-3 Pin Status for 16-b it External Bus Length and 2CA1WR Mode Pin name Function During sleep During stop Bus release (BGRNT) Reset time HIZX=0 HIZX=1 P20 to P27 D16-23 Outpu t retain ed or Hi-Z Output retained or Hi-Z Output Hi-Z/ Input fi xed to 0 Output Hi-Z - D24-31 - A 00-1 5 Out p ut ret a[...]

388 APPENDIX C Pin Status for Each CPU Status PA6 CLK P: Pre vious status ret ained F: CLK outpu t P, F: Previ ous status re tained Output H i-Z/ Input fi xed to 0 CLK Output CLK Output PB0 RAS0 P: Previous status ret ained F: Prev ious value reta ined Executed w hen DRAM pin is set. P: Previou s status re tained F: Previo us value re tained During[...]

389 APPENDIX C Pin Status for Eac h CPU Status PF4 SO1, TRG3 Prev iou s sta tus retained Pre vious status retained O utput Hi-Z/ Input fi xed to 0 Pr e vious s tatu s retained Outp ut Hi-Z/ Input allow ed for all pi ns PF5 SI2, OCPA1 PF6 SO2, OCPA2 PF7 OCPA0, ATGX T able C-3 Pin Status for 16-b it External Bus Length and 2CA1WR Mode (Continued) Pin[...]

390 APPENDIX C Pin Status for Each CPU Status T able C-4 Pin St atus in 8-bit External Bus Mode Pin name Function During sleep During stop Bus release (BGRNT) Reset time HIZX=0 HIZX=1 P20 to P27 Port Previous sta tus retained P revio us st atus retained O utput Hi-Z/ Input fi xed to 0 Previous status retained - D24-31 Output Hi-Z/ Input fixe d to 0[...]

391 APPENDIX C Pin Status for Eac h CPU Status PA6 CLK P: Previous status re tained F: CLK outpu t P, F: Previ ous stat us ret ain ed Output Hi-Z/ Input fi xed to 0 CLK Output CLK Output PB0 RAS0 P: Previous status re tained F: Previou s value ret ained (*2) Sam e as le ft during re fresh (*1) P: Previou s status re tained F: Previ ous value retain[...]

392 APPENDIX C Pin Status for Each CPU Status PF2 SC0, OCPA3 Previou s sta tus retained P revio us st atus retained O utput Hi-Z/ Input fi xed to 0 Previous sta tus retained O utput Hi-Z/ Input allow ed for all pi ns PF3 SI1, TRG2 PF4 SO1, TRG3 PF5 SI2, OCPA1 PF6 SO2, OCPA2 PF7 OCPA0, ATGX T able C-4 Pin Status in 8-bit External Bus Mode (Continued[...]

393 APPENDIX C Pin Status for Eac h CPU Status T able C-5 Pin Status in Single Chip Mode Pin name Function During sleep During stop — Reset time HIZX=0 HIZX=1 P20 to P27 Port Previous status retained Pre vious status retained O utput Hi-Z/ Input fi xed to 0 Output Hi-Z/ Input allow ed for all pi ns P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 [...]

394 APPENDIX C Pin Status for Each CPU Status P: when a general- purpose p ort is spec ified, F: when the sp ecified f unction is selected PB5 DREQ2 Previous status retained O utput Hi-Z/ All pins Input possib le PB6 DACK2 P: Previous status ret ained F: DACK output PB7 Port Previous status retained AN0 to AN3 AN0-3 Previous status retained PE0 to [...]

395 APPENDIX D Notes on Using Little Endian Areas APPENDIX D No tes on Using Little Endian Areas This section contains notes on using little endian areas f or eac h item belo w . D.1 C Compiler (fcc91 1) D.2 Assembler (fasm 911) D.3 Lin ker (flnk911) D.4 D ebug ger (si m911 , eml1 911, mon911)[...]

396 APPENDIX D Notes on Using Little Endian Areas D.1 C Compiler (fcc 911) When the operations described below are perf ormed f or little endian areas fr om pr ograms in C, the re sults of the resp ective operations ma y be rendered unc e r tain. • A lloc atin g variabl e s wi th in itia l value s • Assigning structures b y referencing other st[...]

397 APPENDIX D Notes on Using Little Endian Areas #define STRMOVE(DEST,SRC) DE ST.c=SRC.c;DEST.i=SR C.i; void ma in(voi d) { STRMOV E(little_st,normal _st); } Moreov er, as the memb er allocati on for a stru cture is di fferent for ea ch com piler, it ma y differ from that of another compiler . In this a case, the c orrect resu lt ca nnot be acq ui[...]

398 APPENDIX D Notes on Using Little Endian Areas Do not all ocate dou ble and lo ng double type var iables to l ittle endi an areas. [Example of incorrect processing] Transfer of double type data double b ig = 1.0; /* Big en dian are a */ extern int little; /* Little en dian area */ little = bi g; /* Transfer of double type data */ The exec ution [...]

399 APPENDIX D Notes on Using Little Endian Areas D.2 Assembler (fsm9 11) The f ollo wing tw o items require caution when using little endian areas during programming in FR-series Assemb ler: • Sections • D ata Acce ss ■ Sectio ns Little endi an areas are al located prim arily for data exchange data with little endian type CPU s. Therefore, d[...]

400 APPENDIX D Notes on Using Little Endian Areas /* 32-bi t data is ac cessed with a ST ( or LD) ins truction.*/ ST r0, @r1 /* 16-bi t data is ac cessed with a STH ( or LDH) ins truction. * / STH r2, @r3 /* 8-bit da ta is accessed w ith a ST B (or LDB) instruct ion. */ STB r4, @r5 If the MB91 F109 acces ses data wit h an ope ration for of a differ[...]

401 APPENDIX D Notes on Using Little Endian Areas D.3 Linker (flnk911) The f ollo wing tw o items require caution with respect to link-time section allocation during program design when em p lo y ing little endian areas. • Restrict ion on section types • No detection of error s ■ Res tri ction o n Se ctio n T ypes Only data sections with no i[...]

402 APPENDIX D Notes on Using Little Endian Areas D.4 Debuggers (sim911, em l911, and mon9 11) This section pro vides notes on the simulator deb u g ger an d em ulator or monitor debug g er . ■ Sim ulator D eb ugger There is no memor y area spe cificat ion comm and ind icating little en dian area s. Memory mani pulati on co mmands and instr ucti [...]

403 APPENDIX E Instructions APPENDIX E In structions This section lis ts the instr uctions f or the FR-series. Be f ore the instructions are listed, the follo wing items are explained: • How to r ead instructions • Addressing mode codes • Instruction for mats ■ How to Read Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks ADD *ADD [...]

404 APPEND IX E I nstruc tions 6) Indicates flag c hanges 7) Indicates the op eration f or the instr uction Flag change Changes Does not change Cleared Set C ... ... 0 1 ... ... C ... N ... ... ... - Flag meaning Negative flag Zero flag Ov erflow flag Carr y flag Z V[...]

405 APPENDIX E Instructions ■ Addressing Mode Codes T able E-1 Expl anation of Addressing Mode Codes Code Meaning Ri Regis ter using di rect ad dressing (R0 toR15, A C, FP, SP) Rj Regis ter using di rect ad dressing (R0 to R15,A C,FP,SP) R13 Register using dir ect addres sing (R1 3,AC) Ps Register using dir ect addres sing (Pro gram sta tus regis[...]

406 APPEND IX E I nstruc tions @(R13, Rj ) Regis ter using r elative and indirec t address ing (Rj: R0 to R15, AC, FP, a nd SP) @(R14 ,d isp10) Regi ster usin g relati ve and in direct addr essing (disp10 : -0X200 to 0 X1FC, mu ltiple of 4 only) @(R14, d isp9) Register us ing relati ve and in direct a ddressin g (disp9: -0X100 to 0X FE, multi ple o[...]

407 APPENDIX E Instructions ■ Instruction Formats T able E-2 Instruction Formats Type Instruction format A B C *C’ D E MSB LSB 16bit OP Rj Ri 84 4 OP i8/o8 Ri 484 OP u4/m4 Ri 84 4 ADD ,ADDN,CMP ,LSL,LSR and ASR instr uctions only 75 4 OP Ri s5/u5 OP u8/rel8/dir/reglist 88 OP SUB-OP Ri 84 4[...]

408 APPEND IX E I nstruc tions F T able E-2 Instruction Formats OP rel11 51 1[...]

409 APPENDIX E Instructions E.1 FR-Series Instructi ons This section describes the FR-series instructions in the f ollowing or der: ■ FR-Series I nstructions Table E.1- 1 Addit ion and Su btraction I nstructi ons Table E.1- 2 Compare O peratio n Instructi ons Table E.1- 3 Logical Operation Instruct ions Table E.1- 4 Bit Ope ration Ins tructions T[...]

410 APPEND IX E I nstruc tions ■ Addition and Subtraction Instructions ■ Comp are Oper ation Inst ructio ns T able E.1-1 Addition and Subtra ction Instructions Mnemonic Type OP Cy cle NZVC Operation Remarks ADD Rj, Ri *ADD #s5, Ri ADD #i4, Ri ADD2 # i4, Ri A C’ C C A6 A4 A4 A5 1 1 1 1 CCCC CCCC CCCC CCCC Ri + Rj --> Ri Ri + s5 --> Ri Ri[...]

411 APPENDIX E Instructions ■ Logical Operation Instructions ■ Bit Operation Instructions T able E.1-3 Logical Operation Instructions Mnemonic Type OP Cycle NZVC Operation Remark s AND Rj , Ri AND Rj , @R i ANDH Rj, @Ri ANDB Rj, @Ri A A A A 82 84 85 86 1 1+2a 1+2a 1+2a CC-- CC-- CC-- CC-- Ri &= Rj (Ri) &= Rj (Ri) &= Rj (Ri) &= R[...]

412 APPEND IX E I nstruc tions ■ Multiplication and Divis ion Instructions ■ Shift Instruct ions *3 The assemble r creates BEORL i f the bit is O N in u8& 0x0F and B EORH if the bi t is ON in u8&0xF0. Both BEO RL and BE ORH may b e created. T able E.1-5 Mult iplication and Division Instruc tions Mnemonic Type OP Cycle NZVC Operation Rem[...]

413 APPENDIX E Instructions ■ Immediate V alue S etting or 16/32-Bit Imme diate V alue T ransfer Instruction ■ Memory Load Instr uctions *: Spec ial register Rs : TBR, RP, US P, SSP, MDH, M DL (Notes) The asse mbler calculate s and sets v alues in the o 8 and o4 fiel ds of hardw are specificati ons as follow s: Disp10/4 --> o8, di sp9/2 --&g[...]

414 APPEND IX E I nstruc tions ■ Memory Store Instructions *: Spec ial register Rs : TBR, RP, US P, SSP, MDH, M DL (Notes) The asse mbler calculat es and sets values in th e o8 and o4 fiel ds of hardw are specificati ons as follow s: Disp10/4 --> o8, di sp9/2 --> o8, disp 8 --> o8: D isp10, disp 9, and d isp8 are sig ned. Udisp6/4 -->[...]

415 APPENDIX E Instructions ■ Standard Branch (Without Delay) Instructions (Notes) • The num ber of cyc les item "2 /1" means 2 cycles for branc h and 1 for no nbranch . • The ass embler calc ulates and sets valu es in the rel1 1 and rel8 fie lds of the har dware specif ications as follows: (lab el12-PC-2)/2 -> rel11, (label9-P C[...]

416 APPEND IX E I nstruc tions ■ Delayed-Branch Instructions (Notes) • The ass embler calc ulates and sets valu es in the rel1 1 and rel8 fie lds of the har dware specif ication as follows: (labe l12-PC-2)/2 -> rel11, (label9 -PC-2)/2 -> r el8: Labe l12 and la bel9 are signed. • The next i nstructio n (delay slot) is ex ecuted be fore d[...]

417 APPENDIX E Instructions ■ Other Instructions T able E.1-13 Other Instruct ions Mnemonic T ype O P CYCLE N ZVC Operation Rem arks NOP E 9F-A 1 ---- Remains unchange d. ANDCCR#u8 ORCCR #u8 D D 83 93 c c CCCC CCCC CCR and u8 --> CCR CCR or u8 --> CCR STILM #u8 D 87 1 ---- i8 --> ILM ILM immedi ate value set ting ADDSP #s10*1 D A3 1 ----[...]

418 APPEND IX E I nstruc tions (Notes) • LDM0 (regl ist) and L DM1 (reglist) have a*(n- 1) +b+1 execution c ycles when th e specifi ed number of register s is n. • STM0 (reglist) a nd STM1 ( reglist) have a* n+1 execut ion cycle s when th e specifie d numb er of regis ters is n. ■ 20-Bit Sta ndar d Branch Macro Instructions T able E.1-14 20-B[...]

419 APPENDIX E Instructions ■ 20-Bit Del a yed-Branch Macro Instructions 2) When label20- PC-2 is o utside of the range in 1) and include s an exte rnal referen ce symb o l, an ins truc tion is cr eat ed as foll ows: Bxc c false xcc is the excl usion cond ition of c c. LDI:20 # label20,R i JMP @Ri false: T able E.1-15 20-Bit Delayed-Branch Macro [...]

420 APPEND IX E I nstruc tions ■ 32-Bit Sta ndar d Branch Macro Instructions 2) When label20- PC-2 is o utside of the range in 1) and include s an exter nal referen ce symbo l, an instr u ct ion i s crea ted a s follows: Bxc c false xcc : Counter conditio n of cc LDI:20 # label20,R i JMP:D @Ri false: T able E.1-16 32-Bit Standard Branch Macro Ins[...]

421 APPENDIX E Instructions ■ 32-Bit Del a yed-Branch Macro Instructions 2) When label32- PC-2 is o utside of the range in 1) and include s an exte rnal referen ce symb o l, an ins truc tion is cr eat ed as foll ows: Bxc c false xcc is the exc lusion co ndition o f cc. LDI:32 # label32,R i JMP @R i false: T able E.1-17 32-Bit Delayed-Branch Macro[...]

422 APPEND IX E I nstruc tions ■ Direct Addressing Instructions *: Plac e an NOP afte r the DMO V instruc tion that s pecifie s R13+ as th e transfe r source. (Note) The asse mbler calc ulates a nd sets val ues in the di r8, dir9, a nd dir10 fields as f ollows: dir8 -> d ir, dir9/2 -> dir, dir 10/4 -> dir d ir 8, dir9, and dir1 0 are uns[...]

423 APPENDIX E Instructions ■ Coprocessor Contr ol Instructions Notes: • {CRi|CRj}:= CR0|CR1|CR2|CR3|CR4|CR5|C R6|CR7|CR8|CR9|CR10|CR11|CR12|CR1 3|CR14|CR15 u4: = Channel specifi cation u8: = Command specifi catio n • As this devic e type does n ot have c oprocess ors, these i nstructio ns canno t be used. T able E.1-20 Coprocessor Control In[...]

424 APPEND IX E I nstruc tions[...]

425 INDEX INDEX The index f ollows on the next page . This is listed i n alphabetic or der .[...]

426 INDEX Index Numerics 0-detecti on ................ ................... ................... ..... 295 16/31-b it immedi ate valu e transfer or immed iate value se tting .......... ............. ................... ..... 413 16/8-bit d ata, data transfe r block for .................... 3 45 16-bit bus wi dth .. ................... ....... 142 , 1[...]

427 INDEX bus co ntrol acquisiti on . .................... ................... . 193 bus co ntrol release . ............. ................... .............. 193 bus co nverter, 32 bits - 16 bits ............... ................ 32 bus co nverter, Harvard-Princ eton .... ................... ... 32 bus in terface .... ............ ...................[...]

428 INDEX descriptor, fi rst word of .......... ............. .................. 3 32 descriptor, s econd word of ........... ................... ..... 334 descriptor, th ird word of ................ ................... ..... 334 detection data registe r 0 (BSD0) .. ...... ....... ...... ..... 2 93 detection data registe r 1 (BSD1) .. ...... ......[...]

429 INDEX extern al trigger or internal tim er to start A /D converter , using ............ ................... .................... ....... 2 80 external wait cycle ti ming chart .............. .............. 172 F FBGA-112, ou tside di mension .. .................... ........... 9 FBGA-112, pi n arrangement ..... .................... ......... 12[...]

430 INDEX interrup t flag set timing for d ata rece ption in mode 1 .................. ............. ................... ..... 261 interrup t flag set timing for d ata rece ption in mode 2 .................. ............. ................... ..... 261 interrup t flag set tim ing for data tranmission in mode 0, 1 or 2 .... ................... ......[...]

431 INDEX power-on, in put of sourc e oscillatio n at ............... ... 27 power-on, pi n condition at ... ................... ................ 27 PPDR regi ster ........ ............. ................... .............. 3 40 priority che ck .... ................... ................... ............. . 231 program (read) ............. ....... .....[...]

432 INDEX standby mode (sto p or sleep s tate), returning fro m ........ ................... ............. ..... 234 standby m ode state t ransition ............ .................... 98 standby m ode, type o f operation i n .... .................... 90 starting multiple PWM time r chann el using 16- bit reload time r ........................ ......[...]

433 INDEX W wait cycle .. ....... ...... ...... ....... ...... ....... ...... ....... ....... 1 59 watchdo g controller blo ck diagra m .. ................... ... 99 watchdo g timer res et delay re gister (W PR), bit function o f .......... .................... ............. ......... 85 watchdo g timer res et delay re gister (W PR), configurati on[...]

434 INDEX[...]

CM7 1 - 1 01 0 6-1E FUJITSU SEMICONDUCTOR • CONTROL LER MANUALl FR30 32- B it M icroc ontrol ler MB91F109 Hardwar e Manual February 2000 the first e d it i on P u b l i s h e d FUJITSU LIMITE D Electronic Devices Edited Tec h n ica l Com m unicati on D e pt.[...]

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FUJITSU SEMICONDUCTOR FR30 32-Bit Microcontroller M B91F109 Hard ware Manual[...]