Fujitsu MB86617A Bedienungsanleitung

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI i IEEE1394 Serial Bus Controller for DTV MB86617A LSI Specification Rev. 1.0 August 16, 2001[...]

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI ii Contents CHAPTER 1 OVERVIEW ................................................................................................................................................................ ............ 1 CHAPTER 2 FEATURES ............................................................................[...]

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI iii 7.3. I NSTRUCTION FETCH R EGISTER ................................................................................................................................ ........................... 31 7.4. INTERRUPT - FACTOR I NDICATE R EGISTER / INTERRUPT - MASK S ETTING R EGISTER ......................[...]

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI iv 7.32. P ING T IME M ONITOR R EGISTER ................................................................................................................................ ........................ 70 7.33. PHY/LINK R EGISTER /A DDRESS S ETTING R EGISTER ...................................................[...]

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI v 9.2. D ESCRIPTION OF E ACH I N STRUCTION ................................................................................................................................ ............... 103 CHAPTER 10 INTERRUPT .........................................................................................[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 1 Chapter 1 Overview This chapter explains the overview of MB86617A. MB86617A is Fujitsu ’ s IEEE1394 serial bus controller based on both IEEE1394 Standard (IEEE Std. 1394 - 1995) and P1394.a Standard Draft (rev.2.0). This MB86617A has three ports for network under the 1394 cable environment, diffe[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 2 Chapter 2 Features This chapter explains the features of MB86617A. > Compliant with IEEE1394 high performance serial bus standard and P1394.a standard draft > Integrates PHY and LINK layers into single - chip > 1394 port number : 3 ports > Transfer Data Rate : S100, S200, S400 > On -[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 3 Chapte r 3 Chip Block This chapter explains the MB86617A block diagram and the function of each block. 3.1. Block Diagram 3.2. Function of Each Block[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 4 3.1. Block Diagram MB86617A block diagram is shown below. < < Normal Operation Mode Fig.3.1.1 Block Diagram - Normal Operation Mode - 1394 Interface (Port 0) TPA0 XTPA0 TPB0 XTPB0 TPBIAS0 1394 Interface (Port 1) TPA1 XTPA1 TPB1 XTPB1 TPBIAS1 1394 Interface (Port 2) TPA2 XTPA2 TPB2 XTPB2 TPBIA[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 5 < < Asynchronous Transmit FIFO Extended Mode Fig.3.1.2 Block Diagram - Asynchronous Transmit FIFO Extended Mode - 1394 Interface (Port 0 ) TPA0 XTPA0 TPB0 XTPB0 TPBIAS0 1394 Interface (Port 1) TPA1 XTPA1 TPB1 XTPB1 TPBIAS1 1394 Interface (Port 2) TPA2 XTPA2 TPB2 XTPB2 TPBIAS2 PHY/ LINK Layer [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 6 < < Asynchronous R eceive FIFO Extended Mode Fig.3.1.3 Block Diagram - Asynchronous Receive FIFO Extended Mode - 1394 Interface (Port 0) TPA0 XTPA0 TPB0 XTPB0 TPBIAS0 1394 Interface (Port 1) TPA1 XTPA1 TPB1 XTPB1 TPBIAS1 1394 Interface (Port 2) TPA2 XTPA2 TPB2 XTPB2 TPBIAS2 PHY/ LINK Layer Co[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 7 3.2. Function of Each Block This section explains the function of each block for MB86617A. < < PHY Layer Contro l Circuit This circuit is for the Physical layer of IEEE 1394 with the following functions . > Asynchronous transfer is supported under cable environment. > Maximum transfer d[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 8 Chapter 4 Pin Assignment This chapter explains the pin assignment and table of pin function of MB86617A. 4.1. Pin Assignment 4.2. Corresponding Table of MB86617A Pin 4.3. Outline Drawing of Package[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 9 4.1. Pin Assignment The following diagram shows the MB86617A pin assignment. 88 85 80 75 70 65 60 55 50 45 VSS VDD PMODE LINKON PWR3 PWR2 PWR1 VDD VSS AVSS AVDD TPBIAS0 TPA0 XTPA0 TPB0 XTPB0 AVDD AVSS AVSS AVDD TPBIAS1 TPA1 XTPA1 TPB1 XTPB1 AVDD AVSS AVSS AVDD TPBIAS2 TPA2 XTPA2 TPB2 XTPB2 AVDD AVS[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 10 4.2. Corresponding Table of MB86617A Pin The following table shows the corresponding items of MB86617A pin. Pin No. I/O Pin Name Pin No. I/O Pin Name Pin No. I/O Pin Name Pin No. I/O Pin Name 1 I XRE SET 45 - AVSS 89 133 O SELTSPA 2 I MODE1 46 - AVDD 90 134 I DSSCLKA 3 I MODE0 47 I/O XTPB2 91 135 [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 11 4.3. Outline Drawing of Package This section shows the outline drawing of MB86617A package (LQFP - 176).[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 12 Chapter 5 Pin Function This chapter explains the MB86617A pin function. 5.1. IEE E1394 Interface 5.2. Isochronous (TSP - IC,DV - IC) Interface 5.4. MPU Interface 5.5. Other Pins 5.6. Power/GND Pin[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 13 5.1. IEEE1394 Interface This section explains the pin function of IEEE1394 interface. Signal Name I/O Function TPA 0 I/O I/O pin of TPA + (plus) signal on cable port 0 XTPA0 I/O I/O pin of TPA - (minus) signal on cable port 0 TPB0 I/O I/O pin of TPB + (plus) signal on cable port 0 XTPB0 I/O I/O pi[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 14 5.2. Isochronous Interface This section explains the pin function of Isochronous interface. Signal Name I/O Funct ion TSVALIDA I/O I.O pin for indicating effective data period of TS packet (on port A) ‘ H ’ active signal TSSYNCA I/O Input/Output pin for indicating leading data of TS packet (on[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 15 IERRA O Output pin for noticing error of receive data (on port A) ‘ H ’ active signal IERRB O Output pin for noticing error of rec eive data (on port B) ‘ H ’ active signal DSSCLKA I Clock input pin for DSS data (27MHz) DSSCLKB I Clock input pin for DSS data (27MHz)[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 16 5.4. MPU Interface This section explains the pin function of MPU interface. Signal Name I/O Function A7 – 1 I A ddress input pin for selecting internal register Available only when selecting non - multi mode When selecting multiplex mode, set this signal in fixed ‘ L ’ D15 - 8,0 AD7 – 1 I [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 17 5.5. Other Pins This section explains the pin function like internal PLL. Signal Name I /O Function XRESET I Input signal for resetting signal When operating with cable supply power, set this pin to ‘ L ’ . MODE1 MODE0 I This pin is used for setting operating mode of MPU. This device is operat[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 18 5.6. Power/GND Pin This section explains the power/GND pin. Signal Name I/O Function VDD - 3.3V digital power pin VSS - Digital ground pin AVDD - 3.3V analog power pin AVSS - Analog ground pin[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 19 Chapter 6 Internal Register This chapter explains the MB86617A internal register. Note that the access of internal register is applied only 16 bits access. WRITE READ Address (HEX) Register Name Register Name 00 mode - con trol mode - control 02 (reserved) flag & status 04 Instruction - fetch [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 20 WRITE READ Address (HEX) Register Name Register Name 20 transmit DSS packet header setting [A] (upper) receive DSS packet header setting [A] (upper) 22 transmit DSS packet header setting [A] (medium) receive DSS packet header setting [A] (medium) 24 transmit DSS packet header setting [A] (lower) r[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 21 WRITE READ Add ress (HEX) Register Name Register Name 50 (reserved) data bridge transmit/receive status [B] 52 (reserved) Isochronous channel monitor 1 54 (reserved) I sochronous channel monitor 2 56 (reserved) Isochronous channel monitor 3 58 (reserved) Isochronous channel monitor 4 5A (reserved)[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 22 WRITE READ Address (HEX) Register Name Register Name 80 (res erved) transmit CGMS/TSCH indicate [A] 82 (reserved) transmit CGMS/TSCH indicate [B] 84 transmit CGMS/TSCH indicate status transmit CGMS/TSCH indicate status 86 transmit EMI/OE setting transmit EMI/OE setting 88 (reserved) (reserved) 8 A[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 23 WRITE READ Address (HEX) Regi ster Name Register Name B 0 (reserved) (reserved) B 2 (reserved) (reserved) B 4 (reserved) (reserved) B 6 (reserved) (reserved) B 8 (reserved) (reserved) BA (reserved) (reserved) BC (reserved) (reserved) BE (reserved) (reserved) C 0 (reserved) (reserved ) C 2 (reserve[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 24 WRITE READ Address (HEX) Register Name Register Name E 0 (reserved) (reserved) E 2 (reserved) (reserved) E 4 (res erved) (reserved) E 6 (reserved) (reserved) E 8 (reserved) (reserved) EA (reserved) (reserved) EC (reserved) (reserved) EE (reserved) (reserved) F 0 (reserved) (reserved) F 2 (reserved[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 25 Chapter 7 Internal Register Function Description This chapter explains the details of the internal register of MB86617A. 7.1. mode - control Register 7.2. flag & status Register 7.3. instruction fetch Register 7.4. interrupt - factor Indicate Register/interrupt - mask Setting Register 7.5. Rec[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 26 7.25. Receive Isochronous Packet Header Indicate Register 3 [B] 7.26. Receive Isochronous Packet Header Indicate Register 4 [B] 7.27. FIFO Reset Setting Register 7.28. Data Bridge Transmit/Receive Status Register [A] 7.29. Data Bridge Transmit/Receive Status Register [B] 7.30. Isochronous channel [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 27 7.1. M ode - control Register Mode - control register is the register that performs the relative setting of various operation mode of this LSI . AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00h R/W - - - - CPS soft reset clk off s -[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 28 BIT Bit Name Action value Function 0 Uses 2K byte FIFO on LINK I/F side of bridge for Isochronous transmit/receive. 3 Asyn - FIFO sel Read/ Writ e 1 Uses 2K byte FIFO on LINK I/F side of bridge for Asynchronous transmit/receive. 0 Uses 2K byte FIFO for Asynchronous transmit with Asyn - FIFO se l ([...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 29 7.2. f lag & s tatus Register flag & status register indicates the status of this LSI and data access inquiries. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 02h R IPC b usy tran r eady t ran b usy ISO cycle A - Tx - buff em[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 30 BIT Bit Name Action Value Function 0 Indicates that the device is not in forced sleep. 4 sleep Read 1 Indicates that the device is in forced sleep by accepting “ Start sleep ” (01h) instruction. 0 Indicates that no data is stored in ASYNC receive specific buffer. 3 data req Read 1 Indicates th[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 31 7.3. i nstruction - fetch Register instruction - fetch register is the register that wri tes in instructions for this LSI, and consists of the instruction code and operand. Refer to “ Chapter 9 Instruction ” for each instruction code and operand code. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 1[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 32 7.4. i nterrupt - facto r Indicate Register/i nterrupt - mask Setting Register interrupt - factor indicate register is the register that indicates interrupt reported by this LSI. Refer to “ Chapter 10 Interrupt ” for measure against and details of each Bit and interrupt factor. interru pt - ma[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 33 7.5. Receive Acknowledge Indicate Register Rece ive Acknowledge indicate register is the register that indicates received Acknowledge packet addressed to itself. Read out this register after interrupt report of “ Asynchronous packet send ” . AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 B[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 34 7.6. A - buffer Data Port Receive/Transmit This integrated register is the buffer access port for both ASYNC receive speci fic buffer and ASYNC transmit specific one. Read data is able to be read out IEEE1394 packet data in the order received. (MSB: 1 ST read) Write data is transmitted as IEEE1394[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 35 7.7. TSP Transmit Informa tion Setting Register [A] TSP transmit information setting register [A] is the register that makes settings for transmit packet processed by bridge - Ach. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 10h R/[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 36 BIT Bit Name Action Value Function 0 Selects CGMS information input from TSP - IC as EMI information to be output to CP - IC. 4 EMI select - A Read/ Write 1 Selects setting value of set EMI - A (bit3 to 2) as EMI information to be ou tput to CP - IC. 3 - 2 set EMI - A Read/ Write - Set EMI informa[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 37 7.8. TSP Transmit Information Setting Register [B] TSP transmit information setting register [B] is the register that makes settings for transmit packet processed by bri dge - Bch. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 12h R/[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 38 BIT Bit Name Action Value Function 0 Selects CGMS information input from TSP - IC as EM I information to be output to CP - IC. 4 EMI select - B Read/ Write 1 Selects setting value of set EMI - A (bit3 to 2) as EMI information to be output to CP - IC. 3 - 2 set EMI - B Read/ Write - Set EMI informa[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 39 7.9. Transmit Offset Setting Register [A] Transmit offset sett ing register [A] is the register that sets offset value added to cycle - time - monitor value. Its aim is to generate source packet header (Time - stamp) added to transmit packet processed by bridge - Ach. (Max. 32 ms) Time - stamp val[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 40 7.10. Transmit Offset Setting Register [B] Transmit off set setting register [B] is the register that sets offset value added to cycle - time - monitor value Its aim is to generate source packet header (Time - stamp) added to transmit packet processed by bridge - Bch. (Max. 32 ms) Time - stamp val[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 41 7.11. TSP Receive Information Setting Register TS P receive information setting register performs the setting for outputting received packet to TSP - IC AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1C h R/ W TV2B TV1B - - output DSS[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 42 BIT Bit Name Action Value Function 0 Deletes received data and reports FMT error when MPEG2 - TS data is received. ISO packet header and CIP header are indicated in register. 8 TS - EN Read/ Write 1 Allows receivi ng MPEG2 - TS data. 0 Does not output the packet received by bridge - Ach to port B [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 43 Register setting va lue and selection of output port are shown in the table below. Bit 15 Bit 14 Bit 7 Bit 6 Bit 1 Bit 0 Receive Status TV2B TV1B TV2A TV1A CMP SEL TS CMP TSP - IC I/F Port A TSP - IC I/F Port B 0 0 0 1 0 0 Processing - Ach Receive data - 0 0 1 0 0 0 - Processing - Ach Receive data[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 44 7.12. Receive DSS Packet Header Indicate Register [A]/Transmit DSS Packet Header Setting Register [A] Receive DSS packet header indi cate register [A] indicates DSS packet header range of DSS packet received by bridge - Ach. Transmit DSS packet header setting register [A] sets DSS packet header ra[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 45 7.13. Receive DSS Packet Header Indicate Register [B]/Transmit DSS Packet Header Setting Register [B] Receiv e DSS packet header indicate register [B] indicates DSS packet header range of DSS packet received by bridge - Bch. Transmit DSS packet header setting register [B] sets DSS packet header ra[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 46 7.14. TSP Status Register TSP status register indicates status of TSP - IC I/F. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 32h R CG chg - B TS chg - B no 47h - B TSP FIFOf ull - B TSP FIFO emp - B Tx - len gth - err - B - - CG chg[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 47 BIT Bit Name Active Value Function 9~8 reserved Read - Always indicate ‘ 0 ’ . 0 Indicates that CGMS information input from port A of TSP IC I/F is not changed. 7 CG chg - A Read 1 Indicates that CGMS information input from port A of TSP IC I/F is changed. Clears to ‘ 0 ’ by lead of this r[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 48 7.15. Data Bridge Transmit Information Setting Register 1 [A] Data bridge transmit information setting register 1 [A] is the register th at sets CIP header range added to transmit packet processed by bridge - Ach. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 49 7.16. Data Bridge Transmit Information Setting Register 2 [A] Data bridge transmit information setting register 2 [A] is the register that sets CIP header range, transmit channel, and speed added to transmit packet processed by bridge - Ach. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 50 7.17. Data Bridge Transmit Information Setting Register 3 [B] Data bridge transmit information setting register 3 [B] is the register that sets CIP header range added to transmit packet processed by bridge - Bch. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 51 7.18. Data Bridge Transmit Information Setting Register 4 [B] Data bridge transmit information setting register 4 [B] is the register that sets CIP header range, transmit channel and speed a dded to transmit packet processed by bridge - Bch. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 52 7.19. Data Bridge Receive Information Setting Register Data bridge receive information register performs the setting of receive packet. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3C h R/  Rx start - B Rx end - B Rx channel - B [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 53 7.20. Transmit Packet Link/Split Setting Register Transmit packet link/split setting register is the register that sets number of link and split of source packets to be transmitted. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3E h [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 54 BIT Bit Name Action Value Function 0 Executes 2SP combined transmission as FIFO NFULL operation when setting of 2SP separated transmission or combined transmission for less than 2SP. With more than 3 SP, executes according to setting. 5 NF5SPA Read/ Write 1 Executes 5 SP combined transmission at F[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 55 7.21. Late Packet Decision Range Setting Register [A] Late packet decision range setting register [A] is the register that sets Late decision range of source packet to be transmitted by bridge - Ach. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 56 7.22. Late Packet Decision Range Setting Register [B] Late packet decision range setting register [B] is the register that sets Late decision range of source packet to be transmitted by bridge - Bch. AD R / W Bit 15 Bit 14 Bit 13 Bit 1 2 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 57 7.23. Receiv e Isochronous Packet Header Indicate Register 1 [A] Receive Isochronous packet header indicate register 1 [A] is the register that indicates Isochronous packet header information received by bridge - Ach. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 B it 9 Bit 8 Bit 7 Bit 6 Bit [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 58 7.24. Receive Isochronous Packet Header Indicate Register 2 [A] Receive Isochronous packet header indicate register 2 [A] is the register that indicates Isochronous packet CIP header information received by bridge - Ach. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bi[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 59 7.25. Receive Isochronous Packet Header Indicate Register 3 [B] Receive Isochronous packet header indicate register 3 [B] is the register that indicates Isochronous packet header information received by bridge - Bch. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 60 7.26. Receive Iso chronous Packet Header Indicate Register 4 [B] Receive Isochronous packet header indicate register 4 [B] is the register that indicates Isochronous packet CIP header information received by bridge - Bch. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bi t 9 Bit 8 Bit 7 Bit 6 [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 61 7.27. FIFO Reset Setting Register FIFO reset setting register sets force reset of bridge and each FIFO. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 4C h R/W reset - B resetT SP FIFO - B reset BRG FIFO - B - - - - - reset - A reset [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 62 7.28. Data Bridge Transmit/Receive Status Register [A] Data bridge transmit/receive status register ind icates status of packet to be transmitted/received by bridge - Ach. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 4E h R Tx busy [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 63 BIT Bit Name Acti on Value Function 0 Indicates that the data length of received packet is same as specified data length in format. 10 Rx dlen - err - A Read 1 Indicates that the data length of received packet differs to the specified data length in the format. Clears to ‘ 0 ’ by lead of this [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 64 BIT Bit Name Action Value Function 0 Indicates that CIP header of received Isochronous packet is normal. 1 Rx CIP err - A Read 1 Indicates that CIP header of received Isochronous packet has an error. Clears to ‘ 0 ’ by lead of this register. 0 Indicates that FMT range of CIP header of received[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 65 7.29. Data Bridge Transmit/Receive Statu s Register [B] Data bridge transmit/receive status register [B] indicates status of packet transmitted/received by bridge - Bch. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 50h R Tx busy - B[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 66 BIT Bit Name Action Value Function 0 Indicates that data length of receive packet is same as specified data length in format. 10 Rx dlen - err - B Read 1 Indicates that data length of receive packet differs to the s pecified data length in the format. Clears to ‘ 0 ’ by lead of this register. [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 67 BIT Bit Name Action Value Function 0 Indicates that CIP header of received Isochronous packet is normal. 1 Rx CIP err - B Read 1 Indicates that CIP header of received Isochronous packet has an error. Clea red to ‘ 0 ’ by lead of this register. 0 Indicates that FMT range of CIP header of receiv[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 68 7.30. Isochronous Channel Monitor Register Isochronous channel monitor register is the register that indicates Isochronous packet channel flowing through 1394 bus. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 52 h R Isochronous chan[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 69 7.31. C ycle - timer - monitor Indicate Register Cycle - timer - monitor indicate register indicates value of integrated cycle - timer register. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5A h R cycle - timer - monitor ( hi ) 5C h[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 70 7.32. Ping Time Monitor Register Ping time monitor register is the register that indicates time period of transmitting request packet to receiving response packet to the request. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5E h R P[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 71 7.33. PHY / LINK Register/Address Setting Register PHY/LINK register/address setting register is the register that sets address in order to access PHY/LINK register indirectly. PHY/LINK register indicated with address set by this register can be accesse d from PHY/LINK register/access port. AD R /[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 72 7.34. PHY / LINK Register Access Port PHY/LINK register access port is the port to access PHY/LINK register indirectly. PHY/LINK register indicated with address set by PHY/LINK register/address setting register can be accessed from this port. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 73 7.35. Revision Indicate Register Revision indicate register is the reg ister that indicates chip revision of this LSI. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 64h  Revision code (hi) 66 h R Revision code (lo) Initial Value F[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 74 7.36. Transmit CGMS/TSCH Indicate Register [A] Transmit CGMS/TSCH indi cate register [A] indicates CGMS information and identification of TS type for source packet input from port A at TSP IC I/F. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 75 7.37. Transmit CGMS/TSCH Indicate Register [B] Transmit CGMS/TSCH indicate register [B] indicates CGMS information a nd identification of TS type for source packet input from port B at TSP IC I/F. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 76 7.38. Transmit CGMS/TSCH Indicate Status Register Transmit CGMS/TSCH indicate status register indicates validity of source packet input from TSP IC I/F. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 84 h R / W - - - - - act - TSC HB [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 77 BIT Bit N ame Action Value Function 0 Indicates that the packet indicated in CGMSA - 1 and TSCHA - 1 (80h - bit7 to 0) was finally input from port A at TSP IC I/F. Read 1 Indicates that the packet indicated in CGMSA - 2 and TSCHA - 2 (80h - bit15 to 8) was fina lly input from port A at TSP IC I/F.[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 78 7.39. Transmit EMI/OE Setting Register Transmit EMI/OE setting register sets EMI information and Odd/Even value added to empty packet until valid data is transmitted. AD R / W Bit 15 Bit 14 Bit 13 Bit 12 Bi t 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 86 h R / W IPH sele[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 79 BIT Bit Name Action Value Function 6 - 5 IPH EMI - A Read/ Write - Set EMI information which are set in IPH of empty packet transmitted from bridge - Ach. Valid only when IPH select - A (bit7) is set to ‘ 1 ’ . (MSB: bit 6 , LSB: bit 5 ) EMI information after transmitting valid data depends on[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 80 Chapter 8 PHY / INK Register Function Description This chapter explains the Physical Register and Link register that enables to access from PHY/LINK register access p ort (address 62h) by setting PHYT/LINK register address setting register (address 60h) in detail. 8.1. PHY/LINK Register Table 8.2.[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 81 8.1. PHY / LINK Register Table Table of Physical Register and Link Register is shown below. P HY/LINK addr Write Read 00 h (reserved) Physical register #0 0 02 h Physical register # 01 ← 04 h (reserved) Physical register # 02 06 h (reserved) Physical register # 03 08 h Physical register # 04 ←[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 82 P HY/LINK addr Write Read 2Ch Physical register #17 ← 2Eh Physical register #18 ← 30h Physical register #19 ← 32h Physical register #1A ← 34h Physical register #1B ← 36h Physical register #1C ← 38h Physical register #1D ← 3Ah Ph ysical register #1E ← 3Ch Link register #00 ← 3Eh L[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 83 8.2. Physical register #0 0 (read) Physical Register#00 is the register that indicates Physical ID, root status, and cable power st atus of this node. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 h R - - - - - - - -[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 84 8.3. Physical register # 01 (read/write) Physical Register#01 is the register that set s /indicate s force - root and gap - count. Do not write into this register except for the case that the node is Bus manager or Isochronous resource manager in the envi ronment with no Bus manager . phy/ link - [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 85 8.4. Physical register # 02 (read) Physical Register#02 is the register that indicates if the extended PHY register map is in existence or not, and the number of ports (3 port). phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 86 8.5. Physical register # 03 (read) Physical Register#03 is the register that indicates max. transfer speed (S400) of this node. phy/ link - addr R / W Bit 15 Bit 14 Bit 1 3 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 06 h R - - - - - - - - Max _speed - Delay Fi[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 87 8.6. Physical register # 04 (read/write) Physical Register#04 is the register that sets the parameter of Self - ID packet to be transmitted b y this node. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R Jitter 08 h W - [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 88 8.7. Physical register # 05 (read/write) Physical Register#05 is the register indicating availability of cable supply power standard and timeout detect of arbit ration state machine. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 89 BIT Bit Name Action Value Function 0 Indicates that port event and resume processing have not occurred . Read 1 Indicates that Connected, Bia s, Disabled, Fault bit has changed when Int_enable bit is set at ‘ 1 ’ . Indicates that resume processing was performed when Resume_Int bit is set at ?[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 90 8.8. Physical register # 07, 08, 09 (rea d) Physical Register#07, 08, 09 are the registers that indicate signal condition of IEEE1394 port and cable connection condition. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0C[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 91 8.9. Physical register # 0A, 0B, 0C (read/write) Physical Register#0A, 0B, 0C are the registe rs that indicate bias detect condition of IEEE1394 installed in this node and performs setting of enable/disable of IEEE1394 port. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bi[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 92 8.10. Physical register # 0D, 0E, 0F (read/write) Physical Register#0D, 0E, 0F are the registers that indicate maximum transfer speed of the node connected to IEEE1394 port installed in this node. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 93 8.11. Physical register # 10 (read) Physical Register#10 is the register that indicates C ompliance_level of this node. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1E h R - - - - - - - - Compliance_level Fixed value ?[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 94 8.12. Physica l register # 11, 12, 13 (read) Physical Register#11, 12, 13 are the registers that indicate Vendor_ID of this node. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 20 h R - - - - - - - - Vendor_ID - hi Fixed[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 95 8.13. Physical register # 14, 15, 16 (read) Physical Register#14, 15, 16 are the registers that indicate Product_ID of this node. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 26 h R - - - - - - - - Product_ID - hi Fixe[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 96 8.14. Physical register # 17, 18, 19, 1A, 1B, 1C, 1D, 1E (read /write ) Physical Register#17, 18, 19, 1A, 1B, 1C, 1D, 1E are in the range of 8 bit X 8 Free_RAM. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2C h R / [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 97 8.15. Link register #00 (read/write) Link Register#00 is the register that sets this node to operate as cycle master. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3C h R / W - - - - - - - - - - cycle master - - - - - I[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 98 8.16. Link register #01 (read/write) Link Register#00 is the register that sets this node to perform as cycle master. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3E h R / W - - - - - - - - - - cycle master - - - - - I[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 99 8.17. Link register #0 2 (read/write) Link Register#02 is the register that sets transfer mode of acknowledge packet transmitted by this node and disable setting of Link layer. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bi[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 100 8.18. Link register # 03 (read/write) Link Register#03 is the regis ter that performs Link layer reset and initializes setting of the node. phy/ link - addr R / W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 42 h R / W - - - - - - - - - - -[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 101 Chapter 9 Instruction This chapter explains the instruction codes and details for respective instructions. 9.1. Instruction Code Table 9.2. Description of Each Instruction[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 102 9.1. Instruction Code Table Instruction name c ode Operand Start sleep 01 Remove sleep 02 Asynchronous receive 03 Remove busy mode 04 Send PHY packet 21 Asynchronous Send 31 Speed co de Data - FIFO init 63 FIFO select code DMA Transmit (Asynchronous ) 71 DMA Transmit (PHY packet) 72 D MA Receive [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 103 9.2. Description of Each Instruction < < Start sleep (01 h) This instruction changes this device into forced sleep, stops the driver/r eceiver function of 1394 port, and then changed into the status with this device ’ s cable cut. Also, it stops the clock to be input from integrated PLL t[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 104 < < Asynchronous Send ( 3 1 h) This instruction transmits the data stored at the ASYNC transmit specific buffer. This instruction performs the following serial actions, from access to arbitration by detecting arb - reset - gap, generation and transfer of packet, to receipt of Acknowledge pa[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 105 < < DMA Transmit (Asynchronous) ( 71 h) This instruction writes in the transmit Asynchronous packet to ASYNC transmit specific buffer using DMA transmit. Assert DREQ signal after issuing this instruction. Determine the transmit bite value by transmit data length within packet header, write [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 106 Chapter 10 Interrupt This chapter explains the inturrput - factors and method for interrupt - mask. 10.1. Interrupt - factor Indicator Register & interrupt - mask Setting Register 10.2. Interrupt 10.3. Description of Interrupt[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 107 10.1. Interrupt - factor Indicator Register & interrupt - mask Setting Register AD R /  Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R I NT 1 INT 2 INT 3 INT 4 INT 5 INT 6 INT 7 INT 8 INT 9 INT 10 INT 11 INT 12 INT 13 INT 14 INT 15 I[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 108 10.2. Interrupt Interrupt Interrupt Item INT1 Loop detected INT2 Self - ID packet error INT3 Bus reset complete INT4 Bus reset detected INT5 Isochronous packet receive error (A - ch) INT6 Isochronous packet receive error (B - ch) INT7 Isochronous cycle too long INT8 Bus occupancy violation INT9 A[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 109 10.3. Description of Interrupt Each interrupt items are described below. Interrupt Interrupt Item Description INT1 Loop detected Topology is in Loop. > Need to issue “ Bus reset ” . Occurred convention failure like Physical - ID did not count up each Self - ID packet received during Self I[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 110 Interrupt Interrupt Item Description INT7 Isochronous cycle too long Isochronous cycle exceeded specified time. >Informs only if this node is Cycle master. INT8 Bus occupancy violation Node occupied longer time than MAX_DATA_TIME. >Need to issue “ Bus reset ” . INT9 Asynchronous packet [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 111 Interrupt Interrupt Item Description INT23 Cycle start packet received Received cycle start packet normal ly when self node is not root > Isochronous cycle starts. Set ISO cycle Bit (Bit12) of flag & status register (address 02h) at ‘ 1 ’ simaltaneously with this interrupt report. INT2[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 1 12 Chapter 11 Operation This chapter explains the operation of this device and displays the examples of control f low. 11.1. Initialization 11.2. Self - ID Packet Receiving 11.3. Asynchronous Packet Transmitting 11.4. Asynchronous Packet Receiving 11.5. Isochronous Packet Transmitting 11.6. Isochro[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 113 11.1. Initialization The example of control flow from the system power on to the packet transmitting/receiving possible state is shown below. In this examle, the device is not operated with cable power supply before turning on the power of system. <H ost> <Device> Figure 11.1 Example [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 114 11.2. Self - ID Packet Receiving The example of control flow for receiving Self - ID packet is shown below. 11.2.1 Self - ID Packet Receive during Bus Reset Process 11.2.2 Self - ID Packet Receive after Ping Packet Transmitting[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 115 11.2.1 Self - ID Packet Receive at Bus Reset Process This section explains the receiving process of Self - ID packet. The MB8 6617A device is capable of receiving self - ID packets that each mode transmit in the self - identity stage of bus reset process. When ‘ 1 ’ is written to the s - ID s[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 116 < < Flow chart before bus reset completion <Host> <Device> Figure 11.2.1.1 Flow example for Self - ID packet receiving before bus reset completion Start bus reset.  - ID store END ‘ 0 ’ Report Bus reset detected (INT4) interrupt. (assert XINT) (Assert XINT). Read Bus rese[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 117 < < Flow chart after bus reset completion <Host> <Device> Figure 11.2.1.2 Flow example for Self - ID packet receiving after bus reset completed Note1: When Asyn - FIFO sel (mode - control register[3]) is 1 and send/rec (mode - control register [2]) is 1, Asynchronous receive FIF[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 118 11.2.2 Self - ID Packet Receive after Transmitting Ping Packet Ping Regardless of s - ID store bit setting in the mode - cont rol register (refer to 7.1), the device receives self - ID packet after a ping packet transmitted and stores the data removing logical inverse section in the Asynchronous [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 119 < < Flow chart after r eceiving Self - ID packet <Host> <Device> Figure 11.2.2.2 Flow example after receiving Self - ID packet. START Issue Asynchronous receive (03h) instruction. Read the data of one word from receive Asynchronous data port. Read flag & status register. END[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 120 11.3. Asynchronous Packet Transmitting The example of control flow for transmitting of Asynchronous packet is shown below. < < Flow chart before storing transmitting data into Asynchronous transmit FIFO <Host> <Device> Figure 11.3.1 Flow chart before storing transmitti ng data i[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 121 < < Flow chart after storing transmitting data into Asynchronous transmit FIFO <Host> <Device> Figure 11.3.2 Flow chart after storing transmitting data in Asynchronous transmit FIFO START Issue Asynchronous transmit (31h) instruction. Receive Asynchronous transmit (31h) instruct[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 122 11.4. Asynchronous Packet Receiving The example of control flow for receiving Asynchronous packet is shown below.[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 123 < < Flow chart for received data before storing in Asynchronous receive FIFO <Host> <Device> Figure 11.4.1 Flow example for received data before storing in Asynchronous receive FIFO Receive packet to self - node. Report Header CRC Error(INT14) interrupt and duscard received pack[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 124 < < F low chart for received data after storing in Asynchronous receive FIFO <Host> <Device> Figure 11.4.2 Flow chart for received data after storing in Asynchronous receive FIFO Note1: If the length of received data is below quadret digid, it is stored by quadret unit????. Note[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 125 11.5. Isochronous Packet Transmitting The example of control flow for transmitting Isochronous packet is shown below.[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 126 <Ho st> <Device> Figure 11.5 Flow example for transmitting Isochronous packet END Set value to registers such as Bridge and TSPIF. Set necessary data to registers such as Bridg and TSPIF(Note). Transmit Late evaluation Report Transmit late occurred (INT32) interrupt(assert XINT). Read[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 127 (Note)Register and bit necessary for transmi tting are as follows. Data Address MPEG - TS DSS 00h TSPSB=0, CPSB=0 14h,16h Set value of transmit Offset(Ach). 18h,1Ah Set value of transmit Offset (Bch) 34h DBSA=06h, FNA=3h DBSA=09h, FNA=2h 36h TXFMTA=20h, TXCHA(Iso channel No.) TXFMTA=21h, TXCHA( I[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 128 11.6. Isochronous Packet Receiving The example of control flow for receivi ng Isochronous packet is shown below. <Host> <Device> Figure 11.6 Flow example for transmitting Isochronous packet END Set value to registers such as Bridge and TSPIF(Note). Set necessary data to registers such[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 129 (Note)Register and bit necessary for receiving are as follows. Data Address MPEG - TS DSS DV 00h TSPSB=0, CPSB=0 1Ch TSEN=1, Set TV1A,TV1B,TV2A,TV2B according to Ch received and port. DSSEN=1, Set TV1A,TV1B,TV2A,TV2B according to Ch received and port. DVEN=1, Set TV1A,TV1B,TV 2A,TV2B according to[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 130 Chapter 12 System Con figuration This chapter explains the system configuration of this chip. 12.1. Recommended Connection for 1934 Port (for one port) 12.2. Recommended Connection for Cable Power Supply 12.3. Recommended Connection for Build - in PLL L oop Filter 12.4. Configuration of Feedback [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 131 12.1. Recommended Connection for 1934 Port (for one port) The example of recommended connection of 1934 port terminal for one port is shown below. Figure 12.1 Recomme nded connection for 1934 port (for one port) For unused 1394 port, TPBIAS should be open and TPA, XTPA, TPB and XTPB should be be [...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 132 12.2 Recommended Connection for Cable Power Supply The example of recommended connection of cable power supply for 1394 cable is shown below. Figure 12.2 Recommended connection for cable power supply 510K Ω ± 5% 91 K Ω ± 5% CPS Cable Power (max 33V) 2.2uF[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 133 12.3. Recommended Connection for Build - in PLL Loop Filter The example of recommended connection for build - in PLL loop filter is s hown below. FIL RF Figure 12.3 Recommended connection for build - in PLL loop filter 390 Ω ± 5% 3300pF ± 5% 5.1K Ω ± 5%[...]

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 134 12.4. Configuration of Feedback Circuit at Crystal Oscillator The example of configuration of feedback circuit at crystal oscillator is show n below. No outside resistance is needed because the feedback resistance is built - in.??? Figure 12.4 Configuration of feedback circuit at crystal oscillat[...]