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Intel Core 2 Quad Q6700 Bedienungsanleitung

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Inhaltsverzeichnis der Gebrauchsanleitungen

  • Seite 1

    Document Number: 315592 -005 Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Datasheet —on 65 nm Process in the 775- land LGA Package supporting Intel ® 64 architecture and Intel ® Virtualizati on Technology ± August 2007[...]

  • Seite 2

    2 Datasheet INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH IN TEL PRODUCTS . NO LICENSE, EXPRES S OR IMPLIED , BY EST OPPEL OR OTH ERW IS E , TO AN Y IN T EL LEC T UAL PR OP ERT Y R IG HT S I S G RAN T ED BY TH I S DOCUMENT . EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES N O LIABILITY[...]

  • Seite 3

    Datasheet 3 Contents 1I n t r o d u c t i o n ......... ......... .......... ........... ........ ........... .......... ......... .......... ......... .......... .... 9 1.1 Terminology ........... .......... ......... .......... ........... .......... ........... ........ ........... .......... .. 9 1.1.1 Processor Terminology ........... ........[...]

  • Seite 4

    4 Datasheet 5.2.5 THERMTRIP # Signal ........... ........ ........... .......... ........... .......... ........... ........79 5.3 Platform Environme nt Control Interface (PECI) .... ............ ........... .......... ............. .... 80 5.3.1 Introdu ction ........... ......... .......... ........... ........ ........... .......... ........... [...]

  • Seite 5

    Datasheet 5 Figures 1V CC Static and Transient T olerance ................ ........... .......... ........... .......... ........... ........ 20 2V CC Overshoot Examp le Waveform .............. ........... .......... ........... .......... ........... .......... 21 3 Differential Clock Waveform .......... ........... .......... ........... ........[...]

  • Seite 6

    6 Datasheet Tables 1 References ............... ......... .......... ........... ........ ........... .......... ......... .......... ........... ......11 2 Voltage Identification Definition .... ........... .......... ......... .......... ........... ........ ........... ........15 3 Absolute Maximum and Minim um Ratings ....... ........ .........[...]

  • Seite 7

    Datasheet 7 Revision History § Revision Number Description Date -001 • Initial release November 2006 -002 • Added specificatio ns for the Intel ® Core™2 Quad Processor Q6600 • Updated T able 8, “Signal Char acteristics” . • Updated VTT_SEL description in T able 24. • Updated T able 29, “F an Heatsink P ower and Signal Specificat[...]

  • Seite 8

    8 Datasheet Intel ® Core™2 Extreme Quad-Core Processor QX6000 and Intel ® Core™2 Quad Processor Q6000 Sequence Features The Intel Core™2 Extreme quad-core processor QX6000 sequence and Intel ® Core™2 quad processor Q6000 sequence deliver Intel's adv anced, powerful processors for desktop PCs. The processor is designed to deliver per[...]

  • Seite 9

    Datasheet 9 Introduction 1 Introduction The Intel ® Core™2 Extreme quad-core proce ssor QX6000 sequence and Intel ® Core™2 quad processor Q6000 sequence are the first desktop quad-core processors that combine the performance and power efficiencies of four low-power microarchitecture cores to enable a new level of multi-tasking, multi-media, a[...]

  • Seite 10

    Introduction 10 Datasheet “Front Side Bus” refers to the interface betwee n the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory , and I/O. 1.1.1 Processor Terminology Commonly used terms are expl ained here for clarification: • Intel ® Core™2 Extreme quad -core p[...]

  • Seite 11

    Datasheet 11 Introduction • Enhanced Intel Technology SpeedStep ® Technology — Enhanced Intel T echnology SpeedStep ® T echnology allow s trade-offs to be made betw een performance and power consumptions, based on processor utilization. This may lower aver age power consumption (in conjunction with OS support). • Intel ® Virtualizat ion Te[...]

  • Seite 12

    Introduction 12 Datasheet[...]

  • Seite 13

    Datasheet 13 Electrical Specifications 2 Electrical Specifications This chapter describes the electrical charac teristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VT T and VSS (ground) inputs for on-chip power distribution. All power lands must be [...]

  • Seite 14

    Electrical Specifications 14 Datasheet 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, so me of the high frequency capacitance required for the FSB is included on the processor package. However , additional high frequency capacita nce must be added to the motherboard to properly decouple the return currents[...]

  • Seite 15

    Datasheet 15 Electrical Specifications Table 2. Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 V CC_MAX VID6 VID5 VID4 VID3 VID2 VID1 V CC_MAX 11110 1 0.8500 0 11110 1 . 2 3 7 5 11110 0 0.8625 0 11101 1 . 2 5 0 0 11101 1 0.8750 0 11100 1 . 2 6 2 5 11101 0 0.8875 0 11011 1 . 2 7 5 0 11100 1 0.9000 0 11010 1 . 2 8 7 5 11100 0 0.9125 [...]

  • Seite 16

    Electrical Specifications 16 Datasheet 2.4 Reserved, Unused, and TESTHI Signals All RESERVED lands must re main unconnected. Connection of these lands to V CC , V SS , V TT , or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor [...]

  • Seite 17

    Datasheet 17 Electrical Specifications 2.5 Voltage and Current Specification 2.5.1 Absolute Maximum and Minimum Ratings Ta b l e 3 specifies absolute maximum and mini mum r atings only and lie outside the functional limits of the processor . Within functional operation limits, functionality and long-term reliability can be expected. At conditions o[...]

  • Seite 18

    Electrical Specifications 18 Datasheet 2.5.2 DC Voltage and Current Specification Table 4. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 1, 2 NOTES: 1. Unless other wise noted, all sp ecifications in this table are bas ed on estimates an d simulations or empirical data. These specific ations will be updated with charact[...]

  • Seite 19

    Datasheet 19 Electrical Specifications 8. I CC_MAX specification i s based on the V CC_MAX loadline. Refer to Figur e 1 for details. 9. These Processors have CPUID = 06FBh 10. The maximum instant aneous current the processor wi ll dr aw while the thermal contr ol circuit is active (as indicated by the assertion of PROCHO T#) is the same as the maxi[...]

  • Seite 20

    Electrical Specifications 20 Datasheet NOTES: 1. The loadline s pecificatio n includes both st atic and transient limits e xcept for overshoot allowed as shown in Sectio n 2.5.3 . 2. This loadline s pecificatio n shows the deviation from the VID set point. 3. The loadlines spe cify voltage limits at t he die measured a t the VCC_SENSE and VSS_SENSE[...]

  • Seite 21

    Datasheet 21 Electrical Specifications 2.5.3 V CC Overshoot The processor can tolerate short tr ansient overshoot events where V CC exceeds the VID voltage when transitioning from a high to low current load condition. This ov ershoot cannot exceed VID + V OS_MAX (V OS_MAX is the maximum allowable overshoot v oltage). The time duration of the ov ers[...]

  • Seite 22

    Electrical Specifications 22 Datasheet 2.6 Signaling Specifications Most processor Front Side Bus signals use Gunning T r a nsceiver Logic (GTL+) signaling technology . This technology provides im proved noise margins and reduced ringing through low voltage swings and controlled edge r ates. Platforms implement a termination voltage level for GTL+ [...]

  • Seite 23

    Datasheet 23 Electrical Specifications NOTES: 1. R efer to Section 4.2 for signal descriptions. 2. In processor systems where no debug port is implemented on the system board, the se signals are used to support a debug port in terposer . In systems with the debug port implemented on the system board, these signals are no connec ts. 3. The value of [...]

  • Seite 24

    Electrical Specifications 24 Datasheet 2.6.2 CMOS and Open Drain Signals Legacy input signals such as A20M#, IG NNE#, INIT#, SMI#, an d STPCLK# use CMOS input buffers. All of the CMOS and Open Dr ain signals are required to be asserted/ deasserted for at least four BCLKs for the processor to recognize the proper signal state. See Section 2.6.3 for [...]

  • Seite 25

    Datasheet 25 Electrical Specifications NOTE: 1. V TT supplies the PECI interface. PECI behavior does not affect V TT min/max specificat ions. Refer to Ta b l e 4 for V TT specificat ions. 2. The leakage spec ification applie s to powered devices on the PECI bus. 3. The input buffers us e a Schmitt-triggered input design for impr oved noise immunity[...]

  • Seite 26

    Electrical Specifications 26 Datasheet 2.6.3.1 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integr ated into the processor silicon. See Ta b l e 8 for details on which GTL+ signals do not include on-die termination. V alid high and low levels are determined by the input buffers by comparing w[...]

  • Seite 27

    Datasheet 27 Electrical Specifications 2.7.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Ta b l e 1 6 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor[...]

  • Seite 28

    Electrical Specifications 28 Datasheet 2.7.4 BCLK[1:0] Specifications . Table 17. Front Si de Bus Diffe rential BCLK Specificat ions Symbol Parameter Min Typ Max Unit Figure Notes 1 NOTES: 1. Unless otherwise no ted, all specificat ions in this table apply to all processor frequencies. V L Input Low V oltage -0.30 N/A N/A V 3 2 2. "Steady s ta[...]

  • Seite 29

    Datasheet 29 Electrical Specifications Table 19. FSB Differ ential Cloc k Specifications (1333 MHz FSB) T# Parameter Min Nom Max Unit Figure Notes 1 NOTES: 1. Unless otherwis e noted, all specifi cations in this table apply to all processor cor e frequencies based on a 333 MHz BCLK[1:0]. BCLK[1:0] Frequency 331.635 — 333.364 MHz - 2 2. Duty Cycle[...]

  • Seite 30

    Electrical Specifications 30 Datasheet § § Figure 4. Differential C lock Crosspoint Specification Figure 5. Differential Me asurements 660 670 680 690 700 710 720 730 740 750 760 7 70 780 790 800 810 820 830 840 850 200 250 300 350 400 450 500 550 600 650 VHavg (mV) Crossing Poin t (mV) 550 mV 300 mV 300 + 0. 5 (VHavg - 700) 550 + 0.5 (VHavg - 70[...]

  • Seite 31

    Datasheet 31 Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-L GA6) package that interfaces with the motherboar d via an LG A775 sock et. The package consists of a processor core mounted on a substrate land-carrier . An integrated heat spreader (IHS) is attached to t[...]

  • Seite 32

    Package Mechanical Specifications 32 Datasheet Figure 7. Processor Package Drawing Sh eet 1 of 3[...]

  • Seite 33

    Datasheet 33 Package Mechanical Specifications Figure 8. Processor Package Drawing Sheet 2 of 3[...]

  • Seite 34

    Package Mechanical Specifications 34 Datasheet Figure 9. Processor Package Drawing Sh eet 3 of 3[...]

  • Seite 35

    Datasheet 35 Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep- out zone requirements. A thermal and mechanical solution design must n ot intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside [...]

  • Seite 36

    Package Mechanical Specifications 36 Datasheet 3.5 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide . 3.6 Processor Mass Specificat ion The typical mass of the processor is 2 1.5 g [0.76 [...]

  • Seite 37

    Datasheet 37 Package Mechanical Specifications Figure 11. Processor Top- Side Markings Example for 1333 MHz Processors ATPO S/ N INTEL ©'05 QX6850 INTEL® CORE™2 EXTREME SLxxx [COO] 3.00GHZ/8M/1333/05B [FPO] M e 4[...]

  • Seite 38

    Package Mechanical Specifications 38 Datasheet 3.9 Processor Land Coordinates Figure 12 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . § § Figure 12. Processor Land C oordinates and Quadrants (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 [...]

  • Seite 39

    Datasheet 39 Land Listi ng and Sign al Description s 4 Land Listing and Signal Descriptions This chapter provides the processor la nd assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for th e processor . The land-out footprint is shown in Figure 13 and Figure 14 . These figures represent the[...]

  • Seite 40

    Land Listing and Signal Descriptions 40 Datasheet Figure 13. land-out Diagram ( Top View – Left Si de) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN VCC VCC VSS VSS VCC VCC VSS VS S VCC VCC VSS VCC VCC VSS VSS VCC AM VCC VCC VSS VSS VCC VCC VSS VS S VCC VCC VSS VCC VCC VSS VSS VCC AL VC C VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS V[...]

  • Seite 41

    Datasheet 41 Land Listi ng and Sign al Description s Figure 14. land-out Diagram (Top View – Right Side) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VCC VSS VCC VCC VSS VCC VCC VID_SEL ECT VSS_MB_ REGULA TION VCC_MB_ REGULA TION VSS_ SENSE VCC_ SENSE VSS VSS AN VCC VSS VCC VCC VSS VCC VCC VID7 FC40 VID6 VSS VID2 VID0 VSS AM VCC VSS VCC VCC VSS VCC VCC VSS V[...]

  • Seite 42

    Land Listing and Signal Descriptions 42 Datasheet Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type Direction A3# L5 Source Synch Input/Output A4# P6 Source Synch Input/Output A5# M5 Source S ynch Input/Output A6# L4 Source Synch Input/Output A7# M4 Source S ynch Input/Output A8# R4 Source Synch Input/Output A9# T 5 Source[...]

  • Seite 43

    Land Listi ng and Sign al Description s Datasheet 43 D18# F9 Source Synch Input/Output D19# E9 Source Synch Input/Output D20# D7 Source Synch Input/Output D21# E10 S ource Synch Input/Output D22# D10 Source Synch Input/Output D23# F11 Source Synch Input/Outp ut D24# F12 Source Synch Input/Outp ut D25# D13 Source Synch Input/Output D26# E13 S ource [...]

  • Seite 44

    Land Listing and Signal Descriptions 44 Datasheet FC32 H15 Power/Other FC33 H16 Power/Other FC34 J17 Power/Other FC35 H4 Power/Other FC36 AD3 Power/Other FC37 AB3 Power/Other FC39 AA2 Power/Other FC4 T2 Power/Other FC40 AM6 Power/Other FC8 AK6 Power/Other FERR#/PBE# R3 Asynch CMOS Output GTLREF0 H1 Pow er/Other Input GTLREF1 H2 Pow er/Other Input G[...]

  • Seite 45

    Land Listi ng and Sign al Description s Datasheet 45 TRDY# E3 Common Clock Input TRST# AG1 T AP Input VCC AA8 Power/Other VCC AB8 Power/Other VCC AC23 Power/Other VCC AC24 Power/Other VCC AC25 Power/Other VCC AC26 Power/Other VCC AC27 Power/Other VCC AC28 Power/Other VCC AC29 Power/Other VCC AC30 Power/Other VCC AC8 Power/O ther VCC AD23 Power/Othe[...]

  • Seite 46

    Land Listing and Signal Descriptions 46 Datasheet VCC AJ18 Powe r/Other VCC AJ19 Powe r/Other VCC AJ21 Powe r/Other VCC AJ22 Powe r/Other VCC AJ25 Powe r/Other VCC AJ26 Powe r/Other VCC AJ8 Power/Other VCC AJ9 Power/Other VCC AK11 Powe r/Other VCC AK12 Powe r/Other VCC AK14 Powe r/Other VCC AK15 Powe r/Other VCC AK18 Powe r/Other VCC AK19 Powe r/Ot[...]

  • Seite 47

    Land Listi ng and Sign al Description s Datasheet 47 VCC J28 Power/Other VCC J29 Power/Other VCC J30 Power/Other VCC J8 Power/Oth er VCC J9 Power/Oth er VCC K23 Power/O ther VCC K24 Power/O ther VCC K25 Power/O ther VCC K26 Power/O ther VCC K27 Power/O ther VCC K28 Power/O ther VCC K29 Power/O ther VCC K30 Power/O ther VCC K8 Power/Other VCC L8 Pow[...]

  • Seite 48

    Land Listing and Signal Descriptions 48 Datasheet VID_SELECT AN7 Power/Other Output VID0 AM2 Power/Other Output VID1 AL5 Power/Other Output VID2 AM3 Power/Other Output VID3 AL6 Power/Other Output VID4 AK4 Power/Oth er Output VID5 AL4 Power/Other Output VID6 AM5 Power/Other Output VID7 AM7 Power/Other Ou tput VRDSEL AL3 Pow er/Other VSS A12 Power/Ot[...]

  • Seite 49

    Land Listi ng and Sign al Description s Datasheet 49 VSS AG20 Power/Other VSS AG23 Power/Other VSS AG24 Power/Other VSS AG7 Power/Other VSS AH1 Power/O ther VSS AH 10 Power/Other VSS AH 13 Power/Other VSS AH 16 Power/Other VSS AH 17 Power/Other VSS AH 20 Power/Other VSS AH 23 Power/Other VSS AH 24 Power/Other VSS AH3 Power/O ther VSS AH6 Power/O th[...]

  • Seite 50

    Land Listing and Signal Descriptions 50 Datasheet VSS B20 Power/O ther VSS B24 Power/O ther VSS B5 Power/Othe r VSS B8 Power/Othe r VSS C10 Power/Other VSS C13 Power/Other VSS C16 Power/Other VSS C19 Power/Other VSS C22 Power/Other VSS C24 Power/Other VSS C4 P ower/Othe r VSS C7 P ower/Othe r VSS D12 Power/Other VSS D15 Power/Other VSS D18 Power/Ot[...]

  • Seite 51

    Land Listi ng and Sign al Description s Datasheet 51 VSS N3 Power/Oth er VSS N6 Power/Oth er VSS N7 Power/Oth er VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other VSS P26 Power/Other VSS P27 Power/Other VSS P28 Power/Other VSS P29 Power/Other VSS P30 Power/Other VSS P4 Power/Other VSS P7 Power/Other VSS R 2 Power/Other VSS R23 Power/Othe [...]

  • Seite 52

    Land Listing and Signal Descriptions 52 Datasheet Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction A2 VSS Power/Other A3 RS2# Common Clock I nput A4 D02# Source Synch Input/Output A5 D04# Source Synch Input/Output A6 VSS Power/Other A7 D07# Source Synch Input/Output A8 DBI0# Source Syn ch Input/Output A9 VSS Power/O[...]

  • Seite 53

    Land Listi ng and Sign al Description s Datasheet 53 C20 DBI3# Source Synch Input/Output C21 D58# Source Synch Input/Output C22 VSS Power/Other C23 VCCIOPLL Power/Other C24 VSS Power/Other C25 VTT Power/Other C26 VTT Power/Other C27 VTT Power/Other C28 VTT Power/Other C29 VTT Power/Other C30 VTT Power/Other D1 RESERVED D2 AD S# Common Clock Input/O[...]

  • Seite 54

    Land Listing and Signal Descriptions 54 Datasheet F11 D23# Source Synch Input/Output F12 D24# Source Synch Input/Output F13 VSS Power/Other F14 D28# Source Synch Input/Output F15 D30# Source Synch Input/Output F16 VSS Power/Other F17 D37# Source Synch Input/Output F18 D38# Source Synch Input/Output F19 VSS Power/Other F20 D41# Source Synch Input/Ou[...]

  • Seite 55

    Land Listi ng and Sign al Description s Datasheet 55 H30 BSEL1 Power/Other Output J1 VTT_OUT_LEFT Power/Other Output J2 FC3 Power/Other J3 FC22 Power/Other J4 VSS Power/Other J5 REQ1# Source Synch Input/Outpu t J6 REQ4# Source Synch Input/Outpu t J7 VSS Power/Other J8 VCC Power/Other J9 VCC Power/Other J10 VCC Power/Other J11 VCC Power/Other J12 VC[...]

  • Seite 56

    Land Listing and Signal Descriptions 56 Datasheet M30 VCC Power/Other N1 PWRGOOD Power/Other Input N2 IGNNE# Asynch CMOS Input N3 VSS Power/Oth er N4 RESERVED N5 RESERVED N6 VSS Power/Oth er N7 VSS Power/Oth er N8 VCC Power/Other N23 VCC Power/Other N24 VCC Power/Other N25 VCC Power/Other N26 VCC Power/Other N27 VCC Power/Other N28 VCC Power/Other [...]

  • Seite 57

    Land Listi ng and Sign al Description s Datasheet 57 U28 VCC Power/Other U29 VCC Power/Other U30 VCC Power/Other V1 MSID1 P ower/Other Output V2 RESERVED V3 VSS Power/Other V4 A15# Source Synch Input/Outpu t V5 A14# Source Synch Input/Outpu t V6 VSS Power/Other V7 VSS Power/Other V8 VCC Power/Ot her V23 VSS Power/Ot her V24 VSS Power/Ot her V25 VSS[...]

  • Seite 58

    Land Listing and Signal Descriptions 58 Datasheet AB26 VSS Power/Other AB27 VSS Power/Other AB28 VSS Power/Other AB29 VSS Power/Other AB30 VSS Power/Other AC1 TMS T A P Inp ut AC2 DBR# Power/Other Output AC3 VSS Power/Other AC4 RESERV ED AC5 A25# Source Synch Input/Output AC6 VSS Power/Other AC7 VSS Power/Other AC8 VCC Power/Other AC23 VCC Power/Ot[...]

  • Seite 59

    Land Listi ng and Sign al Description s Datasheet 59 AF12 VCC Power/Ot her AF13 VSS Power/Ot her AF14 VCC Power/Ot her AF15 VCC Power/Ot her AF16 VSS Power/Ot her AF17 VSS Power/Ot her AF18 VCC Power/Ot her AF19 VCC Power/Ot her AF20 VSS Power/Ot her AF21 VCC Power/Ot her AF22 VCC Power/Ot her AF23 VSS Power/Ot her AF24 VSS Power/Ot her AF25 VSS Po[...]

  • Seite 60

    Land Listing and Signal Descriptions 60 Datasheet AH30 VCC Power/Other AJ1 BPM1# Common Clock Input/Output AJ2 BPM0# Common Clock Input/Output AJ3 ITP_CL K1 TAP Input AJ4 VSS Power/O ther AJ5 A 34# Source S ynch Input/Output AJ6 A 35# Source S ynch Input/Output AJ7 VSS Power/O ther AJ8 VCC Power/Other AJ9 VCC Power/Other AJ10 VSS Power/Other AJ11 V[...]

  • Seite 61

    Land Listi ng and Sign al Description s Datasheet 61 AL18 VCC Power/Ot her AL19 VCC Power/Ot her AL20 VSS Power/Ot her AL21 VCC Power/Ot her AL22 VCC Power/Ot her AL23 VSS Power/Ot her AL24 VSS Power/Ot her AL25 VCC Power/Ot her AL26 VCC Power/Ot her AL27 VSS Power/Ot her AL28 VSS Power/Ot her AL29 VCC Power/Ot her AL30 VCC Power/Ot her AM1 VSS Pow[...]

  • Seite 62

    Land Listing and Signal Descriptions 62 Datasheet 4.2 Alphabetical Signals Reference Table 25. Signal Descript ion (Sheet 1 of 9) Name Type Description A[35:3]# Input/ Output A[35:3]# (Address) define a 2 36 -byte physical memory address space. In sub-phase 1 of the address phase, th ese signals transmit the address of a transaction. In sub-phase 2[...]

  • Seite 63

    Datasheet 63 Land Listi ng and Sign al Description s BPM[5:0]# BPMb[3:0]# Input/ Output BPM[5:0]# and BPMb[3:0] # (Break point Monitor) are break point and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for moni toring processor performance. BPM[5:0]# and BPMb[...]

  • Seite 64

    Land Listing and Signal Descriptions 64 Datasheet D[63:0]# Input/ Output D[63:0]# (Data) are the data sign als. These signals provide a 6 4- bit data path between the processor FSB agents , and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY # to indicate a valid data transfer . D[63:0]# are quad-pumped sign[...]

  • Seite 65

    Datasheet 65 Land Listi ng and Sign al Description s DEFER# Input DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order co mple tion. Assertion of DEFER# is normally the responsibility of the addressed me mory or input/ output agent. Thi s signal must connect the approp riate pins/lands of all processor FSB age[...]

  • Seite 66

    Land Listing and Signal Descriptions 66 Datasheet HIT# HITM# Input/ Output Input/ Output HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. An y FSB agent may assert both HIT# and HITM# together to indic ate that it requires a s noop stall, which can be continued by reassertin g HIT# and HITM# together . IERR# Ou [...]

  • Seite 67

    Datasheet 67 Land Listi ng and Sign al Description s LOCK# Input/ Output LOCK# indicates to the syst em that a transaction must occur atomically . This signal must conn ect the appropriate pins/lands of all processor FSB agents. F or a locked sequence of tr ansactions, LOCK# is asserted from the beginnin g of the first transact ion to the end of th[...]

  • Seite 68

    Land Listing and Signal Descriptions 68 Datasheet RS[2:0]# Input RS[2:0]# (R esponse Status) are driv en by the response agent (th e agent responsible for completion o f the current tr ansaction), and must connect th e appr opriate pins/lands of all processor FSB agents. SKTOCC# Output SKTOCC# (Sock et Occupied) will be pulled to ground by the proc[...]

  • Seite 69

    Datasheet 69 Land Listi ng and Sign al Description s THERMTRIP# Output In the even t of a catastrophic c ooling failure, the processo r will automatically sh ut down when the sili con has reached a temperature approximately 20 °C above the ma ximum T C . Assertion of THERMTRIP# (Thermal T rip) indicates the proces sor junction temperature has reac[...]

  • Seite 70

    Land Listing and Signal Descriptions 70 Datasheet § § VRDSEL Input This input should be left as a no connect in order for the processor to boot. The processor will not boot on legacy platforms where this land is connected to V SS . VSS Input VSS are the ground pins for the pr ocessor and should be connected to the system ground plan e. VSSA Input[...]

  • Seite 71

    Datasheet 71 Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temper atures within the operating limits as set forth in Section 5.1 .1 . Any attem pt to operate the processor outside these operating limits ma[...]

  • Seite 72

    Thermal Specifications and Design Considerations 72 Datasheet The case temperature is defined at the geometric top center of the processor . Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the[...]

  • Seite 73

    Datasheet 73 Thermal Specifications and Design Considerations Table 27. Thermal Profile for 130 W Processors Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 42.4 34 48.2 68 54.0 102 59.7 2 42.7 36 48.5 70 54.3 104 60.1 4 43.1 38 48.9 72 54.6 106 60.4 6 43.4 40 49.2 74 55.0 108 60.8 8 43.[...]

  • Seite 74

    Thermal Specifications and Design Considerations 74 Datasheet Table 28. Thermal Profil e for 105 W Processors Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 43.3 28 48.3 56 53.4 84 58.4 2 43.7 30 48.7 58 53.8 86 58.8 4 44.0 32 49.1 60 54.1 88 59.1 6 44.4 34 49.4 62 54.5 90 59.5 8 44.7 3[...]

  • Seite 75

    Datasheet 75 Thermal Specifications and Design Considerations Table 29. Thermal Profile 95 W Processors Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 44.4 28 52.2 56 60.1 84 67.9 2 45.0 30 52.8 58 60.6 86 68.5 4 45.5 32 53.4 60 61.2 88 69.0 6 46.1 34 53.9 62 61.8 90 69.6 8 46.6 36 54.5[...]

  • Seite 76

    Thermal Specifications and Design Considerations 76 Datasheet 5.1.2 Thermal Metrology The maximum and minimum case temper a tures (T C ) for the processor is specified in Ta b l e 2 6 . This temperature specification is meant to help ensure proper oper ation of the processor . Figure 18 illustrates where Intel recommends T C thermal measurements sh[...]

  • Seite 77

    Datasheet 77 Thermal Specifications and Design Considerations under-designed ther mal solution that is not able to prev ent excessive activ ation of the TCC in the anticipated ambient environm ent may cause a noticeable performance loss, and in some cases may result in a T C that exceeds the specified maximum temper ature and may affect the long-te[...]

  • Seite 78

    Thermal Specifications and Design Considerations 78 Datasheet The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 T CC cannot be activ ated via the on demand mode. The Thermal Monitor TCC, how ever , can be[...]

  • Seite 79

    Datasheet 79 Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operat ing temperature. If the Thermal Monitor is enabled (note that the Therm al Monitor must be enabled for the processor to be operating within s[...]

  • Seite 80

    Thermal Specifications and Design Considerations 80 Datasheet 5.3 Platform Environment Control Interface (PECI) 5.3.1 Introduction PECI offers an interface for thermal mo nitoring of Intel processor and chipset components. It uses a single wire; thus, alleviating routing congestion issues. PECI uses CRC checking on the host side to ensure reliable [...]

  • Seite 81

    Datasheet 81 Thermal Specifications and Design Considerations 5.3.2 PECI Specifications 5.3.2.1 PECI Device Address The socket 0 PECI register resides at address 30h and socket 1 resides at 31h. Note that each address also supports two domains (Domain 0 and Domain 1). F or more information on PECI domains, refer to the Platform Environment Control [...]

  • Seite 82

    Thermal Specifications and Design Considerations 82 Datasheet[...]

  • Seite 83

    Datasheet 83 Features 6 Features 6.1 Power-On Configuration Options Several configur ation options can be config ured by hardwa re. The processor samples the hardware configur ation at reset, on the active-to-inactive tr ansition of RESET#. For specifications on these options, refer to Ta b l e 3 1 . The sampled information configures the processor[...]

  • Seite 84

    Feature s 84 Datasheet 6.2.1 Normal State This is the normal operating state for the processor . 6.2.2 HALT and Extended HALT Powerdown States The processor supports the HAL T or Extended HAL T powerdown state. The Extended HAL T Powerdown must be enabled via the BIO S for the processor to remain within its specification. The Extended HAL T state i[...]

  • Seite 85

    Datasheet 85 Features The system can generate a STPCLK# while th e processor is in the HAL T Power Down state. When the system deasserts the ST PCLK# interrupt, the processor will return execution to the HAL T state. While in HAL T Power Down state, the processor will process bus snoops. 6.2.2.2 Extended HALT Powerdown Stat e Extended HAL T is a lo[...]

  • Seite 86

    Feature s 86 Datasheet 6.2.4 Extended HALT Snoo p or HALT Snoop State, Stop Grant Snoop State The Extended HAL T Snoop State is used in conjunction with the new Extended HAL T state. If Extended HAL T state is not en abled in the BIOS, the default Snoop State entered will be the HA L T Snoop State. Refer to the sections below for details on HAL T S[...]

  • Seite 87

    Datasheet 87 Boxed Processor Specifications 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor . Intel boxed processors are intended for system integr ators who build systems from baseboards and standard components. The box ed processor will be supplied with a cooling solution. This chapter documents bas[...]

  • Seite 88

    Boxed Processor Specifications 88 Datasheet 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical spec ifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 22 shows a mechanical representation of the box ed processor. Clear ance[...]

  • Seite 89

    Datasheet 89 Boxed Processor Specifications NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 24. Space Requir ements for the Boxed Processor (Top View) Figure 25. Space Requirements for the Boxed Pr ocessor (Overall View)[...]

  • Seite 90

    Boxed Processor Specifications 90 Datasheet 7.1.2 Boxed Processor Fan Heatsink Weight The boxed pro cessor fan heatsink will not weigh more than 550 grams. Refer to Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2 ) for details on the processor weight and heatsink requirements. 7.1.3 Boxed Processor Retention [...]

  • Seite 91

    Datasheet 91 Boxed Processor Specifications Figure 26. Boxed Processo r Fan Heatsink Power Cable Connector Description Table 32. Fan Heatsink Powe r and Signal Specific ations Description Min Typ Max Unit Notes +12 V : 12 volt fan power supply 11.4 12 12.6 V - IC: - Maximum fan steady-state current dr aw - Av erage fan st eady-stat e current draw -[...]

  • Seite 92

    Boxed Processor Specifications 92 Datasheet 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor . 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cool ed with a fan heatsink. However , meeting the processor's temperature specification[...]

  • Seite 93

    Datasheet 93 Boxed Processor Specifications Figure 28. Boxed Processor Fan Heatsink Airspace Ke epout Requirements (S ide 1 View) Figure 29. Boxed Processor Fan Heatsink Airspace Ke epout Requirements (S ide 2 View)[...]

  • Seite 94

    Boxed Processor Specifications 94 Datasheet 7.3.2 Fan Speed Control Operation (Intel ® Core™2 Extreme processors on ly) The box ed processor fan heatsink is designed to operate continuously at full speed to allow maximum user control ov er fan speed. The fan speed can be controlled by hardware and softw are from the motherboard. This is accompli[...]

  • Seite 95

    Datasheet 95 Boxed Processor Specifications If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designe d with a fan speed controller with PWM output (CONTROL see Ta b l e 3 2 ) and remote thermal diode measu rement capability the boxed processor will oper ate as follows: As processo[...]

  • Seite 96

    Boxed Processor Specifications 96 Datasheet If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard de signs. Under thermistor contro lled mode, the fan RPM is automatically varied based on [...]

  • Seite 97

    Datasheet 97 Debug Tools Specifications 8 Debug Tools Specifications 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer ve ndors to provide logic analyzer interfaces (LAIs) for use in debugging systems. T ektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The followin[...]

  • Seite 98

    Debug Tools Specifications 98 Datasheet[...]