Intel Itanium 2 Processor Bedienungsanleitung

Intel ® It anium ® 2 Processor Intel ® Itanium ® 2 Processor 1.66 GHz with 9 MB L3 Cache Intel ® Itanium ® 2 Processor 1.66 GHz with 6 MB L3 Cache Intel ® Itanium ® 2 Processor 1.6 GHz with 9 MB L3 Cache Intel ® Itanium ® 2 Processor 1.6 GHz with 6 MB L3 Cache Intel ® Itanium ® 2 Processor 1.5 GHz with 6 MB L3 Cache Intel ® Itanium ® [...]

2 Datasheet INFORMA TI ON IN THIS DOCUME NT IS PROVIDED IN CONNECTION WI TH INTEL ® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER WISE, TO ANY INTEL LECTUAL PROPERTY RIGH TS IS GRANTED BY THIS DO CUMENT . EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, IN TEL ASSUMES NO LIABILITY WHA TSOEVER, AND[...]

Datasheet 3 Contents 1 Introduction... ................ ................ ............. ................ ................ ................. ................ . ..... 11 1.1 Overview ................ ................ ............. ................ ................ ................ ................ 11 1.2 Processor Abstraction Layer ............... ...[...]

4 Datasheet 6.1.3 SMBus Device Addressing .... ................. ................ ................ ................ 81 6.2 Processor Information ROM ......... ................ ................ ................ .................... ... 82 6.3 Scratch EEPROM ........ ................ ............. ................ ................ ................ ..[...]

Datasheet 5 A.1.37 ID[9:0]# (I) ....... ................ ................ ................ ................. ................ ...... 99 A.1.38 IDS# (I) ............ ................ ................ ................ ................. ............ .......... 99 A.1.39 IGNNE# (I) ............. ................. ................ ................ .....[...]

6 Datasheet 5-2 Itanium ® 2 Processor Package Thermocouple Location........ ................... .......... 77 6-1 Logical Schematic of S MBus Circuitry ................... ................ ................ ............. 80 Tables 2-1 Itanium ® 2 Processor System Bus Signal Groups .................... ................ .......... 16 2-2 Itanium ® [...]

Datasheet 7 6-2 Thermal Sensing Device SMBus Addr essing on the Itanium ® 2 Processor . ...... 81 6-3 EEPROM SMBus Addres sing on the Itanium ® 2 Processor ......... ... ... ... ... .... ... ... 82 6-4 Processor Information RO M Format ................... ................ ................ ................ 82 6-5 Current Address Read SMBus Packet [...]

8 Datasheet Revision History Revision No. Description Date -001 Initial release of this document. July 2002 -002 Updated content to include inform ation pertaining to Itanium 2 processor (1.5 GHz, 6 M B), Itanium 2 processor (1. 4 GHz, 4 MB) and Itanium 2 processor (1.3 GHz, 3 MB). June 2003 -003 Updated content to include information pertaining to[...]

Datasheet 9 Intel ® It anium ® 2 Processor Intel ® Itanium ® 2 Processor 1.66 GHz with 9 MB L3 Cache Intel ® Itanium ® 2 Processor 1.66 GHz with 6 MB L3 Cache Intel ® Itanium ® 2 Processor 1.6 GHz with 9 MB L3 Cache Intel ® Itanium ® 2 Processor 1.6 GHz with 6 MB L3 Cache Intel ® Itanium ® 2 Processor 1.5 GHz with 6 MB L3 Cache Intel ®[...]

10 Datasheet[...]

Datasheet 11 1 Introduction 1.1 Overview The Itanium 2 processor employs Explicitly Parallel Instructi on Com pu ting (EPIC) design concepts for a tighter coupling between hardware a nd software. In this design style, the interface between hardware and software is designed to enab le the software to exploit all av ailable compile- time informatio n[...]

12 Datasheet Introduction 1.3 Mixing Processors of Different Frequencies and Cache Sizes All Itanium 2 processors on the same system bu s are required to have the same cache size (9 MB , 6 MB, 4 MB, 3 MB or 1.5 MB) and identical core frequency . Mixing components of different core frequencies and cache sizes is not supported and has not been valida[...]

Datasheet 13 Introduction 1.6 Reference Document s The reader of this specification sh ould also be fami liar with mate ri al and concepts pres ented in the following documents: Note: Contact your Intel representativ e or check http:/ /d eveloper .intel.com for the latest rev isio n of the reference documents. Title Doc umen t Nu mber Intel ® Itan[...]

14 Datasheet Introduction[...]

Datasheet 15 2 Electrical Specifications This chapter describes the electrical sp ecifications of the Itanium 2 processo r . 2.1 It anium ® 2 Processor System Bus Most Itanium 2 processor signals use the Itanium processor ’ s assi sted gunning tran scei ver lo gic (AG TL+) signaling technol ogy . The termination voltage, V CTER M , is generated [...]

16 Datasheet Electrical Specifications .. All system bus outputs should be treated as open drain signals and require a high level source provided by the V CTERM supply . AG TL+ inputs have differential input buffers which use V REF as a reference level. AG TL+ output signals require termination to V CTERM . In this document, “AG TL+ Input Signals[...]

Datasheet 17 Electrical Specifications V CTERM System bus termination voltage. GND System ground. N/C No connection can be made to these pins. TERMA, TERMB The Itanium 2 processor uses two pins to control th e on-die termination function, TERMA and TERMB. Both of these terminati on pins must be pulled to VCTERM in order to terminat e the system bus[...]

18 Datasheet Electrical Specifications 2.4 Signal S pecifications This section describes the DC specifications of th e system bus signals. The processor signal’ s DC specifications are defined at the Itanium 2 processor pins. Ta b l e 2 - 4 through Ta b l e 2 - 9 descri be the DC specifications for the AG TL+ , PWRGOOD, HSTL clock, T AP port, sys[...]

Datasheet 19 Electrical Specifications I L Leakage Current All ±100 µA 5 C AG T L+ AG TL+ Pad Capacitance 900 MHz 3 pF 6 1.0 GHz 3 pF 6 1.3 GHz 1.5 pF 6 1.4 GHz 1.5 pF 6 1.5 GHz 1.5 pF 6 1.6 GHz 1.5 pF 6 1.66 GHz 1.5 pF 6 NOTES: 1. The typical transition point between V IL and V IH assuming 125 mV V REF uncert ainty for ODT. V REF_high and V REF_[...]

20 Datasheet Electrical Specifications Ta b l e 2 - 1 0 through Ta b l e 2 - 1 1 list the AC specifications for th e Itanium 2 processor’ s clock and SMBus (timing diagrams beg in with Figure 2-1 ). The Itanium 2 processor uses a differential HSTL clocking scheme with a frequency of 200, 266 or 333 MHz. The SMBus is a subset of the I2C* interface[...]

Datasheet 21 Electrical Specifications T low BCLKp Low T ime 266 1.69 1.88 2.06 ns Figure 2-1 4 T period BCLKp Period 333 3.0 ns Figure 2-1 T skew System Clock Skew 333 60 ps f BCLK BCLKp Frequency 333 333 333 MHz Figure 2-1 T jitter BCLKp Input Jitter 333 50 ps Figur e 2-1 3 T high BCLKp High T ime 333 1.35 1.5 1.65 ns Figure 2-1 4 T low BCLKp Low[...]

22 Datasheet Electrical Specifications 2.4.1 Maximum Ratings Ta b l e 2 - 1 2 contains the Itanium 2 pro cessor stress ratings. Functiona l operation at the absolute maximum and minimum is neither implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functi onal operating conditions are given in the D[...]

Datasheet 23 Electrical Specifications 2.5 System Bus Signal Quality S pecifications and Measurement Guidelines Overshoot (or undershoot) is the absolut e value of the maximum vol tage abov e the nominal V CTERM voltage (or below GND), as shown in Ta b l e 2 - 3 . The overshoot/undershoot specificatio ns limit transitions beyond V CTERM or GND due [...]

24 Datasheet Electrical Specifications 2.5.2 Overshoot/Undershoot Pulse Duration Pulse duration describes the total time an overshoot/undersh oot event exceeds the overshoot/undershoot reference voltage (V CTERM /GND). The total time could encom pass several oscillations above the reference voltage. Multiple overshoot/undersh oot pulses within a si[...]

Datasheet 25 Electrical Specifications Note: AF for the common clock AG TL+ signals is re ferenced to BCLKn, and BCLKp frequency . The wired-OR Signal s (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) are common clock AG TL+ signals. Note: AF for source synchronous (2x) signals is referenced to STBP#[7:0], and STBN#[7 :0]. 2.5.4 Reading Overshoot/Unde rsh[...]

26 Datasheet Electrical Specifications 3. If multiple overshoots and/or multiple undershoots occu r , measure the worst-case pulse duration for each magnitude and compare the results against the AF = 1 specifications. If all of these worst-case overshoo t or undershoot events meet th e specifications (measured time < specifications) in the table[...]

Datasheet 27 Electrical Specifications T able 2-15. Itanium ® 2 Processors (1.5 GHz/4 MB, 1.6 GHz) Source Synchronous AG TL+ Signal Group T ime-Dependent Overshoot/Under shoo t T olerance for 400 MHz System Bus Absolu te Maximum (V) Pulse Duration (ns) Over- shoot Under- shoot AF = 1 1 NOTES: 1. Activity Factor = 1 means signal toggles every 5 ns.[...]

28 Datasheet Electrical Specifications 2.5.6 Wired-OR Signals System bus signals must meet certain overshoot and und ershoot requirements. The maxi mum absolute overshoot voltage is 1.8 V and the m ini mum absolute undershoot voltage is –0.6V . The system bus wired-OR signals (BINIT#, HIT#, HITM#, BNR#, TND#, BER R#) hav e the same absolut e over[...]

Datasheet 29 Electrical Specifications T able 2-19. Itanium ® 2 Processors (1.5 GHz/4 MB, 1.6 GHz) Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) Overshoot/Undershoot T olerance for 400 MHz System Bus Absolu te Maximum (V) Pulse Duration (ns) Over- shoot Under- shoot AF = 1 1 NOTES: 1. Activity Factor = 1 means signal togg les ever[...]

30 Datasheet Electrical Specifications 2.6 Power Pod Connector Signals Power delivery for the Itanium 2 processor is from a DC-DC converter called the “power pod”. The power pod consists of a DC-DC converter and a semi-flexib le connector which delivers the voltage to the processor . Ta b l e 2 - 2 2 lists all of the signals which are part of t[...]

Datasheet 31 Electrical Specifications The power pod provides a sel ectable ou tput voltage controlled via multiple bi nary weighted V oltage Identification (VID) inp uts. The VID valu e (high = 1; low = 0) is defi ned in Ta b l e 2 - 2 3 . VID pads shall be considered as L VTTL inputs to the power po d, having resistive pull-ups (5 k Ω ) included[...]

32 Datasheet Electrical Specifications 2.7 It anium ® 2 Processor System Bus Clock and Processor Clocking The BCLKn and BCLKp inputs cont rol th e oper atin g fr eque ncy of the Itanium 2 process or system bus interface. All Itanium 2 proces sor system bus timing parameters are specified with respect to the falling edge of BCLKn and rising edge of[...]

Datasheet 33 Electrical Specifications Listed in T able 2-25 are the system bus rat ios defi ned fo r the Itanium 2 proces sor . The Itanium 2 processor supports bus rati os of 2/ 9, 2/10, 2/13, 2/14, 2 /15 and 2/16. T able 2-25 lists the system bus ratios defined for the Itanium 2 processor . Each particular implementation of the Itanium 2 process[...]

34 Datasheet Electrical Specifications W arm Reset Sequence : • PWRGOOD remains high throug hout the entire se quence as power is already available and stable to the processor . • The bus ratio configuration pins (A[21:17]#) mu st be asserted the entire ti me RESET# is asserted. • The duration from the assertion of RESET# to the deassertion o[...]

Datasheet 35 Electrical Specifications 2.8 Recommended Connections for Unused Pins Pins that are unused in an application environm ent (as opposed to testing environm en t) should be connected to the states listed in T able 2-26 . Pins that must be used in an applica tion are stated as such and do not have a recommended state for unused connection.[...]

36 Datasheet Electrical Specifications System Management Signals 3.3V GND SMA[2:0] N/C SMSC N/C SMSD N/C SMWP N/C THRMALERT# H 1, 4 L VTTL Power Pod Sign als OUTEN Must be used PPODGD# Must be used CPUPRES# Must be used Reserved Pins N/C N/C NOTES: 1. L = GND, H = V CTERM . 2. AGTL+ output signals SBSY[0:1]#, DBSY[0:1]#, and DRD Y[0,1]# may be left[...]

Datasheet 37 3 Pinout Specifications This chapter describes the Itanium 2 processor signals and pino ut. Note: The pins labeled “N/C” must rema in unconnected. The Itanium 2 pr ocessor uses a JEDEC standard pin naming convention. In this chapter , pin names ar e the actual names given to each physical pin of the processor . System bus signal na[...]

38 Datasheet Pinout Specificat ions Ta b l e 3 - 1 provides the It an ium 2 processor pin list in alph abetical order . Ta b l e 3 - 2 provides the It an ium 2 processor pin list by pin location. T able 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 1 of 15) Pin Name System Bu s Signal Name Pin Location Input/Out put Notes 3.3V B02 IN SMBus [...]

Datasheet 39 Pinout Specifications A040# AA40#/AB40# V24 IN/OUT A041# AA41#/AB41# W25 IN/OUT A042# AA42#/AB42# U23 IN/OUT A043# AA43#/AB43# Y24 IN/OUT A044# AA44#/AB44# W21 IN/OUT A045# AA45#/AB45# V20 IN/OUT A046# AA46#/AB46# W23 IN/OUT A047# AA47#/AB47# V22 IN/OUT A048# AA48#/AB48# U21 IN/OUT A049# AA49#/AB49# Y22 IN/OUT A20M# A20M# AH23 IN ADS# [...]

40 Datasheet Pinout Specificat ions D010# D10# E07 IN/OUT D01 1# D1 1# H02 IN/OUT D012# D12# H04 IN/OUT D013# D13# J03 I N/OUT D014# D14# G03 IN/OUT D015# D15# G07 IN/OUT D016# D16# K04 IN/OUT D017# D17# L03 IN/OUT D018# D18# K06 IN/OUT D019# D19# L05 IN/OUT D020# D20# M02 IN/OUT D021# D21# L07 IN/OUT D022# D22# N07 IN/OUT D023# D23# N03 IN/OUT D02[...]

Datasheet 41 Pinout Specifications D051# D51# M12 IN/OUT D052# D52# L13 IN/OUT D053# D53# L09 IN/OUT D054# D54# P08 IN/OUT D055# D55# N13 IN/OUT D056# D56# L1 1 IN/OUT D057# D57# P12 IN/OUT D058# D58# N09 IN/OUT D059# D59# R13 IN/OUT D060# D60# R1 1 IN/OUT D061# D61# P10 IN/OUT D062# D62# T12 IN/OUT D063# D63# R09 IN/OUT D064# D64# D18 IN/OUT D065#[...]

42 Datasheet Pinout Specificat ions D092# D92# R15 IN/OUT D093# D93# P16 IN/OUT D094# D94# T14 IN/OUT D095# D95# P18 IN/OUT D096# D96# E21 IN/OUT D097# D97# C23 IN/OUT D098# D98# D22 IN/OUT D099# D99# C21 IN/OUT D100# D100# E25 IN/OUT D101# D101# G21 IN/OUT D102# D102# D20 I N/OUT D103# D103# F24 IN/OUT D104# D104# D24 I N/OUT D105# D105# H22 I N/O[...]

Datasheet 43 Pinout Specifications DEP01# DEP1# J05 IN/OUT DEP02# DEP2# T06 IN/OUT DEP03# DEP3# T04 IN/OUT DEP04# DEP4# J09 IN/OUT DEP05# DEP5# J1 1 IN/OUT DEP06# DEP6# T08 IN/OUT DEP07# DEP7# T10 IN/OUT DEP08# DEP8# J19 IN/OUT DEP09# DEP9# J17 IN/OUT DEP10# DEP10# T18 IN/OUT DEP1 1# DEP1 1# T16 IN/OUT DEP12# DEP12# J21 IN/OUT DEP13# DEP13# J23 IN/[...]

44 Datasheet Pinout Specificat ions GND GND AB19 IN GND GND AB21 IN GND GND AB23 IN GND GND AB25 IN GND GND AC02 IN GND GND AC24 IN GND GND AD01 IN GND GND AD03 IN GND GND AD05 IN GND GND AD07 IN GND GND AD09 IN GND GND AD1 1 IN GND GND AD13 IN GND GND AD15 IN GND GND AD17 IN GND GND AD19 IN GND GND AD21 IN GND GND AD23 IN GND GND AD25 IN GND GND A[...]

Datasheet 45 Pinout Specifications GND GND AG22 IN GND GND AG24 IN GND GND AH01 IN GND GND B03 IN GND GND B05 IN GND GND B07 IN GND GND B09 IN GND GND B10 IN GND GND B1 1 IN GND GND B13 IN GND GND B15 IN GND GND B17 IN GND GND B19 IN GND GND B21 IN GND GND B23 IN GND GND B25 IN GND GND C02 IN GND GND C06 IN GND GND C10 IN GND GND C14 IN GND GND C18[...]

46 Datasheet Pinout Specificat ions GND GND F01 IN GND GND F03 IN GND GND F05 IN GND GND F07 IN GND GND F09 IN GND GND F1 1 IN GND GND F13 IN GND GND F15 IN GND GND F17 IN GND GND F19 IN GND GND F21 IN GND GND F23 IN GND GND F25 IN GND GND G02 IN GND GND H03 IN GND GND H05 IN GND GND H07 IN GND GND H09 IN GND GND H1 1 IN GND GND H13 IN GND GND H15 [...]

Datasheet 47 Pinout Specifications GND GND K19 IN GND GND K21 IN GND GND K23 IN GND GND K25 IN GND GND L02 IN GND GND M01 IN GND GND M03 IN GND GND M05 IN GND GND M07 IN GND GND M09 IN GND GND M1 1 IN GND GND M13 IN GND GND M15 IN GND GND M17 IN GND GND M19 IN GND GND M21 IN GND GND M23 IN GND GND M25 IN GND GND N04 IN GND GND N20 IN GND GND N24 IN[...]

48 Datasheet Pinout Specificat ions GND GND T13 IN GND GND T15 IN GND GND T17 IN GND GND T19 IN GND GND T21 IN GND GND T23 IN GND GND T25 IN GND GND U04 IN GND GND U20 IN GND GND U24 IN GND GND V01 IN GND GND V03 IN GND GND V05 IN GND GND V07 IN GND GND V09 IN GND GND V1 1 IN GND GND V13 IN GND GND V15 IN GND GND V17 IN GND GND V19 IN GND GND V21 I[...]

Datasheet 49 Pinout Specifications ID1# IDA1#/IP1 # AB02 IN ID2# IDA2#/DHIT# AC03 IN ID3# IDA3#/IDB3# AA03 IN ID4# IDA4#/IDB4# AD04 IN ID5# IDA5#/IDB5# AB04 IN ID6# IDA6#/IDB6# AE05 IN ID7# IDA7#/IDB7# AC05 IN ID8# IDA8#/IDB8# AD06 IN ID9# IDA9#/IDB9# AB06 IN IDS# IDS# AC07 IN IGNNE# IGNNE# AG23 IN INIT# INIT# AF08 IN LINT0 INT AF22 IN LINT1 NMI AF[...]

50 Datasheet Pinout Specificat ions N/C K02 N/C K12 N/C K14 N/C K24 N/C U05 N/C U1 1 OUTEN OUTEN AF04 IN Power pod signal PMI# PMI# AE25 IN PPODGD# PPODGD# AF20 OUT Power pod signal PWRGOOD PWRGOOD AH15 IN REQ0# REQA0#/LEN0# AE09 IN/OUT REQ1# WSNP#, D/C#/LEN1# AF10 IN/OUT REQ2# REQA2#/ REQB2# AD10 IN/OUT REQ3# ASZ0#/DSZ0# AE1 1 IN/OUT REQ4# ASZ1#/D[...]

Datasheet 51 Pinout Specifications STBP2# STBP2# E1 1 IN/OUT STBP3# STBP3# M10 IN/OUT STBP4# STBP4# E17 IN/OUT STBP5# STBP5# M16 IN/OUT STBP6# STBP6# E23 IN/OUT STBP7# STBP7# M22 IN/OUT TCK TCK AG09 IN JT AG TDI TDI AG07 IN JT AG TDO TDO AH07 OUT JT AG TERMA FSBT1 AF02 IN TERMB FSBT2 AE03 IN THRMTRIP# THRMTRIP# AG25 OUT THRMALERT# THRMALER T# A07 O[...]

52 Datasheet Pinout Specificat ions VCTERM VCTERM G04 IN VCTERM VCTERM G08 IN VCTERM VCTERM G12 IN VCTERM VCTERM G16 IN VCTERM VCTERM G20 IN VCTERM VCTERM G24 IN VCTERM VCTERM J02 IN VCTERM VCTERM J06 IN VCTERM VCTERM J10 IN VCTERM VCTERM J14 IN VCTERM VCTERM J18 IN VCTERM VCTERM J22 IN VCTERM VCTERM L01 IN VCTERM VCTERM L04 IN VCTERM VCTERM L08 IN[...]

Datasheet 53 Pinout Specifications T able 3-2. Pin/Signal In for mation Sorted by Pin Location (Sheet 1 of 15) Pin Name System Bus Signal Name Pin Location Input/Output Notes GND GND A01 IN VCTERM VCTERM A02 IN GND GND A03 IN N/C A04 GND GND A05 IN VCTERM VCTERM A06 IN THRMALERT# THRMALER T# A07 OUT GND GND A08 IN VSSMON VSSMON A09 OUT Power pod si[...]

54 Datasheet Pinout Specificat ions N/C B20 GND GND B21 IN SMSD SMSD B22 IN/OUT SMBus signal GND GND B23 IN SMSC SMSC B24 IN SMBus signal GND GND B25 IN VCTERM VCTERM C01 IN GND GND C02 IN N/C C03 VCTERM VCTERM C04 IN D002# D02# C05 IN/OUT GND GND C06 IN D000# D00# C07 IN/OUT VCTERM VCTERM C08 IN D035# D35# C09 IN/OUT GND GND C10 IN D033# D33# C1 1[...]

Datasheet 55 Pinout Specifications GND GND D1 1 IN D036# D36# D12 IN/OUT GND GND D13 IN D065# D65# D14 IN/OUT GND GND D15 IN D066# D66# D16 IN/OUT GND GND D17 IN D064# D64# D18 IN/OUT GND GND D19 IN D102# D102# D20 IN/OUT GND GND D21 IN D098# D98# D22 IN/OUT GND GND D23 IN D104# D104# D24 IN/OUT GND GND D25 IN VCTERM VCTERM E02 IN D001# D01# E03 IN[...]

56 Datasheet Pinout Specificat ions GND GND F03 IN STBN0# STBN0# F04 IN/OUT GND GND F05 IN D006# D06# F06 IN/OUT GND GND F07 IN D045# D45# F08 IN/OUT GND GND F09 IN STBN2# STBN2# F10 IN/OUT GND GND F1 1 IN D044# D44# F12 IN/OUT GND GND F13 IN D068# D68# F14 IN/OUT GND GND F15 IN STBN4# STBN4# F16 IN/OUT GND GND F17 IN D069# D69# F18 IN/OUT GND GND [...]

Datasheet 57 Pinout Specifications VCTERM VCTERM G24 IN D107# D107# G25 IN/OUT D01 1# D1 1# H02 IN/OUT GND GND H03 IN D012# D12# H04 IN/OUT GND GND H05 IN D009# D09# H06 IN/OUT GND GND H07 IN D042# D42# H08 IN/OUT GND GND H09 IN D032# D32# H10 IN/OUT GND GND H1 1 IN D046# D46# H12 IN/OUT GND GND H13 IN D075# D75# H14 IN/OUT GND GND H15 IN D076# D76[...]

58 Datasheet Pinout Specificat ions GND GND J16 IN DEP09# DEP9# J17 IN/OUT VCTERM VCTERM J18 IN DEP08# DEP8# J19 IN/OUT GND GND J20 IN DEP12# DEP12# J21 IN/OUT VCTERM VCTERM J22 IN DEP13# DEP13# J23 IN/OUT GND GND J24 IN D1 10# D1 10# J25 IN/OUT N/C K02 GND GND K03 IN D016# D16# K04 IN/OUT GND GND K05 IN D018# D18# K06 IN/OUT GND GND K07 IN D049# D[...]

Datasheet 59 Pinout Specifications D053# D53# L09 IN/OUT D056# D56# L1 1 IN/OUT VCTERM VCTERM L12 IN D052# D52# L13 IN/OUT D081# D81# L15 IN/OUT VCTERM VCTERM L16 IN D088# D88# L17 IN/OUT D082# D82# L19 IN/OUT VCTERM VCTERM L20 IN D1 12# D1 12# L21 IN/OUT D1 16# D1 16# L23 IN/OUT VCTERM VCTERM L24 IN D1 13# D1 13# L25 IN/OUT GND GND M01 IN D020# D2[...]

60 Datasheet Pinout Specificat ions STBN1# STBN1# N05 IN/OUT VCTERM VCTERM N06 IN D022# D22# N07 IN/OUT D058# D58# N09 IN/OUT VCTERM VCTERM N10 IN STBN3# STBN3# N1 1 IN/OUT D055# D55# N13 IN/OUT VCTERM VCTERM N14 IN D091# D91# N15 IN/OUT STBN5# STBN5# N17 IN/OUT VCTERM VCTERM N18 IN D085# D85# N19 IN/OUT GND GND N20 IN D127# D127# N21 IN/OUT VCTERM[...]

Datasheet 61 Pinout Specifications D120# D120# P24 IN/OUT GND GND P25 IN VCTERM VCTERM R01 IN GND GND R02 IN D025# D25# R03 IN/OUT VCTERM VCTERM R04 IN D029# D29# R05 IN/OUT D031# D31# R07 IN/OUT VCTERM VCTERM R08 IN D063# D63# R09 IN/OUT D060# D60# R1 1 IN/OUT VCTERM VCTERM R12 IN D059# D59# R13 IN/OUT D092# D92# R15 IN/OUT VCTERM VCTERM R16 IN D0[...]

62 Datasheet Pinout Specificat ions DEP14# DEP14# T 20 IN/OUT GND GND T21 IN DEP15# DEP15# T 22 IN/OUT GND GND T23 IN D123# D123# T24 IN/OUT GND GND T25 IN VCTERM VCTERM U02 IN A005# AA 05#/EXF2# U03 IN/OUT GND GND U04 IN N/C U05 VCTERM VCTERM U06 IN A009# AA09#/BE1# U07 IN/OUT A018# AA18#/DID2# U09 IN/OUT VCTERM VCTERM U10 IN N/C U1 1 A016# AA16#/[...]

Datasheet 63 Pinout Specifications GND GND V15 IN A038# AA38#/AB38# V16 IN/OUT GND GND V17 IN A029# AA29#/xTPRV alue 2# V18 IN/OUT GND GND V19 IN A045# AA45#/AB45# V20 IN/OUT GND GND V21 IN A047# AA47#/AB47# V22 IN/OUT GND GND V23 IN A040# AA40#/AB40# V24 IN/OUT GND GND V25 IN GND GND W02 IN A006# AA06#/EXF3# W03 IN/OUT A012# AA12#/BE4# W05 IN/OUT [...]

64 Datasheet Pinout Specificat ions A035# AA35#/A TTR3# Y18 IN/OUT GND GND Y19 IN A039# AA39#/AB39# Y20 IN/OUT GND GND Y21 IN A049# AA49#/AB49# Y22 IN/OUT GND GND Y23 IN A043# AA43#/AB43# Y24 IN/OUT GND GND Y25 IN GND GND AA02 IN ID3# IDA3#/IDB3# AA03 IN A01 1# AA1 1#/BE3# AA05 IN/OUT DRDY0# DRDY_C1# AA07 OUT DBSY0# DBSY_C1# AA09 OUT A023# AA23#/DI[...]

Datasheet 65 Pinout Specifications GND GND AB19 IN ADS# ADS# AB20 IN/OUT GND GND AB21 IN BERR# BERR# AB22 IN/OUT GND GND AB23 IN BPM5# BPM5# AB24 IN/OUT GND GND AB25 IN GND GND AC02 IN ID2# IDA2#/DHIT# AC03 IN ID7# IDA7#/IDB7# AC05 IN IDS# IDS# AC07 IN DBSY# DBSY# AC09 IN/OUT DRDY# DRDY# AC1 1 IN/OUT RP# RP# AC13 IN/OUT TND# TND# AC15 IN/OUT N/C AC[...]

66 Datasheet Pinout Specificat ions GND GND AD21 IN BPM0# BPM0# AD22 IN/OUT GND GND AD23 IN BPM4# BPM4# AD24 IN/OUT GND GND AD25 IN GND GND AE02 IN TERMB FSBT2 AE03 ID6# IDA6#/IDB6# AE05 IN RS0# RS0# AE07 IN REQ0# REQA0#/LEN0# AE09 IN/OUT REQ3# ASZ0#/DSZ0# AE1 1 IN/OUT SBSY# SBSY# AE13 IN/OUT LOCK# LOCK# AE15 IN/OUT N/C AE17 BPRI# BPRI# AE19 IN TRS[...]

Datasheet 67 Pinout Specifications GND GND AG02 IN TUNER[2] AG03 GND GND AG04 IN N/C AG05 GND GND AG06 IN TDI T DI AG07 IN JT AG GND GND AG08 IN TCK TCK AG09 IN JT AG GND GND AG10 IN N/C AG1 1 GND GND AG12 IN BCLKp CLK AG13 IN GND GND AG14 IN CPUPRES# CPUPRES# AG15 OUT Power pod signal GND GND AG16 IN N/C AG17 GND GND AG18 IN N/C AG19 GND GND AG20 [...]

68 Datasheet Pinout Specificat ions[...]

Datasheet 69 4 Mechanical Specifications This chapter provides the mechanical sp ecifications of the Itanium 2 processor . 4.1 Mechanical Dimensions The Itanium 2 processor package is comprised of an interposer , a processor package substrate, and an integrated heat spreader (IHS), as illustrated i n Figure 4-1 . The interposer interfaces with the [...]

70 Datasheet Mechanical Specifications NOTE: Figure 4-2. Itanium ® 2 Pro cessor Package All dimensions are measured in mm. Not to scale. 000655g 90.00 42.50 38.50 48.26 42.50 38.50 Top View 25 x 1.27 Pitch Bottom View 28 x 1.27 Pitch 34.29 30.48 611 x 0.305 Pins Side View Integrated Heat Spreader Processor Package Substrate Interposer Pins 1.43 0.[...]

Datasheet 71 Mechanical Specifications Figure 4- 3. Itanium ® 2 Processor Package Power T ab All dime nsions a re measur ed in mm . Not to sca le. 001 159a Top View Bottom View 46.96 42.21 46.00 2x 9.10 2x 12.91 4x R1.00 C L 2.98 12x 2.92 2x 25.85 C L 12x 38.76 90.00 45.00 42.46 2x R1.20 46.74 48.26 24.13 10x 1.15 12x 0.86 2x 16.10 2.48 46.96 C L[...]

72 Datasheet Mechanical Specifications 4.2 Package Marking The following section details the processo r top-side and bottom-side markings for the Itanium 2 processor and is provided as an iden tification aid. The processor top-si de mark for the product is a laser marking on the IHS. 4.2.1 Processor T op-Side Marking Figure 4-4 shows an example of [...]

Datasheet 73 Mechanical Specifications NOTE: 2D Matrix Mark only present on Itanium 2 processo r (6 MB), Itanium 2 processor (4 MB) and Itanium 2 processor (1.3 GHz, 3 MB). Figure 4-5. Processor Bottom- Side Marking Placement on Interpo ser 001267b Laser Mark includin g 2D Matrix Mark AH1 A1 AH25 A25 Pin 1 Indicator[...]

74 Datasheet Mechanical Specifications[...]

Datasheet 75 5 Thermal Specifications This chapter provides a descript ion of the thermal features rela ting to the Itanium 2 processor . 5.1 Thermal Features The Itanium 2 processor has an internal thermal ci rcuit which senses when a certain temperature is reached on the processor core. Th is circuit is used for contro lling various ther mal stat[...]

76 Datasheet Thermal Specificat ions 5.1.2 Enhanced Thermal Management ETM is a new feature that has b een added to the Itanium 2 proce ssor . ETM uses a thermal sensing device on the die to monitor a thermal entry poi nt, indicating dangerous operation exceeding the thermal specification. Once the thermal sensing de vice observes the temperature r[...]

Datasheet 77 Thermal Specifications Figure 5- 2. Itanium ® 2 Processor Package Thermocouple Location All dime nsions a re measur ed in mm . Not to sca le. 001 103a Th erm o co uple Lo ca ti on 45. 00 2 4.13[...]

78 Datasheet Thermal Specificat ions[...]

Datasheet 79 6 System Management Feature Specifications The Itanium 2 processor includes a system mana gement bus (SMBus) interface. This chapter describes the features of th e SMBus and SMBus components. 6.1 System Management Bus 6.1.1 System Management Bus Interface The Itanium 2 processor includes an Itanium pr ocessor family SMBus interface whi[...]

80 Datasheet System Management Featu re Specifications Figure 6-1. Logical Sche matic of SMBu s Circuitry NOTE: 1. Actual implementation may vary. 2. For use in general understanding of the architectur e. 000668b Processor Information ROM A0 A1 A2 SC SD V CC 10K 10K 3.3V Scratch EEPROM A0 A1 A2 SD WP V CC SC 10K 10K 10K Thermal Sensing Device VCC A[...]

Datasheet 81 System Management Featu re Specifications 6.1.3 SMBus Device Addressing Of the addresses broadcast across the SMBus, th e memory component s claim those of the form “1010XXYZb”. The “XX” and “Y” bits are used to enable the devices on the processor at adjacent addresses. The Y bit is hard-wired on the pro cessor to GND (‘0[...]

82 Datasheet System Management Featu re Specifications 6.2 Processor Information ROM An electrically programmed read-only m e mory (R O M) provides informatio n about the Itanium 2 processor . The checksum bits for each category pr ovide error correction an d serve as a mechanism to check whether data is corrupt ed or not. This information is perma[...]

Datasheet 83 System Management Featu re Specifications 09h 8 Feature Data Address Byte pointer , 00h if not present 67h 0Ah 8 Other Data Address Byte pointer , 00h if not present 7Ah 0Bh 16 Reserved Reserved for future use 0000h 0Dh 8 Checksum 1 byte checksum Add up by byte and take 2’ s complement. Processor 0Eh 48 S-spec N umber Six 8-bit ASCII[...]

84 Datasheet System Management Featu re Specifications Package 37h 32 Package Revision Four 8-bit ASCII cha racters Itanium ® 2 Package = INT2b, (1.50 GHz 4MB and above) = INT3b: • 37h = I • 38h = N • 39h = T • 3Ah = 2 or 3 3Bh 2 Substrate Revision Software ID 2-bit revision number 00 3Ch 8 Reserved Reserved for future use 00h 3Dh 8 Checks[...]

Datasheet 85 System Management Featu re Specifications 6.3 Scratch EEPROM Also available on the SMBus interface on the pr oces sor is an EEPROM which may be used for other data at the system vendor ’ s discretion (Intel wi ll not be using the scratch EEPROM). The data in this EEPROM, once programmed , can be write-protected by a sserting the acti[...]

86 Datasheet System Management Featu re Specifications controller continues to transmit data bytes until it terminates the sequen ce with a stop. All data bytes will result in an acknowledge from the Scratch EEPROM. If more than eight bytes are written, the internal address will “roll over” and the previous data will be overwritten. In Ta b l e[...]

Datasheet 87 System Management Featu re Specifications THRMALER T# signal (see Section 6 .1.1 for more details). At power up, the appropriate alarm register values need to be pr ogrammed into th e therma l sensing device via the SMBus. It is recommended that the upper thermal reference threshold byte (provided in the processor information ROM) be u[...]

88 Datasheet System Management Featu re Specifications All of the commands are for reading or writing registers in th e thermal sensor except the one-shot command (OSHT). The one-shot command forces the immediate start of a new voltage-to- temperature conversion cycle. If a conversion is in progress when the one-sh ot command is received, then the [...]

Datasheet 89 System Management Featu re Specifications 6.7.2 Thermal Limit Registers The thermal sensing device h as two thermal limi t registers; th ey define high and low lim its for the processor core thermal diode. The en coding for th ese registers is the same as for the thermal reference registers. If the diode thermal value equals or exceeds[...]

90 Datasheet System Management Featu re Specifications 6.7.5 Conversion Rate Register The contents of the conversion rate register dete rmine the nominal rate at which analog-to-di gital conversions happen when the thermal sen sing device is in auto-convert mode. Ta b l e 6 - 1 6 shows the mapping bet ween conversion rate register values and the co[...]

Datasheet 91 A Signals Reference This appendix provides an alph ab etical listing of all Itanium 2 processor system bus signals. The tables at the end of this appendix summarize th e signals by direction: output, inp ut, and I/ O. For a complete pino ut listing in cluding processor specific pins, please refer to Chapter 3, “Pi nout Specifications[...]

92 Datasheet Signals Referenc e Any memory access transaction addr essing a memory region that is less than 64 GB (that is, Aa[49:36]# are all zeroes) must set ASZ[1:0]# to 01. Any memory access transaction address ing a memory region that is equal to or great er than 64 GB (that is, Aa[49:36]# are not all zeroes) must set ASZ[1:0]# to 10. All obse[...]

Datasheet 93 Signals Reference For memory or I/O transactions, the byte-enable signals indicate th at vali d dat a is req u ested or being transferred on the corresponding byt e on the 128-bit data bus. BE[0]# indi cates that the least significant byte is valid, and BE[7]# i ndicates that the most significant byte is valid. Since BE[7:0]# specifies[...]

94 Datasheet Signals Referenc e A.1.10 BINIT# (I/O) If enabled by configuration, the Bus Initialization (BINIT# ) signal is asserted to signal any bus condition that prevents reli able fu ture operation. If BINIT# observation is enabled during power-on configuration, and BIN IT# is sampled asserted, all bus state machines are reset. All agents rese[...]

Datasheet 95 Signals Reference During power-on configuration, the priority ag ent must assert the BR [0]# bus signal. Al l symmetric agents sample their BR[3:0 ]# pins on a sserted-to-deasserted tran sition of RESET#. The pin on which the agent samp les an asserted level determines its ag ent ID. All agents then configure their pins to match the ap[...]

96 Datasheet Signals Referenc e sampling BREQn# asserted by another symmetri c agent, the symmetric owner deasserts BREQ n # as soon as possible to release the bus. A symmetric owner stops issuing new requests that are not part of an existing locked operation on observing BPRI# asserted . A symmetric agent can deassert BREQ n # before it becomes a [...]

Datasheet 97 Signals Reference A.1.22 DBSY_C2# (O) DBSY# is a copy of the Data Bus Busy sign al. This copy of the Data Bus Busy signal (DBSY_C2#) is an output only . A.1.23 DEFER# (I) The DEFER# signal is asserted by an agent to indi cate that the transaction cannot be guaranteed in- order completion. Assertion of DEFER# is norm all y the responsib[...]

98 Datasheet Signals Referenc e The Deferred Reply agent transmits the DID[9:0] # (Ab[25:16]#) signals received during the original transaction on the Aa[25:16]# signals duri ng the Deferred Reply transaction. This process enables the origin al requesting agent to make an identifier match with the o riginal request that i s awaiting completi on. A.[...]

Datasheet 99 Signals Reference A.1.33 FCL# (I/O) The Flush Cache Line (FCL#) signal is driven to the bus on the second clock of the Request Phase on the A[6]# pin. FCL# is asserted to indicate that the memory trans action i s initiated by the global Flush Cache ( FC ) instruction . A.1.34 FERR# (O) The FERR# signal may be asserted to indicate a pro[...]

100 Datasheet Signals Referenc e A.1.39 IGNNE# (I) IGNNE# is ignored in the Itanium 2 processor system environment. A.1.40 INIT# (I) The Initialization (INIT#) signal triggers an unm aske d interrupt to the processor . INIT# is usually used to break into hanging or idle processor states. Semanti cs required fo r platform compatibility are supplied [...]

Datasheet 101 Signals Reference A.1.44 LINT[1:0] (I) LINT[1:0] are local interrupt signals. These pins are disabled after RESET# . LINT[0] is typically software configured as INT , an 8259-compatible maskable in terrupt request sig nal. LINT[1] is typically software configured as NMI, a non-m askable interrupt.Both signals are asynchronous inputs. [...]

102 Datasheet Signals Referenc e All receiving agents observe th e R EQ[5:0]# signals to determ ine the transaction type and participate in the transacti on as necessary , as shown in T able A-10 . A.1.51 RESET# (I) Asserting the RESET# signal rese ts all processors to known st ates and invalidates all caches without writing back Modified (M state)[...]

Datasheet 103 Signals Reference A correct parity signal is high if an even number of covered si gnals are low and low if an odd number of covered signals are low . This definition allow s parity to be high when all covered signals are high. A.1.53 RS[2:0]# (I) The Response Status (RS[2:0]#) signals are driven by the responding agent (the agent resp[...]

104 Datasheet Signals Referenc e A.1.59 STBn[7:0]# an d STBp[7:0]# (I/O) STBp[7:0]# and STBn[7:0]# (and DRDY #) are used to transfer data at the 2x transfer rate in lieu of BCLKp. They are driven by the data transfer agent with a tight skew relationship with respect to its corresponding bus signals, and are us ed by the receiving agent to captu re [...]

Datasheet 105 Signals Reference A.1.64 THRMALERT# (O) THRMALER T# is asserted when the measured temperature from the processor thermal diode equals or exceeds the temperature thres hold data programmed in the hi gh-temp (THIGH) or low- temp (TLOW) registers on the sensor . This sign al can be used by the platform to implement thermal regulation fea[...]

106 Datasheet Signals Referenc e SBSY_C1# Low BCLKp Data SBSY_C2# Low BCLKp Data TDO High TCK T AP THRMTRIP# Low Asynchronou s Error THRMALERT# Low Asynchronous Error T able A-13. Input Signals Name Active Level Clock Signal Group Qualified BPRI# Low BCLKp Arbitration Always BR1# Low BCLKp Arbitratio n Always BR2# Low BCLKp Arbitratio n Always BR3#[...]

Datasheet 107 Signals Reference T able A-14. Input/Output Signals (Single Driver) Name Active Level Clock S ignal Group Q ualified A[49:3]# Low BCLKp Request ADS#, ADS#+1 ADS# Low BCLKp Request Always AP[1:0]# Low BCLKp Request ADS#, ADS#+1 ASZ[1:0]# Low BCLKp System Bus ADS# A TTR[3:0]# Low BCLKp System Bus ADS#+1 BE[7:0]# Low BCLKp System Bus ADS[...]

108 Datasheet Signals Referenc e[...]