Intel SA-1100 Bedienungsanleitung

Intel ® StrongARM ® SA-1 100 Microprocessor Developer’s Manual August 1999 Order Num ber: 27808 8-004[...]

SA-1100 Develop er’ s Man ual Informati on in this docum ent is provid ed in connection with Intel pro ducts. No licens e, express or i mplied, by estop pel or othe rwise , to any intellectual property rights is g ranted by this docu ment. Excep t as provi ded in Inte l’s T erms an d Condit ions of Sa le for such p roducts, In te l assumes no l[...]

SA-1100 De velop er’s M anual iii Contents 1 Introducti on............ ................... .................... ............ .................... ................... ............ . ... 1-1 1.1 Intel® Str ongARM® S A-1100 Mi croproce ssor ............. ................... .................. 1-1 1.2 Overview .......................... ...........[...]

iv SA-1100 De velop er’ s Man ual 5.2.11 Regis ters 10 – 12 RES ERVED ........ ................... ................... ............... 5-6 5.2.12 Register 13 – Process ID Virtual Address Mapping.. ............. ............... 5 -7 5.2.13 Register 14 – Debug Su pport (Breakpo ints) ............. .................... ........ 5-8 5.2.14 Regi[...]

SA-1100 De velop er’s M anual v 9 System Control Mod ule ...... ................... ................... .................... ................... ............. ... 9-1 9.1 General-P urpose I/O .............. ............. .................... ................... ................... ..... 9-1 9.1.1 GPIO Reg ister Definiti ons...... ............. ..[...]

vi SA-1100 De velop er’ s Man ual 9.5.3.6 Booting Afte r Sleep Mod e ...................... ................... ............. 9- 29 9.5.3.7 Reviving th e DRAMs from Self-Refres h Mode ................ ...... 9-30 9.5.4 Notes on P ower Supply S equencing ..... ................... .................... ...... 9-30 9.5.5 Assume d Behavi or of an SA-1[...]

SA-1100 De velop er’s M anual vii 10.5.3 DRAM Access Foll owed by a Refres h Operatio n .. .................... ....... 10-25 10.6 PCMCIA Overview .......... ...... ....... ...... ............. ....... ...... ...... ....... ...... ....... ...... . 1 0-26 10.6.1 32-Bit Da ta Bus Opera tion ................. ............. ................... ......[...]

viii SA-1100 Deve lope r’s M anual 11.7.5.1Li nes Per Panel (LPP) ........ ................... ................... ........... 11-36 11.7.5.2Ve rtical Sync Pulse Wi dth (VSW) .... ................... ................. 11-36 11.7.5.3En d-of-Frame Line Clock Wa it Count ( EFW)............ ........... 11- 37 11.7.5.4Be ginning-of-Frame Line Clock Wa[...]

SA-1100 De velop er’s M anual ix 11.8.3.1U DC Disable (UDD) ............... ................... .................... ....... 11-64 11.8.3.2 UDC Active (UDA ) .......... ................... ................... ............. . 11-64 11.8.3.3B it 2 Rese rved .... ................... ................... .................... ....... 11-64 11.8.3.4E nd[...]

x SA-1100 De velop er’ s Man ual 11.9.1.5Data Field .............. ................... ................... ............. ........... 11-81 11.9.1.6CRC Fi eld ....... .................... ................... ................... ........... 11-81 11.9.1.7Ba ud Rate Generation . .................... ................... ................. 11-81 11.9.1[...]

SA-1100 De velop er’s M anual xi 11.9.9.5R eceive Transi tion Detect S tatus (RTD) (read/write, no ninterruptibl e) ......... ................... ................... . 11-99 11.9.9.6E nd of Frame Fl ag (EOF) (read-only, noninterrupti ble) .......... ................... ................... . 11-99 11.9.9.7C RC Error Status (CRE) (read-only, nonint[...]

xii SA-1100 De velop er’s M anual 11.10.10.4 Transm it FIFO S ervice Re quest Flag (TFS) (read-only, ma skable interrupt) ........ ............ .................... .. 11-122 11.10.10.5 Rec eive FIFO Serv ice Reque st Flag (R FS) (read-only, ma skable interrupt) ........ ............ .................... .. 11-122 11.10.10.6 Framin g Error Status[...]

SA-1100 De velop er’s M anual xiii 11.11.7.2Rec eive FIFO Service Request Flag ( RFS) (read-only, maskable i nterrupt) ................. .................... ..... 11-139 11.11.7.3Rec eiver Idle Status ( RID) (read/write, m askable in terrupt) .......... ................... ............ 11 -140 11.11.7.4Rec eiver Begin of Br eak Status ( RBB) (re[...]

xiv SA-1100 De velop er’s M anual 11.12.6.1A udio Transm it FIFO Service Re quest Flag (A TS) (read-only, ma skable interrupt) ........ ............ .................... .. 11-163 11.12.6.2A udio Rece ive FIFO Servic e Request Flag ( ARS) (read-only, ma skable interrupt) ........ ............ .................... .. 11-163 11.12.6. 3Telecom Tra n[...]

SA-1100 De velop er’s M anual xv 11.12.12 .1Transmit FIFO Not Full Flag ( TNF) (read-only, noninterrupti ble) .......... ................... .................. 11 -181 11.12.12 .2Receive FIFO Not Empty Fla g (RNE) (rea d-only, noninter ruptibl1 1-181 11.12.12 .3SSP Busy Flag (BSY ) (read-only, noninterrupti ble) .......... ................... ...[...]

xvi SA-1100 Deve lope r’s M anual 16.4 Instruction Re gister .......................... ................... ............. ................... ............. 16 -2 16.5 Public Ins tructions ....... .................... ................... ................... ............. ............. 16-2 16.5.1 EXTEST (000 00) ......... .................... ....[...]

SA-1100 De velop er’s M anual xvii Figures 1-1 SA-1100 Features..... .................... ............. ................... ................... .................. 1-1 1-2 SA-1100 Example System ............ ................... ................... .................... ........... 1-5 2-1 SA-1100 Block D iagram .. ................... ............. [...]

xvii i SA-1100 Deve loper’ s Man ual 11-24 HP-SIR Modu lation Ex ample ........... ................... ................... .................... .. 11-104 11-25 UART Frame Fo rmat for IrDA Tran smission (<= 115.2 Kbp s) .................. .. 11-105 11-26 4PPM Mod ulation E ncodings ................ ............. ................... ............[...]

SA-1100 De velop er’s M anual xix 10-5 DRAM Memory Size Options . .................... ................... ................... .............. 10-14 10-6 DRAM Row/Column Address Mult iplexing ...... ................... .................... ....... 10-14 11-1 Peripheral Co ntrol Mod ules’ Regis ter Width a nd DMA Po rt Size ........... ......... [...]

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SA-1100 SA-110 0 Devel oper’ s Manua l 1-1 Introduction 1 1.1 Int el ® StrongARM ® SA-1 100 Microprocessor The Intel ® StrongAR M ® SA-1 100 Micropr ocesso r (SA-1 100) is th e second member of t he StrongARM ® family . It is a high ly integrated communications microcontroller that inco rporates a 32-bit Stron gARM ® R ISC processor core, s[...]

1-2 SA-1100 Deve loper’ s Manual Introductio n T able 1- 1. Features of the SA-1 100 CP U for AA and EA Par ts • High Perfor mance — 150 Dhrys tone 2.1 MIPS @ 133 MHz — 220 Dhrys tone 2.1 MIPS @ 190 MHz • Low power (no rmal mode)† — <230 mW @1 .5 V/133 M Hz — <330 m W @ 1.5 V/200 MHz • Integrated clock generation — Interna[...]

SA-1100 De veloper’s M anual 1-3 Introductio n T able 1-3. Changes to the SA-1 100 Cor e from the SA-1 10 • Data cache reduced fro m 16 Kbyte to 8 Kbyte • Interrupt vector addr ess adjust capability • Read buffer (nonblo c king ) • Minicache for alternate data cachin g • Hardware breakpoints • Memory-managemen t unit (MMU) enhancement[...]

1-4 SA-1100 Deve loper’ s Manual Introductio n 1.2 Overview The SA-1 100 Micropr ocessor (SA-1 100) is a general-purpose, 32- bit RISC microprocessor with a 16 Kbyte instruction cache, an 8 Kbyte write-back data cache, a minicache, a write buffer , a read buffer , and a memory management unit (MMU) combined in a single chip. The SA-1 100 is softw[...]

SA-1100 De veloper’s M anual 1-5 Introductio n The instruction set comprises eight basic instruction type s: • T wo make use of on-chip arithmetic logi c unit, barrel shifter , and mult iplier to perform high-speed operations on data in a bank of 16 logical regi sters (31 physic al registers), each 32 bits wide. • Three classes of instruction[...]

1-6 SA-1100 Deve loper’ s Manual Introductio n 1.4 ARM™ Architecture The SA-1 100 implements the AR M V4 arch itecture as defined in the ARM A rchitectur e Refer ence , 28-July-1 995, with the foll owing optio ns: 1.4.1 26-Bit Mode The SA-1100 supports 26-bit mode but all exceptions are initi ated in 32-bit m ode. The P an d D bits do not af fe[...]

SA-1100 De veloper’s M anual 1-7 Introductio n 1.4.6 W rite Buffer The SA-1 100 has an eight-ent ry write buffer with each en try able to contain 1 to 16 by t es. A drain write bu ffe r operation is supported . 1.4.7 Read Buffer The SA-1 100 h as a fo ur -en try read b uf fer capable of l oading 1 , 4, or 8 words o f d ata per entr y . This facil[...]

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SA-1100 De veloper’s M anual 2-1 Functional Description 2 This chapter provid es a functional description of the Intel ® StrongARM ® SA-1 100 Microprocessor (SA-1 10 0 ). It describes the basic bu ilding bloc ks within the processo r , lists an d describes the pins, and explains the memo ry map. 2.1 Block Diagram The SA-1 10 0 consists of the f[...]

2-2 SA-1100 Deve loper’ s Manual Functiona l Descript ion Figur e 2-1 shows the functional blocks contained in the SA-1 100 integrated pro ces sor . Figure 2- 2 is a funct ional di agram of the SA-1 100. Figure 2-1. SA-1 100 Block Diagram A6832-01 Serial Channel 0 UjSB Serial Channel 2 IrDA Serial Channel 3 UART Serial Channel 1 SDLC JTAG and Mis[...]

SA-1100 De veloper’s M anual 2-3 Func tion al De script ion 2.2 In puts/Output s Figure 2-2. SA-1 100 Functional Diagram A6975-01 Intel ® StrongARM ® * SA-1100 [208-pins] L_DD(7:0) L_FCLK L_LCLK L_PCLK L_BIAS GP(27:0) TXD _2 RXD _2 TXD_1 RXD _1 UDC+ UDC- nCAS(3:0) nRAS/(3:0) nOE nWE nCS(3:0) nPOE nPWE nPIOR nPIOW nPCE<2:1> PSKTSEL nPREG n[...]

2-4 SA-1100 Deve loper’ s Manual Functiona l Descript ion 2.3 Signal D escription The following t able desc ribes the si gnals. Key to Si gnal T ypes: n – Active lo w signal IC – Input, CMOS thres hold ICOCZ – Input, C MOS th reshold, output CMOS l evels, tris tatable OCZ – Output, CMOS levels , tristatable T able 2-1. Signal Desc ription[...]

SA-1100 De veloper’s M anual 2-5 Func tion al De script ion L_FCLK OCZ LCD frame clock. L_LCLK OCZ LCD line clock. L_PCLK OCZ LCD pixel clock. L_BIAS OCZ LCD ac bias drive. TXD_C OCZ CODEC tr ans m it. RXD_C IC CODEC re ceive. SCLK_C OCZ CODEC clock. SFRM_C OCZ CODEC frame signal. UDC+ OCZ Serial port zero transmit pin (UDC). UDC- IC Serial port [...]

2-6 SA-1100 Deve loper’ s Manual Functiona l Descript ion nRESET_OUT O CZ Reset out. This signal is asserted when nR ESET is ass erted and deasserts when the processor has completed resetting. nRESET_OUT is also asserted for "soft" reset events (sleep and watchdog). nTRST IC T est interface re set. Note this pin has an internal pull-dow[...]

SA-1100 De veloper’s M anual 2-7 Func tion al De script ion 2.4 Memory Map Figur e 2-3 shows the SA-1100 memory map. The ma p is divided int o four main part itio ns of 1 Gbyte each. The bottom partition is ded icated to static memory devices (RO M , S RAM, and Flas h) and to the PCMCIA expan s ion bus area. I t occup ies address es 0h0000 000 0 [...]

2-8 SA-1100 Deve loper’ s Manual Functiona l Descript ion Figure 2-3. SA-1 100 Memory Map 0h0000 0000 512 Mbyte Static Memory Internal Registers PCMC IA In terfa ce 512 Mbyte 1GB 512 Mbyte 0h8000 0000 0h4000 0000 Dynamic Memory DRAM Bank 3 (128 Mbyte) DRAM Bank 2 (128 Mbyte) DRAM Bank 1 (128 Mbyte) DRAM Bank 0 (128 Mbyte) 0hC000 0000 Reserved (1G[...]

SA-1100 De veloper’s M anual 3-1 ARM ™ Implementation Options 3 The following sections describe ARM™ architecture options that are implemented by the Intel ® Strong A RM ® SA-1 100 Microp rocessor (SA-1 100). 3.1 Big and Little En dian The big endian b it in the control register sets whether the SA-1 100 treats word s stored in m emory as b[...]

3-2 SA-1100 Deve loper’ s Manual ARM ™ Im plementat ion Options transfer the whole 32 -bit value, and not just the fl ag o r control fields. When multiple ex ceptio ns arise simultan eously , a fixed priority determin es the order in whi ch they are handled. The prio rities are listed later in th is ch apter . Most exceptions are fully defined [...]

SA-1100 De veloper’s M anual 3-3 ARM ™ I mplementat ion Opti ons 3.2.3 Abort An abort can be signalled by the internal memory-management unit, through a data breakpoint, or by a reference to reserved memory . An abor t indicates that the cu rrent memory access cannot be completed or that a prespecified break point address and (op tionally) data[...]

3-4 SA-1100 Deve loper’ s Manual ARM ™ Im plementat ion Options 3.2.4 V ector Summary Ta b l e 3 - 1 lists byte addresses, an d they normally contai n branch instructi ons pointing to the relevant routines. These addr esses (except the reset vector) can be c h anged (to 0x FFFF xxxx) through the vector adjust facility (bit 13, register 1, copro[...]

SA-1100 De veloper’s M anual 3-5 ARM ™ I mplementat ion Opti ons 3.2.6 Inte rrupt Latencies and Enable Timi n g The ability to recogni ze an IRQ or F IQ interrup t is , in part, determined by the I and F b its of the CPSR. T o ensure that a pending interrup t is tak en, an interrupt-enabl ing write to CPSR (msr instruction) mus t be s eparated [...]

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SA-1100 De veloper’s M anual 4-1 Instruction Set 4 This section des cribes the instruction timin g for the Intel ® StrongARM ® SA-1 1 00 Microproces so r (SA-1 100). 4.1 Instruction Set The SA-1 100 implem ents the AR M ™ V4 architecture as defined in the ARM Ar ch itectur e Refer ence, 28-Jul y-1995, with prev iously noted o ptions and addi [...]

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SA-1100 De veloper’s M anual 5-1 Coprocessors 5 The operation an d configur ation of the Intel ® St rongARM ® S A-1 100 Micr oprocesso r (SA-1 100) is controlled with coprocessor instructions, co nfiguration pins, and memory-managemen t page tables. The coprocessor 15 inst ructions manipulate o n -chip regi sters that control the configur ation[...]

5-2 SA-1100 Deve loper’ s Manual Copr ocessor s 5.2 Cop rocessor 15 Definitio n The SA-1 100 coprocessor 15 contains registers t hat control the cache, MMU, an d write buffer operation as well as some clocking functions. These registers are accessed using CPR T instructions to coprocessor 15 with the processor in any privileged mode. Only some of[...]

SA-1100 De veloper’s M anual 5-3 Coproc essors 5.2.2 Register 1 – Control Register 1 is a read/write register containing control bits. All writable bits in this register are forced low by reset. The shaded bits (also labeled r) are res erved and are not readable or w ritable. M bit 0 Enable/di sable 0 – On-chip memory-management unit disabled[...]

5-4 SA-1100 Deve loper’ s Manual Copr ocessor s 5.2.3 Regis ter 2 – T ranslation T able Base Register 2 is a read/write register that hold s the base of the currently active level 1 pag e tabl e. Bits <13:0> are u ndefined o n read, ignored on write. 5.2.4 Register 3 – Domain Access Control Register 3 is a read/write register that holds[...]

SA-1100 De veloper’s M anual 5-5 Coproc essors 5.2.8 Register 7 – Cache Control Operatio ns Register 7 is a write-only register . The CRm and OPC_2 fields are used to encode the cache control operations . Operation for all other values for OPC_2 and CRm is unpr edictable. 5.2.9 Regist er 8 – TLB Operations Register 8 is a write-only reg i ste[...]

5-6 SA-1100 Deve loper’ s Manual Copr ocessor s 5.2.10 Register 9 – Read-Buffer Operations The read buf fer is controlled and accessed throug h register 9 of coprocessor 15. The functions support ed are: fl ush-all buf fers, flush-a-sin g le entry , load-an-entry ( 1, 4 or 8 wor ds), and enable/disable user mode access. The CRm and OPC_2 fields[...]

SA-1100 De veloper’s M anual 5-7 Coproc essors 5.2.12 Register 13 – Proce ss ID V irtual Address Mapping The SA-1 100 suppo rts th e remap ping of v irt ual add ress es thro ugh a pro cess ID (P ID) regis ter . The 6-bit PI D value is OR’ed with bi ts 30..25 of the v irtual add ress when bit s 31..25 of the vir t ual address are zero. This ef[...]

5-8 SA-1100 Deve loper’ s Manual Copr ocessor s 5.2.13 Register 14 – Debug Support (Bre akpoints) The SA - 1 100 sup ports address a nd data break po ints thr ou gh regi ster 14 of copro cessor 15 . The instruction for mats follow . For a description of the b reakpoint operation, see Chapter 15, “Debug Suppo rt” . The following table shows [...]

SA-1100 De veloper’s M anual 5-9 Coproc essors 5.2.14 Register 15 – T est, C lock, and Idle Control Register 15 is a write-only r egis ter . The CRm and OPC_2 fields are used to encode the following control op erations. Op eration for all other values of OPC_2 and CRm is u npredictabl e. Function OPC_2 CRm Enable odd-word loading of the linear [...]

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SA-1100 De veloper’s M anual 6-1 Caches, W rite Buf fer , and Read Buf f er 6 T o reduce effective memo ry access time, the Intel ® St rongARM ® SA-1 100 Micr oprocessor (SA-1 100) has an instruction cac he, a data cache, a write buff er, and a read buffer . All except the read buf fer are transparent to program executio n. The following sectio[...]

6-2 SA-1100 Deve loper’ s Manual Caches, W rite Buffer, and Read Buffe r 6.1.3 Icache Enable/Di sable and Reset The Icache is automatically di sabled and flushed on the ass ertion o f nRESET . Once enabled, cacheable read accesses cause lines to be p laced in the cache. If the Icache is subsequently disabled, no new lines are placed in the cache,[...]

SA-1100 De veloper’s M anual 6-3 Caches , Write Buff er , and R ead Buffer memory-managem ent page table. For this reason, in order to use the Dcaches, the MMU mu st be enabled. The two fun ctions may be enabled s imultaneously with a single write to the control register . Note: The Dcaches operate with virtual addresses, so care must be taken to[...]

6-4 SA-1100 Deve loper’ s Manual Caches, W rite Buffer, and Read Buffe r 6.2.3 Software Dcache Flush The SA-1 100 supports the flush and c lean operations on single entries of the Dcaches by writes to the cache operations registers. The flush whole cache is also supported. Note that since this is a write-back cache, in ord er to prevent the loss [...]

SA-1100 De veloper’s M anual 6-5 Caches , Write Buff er , and R ead Buffer 6.2.4.1 Ena bling the D caches T o enable the D caches, make sure that the MMU is enabled first by setting b it 0 in the control register , then enable the Dcaches by setting bit 2 in the control register . The MMU and Dcach es can be enabled simu ltaneously with a single [...]

6-6 SA-1100 Deve loper’ s Manual Caches, W rite Buffer, and Read Buffe r 6.3.2.2 Writes to a Bufferable and Noncacheable Location (B=1,C=0) If the write buf fer is enabled and the pr ocesso r performs a write to a b ufferab le but noncacheable location and misses in the Dcaches, the data is placed i n the write buf fer and the CPU continues execu[...]

SA-1100 De veloper’s M anual 6-7 Caches , Write Buff er , and R ead Buffer Any two data w ords with the same virtual address may n ot be contained in th e RB at the same time. If an RB allocate references a data word that is already contained in another RB entry , then the old RB entry is invalidated and the new allocation is performed. It is po [...]

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SA-1100 De veloper’s M anual 7-1 Memory-Management Unit (MMU) 7 This chapter describes the memor y -management functions. 7.1 Overview The Intel ® StrongAR M ® SA-1 100 Micropr ocessor (SA-1 100) implemen ts the stan dard ARM ™ memory-management fun ctions using two 32-entry fully associative translation buff ers (TBs). One is used for instru[...]

7-2 SA-1100 Deve loper’ s Manual Memory -Mana gem ent Unit (MMU) 7.3.1 Cacheable Reads (Linefetc he s) A linefetch can be safely aborted on any word in the transfer . If an abort occur s during the linefetch, the cache is purged so it will not contain invalid data. If the abort happens before the word that was requested by the access is returned,[...]

SA-1100 De veloper’s M anual 7-3 Memory-Ma nageme nt Unit (MMU) Note: Care must be taken if the translated addr ess dif fers from the untranslated address because the three instructions follo win g the enabling of th e MMU will h ave been fetched using “flat translati on” , and enabling the MMU m ay be considered a branch with delaye d execut[...]

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SA-1100 De veloper’s M anual 8-1 Clocks 8 This section des cribes the Intel ® Stro ngARM ® SA-1 100 Microprocessor (SA-1 100) clocks. The following d iagram shows the d istributio n o f clocks in the SA-1100. The 3.6864-MHz os cillato r feeds both PLLs. The pr i mary PLL prov ides clocks for the core lo gic and a 7.36-MHz clock for several of t[...]

8-2 SA-1100 Deve loper’ s Manual Clocks 8.2 Core Clo ck Configuration Register The core clock freq uency is configured by software through the core cl ock config uration field (CCF<4:0>) in the power manager phase-lock ed loop (PLL) con figuration r egister (PPCR) . This field shou ld be programm ed during the boot s equence for t he desire[...]

SA-1100 De veloper’s M anual 8-3 Clocks 8.3 Driving SA-1 100 Crystal Pins from an Extern al Source In most applicatio ns , a 3.6864-MHz crystal will be con n ected between the PXT AL and the PEXT AL pins. Similarly , a 32.768-kHz crystal will be connected bet ween th e TXT AL and TEXT AL pins. In some applications, supplying these clocks from an [...]

8-4 SA-1100 Deve loper’ s Manual Clocks If the PXT AL or TXT AL pin is driven above the voltage indi cated, there will be no permanent damage to the p rocessor for pin vol tages less than 2.5 V . However , ESD diodes on these pins will attempt to clamp the voltage at appro ximately 1.5 V . Th e clamping action results in significant noise injecte[...]

SA-1100 De veloper’s M anual 9-1 System Control Module 9 This chapter describes the system contro l module that co ntrols several processor -wide system functions. The units con tained in th e system co ntro l mod ule are: the g eneral- pur pose I/O po rts, the interrupt controller , the real-time clock, the o p erating system timer , the power m[...]

9-2 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.1.1 GPIO Register Definitions There are a total of eight registers within the GPIO control block: o ne is used to monitor pin state; two are used to con trol pin state; on e is used to control pin direction; two are used to specify a p in’ s edge type that should be detected; and one i[...]

SA-1100 De veloper’s M anual 9-3 Syste m Control Mo dule 9.1.1.1 GPI O Pin-Level Regist er (GPLR) The state of each o f the GPIO port pins is visible throu gh the GPIO pin-level register (GPLR). Each bit n umber corresp onds to th e port p in number from bit 0 to bi t 27. This i s a read-only reg ister that is used to determine the cur r ent leve[...]

9-4 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.1. 1.2 GPIO Pin Direct ion Regist er (GPDR) Pin direct ion is controlle d by pro gramming the GPI O pin d irection regis ter (GPDR). The GPDR contains one direction con trol bit for each of the 2 8 port pins. If a direction bit is programmed to a one, the port is an outpu t. If it is pro[...]

SA-1100 De veloper’s M anual 9-5 Syste m Control Mo dule 9.1.1.3 GPIO Pin Output Set Regi ster (GPSR) and Pin Output Clear Register (GPCR) When a port is configured as an output, the user controls the state of the pin by writing to either the GPIO pin o u tput set register (GPSR) or the GPIO pin ou tput clear register (GP CR). An outp u t pin is [...]

9-6 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.1.1.4 GPIO Rising-Edge Detect Register (GRER) and Falling-Edge Detect Register (GFER) Each GPIO port can also be p rogrammed to detect a rising-edge, fa l ling-edge, or either transition on a pin. When an edge is detected that matches the type o f edge programmed f or the pi n, a statu s[...]

SA-1100 De veloper’s M anual 9-7 Syste m Control Mo dule 9.1.1.5 GPI O Edge Detect Status R egister (GEDR) The GPIO edge detect status reg ister (GEDR) contains 28 status bits that correspo nd to the 28 GPIO port pins . When an edg e detect occurs on a pi n that matches the type of edge progr ammed in the GRER and/or GFER registers, the co rrespo[...]

9-8 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.1.1.6 GPIO Alternate Function Register (GAFR) The GPIO alternate function reg is ter (GAFR) contains 28 contro l bits that corr es pond to the 28 GPIO port pins. When the pro ces sor sets a bit in the GAFR, the corresponding GPIO p in is switched over to that pin’ s alter nate function[...]

SA-1100 De veloper’s M anual 9-9 Syste m Control Mo dule 9.1.2 GPIO Alte rnate Fun ctions Most GPIO pins have an alternate function that can be in v oked to enable additio nal fu nctionality within the SA-1 1 00. If a GPIO is used for this alternate fun ctio n, th en it can not be used as a GPIO at the same time. Pins 0 and 1 are reserved becau s[...]

9-10 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.1.3 GPIO Register Locations The following table shows the re gisters associated with the GPIO block and the physical a ddre sses used to access them. Address Name Description 0h 9004 0000 GPLR GPIO pin-level register 0h 9004 0004 GPDR GPIO pin direction register 0h 9004 0008 GPSR GP IO [...]

SA-1100 De veloper’s M anual 9-11 Syste m Control Mo dule 9.2 Interrupt Contro ller The SA-1 100 interrupt co ntroller provides masking capability for all interrupt sources an d combines them into their fi nal state, either an FIQ or IRQ p rocessor interrupt. The inte rrupt hierarchy of the SA-1 100 is a two-l evel struct ure. The fir s t level o[...]

9-12 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.2.1.1 Interrupt Cont roller Pending Register (ICPR) The ICPR is a 32-bit read-only reg ister that shows all active interrupts in the system. These bits are not affected by the state of the mask register (ICMR). The f o llowing table shows the pending interrupt source assigned to each bi[...]

SA-1100 De veloper’s M anual 9-13 Syste m Control Mo dule 9.2.1.2 Interrupt Controller IRQ Pending Register (ICIP) and FIQ Pending Regist er (ICFP) The ICIP and the IC FP contain one flag per interrup t (32 total) that indicates an interrupt request has been made by a unit. Inside the interrupt service ro utine, the ICIP and IC FP are read to det[...]

9-14 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.2.1.3 Interrupt Cont roller Mask Register (ICMR) The inter rupt contro ller mask register (ICMR) contains on e mask bit per pe nding int errupt b it (32 total). The mask b its co ntrol whether a pendin g interrupt bit will generate a processo r int errupt (IRQ or FIQ). When a pending in[...]

SA-1100 De veloper’s M anual 9-15 Syste m Control Mo dule 9.2.1.4 Interrupt Controller Level Register (ICLR) The interrupt controller level register (ICLR) cont rols whether a pending interrupt generates an FIQ or an IRQ CPU in terrup t. If a pending i nterr upt is unmasked, th e corr espond ing IC LR bit fiel d is decoded to select which CPU int[...]

9-16 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.2.1.5 Interrupt Cont roller Control Register (ICCR) The interrupt controll er control register (ICCR) contains a single control bit, the disable idle m ask bit (DIM). When set, this bit inhibits the idle mo de operation where the output of the ICMR is OR’ed to all ones. If this bit is[...]

SA-1100 De veloper’s M anual 9-17 Syste m Control Mo dule 9.2.2 Interrupt Controller Register Locations The following table shows th e registers associated with the in terrupt controller block and the physical addresses used to access them. 9.3 Real-Time Clock The SA-1 100 contains a real-time clock (R TC) that p rovid es a general-p urp ose real[...]

9-18 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.3.2 RTC Alarm R egister (RT AR) The real-time clock alarm register is a 32-bit register that is readable and writable by the processor . Following each rising edg e of the 1- Hz clock, this r egister is compared to the RCNR. If the two are equal and th e enable bit is set, then the alar[...]

SA-1100 De veloper’s M anual 9-19 Syste m Control Mo dule 9.3.4 RTC T rim Register (RTTR) The R TTR is prog rammed by the user to select the frequency o f the 1-Hz clock. If this register is not programmed and left at its reset value (all zeros), then the 1-Hz clock will actually be running at 32.768 kHz. See the follow ing section for details on[...]

9-20 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.3.5.2 RTTR V alue Calculations After the true frequency of th e oscillator is known , it mu st b e split into integer and fraction a l portions. Th e integer portion of the value (minus one) is load ed into the C0-C15 field of the R TTR. This val ue is compared agai nst a 16-bit cou nte[...]

SA-1100 De veloper’s M anual 9-21 Syste m Control Mo dule This trim setting leaves an error o f .16 cycles pe r 1023 seconds. Th e error calculation yields (in parts-per-million or p pm): Maximum Error Calculation V ersus Real-Time Clock Accuracy As seen from trim example #2, the maximu m possible erro r approaches 1 clock per 2 10 -1 seconds. Ca[...]

9-22 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.4.1 OS Ti me r Co unt Register (OSCR) The OS timer count reg ister is a 32-bit counter th at increments on rising edges of the 3 .6864-MHz clock. This counter can be read or written at any time. It is recommended th at the system write-protect this register through the MMU protection me[...]

SA-1100 De veloper’s M anual 9-23 Syste m Control Mo dule 9.4.4 OS T imer Status Register (OSSR) This status register contains status bits indicating whether a match has occurred on any of the f our match registers. These bits are set when the event occurs (follo wing the rising edge of the 3.6864-MHz clock) and cleared by writing a one to the pr[...]

9-24 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.4.5 OS T imer Interru pt Enable Register (OIE R) This register contains fou r enable bits indicating whether a match between one of the match registers and the OS tim e r coun ter will s et a status bit in the OSS R. Each m atch register has a corresponding enable bit. C learing an enab[...]

SA-1100 De veloper’s M anual 9-25 Syste m Control Mo dule 9.4.7 OS T imer Register Locations Ta b l e 9 - 1 shows the registers associated with the OS timer and the physical addresses used to access them. T able 9-1. OS T ime r Register Loc ations Address Name Description 0h 9000 0000 OS MR<0> O S timer match registers<3:0> 0h 9000 00[...]

9-26 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.5 Po wer Manager The SA-1 100 co ntains power management logic that co ntrols the transition between three dif fer ent modes of operation: r un, idle, and sleep. Th es e mode s are used to reduce processor po w er consumption at times when so me functions are no t needed, or when the sy[...]

SA-1100 De veloper’s M anual 9-27 Syste m Control Mo dule 9.5.2.2 Exiting Idle Mod e Any enabled interrupt from the system unit or peripheral un it will cause a transition from idle mode back to run mode. Note that the interru pt co nt roller (ICMR) mask register is ignored during idle mode, meani ng that an int errupt does not need to be unmaske[...]

9-28 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.5.3.3 The Sleep Shutdow n Seque nce The sleep state machine begins the shutdo wn sequence. This sequence co nsists of three steps. • In the first step, the following act ions occur: a. P ower manager switches the GPIO ou t put pins to their sleep state. Th is sleep state is programmed[...]

SA-1100 De veloper’s M anual 9-29 Syste m Control Mo dule • In the first step of the wake- up sequence, the following action s occur: a. The PW R_EN pin is asserted, indicating that the external supply must appl y power on the VDDI pins. b. An internal timer begins to tim e the power ramp. This tim er wait s for app roximately 10 ms. c. Th e 3.[...]

9-30 SA-1100 Deve loper’ s Manual System Cont ro l Modu le Also, the S A-1100 p rovides the power manager scratchpad regis ter (PSPR) f o r saving any general processor state during s leep. This reg ister may be written by the processor and the contents will survive sleep mod e. The bits in this register are not expli citly used by the SA-1 1 0 0[...]

SA-1100 De veloper’s M anual 9-31 Syste m Control Mo dule Figure 9-3. T ransitions Between Mo des of Operation T able 9-2. SA-1100 Power and Cloc k Supply Sources and S tates During Power-Down M odes Power Ma nageme nt Mode Modu le Supp ly So u rc e Run Idle Sleep Pwr Clk Pwr Clk Pwr Clk Pwr Clk CPU VDD 3.686 4 MHz On Running O n Stoppe d Disable[...]

9-32 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.5.6 Pin Operation in S leep Mode The SA-1 100 pins are categorized by th e fo llowi ng t ypes b ased on t heir behavi or duri ng sl eep mode: T ype 1 – T hese pins are outputs and are driven low d uring sleep. These pins hold their state after sleep mode is exi ted until the DRAM_con [...]

SA-1100 De veloper’s M anual 9-33 Syste m Control Mo dule 9.5.7 Power Mana ger Registers The power manag er is controlled thro ugh eight 32- bit registers . The power manager co ntrol register (PMCR) is used to allow software invocatio n of sleep mode. The sleep status register (PSSR) contains status bits that indicate why sleep m ode was invoked[...]

9-34 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.5.7.2 Power Manager General Configuration Register (PCFR) The PCFR co ntains bits used to configure various fu nctions within the SA-110 0. The OPDE bit, i f set, allows t he 3.6864- MH z osci llator t o be disabl ed during s l eep mo de. This bi t is cleared on the assertion of nRESET [...]

SA-1100 De veloper’s M anual 9-35 Syste m Control Mo dule 9.5.7.3 Power Manager PLL Configuration Register (PPCR) The PPCR contains bits used to conf igur e the core oper ating freq uency gener a ted by the PLL. The following tab le shows the bit-field definitio ns for this register . See Chapter 8, “Clocks” fo r the frequencies generated thr[...]

9-36 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.5.7.4 Power M anager W ake-Up E nable Register (PWER) The following table s hows the location of all wake-u p interrupt enable bits in th e PWER. For a GPIO to serve as a wake-up source, it must be pro gramm ed as an input in the GPDR. When a fault condition is detected in the VDD_F AUL[...]

SA-1100 De veloper’s M anual 9-37 Syste m Control Mo dule 9.5.7.5 Power Manager Sleep Status Register (PSSR) PSSR contains five status flags. The software sleep status flag is set when sleep mode is entered as a result of the force sleep (FS) control bit b eing set by the CPU. The battery faul t status bit is set any time the BA TT_F AUL T pin is[...]

9-38 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 3D H DRAM control hold. This bit is set upon ex it from sleep mode and indicates that the RAS<3:0> and CAS <3:0> continue to be held low and th at the DRAMs are still in self-refresh mode. This bit should be cleared by the processor (by writing a one to it) after the DRAM inte[...]

SA-1100 De veloper’s M anual 9-39 Syste m Control Mo dule 9.5.7.6 Power Manager Scratch Pad Register (PSPR) The power manag er als o contains a 32-bit reg ister to save processor con figuration inform at ion in any format the u ser desires. The power m anager scratch p ad register (PSPR) is a h olding register that is powered by the VDDx power su[...]

9-40 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.5.7.8 Power Manager Oscillator Status Register (POSR) The power manager oscillat or status re gister (POSR) is a singl e-bit, read-on ly regist er that contains a status bit indicat ing whether the 32.768-kHz os cillator is up to speed after a hardware reset. This bit is set after the e[...]

SA-1100 De veloper’s M anual 9-41 Syste m Control Mo dule 9.6 Reset Controller The reset controller manag es the various reset sources within the SA-1 100. From a programmer’ s view , it is visible as two registers: one used to invoke sof tware reset and one to read status after booting to indicate why t he proc essor was res et. The four types[...]

9-42 SA-1100 Deve loper’ s Manual System Cont ro l Modu le 9.6.1 R eset Controller Registers The reset controller co ntains two registers, the reset contr oller software reset regis t er (RSRR) and the reset controller reset s tat us register (RCSR). 9.6. 1.1 Reset Controller S oftware Reset Register (RS R R) The reset controller software reset r[...]

SA-1100 De veloper’s M anual 9-43 Syste m Control Mo dule 9.6.1.2 R es et Control ler Stat us Re gister (R C SR) The reset controller reset status reg is ter (RCSR) is used by the CPU to determine the last cause or causes of t he reset. The SA-1 100 has f our sources of rese t: • Hardware reset • Software reset • W atchdog r eset • Sleep [...]

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SA-1100 De veloper’s M anual 10-1 Memory and PCMCIA Control Module 10 The external memory bus interface for the Intel ® StrongAR M ® S A-1 100 Microprocesso r (SA-1 100) supp orts standard fas t-page and EDO asynchr onous DRAMs, burst an d nonburst ROMs, Flash EPROMs, SRAM, an d PCMCIA expans ion devices . It is programmable through the memory [...]

10-2 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule 4 byte selects, nCAS <3:0>, 12 bits of multiplex ed row an d column ad dresses, nWE, an d nOE. The SA-1 100 performs CAS before RAS refresh ( CBR) during normal operation and supports self-refres hin g DRAMs during power -down sleep mode. • Static Memory Interface The sta[...]

SA-1100 De veloper’s M anual 10-3 Memory an d PCMCIA Co ntrol Modul e 10.1.1 Example Memory System Figure 10-2 sho w s a sys tem us i ng 1M x 16 DRAMs for a to ta l of 16 Mbyte of DRAM. T wo banks of ROM and two b anks of Flash EPROM are sho wn, each on a 32 -bitwide databus. The PCMCIA interface is not sho wn. Figure 10-2. Example Memory Configu[...]

10-4 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule 10.1.2 T ypes of Memory Accesses The SA-1 100 performs memory accesses for the f ollowing operations: SA-1 100 will onl y genera te a subs et of all possible transact ions on the bus. Many of th ese transactions may be completed in ternal to the processor by accessing caches, the[...]

SA-1100 De veloper’s M anual 10-5 Memory an d PCMCIA Co ntrol Modul e 10.1.6 Read-Lock-W rite The read-lock-write sequence is generated b y an SWP instruction to a noncacheable/nonbu f ferable location. Locked access to memory i s ensured through internal arbitration o f access es to the memory contro l ler . 10.1.7 Abort s and Nonexistent Memory[...]

10-6 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule 10.2 Memory Con figuration Re gisters The SA-1 100 memory interface is program med through a s et of configu rati on register s that are described in the following sections. T able 10- 2 shows the registers associated with the memo ry interface and th e physical addresses used to[...]

SA-1100 De veloper’s M anual 10-7 Memory an d PCMCIA Co ntrol Modul e 10.2.1 DRAM Configuration Register (MDCNFG) MDCNFG is a read/write register and contains control b its for configuring the DRAM. All DRAM banks must be implemented with the same typ e of DRAM devices. Question marks indicate that the values are un known at reset. B i t 3 1 3 0 [...]

10-8 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule 31..17 D RI<14:0> DRAM refresh interval. The num be r o f memory clo ck cycles (di vided by 4) b et ween CAS befor e R AS (CBR) refre sh cycl es. One row is refre shed in ea ch DRA M bank dur ing each C BR re fresh cycle. The value that must be loaded into this register is [...]

SA-1100 De veloper’s M anual 10-9 Memory an d PCMCIA Co ntrol Modul e 10.2.2 DRAM CAS W a vefor m Shift Registers (MDCAS0, MDCAS1, MDCAS2) MDCAS0, MDCAS1, and MDCAS2 are 32- bit read/write registers that contain t he nCAS waveform for a full 8-beat burst read or write to asynchr onous DRAM. Each bit represents o n e CPU cycle if MDCNFG:CDB2 is 0 [...]

10-10 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule 10.2.3 Stati c M emory Control Registers ( MSC1–0) MSC1 and MSC0 are read/write regi sters and contain control bits for configuring s tatic memory selected by nCS<3:0>. Reset forces the valu es in these registers to the slowest possible nonburst ROM timing. T iming field[...]

SA-1100 De veloper’s M anual 10-11 Memory an d PCMCIA Co ntrol Modul e 1 When SMCNFGx:RT=01, accesse s to the selected bank will output a byte mask on nCAS<3:0> for bo th reads an d writes. Th is option sho uld be sele cted only when t here is no D RAM in the system. 12..8 RDNx<4:0> ROM delay next access. Number of memory c lock cycle[...]

10-12 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule 10.2.4 Expansion Memor y (PCMCIA) Configuration Register (MECR) MECR is a read/write register that contains control bits for configur ing the timing of the PCMCIA interface. This register is unaffected by reset; question marks indicate that the values are unknown at reset. W rit[...]

SA-1100 De veloper’s M anual 10-13 Memory an d PCMCIA Co ntrol Modul e T o calculate the recommended BS_xx value for each address space: divide the comm and width time (the greater of twIOW R and twIORD, or the greater of tw WE and twOE) by processor cycle time; divi de by 2; divid e again by 3 (numb er of BCLKs per comman d assertion); r ound up[...]

10-14 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule 10.3 Dynam ic Interface Operation This section describes the dynamic memo ry interface. 10.3.1 DRAM Overview The dynamic memor y interface supports up to four bank s of identical size and type dynamic memory on a 3 2-bit bus. Initialization soft ware must set up the memory i nte[...]

SA-1100 De veloper’s M anual 10-15 Memory an d PCMCIA Co ntrol Modul e 10.3.2 DRAM T iming The DRAM nCAS timin g is generated using s hift registers. The rate at which these shift registers are clocked is determined by MDCNF G:C DB2. The time at which to sample the read data is programmable t o coincide with t h e deassertion of n C AS or up to 3[...]

10-16 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule Figure 10-3 shows the rate of t he shift regis ters during DRAM nCAS timing for a s ingle-beat transaction. Figure 10-3. DRAM Single-Be at T ransactions A4777-01 CPU Clock Memory Clock ADDR Reads: Latch Input Data nOE TRP nRAS nCAS COL DO ROW ROW Writes: Input Data DO Write Data[...]

SA-1100 De veloper’s M anual 10-17 Memory an d PCMCIA Co ntrol Modul e Figure 10-4 s hows the rate of th e shift registers during DRAM nCAS timing fo r burst-of-eight transactions. Figure 10-4. DRAM Bur st-of-Eight T ransactions A4778-01 Memory Clock ADDR Input Data Latch Input Data (internal): Reads: TRP nRAS nOE Writes: Write Data nWE nCAS COL [...]

10-18 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule 10.3.3 DRAM Refresh The SA-1 100 provides support for CAS befo re RAS (CBR) refresh. When the DRAM interface is enabled [by s e ttin g any of MDCNFG:DE(3-0 ) and setting MDCNFG :DRI g reater than zero], the refresh counter starts counting up every memory cycle (2 CPU cycles) f r[...]

SA-1100 De veloper’s M anual 10-19 Memory an d PCMCIA Co ntrol Modul e The R T fields in the MSCx regi sters specify the typ e of mem ory (b urst- of-fo ur ROM, bu rst-of -eight ROM, nonb urst RO M, Flash, SRAM) and the RBW fields specify th e bus width for th e memory s pace selected by nCS<3:0>. If a 16- bit bus width is specified, tr ans[...]

10-20 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule Figure 10-6. Burst-of-Eight ROM Timing Diagram A4780-01 Memory Clock Note: One extra CPU cycle (1/2 memory cycle) is added to the first access after nCS is asser ted. In this example , MSC0:SCNFG0:RDF = 12 (decimal), RDN = 4, RRR = 2. nCS0 RDF+1.5 RDN+1 RDN+1 RDN+1 RDN+1 RDN+1 R[...]

SA-1100 De veloper’s M anual 10-21 Memory an d PCMCIA Co ntrol Modul e Figure 10-7. Eight Beat Bur st Read from Burst-of-Four ROM Figure 10-8. Nonburst ROM, SRAM, or Flash Read Timing Diagram – Four Data Beats A4781-01 Memory Clock nCS0 RDF+1.5 RDF+1 RDN+1 RDN+1 RDN+1 RDN+1 RDN+1 RDN+1 (2*RRR)+1 A[25:5] A[4] nOE Input Data Latch nCS1 Input Data[...]

10-22 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule 10.4.3 SRAM Interfac e Overvie w The SA-1 100 provides a 32-bit asynchro nous SRAM interface that uses the nCAS pins for byte selects on both reads and writes (nCS<3:0> selects the SR AM bank, nOE is asserted on reads, and nWE is asserted on writes ). Addres s bits A<25[...]

SA-1100 De veloper’s M anual 10-23 Memory an d PCMCIA Co ntrol Modul e In Figur e 10-9 , some of the parameters are defin ed as follows: tAS = Address setup to nCS = 1 CPU cy cl e tCES = nCS, nCAS setup to nWE = 2 memory clock cycles (4 CPU cycles) tASW = Address setup to nWE low (a sserted) = 1/2 memory cycle (1 CPU cycle) [For A<25:5>, tA[...]

10-24 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule 10.4.6 FLASH EPROM Timing Diagrams and Parameters Flash reads have the same timing as nonb urst ROMs as shown in the precedin g figures. Figure 10-1 0 show s th e timing for Flash writes . In Fi gure 10-10 , some of the parameters are def ined as follows: tAS = Address setup to [...]

SA-1100 De veloper’s M anual 10-25 Memory an d PCMCIA Co ntrol Modul e 10.5 General Memory B US T imin g This section explains the boundary cas es between DRAM, static, and refr esh operations. 10.5.1 S tatic Access Followed by a DRAM Access W ith a static memory access, nWE is deasserted 1 memory cl ock cycle prior to th e deass ertion of nCS. T[...]

10-26 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule 10.6 PCMCIA Overview The SA-1 100 PCMCIA interface provides controls for one PC MC IA card slot with a PSKTSEL pin for suppor t of a second s lot. This 16-bit host interface supp orts 8- and 16-bit peripherals and handles common memo ry , I/O, and attribute memory acc es ses . T[...]

SA-1100 De veloper’s M anual 10-27 Memory an d PCMCIA Co ntrol Modul e 10.6.1 32-Bit Dat a Bus Operation The SA-1 100 PCMCIA interf ace supports the use of a 32-bit data bus. Because the PCMCIA 2.0 is 8- or 16-bit only , the 32-bit operati on is outside the s cope of the PCMCIA sp ecification. This 32-bit mode is intended for use as a nonst andar[...]

10-28 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule 10.6.2 External Logic for PCMCIA Implementation The SA-1 100 requires external logic to complete the P CMCIA socket interface. F igure 10-12 and Figure 10-1 3 show general solutions for a one- an d two-socket configur ation. Figure 10-14 s hows a solution for the voltage-control[...]

SA-1100 De veloper’s M anual 10-29 Memory an d PCMCIA Co ntrol Modul e Figure 10-12. PCMCIA Ex ternal Logic for a T wo-Sock et Configuration A6840-01 D<15:0> GPIO<w> GPIO<x> GPIO<y> GPIO(z) PSKTSEL A<25:0> nPREG nPWAIT nPIOIS16 nPCE<1:2> nPOE, nPWE nPIOW, nPIOR Intel ® StrongARM ® * SA-1100 D<15:0> CD1#[...]

10-30 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule Figure 10-13. PCMCIA External Logic for a One-Socket Configuration A6844-01 D<15:0> GPIO<y> GPIO<z> PSKTSEL A<25:0> nPREG nPWAIT nPIOIS16 nPCE<1:2> nPOE, nPWE nPIOW, nPIOR Intel ® StrongARM ®* SA-1100 D<15:0> CD1# CD2# RDY/BSY# NC WAIT# IOIS[...]

SA-1100 De veloper’s M anual 10-31 Memory an d PCMCIA Co ntrol Modul e Figure 10-14. PCMCIA V oltage-Control Logic The PCMCIA car d voltage may be contro lled through a set of discrete regist ers mapped into a static chip select. For example, F igure 10 -14 shows mapping to chip select 3. 10.6.3 PCMCIA Interface T iming Diagrams and Paramete rs F[...]

10-32 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule Figure 10-15. P CMCIA Memory or I/O 16-Bit Access A4788-01 CPU Clock Memory Clock BS_xx+1 BS_xx = 1 BS_xx+2 BS_xx+1 3*(BS_xx+1) 3*(BS_xxL+1) BCLK nPCE2, nPCE1 A, nPREG, PSKTSEL nPWE, nPIOW , nPOE, or nPIOR nPWAIT Latch Read Data Read Data [15:0] Write Data [15:0] nIOIS16 (for I/[...]

SA-1100 De veloper’s M anual 10-33 Memory an d PCMCIA Co ntrol Modul e T iming parameters are in CPU clock cycle units. All are minimums except as noted: Address access time: 6*(BS_xx+1) Command (n POE, nPWE, nPIOR, n PIOW) asse rtion ti me: 3*(BS_xx+1) Address s etup to command ass ert: 3*(BS_xx+1) Address ho ld after command d eassertion : BS_x[...]

10-34 SA-1100 Deve loper’ s Manual Memory and PCMCIA Control M odule 10.7 I nitialization of the Me mory Interface On power- on reset, the dynamic memory interface is disabled and the stati c interface f or the boot ROM, connected to nCS0, is con figured for the slowest nonbu rst ROM/Flash EPROM. The ROM_SEL pin determines the bu s size of the bo[...]

SA-1100 De veloper’s M anual 10-35 Memory an d PCMCIA Co ntrol Modul e The following flow s hould be follo wed when coming out of reset, whether for sleep or power-up: • Read boot R OM and write to memor y confi gurati on regis ters, but do not enab le DRAM b anks. • If necessary , finish any DRAM power -up wait period (u s ually about 10 0 ?[...]

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SA-1100 De veloper’s M anual 11-1 Peripheral Control Module 11 This chapter describes the periph eral control units that are integrated within the Intel ® StrongARM ® SA-1100 Microprocessor (SA-1 100) and the DMA contro ller that services them. The periph eral u nit s in cl ude one paral l el data por t to drive an LC D di sp l ay , one synch r[...]

11-2 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e Figure 1 1- 1. Peripheral Control M odule Block Diagram 1 1.2 Memory Organ ization Several of the serial ports contain m ore than one serial engine. Each indiv i dual engine is self-cont ai ned (no sh ared l ogic or regi s ters ) and im plements a separate serial pro tocol. Serial por[...]

SA-1100 De veloper’s M anual 11-3 Periphe ral Control Module T able 1 1-2 shows the base address for each of the periph eral control units. 1 The PPC does not support DMA requests. Ta b l e 11 - 2 . Peri pheral Units’ Ba se Addresses Peripheral Se rial Protocol Base Address LCD Controller 0h B010 0000 Serial Port 0 USB 0h 8000 0000 Serial Port [...]

11-4 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.3 I nterrupts Each peripheral unit in terfaces to the interrupt con troller within the system control mod u le. The interrupt contr oller contains a 32-bit interrupt p ending register , which when read, informs the user of all the units on the SA-1 100 that are cu rrently generati[...]

SA-1100 De veloper’s M anual 11-5 Periphe ral Control Module 1 1.4 Periph eral Pins Each peripheral has a n u mber of dedicated pins with which to co mmunicate to off-chip devices. The six peripherals of th e SA-1 100 use a to tal of 24 pi ns: th e LCD uses twelve pi ns; serial port 4 four pins; and serial port 0 through 3 each use two pins. Many[...]

11-6 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.5 Use of the GPIO Pins for Alternate Function s Each of the SA-1 1 00’ s six peripheral un its has a numbe r of dedicated pins that can be used to drive an LCD display , comm unicate serially with off-chip devices, or be used as general-purpose digital input/ou tput pins . Each [...]

SA-1100 De veloper’s M anual 11-7 Periphe ral Control Module 1 1.6 DMA Controller The DMA controller consists of six independ ent DMA channels. Each channel can be conf igured to service any of the s erial controllers. T wo channels are required to service a full-d uplex serial controller . The DM A controll er is intended to reliev e the process[...]

11-8 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.6.1.1 DMA Device Address Register (DDARn) The DDAR n i s a 32- bit read/wr ite regi st er containi ng chann el informat ion regardi ng t he ta r get device. W rites to this register are blocked i f t he RUN bit i n th e DCSRn is one. The follo wing f igu re shows the format for th[...]

SA-1100 De veloper’s M anual 11-9 Periphe ral Control Module The value written to the device select DS<3:0> field specifies which DMA request this channel responds to. The d evice datum width (DW) f ield value is fixed fo r each device type and indicates wheth er the de vice’ s data por t is one or two byte s wide. If the dat um wid t h i[...]

11-10 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e T able 1 1-6. V alid Settings for the DDARn Register Unit Name Funct ion Device Address DDAR Fields DA<31:8> DS<3:0> DW BS E RW Serial port 0 UDC transmit 0x 8000 0028 0x80000A 0000 0 1 0/1 0 UDC receive 0x 8000 0028 0x80000A 0001 0 1 0/1 1 Serial port 1 SDLC transmit 0x [...]

SA-1100 De veloper’s M anual 11-11 Periphe ral Control Module 1 1.6.1.2 DMA Control/Status Register (DCSRn) The DCSRn is a 32-bit read/write register that contains control and status bits for the channel. The following figure shows the for mat for this register; question marks i ndicate that the values are unknown at res et. The RUN bit is the ch[...]

11-12 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The IE bit is the interr upt enable for the channel. An inter rupt is generated i f the DONEA, DONEB, or ERROR bit s are set and the IE bit is set. The interru pt is neg ated when all of these status bits are cleared. The ERROR bit is set if the DMA controller is incorrectly prog ram[...]

SA-1100 De veloper’s M anual 11-13 Periphe ral Control Module 1 1.6.1.5 DMA Buffer B Start Address Register (DBSBn) The DBSBn is a 32-bit read/write regi ster that contains the starting memory address for buf fer B. This register may be written o nl y while STR TB in the DCSR is zero. 1 1.6.1.6 DM A Buffer B T ransfer Count Regist er (DBTBn) The [...]

11-14 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.6.3 DMA R egister List The following table lists the registers con tai ned within the DMA con t roller: Physical Address Register Name Symbol Channel 0 Registers 0h B000 0000 DMA device a ddress register . DDAR0 0h B000 0004 DMA control/status register 0. Write ones t o set. DCSR[...]

SA-1100 De veloper’s M anual 11-15 Periphe ral Control Module 0h B000 0070 DMA buffer A start address 3. DBSA3 0h B000 0074 DMA buffer A transfer count 3. DBT A3 0h B000 0078 DMA buffer B start address 3. DBSB3 0h B000 007C DMA buffer B tra nsfer count 3. DBTB3 Channel 4 Registers 0h B000 0080 DMA devic e address register 4. DDAR4 0h B000 0084 DM[...]

11-16 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.7 LCD Controller The SA-1 100’ s LCD contr oller has three types o f displays: Passive Co lor Mode Suppo rts a t otal of 337 5 possible col ors, allowing any 256 colors to be displayed each frame. Active Colo r Mode Support s up to 65536 col ors (16-bit). Passive Mon ochrome Mo[...]

SA-1100 De veloper’s M anual 11-17 Periphe ral Control Module When the LCD controll er is disabled, control of its p ins is given to the peripheral pin controller (PPC) to be used as general-purpose d i gital in put/output pi ns that are n oninterruptibl e. The LCD controll er ’ s pins includ e: • LDD<7:0 > Data lines used to transmit e[...]

11-18 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.7 .1 LCD Controller Operatio n The LCD controller supports a variety of user -programmable options including display type and size, frame buffer , encoded pixel size, and output data width. Although all programmable c ombinations are possible, th e selection of dis plays availa b[...]

SA-1100 De veloper’s M anual 11-19 Periphe ral Control Module Figure 1 1-3. Palette B uffer Format . Individu al Palette Entr y B i t 1 5 1 4 1 3 1 2 1 1 1 0 9876543 210 Col or Unused PBS* Red (R) Green (G) Blue (B) B i t 1 5 1 4 1 3 1 2 1 1 1 0 9876543 210 Mono Unused PBS * Unused Monochrome (M ) * Note: Pixel bit size (PBS ) is contained only w[...]

11-20 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The first palette entry (palette entry 0) al so contains an extra field that is used to synchr onously configure the LCD controller at the beginning of each frame. Bits 12 and 13 of the first palette entry contain a field that is used t o select the number of bits per pix el that is [...]

SA-1100 De veloper’s M anual 11-21 Periphe ral Control Module Figure 1 1-5. 8-Bits Per Pixel Da ta Memory Organiz ation (Little Endia n ) Figure 1 1-6. 12 -Bits Per P ixel Data Memor y Organiza tion (Passive Mode Only) Figure 1 1-7. 16 -Bits Per P ixel Data Memor y Organiza tion (Active Mo de Only) ) B i t 76543210 8 bits/pixel Encoded Pixel Data[...]

11-22 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e In dual-panel mode, pixels are pre sented to two halves of the screen a t the same time (upper and lower). A second DMA channel and input FIFO exist to support dual-panel operation. The DMA c hannels alternate service requests when f illing the two input FIFOs. The palette buf fer is[...]

SA-1100 De veloper’s M anual 11-23 Periphe ral Control Module 1 1.7.1.3 Input FIFO Data from the LCD’ s DMA is directed either to the palette or the input FIFO. The direction of data flow is switched whenever the LCD contro ller is first enabled and b y each frame pulse. Af t er the LCD controller is config ured and enabled, the first 32 ( 4 -,[...]

11-24 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.7.1 .5 Color/Gray-Scale Dithering For passive displays, entries selected from the loo kup palette are sent to the color/gray -scale space/time bas e dither generator . Each 4-bit value is u sed to select one of 15 inten sity lev els. Note that two of the 16 dither values are iden[...]

SA-1100 De veloper’s M anual 11-25 Periphe ral Control Module 1 1.7.1.7 LCD Controller Pins Pixel data is rem ov e d from the bottom of the o u tput FIFO and is driven in parallel onto the LCD ’ s data lines on the edge selected by the pixel clock polar ity (PCP ) bit. F or a 4-bit wide bus, data is driven onto the LC D data lines LDD<3:0 &g[...]

11-26 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.7.3 L CD Controller Control Register 0 LCD controlle r control register 0 (LCCR0) con tains 10 bit fiel ds that are used to cont rol various functions wi thin the LCD controller . 1 1.7.3 .1 LCD Enable (LEN) The LCD enable (LEN) bi t is used to enable and disable all LCD c ontrol[...]

SA-1100 De veloper’s M anual 11-27 Periphe ral Control Module T able 1 1-8 shows the LCD data pins and G PIO pins used f or each mode of operation and th e ordering of pixels delivered to a screen for each mod e of operation. Figure 1 1-8 shows the LC D data pin pixel ord ering. Note that when dual-panel color operation is enabled, the user must [...]

11-28 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e Figure 1 1-8. LCD Data-Pin Pixel Ordering LDD<0> LDD<1> LDD<2> L DD<3> L DD<0> LDD<1> LDD<2> LDD<3> LDD<0> Top Lef t Co rne r of Screen Colu mn 0 Co lumn 1 Column 2 C olumn 3 Col umn 4 Column 5 Col umn 6 Column 7 Colum n 8 Row 0 R[...]

SA-1100 De veloper’s M anual 11-29 Periphe ral Control Module 1 1.7.3.4 LCD Disable Done Interrupt Mas k (LDM) The LCD dis able done interrupt mask ( LDM ) bit is used t o mask or enable interru pt requests that are asserted after the LCD is disabled and the frame currently being output to the pins h as completed. When LDM=0, the i nterrupt is en[...]

11-30 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e Thus two 16-bit values are packed into each word in the frame buffer . Each 16-bit value is transferred via the DMA from off-chip memory to the inpu t FIFO. Unlike 4- and 8-bit per pixel modes, the 16-bit value bypasses both the palette a nd the dither logic, and is placed directly i[...]

SA-1100 De veloper’s M anual 11-31 Periphe ral Control Module 1 1.7.3.8 Big/Little Endian Select (BLE) The big/little endian select (BLE) bit selects whether the LCD controller views external memo ry organization of the frame buffer as big or little endian. When BLE=0 , little endian mode is select ed and pixel d ata is or ganized within t he off[...]

11-32 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The following table shows the location of all 10 bit-fields located in LCD control register 0 (LCCR0). The user must program the co nt rol bits within all other co ntro l registers before setting LEN=1 (a w ord write can be used to co nfigure LCCR0 wh ile setting LEN after all oth er[...]

SA-1100 De veloper’s M anual 11-33 Periphe ral Control Module 7P A S P ass ive/active display select. 0 – Pass ive or STN display operation enabled. Dither logic is enabled. 1 – Active or TF T display operation enable. Dither logic bypassed, pin timing changes to support continuous pixel clock, output enable, VSYNC, HSYNC signals. 8B L E B ig[...]

11-34 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.7.4 L CD Controller Control Register 1 LCD controller control register 1 (LCCR1) contains fou r bit fields that are used as modulus values for a collection of down counters, each of wh ich performs a dif ferent function to control the timing of severa l of th e LCD’ s pins. 1 1[...]

SA-1100 De veloper’s M anual 11-35 Periphe ral Control Module 1 1.7.4.4 Beginning-of-Line Pixel Clock W ait Count (BL W) The 8-bit b eginning-of-l ine pixel clock wait count (B L W) field is used to specif y the num ber of “dummy” pixel clock s to insert at the b eginning of each line or row of p ixels . After the line clock for the p revious[...]

11-36 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.7.5 L CD Controller Control Register 2 LCD controller control register 2 (LCCR2) contains fou r bit fields that are used as modulus values for a collection of down counters, each of wh ich performs a dif ferent function to control the timing of severa l of th e LCD’ s pins. 1 1[...]

SA-1100 De veloper’s M anual 11-37 Periphe ral Control Module VSW does not affect g eneration of the frame clock signal in passive m ode. Passi ve LCD displays require that the frame clock i s active on the risin g edge of the f i rst line clock p ulse of each frame, with adequate setup and ho ld t ime. T o meet this req uirement, th e LC D co nt[...]

11-38 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The following table s hows the location of the four bit fields located in LCD control register 2 (LCCR2). The LCD contro ller must be disabled (LE N =0) when changing the state of any f ield within this register . Address: 0h B010 0024 LCCR2: LCD Controller Control Regist er 2 Read/W[...]

SA-1100 De veloper’s M anual 11-39 Periphe ral Control Module 1 1.7.6 LC D Controller Contr ol Register 3 LCD controller control reg ister 3 (LCCR3) contains seven different bit fields that are used to control var ious functions within the LCD c ontroller . 1 1.7.6.1 Pixel Clock Divide r (PCD) The 8-bit p ixel clock di vider (PCD) field is used t[...]

11-40 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.7.6 .3 AC Bias Pin T ransitions Per Interrupt (AP I) The 4-bit ac b i as pin t ransitions per interrupt (API) field is used to sp ecify the number of L_ BIAS pin transitio ns to count be fore setti ng the ac bias coun t status (ACS) bi t in the LCD controller status register that[...]

SA-1100 De veloper’s M anual 11-41 Periphe ral Control Module 1 1.7.6.7 Output Enable Polarity (O EP) The output enable polarity (OEP) bit is used to selec t the active and inactive states of the output enable signal in active display mode. In this mode, the ac bias pin is used as an enable that signals the off-chi p devi ce when data is acti vel[...]

11-42 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.7.7 L CD Controller DMA Registers The LCD controller has two fully independen t DMA channels used to tran sfer frame buf fer data for each frame disp layed from of f-chip memor y to the LCD’ s palette R A M and the in put FIFO. DMA channel 1 is used for single- panel disp lay m[...]

SA-1100 De veloper’s M anual 11-43 Periphe ral Control Module 1 1.7. 8 DMA Channel 1 Base Add ress Register DMA channel 1 base addr es s register (DBAR1) is a 32-bit reg is ter that is used to specify the base address of the of f-chip frame buf fer for DMA channel 1. The b ase address pointer reg ister can be both read and written. Add r ess es p[...]

11-44 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.7.9 D MA Channel 1 Cu rrent Address Register DMA channel 1 current ad dress register (DCAR1) is a 32-bit read- only register that is used by DMA channel 1 to keep trac k of the address of the DMA transfer c urrently in progress or the address of the next DMA transfer . Any time t[...]

SA-1100 De veloper’s M anual 11-45 Periphe ral Control Module 1 1.7. 10 DMA Ch annel 2 Base and Current Address Registers DMA channel 2’ s base a nd current addres s re gisters (DBAR2 and DCAR2) function exactly like DMA channel 1’ s except that they are used exclus ively for dual-p anel opera tion. (Se e the prece ding sections.) When SDS=1,[...]

11-46 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.7.1 1 LCD Controller Status Register The LCD cont roll er st atus r egister (LCSR) co ntains b its th at si gnal ov errun an d un derrun errors for both th e input and outp ut FIFOs, ac bias pin tr ansition count, LC D disabled, DM A base update ready , and DMA tran s fer bus err[...]

SA-1100 De veloper’s M anual 11-47 Periphe ral Control Module 1 1.7.1 1.4 AC Bias Count Status (ABC ) (read/write, nonmaskable interrupt) The ac bias count statu s (ABC) bit it set each ti me the ac bias pi n (L_BIAS) transitions a particular number of times as specified b y the ac bias pin t ransitions per interrup t (API) field in LCCR3. I f AP[...]

11-48 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.7.1 1.10 Output FIFO Underrun Lower Panel Status (OUL) (read/write, maskable int errupt) The output FI FO underrun lower panel stat us (OUL) bi t is set when t he lower pan el’ s output FIFO is completely emp ty and the LCD’ s data pin driver logic attempts to fetch d ata fro[...]

SA-1100 De veloper’s M anual 11-49 Periphe ral Control Module 2B E R Bus error st atus . 0 – DMA has not attempted an access to r eserv ed/nonexistent memory space. 1 – DMA has attempted an access to a reserved/nonexistent locati on in external memory . The errant DMA read re turns zeros. 3A B C AC bias coun t status. 0 – AC bias transition[...]

11-50 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.7.12 LCD Controller Register Locations T able 11-9 shows the registers associated with the LCD contr oller and the physical ad dresses used to access them. Figure 1 1-34 to Figure 1 1-38 describe the LCD controller timing p arameters. T able 1 1-9. LCD Controller Control, DMA, a [...]

SA-1100 De veloper’s M anual 11-51 Periphe ral Control Module 1 1.7.13 LC D Controller Pin T iming Diagrams Figure 1 1- 10. Passive Mode Beginning-of-Frame Timing A4790-01 L_FCLK L_LCLK L_PCLK LDD[x:0] Notes: LEN - LCD enable: 0 - LCD is disabled. 1 - LCD is enabled. VSP - V ertical sync polarity: 0 - F rame clock is active high, inactive low . 1[...]

11-52 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e Figure 1 1- 1 1. Pas sive Mode End-of-Frame Timing A4791-01 L_FCLK L_LCLK L_PCLK LDD[x:0] Notes: BLW - Beginning-of -line pixel clock wait count: 0 to 256 "dummy" pixel clock periods to wait after line clock is negated before asserting pixel clocks (pixel clock does not tra[...]

SA-1100 De veloper’s M anual 11-53 Periphe ral Control Module Figure 1 1- 12. Passive Mode Pixe l Clock and Data Pin Timing A4792-01 L_FCLK L_LCLK L_PCLK LDD[3:0]* *DPD = 0 Notes: PCP - Pixel clock polarity: 0 - Pixels sampled from data pins on rising edge of pixel clock. 1 - Pixels sampled from data pins on falling edge of pixel clock. DPD - Dua[...]

11-54 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e Figure 1 1- 13. A ctive Mode Timing A4793-01 L_FCLK (VSYNC) L_LCLK (HSYNC) L_BIAS (OE) L_PCLK LDD[7:0], GPIO[9:2] Notes: LEN - LCD enable: 0 - LCD is disabled. 1 - LCD is enabled. VSP - V ertical sync polarity: 0 - V ertical sync clock is active high, inactive low . 1 - V ertical syn[...]

SA-1100 De veloper’s M anual 11-55 Periphe ral Control Module Figure 1 1- 14. Active Mode Pixel Clock and Data Pin Timing A4794-01 L_FCLK (VSYNC) L_BIAS OE) L_LCLK (HSYNC) L_PCLK LDD[7:0], GPIO[9:2] Notes: PCP - Pixel clock polarity: 0 - Pixels sampled from data pins on rising edge of pixel clock. 1 - Pixels sampled from data pins on falling edge[...]

11-56 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.8 Serial Port 0 – USB Device C ontroller This section describes the implementation-specific op ti ons of the USB protocol for a device controller as it applies to seri al port 0, such as nu mber , type, and function of the endpoints, interrupts to the CPU, transmit/receive FIFO[...]

SA-1100 De veloper’s M anual 11-57 Periphe ral Control Module 1 1.8.1.1 Signalling Levels USB uses differential signallin g to encode data and to com municate various bu s con d itions. The USB specification refers to the J and K data stat es to dif ferentiate between high- and low-speed transmission. Because the UDC supports only 12-Mbps transmi[...]

11-58 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1 .8.1 .2 Bit Encoding USB uses nonreturn to zero inverted (NRZI) to encode individual bits. Both the clock and the data are encoded and transmitted within th e same signal. Ins tead of representing data b y controlling t he state of the signal, transitions are used . A zero is rep[...]

SA-1100 De veloper’s M anual 11-59 Periphe ral Control Module 1 1.8.1.3 Field Formats Individual bits are assemb led into groups called fi elds. Fields are used to construct p ackets and packets are used to construct f rames or transactions. The seven USB field types include: sync, packet identifier , address, endp oint, frame number , data, and [...]

11-60 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1 .8.1 .4 Packet Formats USB supports fou r packet types: token, data, handshake, and special. A token packet is placed at the beginning of a fram e and is u sed to iden tify OUT , IN, SOF , and SETUP transactions. OUT and IN frames are used to transfer data, SOF packets are used t[...]

SA-1100 De veloper’s M anual 11-61 Periphe ral Control Module 1 1.8.1.5 T ransaction Formats Packets are assembled into groups to form transactions. Four dif fer ent transaction for mats are used in the USB protoco l. Each is specific to a particular endpoint type: bul k, contro l, interru pt, and isochron ous. Note that isoch ronous and interrup[...]

11-62 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e Figure 1 1-21. C ontrol T ransaction Formats Control trans fers are assembled by the host by first send in g a control transaction to tell the UDC what type of control transfer is taking place (contro l read or control write), fo ll owed by two or more bulk data tran s actions. The c[...]

SA-1100 De veloper’s M anual 11-63 Periphe ral Control Module T able 1 1-1 2 shows a summary of all device reques ts. Users shou ld refer to the Universa l Serial Bus Specific ation Revi sion 1. 0 for a fu ll de scri pti on of h ost dev i c e requ e sts. 1 1.8.2 UDC Register Defin itions All configu ration, reques t/servi ce, and status report in[...]

11-64 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.8 .3 UDC C ontrol R egister The UDC contro l register (UDC R) contains seven cont rol bits: two to enab le or disable the UDC and five to mask the tran s mit and receive FIFO ser vice requests. 1 1.8.3 .1 U DC Disable (UDD) The UDC disable (UDD) bit is used to enab le and disable[...]

SA-1100 De veloper’s M anual 11-65 Periphe ral Control Module 1 1.8.3.7 Suspend/Resume Inte rrupt Mask (SRM) The suspend/resume interru pt mask (SRM) bit is used to mask or enab le the suspend/resume interrupt request. When SR M=1, the interrupt is masked, and the SUSIR/RESIR bits in th e status/interrup t regis ter are not allowed to be set. Whe[...]

11-66 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.8.4 UDC A ddress Register The UDC address register contains a 7- bit field that holds the device address. After a reset of the UDC core, the value of this register is zero. The CPU writes an address to this register when it receives a SET_ADDRESS from the USB host co ntroller . I[...]

SA-1100 De veloper’s M anual 11-67 Periphe ral Control Module 1 1.8. 6 UDC IN Max Packet Register The UDC IN max pack et register holds the value of the number of bytes the UDC core is to transmit minus one. This is done in order to accommodate maximum packets of 256 bytes, without going to a max packet f ield o f more th an 8 bits. I n order to [...]

11-68 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.8.7 U DC Endpoint 0 Contro l/Status Register The UDC endpoint zero control/status register co ntains 8 bits that are used to operate endpoint zero (contr ol endpoin t). 1 1.8.7 .1 OUT Packet Ready (OPR) The OUT packet ready bit is set by the UDC when it receives a valid token to [...]

SA-1100 De veloper’s M anual 11-69 Periphe ral Control Module 1 1.8.7.8 Serviced Setup End (SS E ) The serviced setup end bit will clear the SE bit (5 ) when writing a one. Address: 0h 8000 0010 UDCCS0 Read/Write B i t 765 43210 SSE SO SE DE FST SST IPR OPR R e s e t 000000 00 Bit Name Description 0O P R OUT packet ready (read-only). 1 – OUT pa[...]

11-70 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.8.8 U DC Endpoint 1 Contro l/Status Register The UDC endpoint 1 contr o l/s tatus register contains 6 bits that are used to operate endpoint 1 (OUT endpoint) . 1 1 .8.8.1 Receive FIFO Serv ice (RFS) The receive FIFO service bit will be set if the receive FIFO has between 8 and 12[...]

SA-1100 De veloper’s M anual 11-71 Periphe ral Control Module 1 1.8.8.7 Bits 7..6 Reserved Bits 7..6 are reserved for future use. Address: 0h 8000 0014 UDCCS1 Read/Wri te B i t 765 43210 Res. RNE FS T SST RPE RPC RFS R e s e t 00 000000 Bit Name Description 0R F S Receive FIFO service (r ead-only). 0 – Receive FIFO has less t han 12 bytes. 1 ?[...]

11-72 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.8.9 U DC Endpoint 2 Contro l/Status Register The UDC endpoint 2 contr o l st atus register con tains 6 bits that are used to operate endpo int 2 (IN e ndpoi nt). 1 1.8.9 .1 T ransmit FIFO Ser vice (TFS) The transmit FIFO service bit will be active if there are 8 or less (out of 1[...]

SA-1100 De veloper’s M anual 11-73 Periphe ral Control Module 1 1.8.9.7 Bits 7..6 Reserved Bits 7..6 are reserved for future use. Address: 0h 8000 0018 UDCCS2 Read/Wri te B i t 765 43210 Res. FST SST TUR TP E TPC TFS R e s e t 00 000000 Bit Name Descript ion 0 TFS T ransmit FIFO service (read-only). 0 – Tr ansmit FIFO has more than 8 bytes. 1 ?[...]

11-74 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.8.10 UDC Endpoint 0 D ata Register The UDC endpoi nt 0 data register is actually an 8 -bit x 8-entr y bidirect ional FIF O. When th e host transmits data to the UDC endpoint 0, the CPU reads the UDC endpoint 0 register to access the data. When the UDC is s ending data to the host[...]

SA-1100 De veloper’s M anual 11-75 Periphe ral Control Module 1 1.8.12 UDC Da ta Register The UDC data register (UDDR) is an 8-b i t register correspond ing to both the top and bottom entries of the transmit and r eceive FIFOs, respectively . Data is placed by the UDC’ s receive logic into the top of th e receive FIFO. The data is transferred d[...]

11-76 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.8.13 U DC Status/Interrupt Register The UDC status/interrupt register (UDCSR) contains bits that are u sed to generate the UDC’ s interrupt request. Each bit in the UDC status/interrup t register is logically ORed together to produce one interrup t request. When the ISR for the[...]

SA-1100 De veloper’s M anual 11-77 Periphe ral Control Module 1 1.8.13.6 Reset Interrupt Request (RSTIR) The reset interrupt requ est register will be set if the REM bit in th e UDC control register is cl eared and the host issues a reset. When the host issues a reset, the entire UDC is reset. The RSTIR bit retains its state so so ftware can de t[...]

11-78 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.8.14 UDC R egister Locations T able 11- 13 shows the registers associated with the UDC and the physical addresses used to access them. 1 1.9 Serial Port 1 – SDLC/UART Serial por t 1 is a combin ation syn chronous data link controll er (SDLC) an d universal asynchro nous receive[...]

SA-1100 De veloper’s M anual 11-79 Periphe ral Control Module Used as a UAR T , serial port 1 is identical to serial port 3. It supports mo s t of the f unctionality of the 16C550 pr otocol includ ing 7 and 8 bits of d ata (odd, even, or no par ity ), one start bit , either on e or two sto p bits, and t ransmits a conti nuous bre ak signal. An in[...]

11-80 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1 .9.1.2 Frame Format SDLC uses a flag (reserved bit pattern) t o denote the beg inning of a fr ame of info rmation and to synchronize frame transmission. The flag contains eig ht bits that start and end with a zero, and contains s ix s e qu ent ia l ones in the middle (01 1 1 1 1 [...]

SA-1100 De veloper’s M anual 11-81 Periphe ral Control Module 1 1.9.1.5 Data Field The data field can be any leng th that is a multip le of 8 bits, including zero. The user determines th e data field length according to the application requirements and transmission characteristics of the target system. Usually a leng th is s elected that maximize[...]

11-82 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1 .9.1.8 Receive Operation Once the SDLC receiver is enabled, it en ters hunt mode, searching the in coming data stream for the flag (01 1 11 1 10). The flag serves to achieve bit synch ronization, denotes the beginning of a frame, and deli neates th e bound aries of in divid ual b[...]

SA-1100 De veloper’s M anual 11-83 Periphe ral Control Module If the user di sables the receiver dur i ng operation , reception of the c urrent data byte is stop ped immediately , the serial shifter and receive FIFO are clear ed, control of th e RXD1 pin is given t o the peripheral pin con trol (PPC) unit, and all clocks u sed by the receive lo g[...]

11-84 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.9.1 .1 1 T ransmit and Rece ive FIFOs T o reduce chip size and power consump ti on, the SDLC’ s FIFOs use self-timed logic (they are not clocked). Because of pro ces s and environm ental variations, the depth at which a service request is triggered to empty th e receive FIFO is[...]

SA-1100 De veloper’s M anual 11-85 Periphe ral Control Module The status registers contain bits that signal CRC, overrun , underrun, and receiver abor t errors, and the transmit FIFO service requ est, receive FIFO service requ est, and end-o f-frame conditions. Each of these hardware- detected events sign als an in terrupt req uest to the in terr[...]

11-86 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.9.3.4 Bit Modulat ion Select (BMS) The bit modulation select (BMS) bit selects whether the S DLC uses NRZ or FM0 bit encoding f o r both transmit and receive d ata. When BMS=0, FM0 encoding is selected and when BMS=1, NRZ encoding is selected. In freq uency modulation zero (FM 0)[...]

SA-1100 De veloper’s M anual 11-87 Periphe ral Control Module 1 1.9.3.7 Receive Clock E dge Select (RCE) When sample clock operation is enabled (SCE=1), the r eceive clock edge select (RCE) bit is used to select whi ch edge of t he clock inp u t from or output to GPIO pin 16 to use (rising or f alling) to synchronously sample data fr om the recei[...]

11-88 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.9.4 SDLC Control Regi ste r 1 SDLC con trol register 1 (SDCR1) contain s eight bit fields that co ntrol various functions wit hin the SDLC . 1 1.9.4 .1 Abort After Frame (AAF) The abort after fram e (AAF) bit controls whether or not the SDLC transmits an abort at the end of each [...]

SA-1100 De veloper’s M anual 11-89 Periphe ral Control Module 1 1.9.4.2 T ransmit Enable (TXE) The transmit enable ( TXE) bit is used to enable and disable SDLC transmit operation. When TXE=0, the transmit logic is disabled and its clocks are turned off to conserve power . When TXE=1, the SDLC transmitter logic is enabled fo r serial transmiss io[...]

11-90 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.9.4 .6 Address Match Enable (AME) The address match enable (AME) bit is used to enable o r disable the receive logic fro m com paring the address progr ammed in the addr ess match va lue (AMV) b it field to the add ress of all incoming frames. When AME=1, data is stored in the re[...]

SA-1100 De veloper’s M anual 11-91 Periphe ral Control Module The following table shows the location of the bits within SDLC co ntr ol regi st er 1 . RXE and T XE are the only control bits in this regist er that are reset to a known state to ensure the SDLC is disabled following a reset of the S A- 1 100. The reset state of al l o ther con trol b[...]

11-92 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.9.5 SDLC Control Regi ste r 2 SDLC control register 2 (SDCR2) contains the 8 -bit address match value field that is used by the SDLC to selectively receive frames. 1 1.9.5 .1 Address Match V alue (AMV) The 8-bit address match value (AMV) field is programmed with an address value [...]

SA-1100 De veloper’s M anual 11-93 Periphe ral Control Module 1 1.9.6 S DLC Con trol Regi sters 3 and 4 SDLC cont rol regi ster 3 (SDCR3) contains t he upper 4 bits and SDLC control register 4 (SDCR4) the lower 8 b its of the ba ud rate di visor fi eld. 1 1.9.6.1 Baud Rate Divisor (BRD) The 12-bit baud rate divisor (BRD) field is used to select t[...]

11-94 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.9 .7 SDL C Data R egister The SDLC data register (S DDR ) is an 8-bit register correspo ndin g to both the top and botto m entries of the transmit and receive F IFOs, respectively . When SDDR is read, the lower 8 bits of the bottom entr y of th e 1 1-bit receive FIFO is accessed.[...]

SA-1100 De veloper’s M anual 11-95 Periphe ral Control Module The following table shows the bit locations correspondin g to the data field and end-of-fr ame bit as well as the cyclic redundancy check and receiver over run error bits within the S DLC data register . Note that both FIFOs are cleared when the SA-1 100 is re set, the transmit FIFO is[...]

11-96 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.9.8 SDLC Status Register 0 SDLC status r egi ster 0 (SD SR0) contains bits tha t sig nal th e tr ansmit FIFO service requ est, r ecei ve FIFO service re qu est, re ceiver abort, tr ansmit FI FO u n derru n , and t he en d/e rr or in r ece ive FIFO condition. Each of these har dwa[...]

SA-1100 De veloper’s M anual 11-97 Periphe ral Control Module which indicates that the add r ess, control, and data fields did not add up to an even mu ltiple of 8 bits. When an ab ort is received, the curren t data byte within the serial shifter is d is carded, the least recent byte (the oldest of the two bytes) of data in the temp orary FIFO is[...]

11-98 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The following table s hows the bit locations co rresponding to the stat us and flag bits within SDLC status register 0. Note that the reset state of all writable status bits is unkn own (indicated by question marks) and mu s t be cleared (by writing a one to them) before en abling th[...]

SA-1100 De veloper’s M anual 11-99 Periphe ral Control Module 1 1.9.9 SDLC Status Register 1 SDLC status register 1 (SDSR1) contains flags and status bits that in dicate when the receiver is synchronized, the transmitter is active, that the transmit FIFO is not full, th at the receive FIFO is not empty , a transition has been d etected on the rec[...]

11-1 00 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e register . After the error in FIFO (EIF) status bit is set, the user should alw ays read SDSR1 first to check EOF before reading the data value from SDDR because EOF corresponds to the current data byte at the bottom of t he receive FI FO and is updated each time da ta is removed f[...]

SA-1100 De veloper’s M anual 11-1 01 Periphe ral Control Module The following table shows the lo cation of the flag and status bits within SDLC status register 1. The bits within this regist er do not produce interrupt reques ts. No te that the reset value of R TD is unknown (ind icated by question mark s ) and must be clear ed if set following a[...]

11-1 02 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.9.10 UART Register Locations T able 11- 14 shows the registers associated with the UAR T and the p hysical addresses used to access them. See the S ection 1 1.9, “Serial P o rt 1 – SDLC/UAR T” on page 11- 78 for a description of the programming and op eration o f the UAR [...]

SA-1100 De veloper’s M anual 11-1 03 Periphe ral Control Module 1 1.9.1 1 S DLC Registe r Locatio ns T able 1 1-1 5 shows the registers associated with the SDLC and the physical addresses used to access them. 1 1.10 Serial Port 2 – In frared Commun ications Port (ICP) The infrar ed communication s port (ICP) operates at ha lf-duplex and provide[...]

11-1 04 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.10.1 Low-Speed ICP Operat ion Following reset, both the UAR T and HSSP are disabled, which causes the peripheral pin controller (PPC) to assume control of the po rt’s pins. Reset causes the PPC to configure all of the periph eral pins as inputs, including serial port 2’ s t[...]

SA-1100 De veloper’s M anual 11-1 05 Periphe ral Control Module Figure 1 1-25. UART Frame Format for IrDA Transmission (<= 1 15.2 Kbps) 1 1.10. 2 High-Speed ICP Operation Before enabling the ICP f or high- speed o peration , the user m ust first clear an y writab le or “sticky” status bits that are set by writing a on e to each bit. Next, [...]

11-1 06 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1 .10.2.2 HSSP Frame Format When the 4-Mbps transmission rate is used, the h igh-speed serial/parallel (HSSP) interface within the ICP is used along with the 4 P PM bit encoding. The hig h -speed frame format shown in Figure 1 1-28 is similar to serial port 1’ s SD LC form at w[...]

SA-1100 De veloper’s M anual 11-1 07 Periphe ral Control Module 1 1.10.2 .3 Address Field The 8-bit address field is used by a transmitter to target a select group of receivers when multiple stations are connected to the same set of s erial lines. The address allows up to 255 stations to be uniquel y address ed (00000000 to 11 1 1 11 10) . The gl[...]

11-1 08 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.10.2. 7 Baud Rate Generation The baud ra te is derived by dividing down a f ixed 48-MHz clock generat ed by one of the two on-chip PLLs by six . The 8-MHz baud (or timeslot) clock for th e receive logic is synchronized with the 4 PPM data stream each ti me a transition is detec[...]

SA-1100 De veloper’s M anual 11-1 09 Periphe ral Control Module When the receive FIFO is one- to two-thi rds full, an interrupt or DMA transfer is s ignalled. If the data is not removed so on enough and th e FIFO is co mpletely filled, an overrun error is si gnalled when the receive logic attemp ts to place additional data into the f ull FIFO . O[...]

11-1 10 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e At the end of each frame transmitted, the HSSP outputs a p ulse called the s erial infrared interaction pulse (SIP ). A SIP is required at least every 50 0 ms to keep slo wer speed devices (1 15.2 Kb ps and slower) from colliding with the higher speed transmission. The SIP si mulat[...]

SA-1100 De veloper’s M anual 11-1 11 Periphe ral Control Module operations. All reads and writes o f the ICP by the CPU should be wordwide. T wo separate, dedicated DMA requests exist for both the transmit and the receive FIFOs. If the DMA controller is used to service the transmit and/o r receive FIFOs, the user mu s t ensure the DMA is properly[...]

11-1 12 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.10.5 HSSP R egister Definitions There are six regi sters within the HSSP: three control registers, one data regis ter , and two stat us registers. The control registers are used to select IrDA transmission rate, address match value, whether an abort or end of frame o ccurs when[...]

SA-1100 De veloper’s M anual 11-1 13 Periphe ral Control Module 1 1.10.6.3 T ransmit FIFO Underrun S elect (TUS) The transmit FIFO under run select (TUS) bit is used bo th to select what action to take as a re sult of a transmit FIFO underrun as well as m a sk or enable the transmit FIFO u nde rrun int errupt. When TUS=0, transmit FIFO under runs[...]

11-1 14 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e transmitting and receiving data at the same time; bo th are fully independent units. This function is particularly useful when using the HS SP in loopback mode. See the Section 1 1.1 0.6 .2, “Loop back Mode (LBM)” on page 1 1- 112 . 1 1.10.6 .5 Rec eive E n able (RXE) The recei[...]

SA-1100 De veloper’s M anual 11-1 15 Periphe ral Control Module The following table shows th e location of the bit s within HSSP control register 0. R XE and TXE are the only co nt rol bits that are res e t to a k now n state to ensure the HSSP is disabled f ollowing a reset of the SA-1 100. The reset s tate of all other co ntrol bits is unknown [...]

11-1 16 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.10.7 HSSP C ontrol Register 1 HSSP control register 1 (HSCR1) contains the 8-bit add ress match value field that is used by t he HSSP to selectively receive frames. 1 1.10.7.1 Address Ma tch V alue (AMV) The 8-bit address match value (AMV) field is programmed with an address va[...]

SA-1100 De veloper’s M anual 11-1 17 Periphe ral Control Module 1 1. 10. 8 HSSP Control Register 2 The HSSP control register 2 (HSC R2) contains two bit-fields that control the polarity of th e transmit and receive data pins. Note that unlike the rest of the HSSP’ s registers, its bits are located in byte 2 of the addressed word ( bits 23..16).[...]

11-1 18 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The following table shows the locati on of the bit s with in HSSP control register 2. Both bits are set to one t o ensure s erial port 2’ s pi ns default to n o rmal “true” data operation fo llowing a reset of the SA-1 100. Not e that the HSSP and UAR T must be disabled (RXE=[...]

SA-1100 De veloper’s M anual 11-1 19 Periphe ral Control Module 1 1. 10. 9 HSSP Data Register The HSSP data register (HSDR) is an 8-bit register corresponding to both the top and bottom entry of the transmit and receiv e FIFOs, respectively . When HSDR is read, the lower 8 b its of the bottom en try of the 1 1-bit receive FIFO is accessed. As dat[...]

11-1 20 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The following table shows the bit locat ions correspond ing to the data field, end- of-frame bit as well as the cyclic redu ndancy check and receiv er overrun error bits within the HSSP data register . Note that both FIFOs are cleared when the SA-1 100 is r eset, the transmit FIFO [...]

SA-1100 De veloper’s M anual 11-1 21 Periphe ral Control Module 1 1.10.10 HSSP Status Register 0 HSSP status register 0 (HSSR0) contains bits that si gnal the transmit FIFO service request, receive FIFO service request, receiver abort, transmit FIFO underrun, framing error, and the end/error in receive FIFO conditions. Each of these hardware-dete[...]

11-1 22 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.10 .10.4 T ransmit FIFO Service Re q uest Flag (TFS) (r ead-only , m askable interrupt) The transmit FIFO s ervice request flag (TFS) is a read-only bit th at is set when the transmit FIFO is nearly empty and requires s ervice to prevent an underrun. TFS is set any ti me the t [...]

SA-1100 De veloper’s M anual 11-1 23 Periphe ral Control Module 1 1.10.10.6 Framing Error Status (FRE) (read/wri te, nonmaskable interrupt) The framing err o r status (FR E) bit is set when a fr ame alignment error is detected by t he receive logic. A frame alignmen t erro r is detected on received d at a when a preamble is followed by something [...]

11-1 24 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.10.1 1 HSSP Status Register 1 HSSP stat us register 1 (HSSR1) contains flags that indicate when the receiver is synchronized, the transmitter is active, the transmit FIFO is not full, th e receive FIFO is not empty , and when an end-of-frame, C RC erro r , or underr un er ror h[...]

SA-1100 De veloper’s M anual 11-1 25 Periphe ral Control Module 1 1.10.1 1.6 CRC Error Status (CRE) (read-only , noninterruptible) The CRC error flag (C RE) is set when the CRC value calculated by the r ecei ve logic does not match the CRC valu e contained within th e incoming serial data s tream. The receive FIFO contain s three tag bits (8, 9, [...]

11-1 26 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The following table s hows the location of the flags within HSSP status re gis ter 1. The bits withi n this r egister are read-o nly and do not pro duce int errupt requests. No te that writes t o bit 7 are ignored and read s return zero. Address: 0h 8004 0078 HSSR1 Read-Only B i t [...]

SA-1100 De veloper’s M anual 11-1 27 Periphe ral Control Module 1 1.10. 12 UART Register L ocations T able 1 1-1 6 shows t he registers associated with the UAR T b lock and the physical addresses used to access them. 1 1. 10. 13 HSSP Register Locations T able 1 1-1 7 shows the registers associated with the HSSP block and the physical addresses us[...]

11-1 28 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.1 1 Serial Port 3 - UART Serial port 3 is a general-purpose, full-duplex, universal asynchronous receiver/transmitter (UAR T) that supports much o f the functionality of th e 16550 protocol. It can operate at baud rates from 56.24 bps t o 230.4 Kbps . It supports 7 or 8 bits o [...]

SA-1100 De veloper’s M anual 11-1 29 Periphe ral Control Module 1 1.1 1.1.1 Frame Format NRZ encoding is used by the UAR T to represent individual bit values. A one i s represented by a line transition and a zero i s represented by no line transition. Figur e 1 1-30 shows the N RZ encoding of the data byte 8b 0100 101 1. Note th at the byt e’ s[...]

11-1 30 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The parity , framing, and overrun er ror bits a re tran sferred down th e receive FIFO alon g with th e data that caused t he error . Whenever any o f the four b ottom FIFO entr ies contain o ne or more error b its that are set, an interrupt is genera ted and re ceive FIFO DMA r eq[...]

SA-1100 De veloper’s M anual 11-1 31 Periphe ral Control Module removed from the receive FIFO without checking if more data is av ailable. After this point, the user must poll a set of status bits that indicates if any data remains in the receive FIFO or if space is available in the trans m it FIFO b efore emptying or filling the FIFOs an y furth[...]

11-1 32 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The transmit log ic set s or clears the parity bit to m a k e the total number of ones transm itted (includi ng the parity bit) match the parity type prog ram med using OES (if even parity is selected (OES =1) and ther e is an odd number of on es in the data to be transmitted, the [...]

SA-1100 De veloper’s M anual 11-1 33 Periphe ral Control Module 1 1.1 1.3.7 T ransmi t Clock Edge S elect (TCE) When SCE=1, the transmit clock ed ge select (TCE) bit is used to select which edge of the clock input from the GPIO pin to u se (rising or falling) to sy nchronously drive data onto the transm it pin. When TCE=0, each bit tran smitted i[...]

11-1 34 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.1 1.4 UART Control Registers 1 and 2 UAR T control reg ister 1 (UTCR1 ) contains the up per 4 bits and UTCR2 the lower 8 bits o f the baud rate di visor field. 1 1.1 1.4.1 B aud Ra te Divisor (B RD) The 12-bit bau d rate divisor (BRD) field is us ed to select the baud or bit ra[...]

SA-1100 De veloper’s M anual 11-1 35 Periphe ral Control Module 1 1.1 1.5 UA RT Control R egister 3 UAR T contro l register 3 (U TCR3) cont ains six dif ferent bit fields that cont rol vari ous fun ctions within the UAR T . 1 1.1 1.5.1 Receiv er Enable (RXE) The receiver en able (RXE) bit is used to enable an d disable all UAR T receive o peratio[...]

11-1 36 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.1 1.5.5 T ransmit FIFO Interrupt Ena ble (TIE) The transmit FIFO interrupt enab le (TIE) bit is used to mask or enable the transmit FIFO serv ice request interrupt. When TIE=0 , the interrupt is masked and the state of the transmit FIFO service request (TFS) bit is igno red b y[...]

SA-1100 De veloper’s M anual 11-1 37 Periphe ral Control Module 1 1.1 1.6 UAR T Data Regis ter The UAR T data register (UTDR) is an 8-bit regist er corresponding to b o th the top and bott om entries of the transmit and r eceive FIFOs, respectively . When UTDR is read, the lower 8 bits of the bottom entry of the 10-bit receive FIF O are accessed.[...]

11-1 38 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The following table s hows the bit locations co rresponding to the d ata field, parity , framing, and receiver overrun error bits within the UAR T data register . Note that both FIFOs are cleared when the SA-1 100 is reset, the transmit FIFO is cleared when writing TXE=0, and the r[...]

SA-1100 De veloper’s M anual 11-1 39 Periphe ral Control Module 1 1.1 1.7 UA RT Status Register 0 UAR T status register 0 (UTSR0) contains bits that signal the tran s mit FIFO interrupt request, receive FIFO interrup t request, r eceiver idle detect, the begin and end of receiver b reak detect conditions, and the error in receive FIFO condition .[...]

11-1 40 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.1 1.7.3 Receiver Idle Sta tus (RID) (read/write, m askable interrupt) The receiver idle status bit (RID) is set when the receiver is enabled (RXE=1), the receive FIFO is not empty (c ontains at least one entry of data), an d three frame periods elapse without any d ata having b[...]

SA-1100 De veloper’s M anual 11-1 41 Periphe ral Control Module The following table shows the bit locations corres ponding to the status bits within UAR T status register 0. Note that the reset state of all writable status bits is unkn own (indicated by question marks) and must be cleared (by writing a o ne to th em) before enabling the UAR T . A[...]

11-1 42 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.1 1.8 UART Status Register 1 UAR T status register 1 (UTSR1) contains flag s that indicate when the UAR T is actively transmitting characters, that the transmit FIFO is no t full, that the receive FIFO is not empty , and when parity , framing, overr un, and underrun err ors hav[...]

SA-1100 De veloper’s M anual 11-1 43 Periphe ral Control Module 1 1.1 1.8.5 Framing Error Flag (FRE) (read-only , noninterruptible) The framing error status bit (FRE) is set when the stop bit within a frame of incoming serial data is a zero instead of a on e. The receive FIFO contains three bit s (8, 9, and 10) that are not directly readable. The[...]

11-1 44 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The following table s hows the bit locations co rresponding to the flag b its within UAR T status register 1. Note that these flags do not generate interrupts, all bits are read-only , writes are ignored, and reads of reserved bits return zeros. Address: 0h 8005 0020 UTSR1 Read-Onl[...]

SA-1100 De veloper’s M anual 11-1 45 Periphe ral Control Module 1 1.1 1.9 UART R egister Locations T able 1 1-1 8 shows the registers associated with serial port 3 and the physical addr es ses used to access them. 1 1.12 Serial Port 4 – MCP / SSP Serial port 4 contains two separate full-duplex synchrono us serial interfaces. The multimedia comm[...]

11-1 46 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e Both the MCP and the of f-chip codec cont ain programmable 7 -bit divisors, one each for the telecom and audio data. These values are used to div ide the bit clock to generate a desired sampling frequency . When the codec is enabled, the d i visor pair s are synchr onously transfe [...]

SA-1100 De veloper’s M anual 11-1 47 Periphe ral Control Module 1 1.12.1 .1 Frame Format Each MCP data frame is 128 bits long and is divi ded into two su bframes: 0 and 1. S ubframe 0 i s used by the MCP to communicate data t o and from the UCB1 100 or UC B1200. Su bframe 1 is not used by the MCP because it is typically used to in terface to high[...]

11-1 48 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e Note that the transmit line is pulled low any time data is not being driven o nto the pin. The UCB1100 and UCB1200 have a programming op tion that allows t hem to either tristate or dri ve the receive line low when data is not being driven on to RXD4. As shown in Figure 1 1-32 , MC[...]

SA-1100 De veloper’s M anual 11-1 49 Periphe ral Control Module If the input po rtion of the audio codec is enabled, when the counter reac hes zero, a sample and A-to-D conversion is made and the converted value is placed within the correct field of the cod ec’ s serial shift register for transmission back to the MCP in the next data frame. If [...]

11-1 50 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The width of each entry within the audi o and telecom FIFOs is 16 bits. However , the audio codec’ s sample/con version data size is 12 bits and the telecom is 14 bits. Conv e rsio ns and samples are left justified withi n the 16-bit audio and te lecom d ata fields in the MCP fra[...]

SA-1100 De veloper’s M anual 11-1 51 Periphe ral Control Module A register r ead is performed by writing a value to MCP data register 2 t hat contains the address of the register and t he read/write bit s et to a zero. Again, the data is transferred to the serial shifter on the next ri sing edge of the SFRM signal and is transmitt ed to the UCB1 [...]

11-1 52 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.12.2 MCP Register Definitions There are si x registers within the MCP : two control registers, t hree data registers, and one status register . The control regist er is us ed to p rogram t he audio and t elecom s a mple rate s, to mask or unmask interrupt reques ts to service t[...]

SA-1100 De veloper’s M anual 11-1 53 Periphe ral Control Module Once enabled, the M CP’ s audio sample rate clock decrem ents at the programmed frequency with a 50% duty cycle. The action outli ned in the above first bul let item causes the MCP’ s audio transmit FIFO logi c to transfer the next available value to the a udio data field within [...]

11-1 54 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.12 .3.3 Multimedia Communications Port Enable (MCE) The MCP enable (MCE) bit is used to en able and disable all MCP operation. Since the MCP and SSP both share the same pins, only one can be enabled at a time. If the user enables both at the same time, the MCP has preced ence a[...]

SA-1100 De veloper’s M anual 11-1 55 Periphe ral Control Module MCP within a receive data frame, the data valid bit is reset to zero for subsequen t data frames until a new A-to-D sample is triggered and transmitted to the MCP . In this mo de, the user should program ADM=0. In the other mode, the data valid bi t is set once when the first A-to-D [...]

11-1 56 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.12.3. 10 L oopback Mode (LB M) The loopback mode (L BM ) bit is used to enable and disable the ability of th e MC P’ s transmit and receive logic to commun icat e. When LBM=0, the MCP operates nor mally . The transm i t and receive data paths are indepen dent and communicate [...]

SA-1100 De veloper’s M anual 11-1 57 Periphe ral Control Module 16 MCE Multimedia communications port enab le. 0 – MCP operation disabled, control of the TXD4, RXD4, SCLK, and SFRM pins given to the PPC to be used as general-purpose I/O pins. 1 – MCP operation enabled. Note that the MCP has precedence over the S SP , if MCE=1; SSE is ignor ed[...]

11-1 58 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.12.4 M CP Control Register 1 The MCP control register 1 (MCCR1) contains one bit that selects one of tw o fixed fr equencies to drive the MCP . Note that this register resides within the PPC’ s address space. 1 1 .12.4.1 Clock Frequency S e lect (CFS) When the on-chip clock i[...]

SA-1100 De veloper’s M anual 11-1 59 Periphe ral Control Module 1 1. 12.5 .1 MCP Dat a Regist er 0 When MCP data register 0 (MCDR 0) is read, the bottom entry of a udio receive FIFO is accessed. As data is removed b y the MCP’ s receive logic from the incoming data fr ame, it is placed into the top entry of the audio receive FIFO and is transfe[...]

11-1 60 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.12.5.2 M CP Data Register 1 When MCP data register 1 (MCDR1) is read, the b ottom entry of the telecom receiv e F IFO is accessed. As data is removed by the MCP’ s receive logic fr om the incoming data frame, it is placed into the top entry of the telecom receive FIFO and is [...]

SA-1100 De veloper’s M anual 11-1 61 Periphe ral Control Module 1 1. 12.5 .3 MCP Dat a Regist er 2 MCDR2 cont ains 21 bits and is used to perform reads and wri tes to any of the UCB1 100’ s or UCB1200’ s registers. MCDR2 cont ains three separate field s : MCDR2<15:0 > is the 1 6-bit register data field, MCDR2< 1 6> is a 1-bit read[...]

11-1 62 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e The following table s hows the location of MCP d a ta regis ter 2. Note that the reset state of all MCDR2 bits is unknown (indi cated by question mar ks), writes to r eserved b its are ignored, and reads return zeros. . Address: 0h 8006 0010 MCP Data Register 2: MCDR2 Read/Write B [...]

SA-1100 De veloper’s M anual 11-1 63 Periphe ral Control Module 1 1. 12. 6 MCP Status Register The MCP status register (MCSR) contains bits that sign al F IFO overr un and unde rrun errors, and FIFO service requests. Each of these cond iti ons signal an interrupt req u est to the interrup t controller . The status regi ster also flags when transm[...]

11-1 64 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1 .12.6.3 T elecom T ran smit FIFO Se rvice Request Flag (TTS) (read-only , maskable int errupt) The telecom transmit FIFO service request flag (TTS) is a read-only bit that is set when the telecom transmit FIFO is nearly empty and r equires service to prevent an underrun. TTS is[...]

SA-1100 De veloper’s M anual 11-1 65 Periphe ral Control Module 1 1.12.6.7 T elecom T ransmit FIFO Underr u n Status (TTU) (read/ write, nonmaskable interrupt) The telecom transmit FIFO u nderrun status bit (TTU) is set when th e teleco m transmit logic attempts to fetch data fro m the FIFO after it has been completely empti ed. When an underrun [...]

11-1 66 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.12.6. 12 T elecom Receive FIFO Not Empty Flag (TNE) (read-only , noninterruptible) The telecom receive FIFO not empty flag ( TNE) is a read-only bit that is set whenever the telecom receive FIFO contains one o r more entries of valid data an d is cleared when it no long er cont[...]

SA-1100 De veloper’s M anual 11-1 67 Periphe ral Control Module The following table shows the b it locations corresponding to the status and flag bits within the MCP status register . MCSR contains a collection of read/write, r ead-only , interruptible, and noninterruptible b its (refer to the bit descr iptions above). W rites to read-only bits h[...]

11-1 68 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 6 TTU T elecom transm it FIFO underrun. 0 – T elecom transmit FIFO has not experienced an underrun. 1 – T elecom transmit logic attempted to fetch data from transm it FIFO while it was empty , request interrupt. 7T R O T elecom receive FIFO overrun. 0 – T elecom receive FIFO [...]

SA-1100 De veloper’s M anual 11-1 69 Periphe ral Control Module 1 1. 12.7 SSP Operation Followin g reset, both th e MCP and SSP logic within seri al port 4 is disabled and control of its pins is given to the PP C t hat con fig ures all four pins as in put s. T o enable SSP op erati on, t he prog ram mer should firs t clear any interru ptible stat[...]

11-1 70 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e Figure 1 1-35 shows the T exas Inst ruments* synch ronous serial fram e format for a si ngle transmitted frame and when back-to-b ack frames are transmitted. In this mode, SCLK and SFRM are forced low , and the transmit data line SA-1 100. Once the bo t tom entry of the transmit FI[...]

SA-1100 De veloper’s M anual 11-1 71 Periphe ral Control Module Figur e 1 1-36 shows on e of the fou r poss ible conf igurati ons for t he Motoro la* SPI frame format fo r a single trans mitted frame and when back -to-back frames are transmitted. In this mo de, SCLK and the transmit data line (TXD4) are f o rced low and SFRM is forced high, whene[...]

11-1 72 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e Figure 1 1-37 shows the Nation al Microwire * frame format for a single transmitted frame and when back-to-back frames are transmitted. M icrowire format is v ery si milar to SPI format, except that transmi ssion is half- instead o f full-duplex, u sing a master -slave message pass[...]

SA-1100 De veloper’s M anual 11-1 73 Periphe ral Control Module 1 1.12.7 .2 Baud Rate Generation The baud or bit rate is deriv ed by dividing down the 3.686 4-MHz clock gen erated by t he on-chip PLL. The clock is first divided by a fixed value of 2 and then by a programmable number between 1 and 256. This p r og rammability provides a range of t[...]

11-1 74 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.12.7.4 CPU and DMA Re gi ster Ac ce ss Size s Bit positio n ing, byte ordering , and addressing of the SSP are described in terms of little endian ordering. Al l SSP r e g isters are 16-bits wide and are located in the least significant half-wo r d of individu al words. The ARM[...]

SA-1100 De veloper’s M anual 11-1 75 Periphe ral Control Module 1 1.1 2.9.1 Data Size Sel ect (DSS) The 4-bit data size select (DS S) field is used to select the size of the data transmitted and received by the SSP . Data can be 4 to 16 bits in length. When data is programmed to be less than 16 bits, received data is automatica lly right justifie[...]

11-1 76 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.12.9.4 Serial Cloc k Rate (SC R) The 8-bit serial clo ck rate (SCR) bit field is used t o s elect the bau d or bi t rate of t he S SP . A total of 256 dif ferent b it rates can be selected, ranging from a minimu m of 7.2 Kbps to a maximu m of 1.8432 Mbps. The serial clock gener[...]

SA-1100 De veloper’s M anual 11-1 77 Periphe ral Control Module 1 1. 12.10 SSP Control Register 1 The SSP control register 1 (SSCR1) contains six dif ferent bit fields that control various function s within the SSP . 1 1.12.1 0.1 Receive FIFO Interrupt Enable (RIE) The receive FIFO interrupt en able (RIE) bit is used to mask or enable the receive[...]

11-1 78 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1 .12.10.5 Serial Cloc k Phase (SPH ) The serial clock phase (SPH) bit selects the phase relatio nship of the serial clock (SCLK) signal with the serial frame (S FRM) signal when Moto rola* SPI form at is selected (FRF=00). When SPH=0, SC LK remains in its inactive st ate (as pro[...]

SA-1100 De veloper’s M anual 11-1 79 Periphe ral Control Module 1 1.12. 10.6 Ext ernal Clock Sele ct (EC S) The external clock select (EC S) bit selects whether the on-chip 3. 6864-MHz clock is used by the SSP or if an off-chip clock is supplied vi a GPIO pin 1 9 . When ECS=0, the SS P uses the on- chip 3.6864-MHz clock to produce a range of seri[...]

11-1 80 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.12.1 1 SSP Data Register The SSP data regi ster (SSDR) is 1 6 bits wide and correspon ds to the top and b ottom entries of t he transmit and receive FIFOs, respectively . When SSDR is read, the bottom entry of receive FIFO is accessed. As data is removed by the SSP’ s receive[...]

SA-1100 De veloper’s M anual 11-1 81 Periphe ral Control Module 1 1. 12.12 SSP St atus Register The SSP status register (SSSR) con tains bits that signal overrun errors as well as the transmit and receive FIFO service req uests. Each of these hardwar e-detected events signals an interrupt request to the interrupt con troller . The status register[...]

11-1 82 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.12.12.5 R eceive FIFO Service Request Flag (RFS) (read-only , maskable interrupt) The receive FIFO service request flag (RFS) is a re ad-only bit that is set when the rec eive FIFO is nearly filled and requires service to prevent an overrun. RFS is set whenever the receive FIFO[...]

SA-1100 De veloper’s M anual 11-1 83 Periphe ral Control Module 1 1.12. 13 MCP Register Locations T able 1 1-1 9 shows the register s associated with the MCP and the ph ysical addresses used to access them . 1 1. 12.14 SSP Regis ter Locations T able 1 1-20 shows the registers associ ated with the SSP and the physi cal addresses used to access the[...]

11-1 84 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.13 Peripheral Pin Controll er (PPC) The peripheral pin con troller (PPC) takes individual con trol of the LCD’ s and serial port 1..4’ s pins when one or more of the u nits are disabled, allowing the user to utilize them as general-purpose digital I/O pins to communicate to[...]

SA-1100 De veloper’s M anual 11-1 85 Periphe ral Control Module Serial port 1 and serial port 4 both contain two serial-to-parallel engines th at operate independ ently . However , because each port contains only on e set of serial pins, the user can assign these pins to only one of the two protoc ols at a time. T o allo w the user to utilize bot[...]

11-1 86 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e Bit Name Descri ption 7..0 LDD<7:0 > LCD data pin direction. 0 – If LCD controller disabled, LCD data pin configured as general-purpose input. 1 – If LCD controller disabled, LCD data pin configured as general-purpose output. 8 L_PCLK LCD pix el clock pin direction. 0 –[...]

SA-1100 De veloper’s M anual 11-1 87 Periphe ral Control Module 1 1. 13. 4 PPC Pin State Register Pin state is bot h mon itored and co ntro ll ed by r eading/ writing t he P PC pin st ate regist er (PPS R). The PPSR contains 1 state bit for each of the 22 peripheral pins. This register may be read at any time to determine the current st ate o f a[...]

11-1 88 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e Bit Name Description 7..0 LDD<7:0 > LCD data pin state. Read – Current s tate of LCD data pin returned. Write – If LCD disabled and p in configured as an output, drive v alue to LCD data pin. 8 L_PCLK LC D pixel clock pin state. Read – Current state of LCD pixe l clock [...]

SA-1100 De veloper’s M anual 11-1 89 Periphe ral Control Module 1 1. 13. 5 PPC Pin Assignment Register The UAR T in serial port 1 and the SSP in serial port 4 can be reassigned to GPIO pins using the PPC pin assign ment regi ster (PP AR) . The PP AR contains two bits th at contro l the reassignm ent of each serial engine to an indi vidual set of [...]

11-1 90 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.13.6 PPC Sleep Mode Pin Direct ion Register When sleep mode is entered, reset is asserted to all of the SA-1 100’ s peripherals and to the PPC unit. The PPC pin direction register is cleared during a hard, soft, or sleep reset, causing the peripheral pins under the PPC’ s c[...]

SA-1100 De veloper’s M anual 11-1 91 Periphe ral Control Module Bit Name Description 7..0 LDD<7:0 > LCD data sleep mode pin direction. 0 – LCD data pin c onfigured as output and is driven low during sleep. 1 – LCD data pin c onfigured as input during sleep. 8 L_PCLK LCD pixel clock sleep mode pin direction. 0 – LCD pixel cl ock pin co[...]

11-1 92 SA-1100 Deve loper’ s Manual Periphe ral Contr ol Modul e 1 1.13.7 PPC Pin Flag Register The PPC pin flag register (PPFR) is used to determine which p eripherals are currently under the control of the PPC unit. The eight read-only flags denote whether or not each o f the peripherals (except serial port 0) is enabled or is disabled and bei[...]

SA-1100 De veloper’s M anual 11-1 93 Periphe ral Control Module 1 1.13. 8 PPC Register Locations T able 1 1-21 shows the registers associated with the PPC and the ph ysical addresses used to access them. Note that serial port 2 ( I C P) has implemen t ed HSSP control register 2 and serial port 4 (MCP) has also implemented MCP control regist er 1 [...]

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SA-1100 De veloper’s M anual 12-1 DC Parameters 12 This chapter defines the dc parameters for the Intel ® Stro ngARM ® SA-1 100 Microprocessor (SA-1 100). 12.1 Absolute Maxi mum Ratings T able 12-1 lists the absolut e maximum ratings for the SA -1 100. T able 12-1. SA-1 100 DC Maximum Ra tings Symbol Paramete r Min Max Units Note VDD C ore supp[...]

12-2 SA-1100 Deve loper’ s Manual DC Parameters 12.2 D C Operating Cond itions T able 12- 2 lists the functional op erating dc parameters for the SA-1100. T able 12-2. SA-1 100 DC Oper ating Conditions Symbol Parameter Min Nom Max Units Notes Vihc † I C input high voltage 0.8 × VDDX — VDDX V 1, 2 Vilc † I C input low voltage 0.0 —0 . 2 ?[...]

SA-1100 De veloper’s M anual 12-3 DC Parameters 12.3 Power Supply V oltages and Cu rrents T able 12-3 specifi es the po wer supp ly voltages and current s for th e SA-110 0. For power s upply voltages and curren ts for 2.0-V devices, contact the In tel Massachusetts Customer T echnology Cent er . . † AA, CA, DA and EA refer to TQFP pac kage. AB[...]

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SA-1100 De veloper’s M anual 13-1 AC Parameters 13 This chapter defines the ac p arameters for the Intel ® StrongARM ® SA-1 100 Micr oprocessor (SA-1 100). 13.1 T est Conditio ns The AC timing diagram s presented in this chapter assume that the o utputs of SA-1 100 have been loaded with a 50-pF capacitive load on output signals. The output pads[...]

13-2 SA-1100 Deve loper’ s Manual AC Paramete rs 13.2 Modu le Consideration s The edge rates for the SA-1 100 processor are such that the lumped load model pr esented ab ove can only be used for etch lengths up to one inch. Over one inch of etch, the signal is a transmission line and needs to be mod eled as such. 13.3 Me mory Bus and PCMCIA Sign [...]

SA-1100 De veloper’s M anual 13-3 AC Paramete rs 13.4 LCD Contro ller Signals Figure 13-2 describes the LCD timing parameters. Th e LCD pin timing specifi cation s are referenced to the p ixel clock (L_PCLK). 13.5 MCP Signals Figure 13-3 describes the MCP timing parameters. The MCP pin timing specification s are referenced to SCLK_C. Figure 13-2.[...]

13-4 SA-1100 Deve loper’ s Manual AC Paramete rs 13.6 Timing Parameters T able 13- 2 lists the ac timing parame ters for the S A-1 100 for AA and BA parts. For timing parameters for 2.0- V devices, contact the Intel Massachusetts Customer T echnology Center . T able 13-2. SA-1 100 AC Timing T able for AA and BA Parts Pin Name Symbol Parameter Min[...]

SA-1100 De veloper’s M anual 13-5 AC Paramete rs 13.6.1 Asynchronous Signal Timing Descriptions nPW AIT is an input and is received t hrough a synchronizer . As such, it has no setup and ho ld specification. The user must adhere to the protocol definition. When the peripheral pins are in GPIO mode, they are read or written under software con trol[...]

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SA-1100 De veloper’s M anual 14-1 Package and Pinout 14 14.1 Mechanical Data a nd Packagin g Information Figure 14-1 sh ows t he SA-1 100 208-pin LQFP mechanical drawi ng. All measu remen ts are in millime ters. T able 1 4-1 lists the SA-1 100 pins in numeric order , showing th e signal typ e for each pin. . Figure 14-1. Quad Fla t Pack – 1.4mm[...]

14-2 SA-1100 Deve loper’ s Manual Packag e and P inout Note: All VDDX1 , VDDX2 , and V DDX3 pins should be connected directly to the VDDX power plane of the sy stem boar d. VDDP should be connected directly to the VDD plane o f the system board. Ta b l e 1 4 - 1 . SA-1 100 Pinout – 208-Pin Quad Flat Pack Pin Signal T ype Pin Signal T ype Pi n S[...]

SA-1100 De veloper’s M anual 14-3 Pack age and Pi nout 14.2 Mini-Ball Grid Array – (mBGA) Figure 14-2 s hows the SA-110 0 256 min i-ball gr id array (mBGA) mech anical drawin g. T able 14-2 lists the SA-1100 pin s in numeric or der, showing the signal type for each pin . Figure 14-2. SA-1 1 00 256 Mini-Ball Grid Array Mechanical Dr awing A6843-[...]

14-4 SA-1100 Deve loper’ s Manual Packag e and P inout Note: All VDDX1 , VDDX2 , and V DDX3 pins should be connected directly to the VDDX power plane of the sy stem boar d. VDDP should be connected directly to the VDD plane o f the system board. Ta b l e 1 4 - 2 . SA-1 100 Pinout – 256-Pin Mini-Ball Grid Array Pin Signal T ype BGA Pad Pin Signa[...]

SA-1100 De veloper’s M anual 15-1 Debug Support 15 Due to the integ ration level o f the Intel ® Stro ngARM ® SA-1 100 Microproces sor (SA-1 100), man y functions are not directl y visib le on the external pins . Therefore, some b asic debug facilities are provided that are not present on the Intel ® StrongARM ® SA-110 Microprocessor (SA-1 10[...]

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SA-1100 De veloper’s M anual 16-1 Boundary-Scan T est Interface 16 The boundar y-scan interface conforms to the IEEE Std. 1 149.1 – 1990, Standa r d T est Access Port and Bound ary-Scan Ar chitectur e. (Refer to this standard for an explanation of the terms used in this section an d for a description of the T AP controller states.) The Intel ®[...]

16-2 SA-1100 Deve loper’ s Manual Bound ary-Sca n T est I nterface 16.2 Reset The boundary -scan interface includ es a state-machine controller (the T AP controller). I n order to force the T AP controller into th e correct state after po w er -up of th e device, a reset pulse must be applied to the nTRST pin. If the b oun dary -scan in terface i[...]

SA-1100 De veloper’s M anual 16-3 Boundar y-Scan T est Interfac e 16.5.1 EXTEST (00000) The boundar y-scan (BS) register is placed in test mode by the EXTEST instruction. The EXTEST instruction connects the BS r egister between TDI and TDO. When the instruction register is loaded with the EXTEST instruction, all the boundary- scan cells are place[...]

16-4 SA-1100 Deve loper’ s Manual Bound ary-Sca n T est I nterface 16.5.4 HIGHZ (00101) The HIGHZ instruction connects a 1- bit shift register (the BYP ASS register) between TDI and TDO. When the HIGHZ instruction is loaded into the instruction register , all outputs are placed in an inactive drive state. In the CAP TURE-DR state, a logic 0 is ca[...]

SA-1100 De veloper’s M anual 16-5 Boundar y-Scan T est Interfac e 16.6 T est Data Registers Figure 16-2 illustrates the structure of the bound ary-scan logic. Figure 16-2. Boundary-Scan Block Diagr am 16.6.1 Bypass R egister Purpose: This is a single- bit register that can be selected as the path between TDI and TDO to allow the devi ce to be by [...]

16-6 SA-1100 Deve loper’ s Manual Bound ary-Sca n T est I nterface 16.6.2 SA-1 100 Device Identification (ID) Code Register Purpose: This register is used to read the 32-bit device identification code. No program mable supp lem entary id entification code is p rovided. Length: 32 b its Operating Mode: When the IDC ODE instruction is current, the [...]

SA-1100 De veloper’s M anual 16-7 Boundar y-Scan T est Interfac e 16.7 Boundary-Sca n Interface Signals Figure 16-3. Boundary-Scan General Timing A4772-01 tck Data In Data Out tdo tms, tdi Tbscl Tbsch Tbsis Tbsih Tbsoh Tbsod Tbsss Tbssh Tbsdh Tbsdd[...]

16-8 SA-1100 Deve loper’ s Manual Bound ary-Sca n T est I nterface Figure 16-4. Boundary-Scan T ristate Timing Figure 16-5. Boundary-Scan Reset Timing A4773-01 tck Data Out tdo Tbsoe Tbsoz Tbsde Tbsdz A4771-01 ntrst tms Tbsrs Tbsr Tbsrh[...]

SA-1100 De veloper’s M anual 16-9 Boundar y-Scan T est Interfac e T able 16-1 shows the SA-1 100 boundary-scan in terface timing specifications. T able 16-1. SA-1 100 Boundary-Scan Interface Timing Symbol Parameter Minimum T ypical Maximum Units Notes Tbscl TCK low pe riod 50 –– n s 8 Tbsch TCK high period 50 – – ns 8 Tbsis TDI , TMS setu[...]

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SA-1100 De veloper’s M anual A-1 Register Summary A This appendi x describes all of the Intel ® St rongARM ® SA-1 100 Micro processor (SA-1 100) internal registers . Physical Address Symbol Register Name GPIO Registers 0h 9004 0000 GPLR GPIO pin level register . 0h 9004 0004 GPDR GPIO pin direc tion register . 0h 9004 0008 GPSR GPIO pin output [...]

A-2 SA-1100 Deve loper’ s Manual Register S ummary Power Manager Registers 0h 9002 0000 PMCR Power m anager control register . 0h 9002 0004 PSSR Power m anager sleep status register . 0h 9002 0008 PSPR Powe r manager scra tchpad register . 0h 9002 000C PWER Power m anager wakeup enable r egister . 0h 9002 0010 PCFR Power m anager configuration re[...]

SA-1100 De veloper’s M anual A-3 Reg ist er Su mmar y 0h B000 0044 DCSR2 DMA control/status register 2 – write ones to set. 0h B000 0048 Wr ite ones to clear . 0h B000 004C Read only . 0h B000 0050 DBS A2 DMA buffer A start addres s 2. 0h B000 0054 DBT A2 DMA buffer A transfer count 2. 0h B000 0058 DBS B2 DMA buffer B start addres s 2. 0h B000 [...]

A-4 SA-1100 Deve loper’ s Manual Register S ummary LCD Controller Registers 0hB010 0000 LCCR 0 LCD controller control register 0. 0hB010 0004 LCS R LCD controller status register . 0hB010 0008 – 0hB010 000C — Reserved. 0hB010 0010 DB AR1 DMA channel 1 base address register . 0hB010 0014 DCA R1 DMA channel 1 current address register . 0hB010 0[...]

SA-1100 De veloper’s M anual A-5 Reg ist er Su mmar y SDLC Registers (Serial Port 1) 0h 8002 0060 SDCR0 SDLC control reg ister 0. 0h 8002 0064 SDCR1 SDLC control reg ister 1. 0h 8002 0068 SDCR2 SDLC control reg ister 2. 0h 8002 006C SDCR3 SDLC control register 3. 0h 8002 0070 SDCR4 SDLC control reg ister 4. 0h 8002 0074 — Reserved. 0h 8002 0078[...]

A-6 SA-1100 Deve loper’ s Manual Register S ummary UART Registers (Serial Port 3) 0h 8005 0000 UTCR0 UART control register 0. 0h 8005 0004 UTCR1 UART control register 1. 0h 8005 0008 UTCR2 UART control register 2. 0h 8005 000C UTCR3 UART control register 3. 0h 8005 0010 — Reserved. 0h 8005 0014 UTDR UART data register . 0h 8005 0018 — Reser v[...]

SA-1110 De veloper’s M anual B-1 3.6864–MHz Oscillator Specifications B A 3.6864-MHz c rystal oscillat or is i ntegrated o n the Inte l ® Strong ARM ® SA- 110 0 Micropr ocessor (SA-1 100) for use as a reference frequency for the PLLs that generate the i nternal clocks t o the processor . The p h ase noise of this reference frequency sho uld b[...]

B-2 SA-1110 Deve loper’ s Manual 3.6864– MHz Osci llator Sp ecificati ons approximately twice the values given, the s tartup time in this situatio n will be about doub le the specified startup tim e and the current consumption will increase. Capacitances larger than twice the specified values may preven t the oscillator from starting. B.1.1. 1.[...]

SA-1110 De veloper’s M anual B-3 3.6864–MHz Oscilla tor Specif ications B.1.2 Quartz Crystal Specification The following specifications fo r the quartz crystal are shown in the figure and table below . Resonance frequency ( fs ): Resonance frequency of t he crystal. Motional capacitance ( Cm ): Equivalent serial capac itance in the crystal mode[...]

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SA-1100 De veloper’s M anual C-1 32.768–kHz Oscillator Specifications C A 32.768-kHz crystal o scillator is in tegrated on the In tel ® StrongARM ® SA-1 100 Microprocessor (SA-1 100) for use as a time base for the real- time clock (R TC). The output frequency of the crystal oscillator is divided by 32768 (2 15 ) to deliver a 1-Hz signal t o t[...]

C-2 SA-1100 Deve loper’ s Manual 32.768– kHz Os cillato r Speci fica tions approximately twice the v alues given; the startu p tim e in this situation will b e about double the specified startup tim e and the current consumption will increase. Capacitances larger than twice the specified values may preven t the oscillator from starting. C.1.1.4[...]

SA-1100 De veloper’s M anual C-3 32.768–k Hz Oscilla tor Spec ifications C.1.2 Quartz Crystal Specification The following specifications fo r the quartz crystal are shown in the figure and table below . Parasitic capacitance off - chip between TXT AL or TEXT AL and VSS ——2 p F Parasitic resistance between TXT A L or TEXT AL to VSS 1 0 —?[...]

C-4 SA-1100 Deve loper’ s Manual 32.768– kHz Os cillato r Speci fica tions The following valu es are not required for the crystal os cillator to function , but th ey d irect ly affect the performance of the oscillator in the system because they determine the accuracy of the crystal itself. The values given represent those seen on typical cr yst[...]

SA-1100 De veloper’s M anual D-1 Internal T es t Internal T est D The T est Unit contains a reg i ster that enables certain test modes. Some of these test modes are reserved fo r manufacturing tes t and should no t be invoked by an end user . D.1 T est Unit Control Registe r (TUCR) The T est Unit Contro l R egister (TUCR) contains control bits th[...]

D-2 SA-1100 Deve loper’ s Manual Internal T est 27..28 Reserved — 29..31 T SE L2-0 T est selects. Routes internal signals out onto GPIO<27> for observing i nternal clock signals. T o observe these clocks, set bit 27 to one in the GAFR and GPDR registers and set the TSEL bits to the following settings to select which clock is driven onto G[...]

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