NEC PD75P402 Bedienungsanleitung

USER'S MANUAL µ PD75402A 4-BIT SINGLE-CHIP MICROCOMPUTER µ PD75402A µ PD75P402 Document No. IEU1270C (O. D. No. IEU-644D) Date Published March 1994 P Printed in Japan © NEC Corporation 1989[...]

The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for inf[...]

Major Revisions in This Version Section Description Amendment: Fig. 5-52 “Data Transmission from Slave Device to Master Device” Change: Appendix B “Development Tools” P.117 P.179 to 181 The mark ★ shows main revised points.[...]

PREFACE USER This manual is intended for user engineers who wish to understand the µ PD75402A’s, 75P402’s functions and design an application system using them. OBJECTIVE The objective of this manual is for the user to understand the µ PD75402A’s, 75P402’s hardware functions shown below. COMPOSITION This manual is composed roughly of the [...]

Related Documentation Device Related Documents Document Name Document Number IE-75000-R/IE-75001-R User's Manual EEU-846 IE-75000-R-EM User's Manual EEU-673 EP-75402C-R User's Manual EEU-701 EP-75402GB-R User's Manual EEU-702 PG-1500 User's Manual EEU-651 RA75X Assembler Package l EEU-731 User's Manua EEU-730 PG-1500 C[...]

- i - CONTENTS CHAPTER 1. GENERAL ............................................................................................................................... 1 1.1 OUTLINE OF FUNCTIONS . .......................................................................................................................... 2 1.2 ORDERING INFORMATION AND QUALI[...]

- ii - CHAPTER 4. INTERNAL CPU FUNCTIONS ........................................................................................... 3 1 4.1 PROGRAM COUNTER (PC) ........................................................................................................................... 3 1 4.2 PROGRAM MEMORY (ROM) . .................................[...]

- iii - 6.5 MACHINE CYCLES BEFORE INTERRUPT SERVICING .............................................................................. 135 6.6 INTERRUPT APPLICATIONS ........................................................................................................................ 1 37 CHAPTER 7. STANDBY FUNCTION . ..............................[...]

- iv - CONTENTS OF FIGURES Fig. No Title Page 3-1 Static RAM Address Updating Method ............................................................................................. 25 4-1 Program Counter Configuration ......................................................................................................... 31 4-2 Program Memory Map ..[...]

- v - Fig. No. Title Page 5-32 Example of SBI Serial Bus System Configuration ........................................................................... 93 5-33 SBI Transfer Timing ............................................................................................................................. 95 5-34 Bus Release Signal ...............[...]

- vi - CONTENTS OF TABLES Table No. Title Page 1-1 Differences Between µ PD75402A and µ PD75402, 75P402 ................................................................. 4 2-1 Port Pin List ........................................................................................................................................... 11 2-2 List of Pin[...]

1 CHAPTER 1. GENERAL Name Program Memory Data Memory µ PD75402A 1920 × 8 (mask ROM) 64 × 4 (RAM) µ PD75P402 1920 × 8 (one-time PROM) 64 × 4 (RAM) CHAPTER 1. GENERAL The µ PD75402A, 75P402 is a CMOS 4-bit single-chip microcomputer adopting the 75X architecture. With its built- in NEC standard serial bus interface (SBI), it is suitable as a sl[...]

2 CHAPTER 1. GENERAL Item Description 1.1 OUTLINE OF FUNCTIONS Number of basic instructions Instruction execution time Built-in memory General register Accumulators I/O line Pull-up resistor Clock output Timer/Counter Serial interface Vectored interrupt Test input Standby Instruction set Package 37 • 0.95 µ s, 1.91 µ s, 15.3 µ s (at 4.19 MHz o[...]

3 CHAPTER 1. GENERAL Ordering Code Package Program Memory µ PD75402AC- ××× 28-pin plastic DIP (600 mil) Mask ROM µ PD75402ACT- ××× 28-pin plastic shrink DIP (400 mil) µ PD75402AGB- ××× -3B4 44-pin plastic QFP ( ■ ■ 10mm) µ PD75P402C 28-pin plastic DIP (600 mil) One-time PROM µ PD75P402CT 28-pin plastic shrink DIP (400 mil) µ PD75[...]

4 CHAPTER 1. GENERAL Instruction execution time Port 5’s pull-up resistor Supply voltage Operating temperature range Package 1.3 DIFFERENCES BETWEEN µ PD75402A AND µ PD75402, 75P402 Table 1-1 shows the differences between the µ PD75402A and the µ PD75402, 75P402. Otherwise the µ PD75402A and the µ PD75402, 75P402 have the same functions and[...]

5 CHAPTER 1. GENERAL  BASIC INTERVAL TIMER SERIAL INTERFACE INTERRUPT CONTROL INTBT INTCSI SI SO/SB0 SCK INT0 INT2 PROGRAM COUNTER(11) ROM (PROM)  PROGRAM MEMORY 1920 × 8 bits ALU CY SP (5) DECODE AND CONTROL GENERAL REG. RAM DATA MEMORY 64 x 4 bits POR[...]

6 CHAPTER 1. GENERAL 1.5 PIN CONFIGURATION 1.5.1 28-Pin Plastic Dip (600 mil), Shrink Dip (400 mil) (1) Normal operating mode P00 to P03 : Port 0 SCK : Serial clock input/output P10, P12 : Port 1 SO/SB0 : Serial output/input/output P20 to P23 : Port 2 SI : Serial input P30 to P33 : Port 3 PCL : Clock output P50 to P53 : Port 5 INT0 : External vecto[...]

7 CHAPTER 1. GENERAL (2) PROM mode A0 to A14 : Address input O0 to O7 : Data input/output CE : Chip enable input OE : Output enable input V DD : Power supply V PP : Program power supply V SS : Ground V PP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 V SS 1 2 3 4 5 6 7 8 9 10 11 12?[...]

8 CHAPTER 1. GENERAL P30 P31 P32 V SS P33 P60 P61 NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 44 43 42 41 40 39 38 37 36 35 34 [...]

9 CHAPTER 1. GENERAL (2) PROM mode O0 O1 O2 NC NC V SS NC O3 O4 O5 NC A6 A7 A12 V PP NC NC NC V DD A14 A13 NC 1 2 3 4 5 6 7 8 9 10 11 23 24 25 26 27 28 29 30 31 32 33 12 13 14 15 16 17 18 19 20?[...]

CHAPTER 2. PIN FUNCTIONS 10 CHAPTER 2. PIN FUNCTIONS The µ PD75402A operates by the pin functions in the normal operating mode. For the µ PD75P402’s pin functions, the 2 modes of the normal operating mode ( µ PD75402A mode) and the PROM mode are available. The operating mode switches according to the V PP pin level as shown in the table below.[...]

11 CHAPTER 2. PIN FUNCTIONS Functions A 4-bit input port (Port 0). For P01 to P03, it is designatable to build in the pull-up resistor by software in 3-bit units. A 2-bit input port (Port 1). P10 is built in with the noise eliminator by the sampling clock. P12 is built in with the noise eliminator by analog delay. For P12, it is designatable to bui[...]

CHAPTER 2. PIN FUNCTIONS 12 Dual-Function Pin P10 P12 P03 P02/SB0 P01 P02/SO P22 2.1.2 List of Pins Other Than Port Pins Table 2-2 List of Pins Other than Port Pins Pin Name INT0 INT2 SI SO SCK SB0 PCL X1, X2 RESET V DD V SS NC * 8 Functions An edge-detected vectored interrupt request input pin (detected edge selectable by mode register). Built in [...]

13 CHAPTER 2. PIN FUNCTIONS Port 0 Dual-Function Pin Port 1 Dual-Function Pin P00 P10 INT0 P01 SCK P12 INT2 P02 SO/SB0 P03 SI 2.2 NORMAL OPERATING MODE 2.2.1 P00 to P03 (Port 0) ..... SCK, SO/SB0, SI Dual-Function Input P10, P12 (Port 1) ..... INT0, INT2 Dual-Function Input P00 to P03 are the 4-bit input port: Port 0’s input pins. P10 and P12 are[...]

CHAPTER 2. PIN FUNCTIONS 14 2.2.2 P20 to P23 (Port 2) ..... PCL Dual-Function 3-Stae Input/Otput P30 to P33 (Port 3) ..... 3-State Input/Output P50 to P53 (Port 5) ..... N-ch Open Drain Middle-Voltage (10 V) Input/Output P60 to P63 (Port 6) ..... 3-State Input/Output The 4-bit input/output port with the output latch: Port 2’s, 3’s, 5’s, 6’s[...]

15 CHAPTER 2. PIN FUNCTIONS V DD V DD X1 X2 PD75402A µ Crystal Resonator or Ceramic Oscillator X1 X2 PD74HC04 µ External Clock (Standard 4.194304 MHz) PD75402A µ 2.2.7 X1, X2 (Crystal) The built-in clock oscillation crystal/ceramic input. It is also possible to supply the clock from the exterior[...]

CHAPTER 2. PIN FUNCTIONS 16 2.3 PROM MODE The PROM mode is designatable in the µ PD75P402 alone. 2.3.1 A0 to A14 (Address) ..... Input A 15-bit address input pin at PROM write/verify, read. As the PROM built into the µ PD75P402 has 2K bytes, it is addressed by the low-order 11 bits (A0 to A10). A11 to A14 should be fixed to the low level. 2.3.2 O[...]

17 CHAPTER 2. PIN FUNCTIONS Input/Output Type µ PD75402A µ PD75P402 P00 B P01/SCK F - A P02/SO/SB0 F - B P03/SI B - C P10/INT0 B P12/INT2 B - C P20, P21, P23 P22/PCL P30 to P33 E - B P50 to P53 M M - A P60 to P63 E - B RESET B 2.4 PIN INPUT/OUTPUT CIRCUITS The input/output circuit of each pin is shown below in a partly simplified format. Table 2-[...]

CHAPTER 2. PIN FUNCTIONS 18 V DD P-ch P.U.R. enable IN P.U.R. V DD P-ch N-ch OUT data output disable V DD P-ch N-ch IN Type A (for Types E - B) Type B Type B - C Type D (for Type E - B, F - A, Y - D) Type E - B Type F - A IN P. U. R : Pull-Up Resistor P. U. R : Pull-Up Resistor P. U. R : Pull-Up[...]

19 CHAPTER 2. PIN FUNCTIONS V DD IN/OUT N-ch (+10 V Withstand Voltage) data output disable P.U.R (Mask Option) IN/OUT N-ch (+10 V Withstand Voltage) data output disable Type F - B Type M Type M - A P. U. R : Pull-Up Resistor Middle-High Voltage Input Buffer (+10 V Withstand Voltage) P. U. R : Pull-[...]

CHAPTER 2. PIN FUNCTIONS 20 V DD V DD V DD V DD Diode with Small V F P00, RESET P00, RESET 2.5 UNUSED PIN TREATMENT Pin P00 P01 to P03 P10 and P12 P20 to P23 P30 to P33 P50 to P53 P60 to P63 NC * If using the µ PD75P402 and the printed circuit board commonly, the NC pins should be connected directly to V SS . 2.6 NOTES ON U[...]

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 21 CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP The µ PD75402A’s architecture is a subset of the 75X architecture. Its features are outlined below. 3.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES 3.1.1 Data Memory Bank Configuration The µ PD75402A’s data memory space has a bank [...]

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 22 Adress 000H 003H 020H 03FH F80H FB0H FBFH FF0H FFFH Table 3-1 Data Memory Configuration and Address Range in Each Addressing Mode Addressing Mode Data Memory General Register Area Not built in. Stack Area mem mem. bit @ HL Stack Addressing fmem. bit Peripheral Hardw[...]

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 23 Table 3-2 Addressing Mode List Addressing Mode 1-bit direct addressing 4-bit direct addressing 8-bit direct addressing 4-bit register indirect addressing Bit manipulation addressing Stack addressing Notation mem. bit mem @HL fmem. bit – Specified Address The bit indicated by bit of the address[...]

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 24 3.1.2 Data Memory Addressing Modes In the µ PD75402A, the 6 types of addressing modes listed on Table 3-2 are available for the data memory space for efficient addressing per the bit length of the data to be processed. Also in the µ PD75402A, the memory bank to be accessed is fixed by the addr[...]

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 25 (3) 8-bit direct addressing (mem) An addressing mode to specify the whole data memory space directly by the instruction’s operand per 8 bits. The specified memory bank (MB) is MB = 0 if the address specified by the operand is 00H to 3EH and MB = 15 if it is 80H to FEH. Consequently, both the s[...]

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 26 P30 P61 P53 (i) SET1 CY ; CY ← 1 AND1 CY, PORT3. 0 ; CY ∧ P30 AND1 CY, PORT6. 1 ; CY ∧ P61 SKT CY ; CY = 1? BR SETP CLR1 PORT5. 3 ;P53 ← 0 . . SETP: SET1 PORT5. 3 ; P53 ← 1 (ii) SKT PORT3. 0 ; P30 = 1? BR SETP SKT PORT6. 1 ; P61 = 1? BR SETP CLR1 PORT5. 3 ; P53 ← 0 . . SETP:[...]

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 27 (6) Stack addressing This addressing mode is for the saving/restoring operation during the interrupting process, subroutine process. The data memory is addressed indirectly according to the content of the stack pointer (SP : 8 bits). The memory bank (MB) addressed in this addressing mode is fixe[...]

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 28 3.2 MEMORY-MAPPED I/O The µ PD75402A adopts memory-mapped I/O to map such peripheral hardware as the input/output port, serial interface at addresses F80H to FFFH in the data memory space shown in Table 3-1. As a result, there is no special instruction to control the peripheral hardware; the pe[...]

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 29 W W Bit 2 is fixed to 0. W W R/W R/W R/W R/W R/W R/W R/W R/W FB2H FB3H FB4H FB8H FBDH FBEH FBFH Bit 0 is fixed to 0. F80H F85H F86H W b3 b2 b1 b0 Stack pointer (SP) Basic interval timer mode register (BTM) Basic interval timer (BT) Table 3-4 µ PD75402A I/O Map (1/2) Address 1 Bit 4 Bits 8 Bits [...]

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 30 * 1 * 2 * 3 W W W RR RR R/W R/W R/W R/W R/W R/W R/W R/W Port 0 (PORT 0) Port 1 (PORT 1) Port 2 (PORT 2) Port 3 (PORT 3) Port 5 (PORT 5) Port 6 (PORT 6) FF0H FF1H FF2H FF3H FF5H FF6H R/W Serial operation mode register (CSIM) Table 3-4 µ PD75402A I/O Map (2/2) FE0H FE1H FE2H FE3H FE4H FE6H FE8H F[...]

CHAPTER 4. INTERNAL CPU FUNCTIONS 31 The program counter operates as follows. • Normal operation The content is incremented automatically according to the number of bytes of the instruction every time one is executed. • Branch instruction (BR, BRCB) execution The immediate data indicating the address of the destination of branching is set in th[...]

32 CHAPTER 4. INTERNAL CPU FUNCTIONS 4.2 PROGRAM MEMORY (ROM) ..... 1,920 WORDS × 8 BITS A mask programmable ROM of a 1,920-word × 8-bit configuration. It stores the program, table data, etc. The program memory is addressed by the program counter. It is also possible to read the table data in the ROM by the table refer instruction (MOVT). It is p[...]

CHAPTER 4. INTERNAL CPU FUNCTIONS 33 4.3 DATA MEMORY (RAM) The data memory consists of the data and peripheral hardware areas as shown in Fig. 4-3. Fig. 4-3 Data Memory Map (1) Data area The µ PD75402A’s data area consists of the static RAM (64 words × 4 bits). The data area is used to store processing data and is operated by the memory manipul[...]

34 CHAPTER 4. INTERNAL CPU FUNCTIONS (2) Peripheral hardware area The peripheral hardware area is mapped to memory bank 15’s addresses F80H to FFFH. The operation is performed by the memory manipulation instruction just as in the static RAM. In the peripheral hardware, however, the operable bit unit differs from one address to another. It is impo[...]

CHAPTER 4. INTERNAL CPU FUNCTIONS 35 4.4 GENERAL REGISTER ..... 4 × 4 BITS The general register is assigned to a specific address of the data memory. There are four 4-bit registers (H, L, X, A). While each general register is operated per 4 bits, HL and XA make up register pairs, each of which is operated per 8 bits. The HL register pair is availa[...]

36 CHAPTER 4. INTERNAL CPU FUNCTIONS 4.5 ACCUMULATOR In the µ PD75402A, the A register and the XA register pair function as accumulators. The 4-bit data process instruction is executed mainly by the A register and the 8-bit data process instruction is executed mainly by the XA register pair. In the bit manipulation instruction, the carry flag (CY)[...]

CHAPTER 4. INTERNAL CPU FUNCTIONS 37 4.6 STACK POINTER (SP) ..... 8 BITS The µ PD75402A uses a static RAM as the stack memory (LIFO format). The 8-bit register holding the top address information of such a stack memory area is the stack pointer (SP). Fig. 4-7 shows its format. As the SP’s high-order 3 bits are fixed to 001, the stack area is at [...]

38 CHAPTER 4. INTERNAL CPU FUNCTIONS Fig. 4-8 Data Saved to Stack Memory Stack Stack Stack Register Pair Low Order Register Pair High Order SP - 2 SP - 1 SP SP - 2 SP - 1 SP SP - 4 SP - 3 PC10 - PC8 0 0 0 0 0 PC3 - PC0 PC7 - PC4 SP - 2 SP - 1 SP SP - 4 SP - 3 SP - 6[...]

CHAPTER 4. INTERNAL CPU FUNCTIONS 39 4.7 PROGRAM STATUS WORD (PSW) ..... 8 BITS The program status word (PSW) consists of various flags concerning closely the processor operation. Fig. 4-10 shows its configuration. Saved to the stack memory per 8 bits at the interrupt acceptance and restored from the stack memory per 8 bits at the RETI instruction [...]

40 CHAPTER 4. INTERNAL CPU FUNCTIONS Example Take AND of bit 3 at address 3FH and P33 and set the result in CY. SET1 CY ; CY ← 1 SKT 3FH. 3 ; Skip if bit 3 at address 3FH is 1 CLR1 CY ; CY ← 0 AND1 CY, PORT 3. 3 ; CY ← CY ∧ P33 (2) Skip flag (SK2, SK1, SK0) The skip flag is a flag to store the skip status. It is set/reset automatically as t[...]

41 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 DIGITAL INPUT/OUTPUT PORTS The µ PD75402A has the following digital input/output ports on chip: Ports 0 through 3, 5 and 6. The µ PD75402A uses memory mapped I/O, and all input/output ports are mapped onto data memory space. All data memory handling instructi[...]

42 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1.1 Digital Input/Output Port Types, Characteristics and Configuration The different types of digital input/output ports are shown in Table 5-1, and the configuration of each port is shown in Figs. 5-2, 5-3, 5-4 and 5-5. Table 5-1 Digital Input/Output Port Types and Characteristics Port (Symbol) Functio[...]

43 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-2 Configuration of Ports 0 and 1 Input Buffer Internal Bus Input Buffer or f XX /64 Noise Elimination Circuit Input Buffer with Hysteresis Characteristics INT0 INT2 P12/INT2 P10/INT0 P-ch Pull-Up Resistor PO0 POGA Bit 0 V DD Output Buffer with C[...]

44 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-3 Configuration of Port 3 Remarks n = 0 to 3 Input Buffer PM 3 n=0 PM 3 n=1 M P X Output Latch PM 3 n PMGA Bit n Output Buffer POGA Bit 3 PO3 P-ch Pull-Up Resistor V DD P 3 n Internal Bus[...]

45 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-4 Configuration of Ports 2 and 6 * Input/output mode specification is performed by bit 2 (PM2) of PMGB for port 2 and by bits 4 to 7 (PM60 to 63) of PMGA for port 6. Remarks m = 2 or 6 Internal Bus Output Latch PM2/ PM60 to 63 Input Buffer POGA Bit m POm PMm = 0 PMm = [...]

46 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-5 Configuration of Port 5 Pull-Up Resistors (Mask Option; µ PD75402A Only) 5.1.2 Input/Output Mode Setting The input/output mode for each input/output port is set by a port mode register as shown in Fig. 5-6. For port 3, input/output can be specified bit by bit by port mode register group A (PMGA)[...]

47 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-6 Format of Port Mode Registers Port Mode Register Group A Port Mode Register Group B Specification 0 Input mode (output buffer off) 1 Output mode (output buffer on) Address 76543210 Symbol FE8H PM63 PM62 PM61 PM60 PM33 PM32 PM31 PM30 PMGA P30 Input/Output Specification P31 Input/Output Specificati[...]

48 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (1) Bit handling instructions Direct addressing of specific address bits (fmem.bit) can be used on all digital input/output ports. Example To OR P50 and P31 and output the result to P61. SET1 CY ; CY ← 1 AND1 CY, PORT5.0 ; CY ← CY ∧ P50 OR1 CY, PORT3.1 ; CY ← CY ∨ P31 SKT CY BR CLRP SET1 PORT6.1[...]

49 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1.4 Digital Input/Output Port Operations Port and port pin operations when a data memory handling instruction is executed for a digital input/output port differ according to the input/output mode setting (see Table 5-3). This is because, as can be seen from the input/ output port configurations, data fe[...]

50 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Table 5-3 Operations with Input/Output Port Handling Instructions SKT PORTn.bit SKF PORTn.bit AND1 CY, PORTn.bit OR1 CY, PORTn.bit XOR1 CY, PORTn.bit IN A, PORTn MOV A, PORTn OUT PORTn, A MOV PORTn, A XCH A, PORTn INCS PORTn SET1 PORTn.bit CLR1 PORTn.bit SKTCLR PORTn.bit Output Mode Tests output latch dat[...]

51 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1.5 Internal Pull-up Resistors The µ PD75402A can incorporate internal pull-up resistors for all port pins except P00 and P10. The µ PD75P402 can incorporate internal pull-up resistors for all port pins except P00, P10, and P50 through P53. As shown in Table 5-4, internal pull-up resistors can be spec[...]

52 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-7 Format of Pull-Up Resistor Specification Register Address 7 6 5 43210 Symbol FDCH – PO6 – – PO3 PO2 PO1 PO0 POGA Port 0 (P01 to P03) Port 1 (P12) Port 2 (P20 to P23) Port 3 (P30 to P33) Port 6 (P60 to P63) Specification 0 Pull-up resistor not incorporated 1 Pull-up resistor incorporated The[...]

53 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1.6 Digital Input/Output Port Input/Output Timing The timing for outputting data to the output latch and fetching pin data or output latch data onto the internal bus is shown in Fig. 5-9. Fig. 5-9 Digital Input/Output Port Input/Output Timing (a) Data fetch by 1-machine-cycle instruction (b) Data fetch [...]

54 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.2 CLOCK GENERATION CIRCUIT The clock generation circuit supplies various clocks to the CPU and peripheral hardware, and controls the operating mode of the CPU. 5.2.1 Clock Generation Circuit Configuration The configuration of the clock generation circuit is shown in Fig. 5-10. Fig. 5-10 Clock Generation[...]

55 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.2.2 Clock Generation Circuit Function and Operaion The clock generation circuit generates the CPU clock ( Φ ) and various clocks for supply to peripheral hardware, and controls the CPU operating mode, such as standby mode etc. Clock generation circuit operation is determined by the processor clock cont[...]

56 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-11 Processor Clock Control Register Format Note When using a calue of f XX such that 4.19 MHz < f XX ≤ 5.0 MHz, if maximum speed mode : Φ f XX /4 (PCC1, PCC0 = 11) is set as CPU clock frequency, 1 machine cycle is less than 0.95 µ s and the standard minimum value 0.95 µ s is not kept. There[...]

57 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (2) System clock oscillation circuit The system clock oscillation circuit oscillates by means of a crystal resonator or ceramic resonator connected to the X1 and X2 pins (standard: 4.194304 MHz). An external clock can also be input. Fig. 5-12 System Clock Oscillation Circuit External Circuitry (a) Crystal[...]

58 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-13 Example of Poor Resonator Connection Circuit (2/2) (c) Signal line close to varyin high current (d) Current flows an oscillator power supply line. (potentials at A, B and C fluctuate.) High current X1 X2 V DD V DD µ PD75402A X1 X2 A V DD V DD PORTn C B [...]

59 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS ; Assume PCC = 0011. MOV A, #0000 0.95 µ s/4.19 MHz MOV PCC, A ; PCC ← 0000 BR 16 machine cycles 15.3 µ s/4.19 MHz 5.2.3 CPU Clock Setting The CPU clock Φ is the clock supplied to the µ PD75402A’s internal CPU, and the reciprocal of this clock is the minimum instruction execution time (defined in [...]

60 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS As the PCC is set in 0 by RESET input, Φ is reset-started at the slowest speed (state in which the operating voltage range is wide). For this reason, in a system with a slow supply voltage rise (such as a system with a high- capacitance capacitor connected), correct operation is possible even when an ade[...]

61 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.2.4 Differences Between µ PD75402A and µ PD75402 Part of the clock generation circuit differs between the µ PD75402A and the µ PD75402. The µ PD75402 does not include the sections enclosed in dotted lines. Fig. 5-16 Clock Generation Circuit - Differences between µ PD75402A and µ PD75402 * Instruc[...]

62 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Next, the processor clock control register (PCC) of the µ PD75402 is shown below. Setting of bit 1 of the PCC is performed by a 4-bit memory handling instruction. At this time, ensure that bits 3, 2 and 0 are reset to “0” so that the pattern “00 × 0” is written. Fig. 5-17 µ PD75402 Processor Cl[...]

63 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulses from the P22/PCL pin, and is used to supply clock pulses to peripheral LSIs, etc. 5.3.1 Clock Output Circuit Configuration The configuration of the clock output circuit is shown in Fig. 5-18. Fig. 5-18 Clock Output Circuit Configuratio[...]

64 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.3.2 Clock Output Mode Register (CLOM) CLOM is a 4-bit register used to control clock output. CLOM is set by a 4-bit memory handling instruction. Bit handling instructions cannot be used. Also, this register cannot be read. RESET input clears CLOM to zero and selects the clock output disabled state. Fig.[...]

65 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.3.3 Clock Output Procedure Clock pulse output is performed by the following procedure. (i) Set the clock output mode register. (ii) Write 0 to the P22 output latch. (iii) Set the port 2 input/output mode to output. This procedure may be reversed depending on the treatment of P22/PCL prior to clock outpu[...]

66 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4 BASIC INTERVAL TIMER The µ PD75402A is equipped with an 8-bit basic interval timer which has the following functions: (a) Standard time generation (2 different time intervals) (b) Reading counter contents This basic interval timer can also be used as a watchdog timer for the detection of inadvertent [...]

67 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4.2 Basic Intercal Timer Mode Register (BTM) BTM is a 4-bit register which controls the operation of the basic interval timer. BTM is set by a 4-bit memory handling instruction. Bit operations are not possible. Example To set the interrupt generation interval to 1.95 ms (4.19 MHz). MOV A, #1111B MOV BTM[...]

68 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4.3 Basic Interval Timer Operation The basic interval timer (BT) is constantly incremented by the clock from the clock generation circuit, and sets the interrupt request flag (IRQBT) when it overflows. The BT count operation cannot be stopped. Either of two times can be selected as the interrupt generat[...]

69 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4.4 Examples of Basic Interval Timer Applications Example 1. In this example the basic interval timer is enabled, and the interrupt generation interval is set to 1.95 ms (at 4.19 MHz operation). SEL MB15 MOV A, #1111B MOV BTM,A ; Setting and start EI ; Enable interrupts EI IEBT ; Enable BT interrupts Ex[...]

70 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.5 SERIAL INTERFACE 5.5.1 Serial Interface Functions The µ PD75402A incorporates a clocked 8-bit serial interface, with the following three modes available. (1) Operation-halted mode This mode is used when no serial transfer is to be performed, and allows power dissipation to be reduced. (2) 3-wire seri[...]

71 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (3) SBI mode (serial bus interface mode) In the SBI mode, communication is performed with multiple devices by means of two lines: The serial clock (SCK) and the serial data bus (SB0). This mode conforms to the NEC serial bus format. In the SBI mode, the sender can output to the serial data bus an address [...]

72 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-24 Serial Interface Block Diagram   Internal Bus 8 8 8 Bit Test CSIM P03/SI P02/SO/SB0 P01/SCK Slave Address  Register (SVA)  Address Comparator Shift Registe (SIO)r Bus Release/ Command/Ac- Knowledge Detection Circuit Serial Clock?[...]

73 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (1) Serial operating mode register (CSIM) CSIM is an 8-bit register which specifies the serial interface operating mode, serial clock, wake-up function, etc. (See 5.5.3 (1) “Serial operating mode register” for details.) (2) Serial bus interface control register (SBIC) SBIC is an 8-bit register compose[...]

74 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (8) INTCSI control circuit Controls the generation of interrupt requests. In the following case, the interrupt requests (INTCSI) are generated and interrupt request flags (IRQCSI) are set (see Fig. 6-1 “Interrupt Control Circuit Block Diagram” ). • In 3-wire serial I/O mode An interrupt request is g[...]

75 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-25 Serial Operating Mode Register (CSIM) Format (1/2) Address 7 6 5 4 3 2 1 0 Symbol FE0H CSIE COI WUP 0 CSIM3 0 CSIM1 0 CSIM Serial Clock Selection Bit (W) Serial Interface Operating Mode Selection Bit (W) Wake-up Function Specification Bit (W) Signal from Address Comparator (R) Serial Interface O[...]

76 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Note If WUP = 1 is set during BUSY signal output, BUSY is not released. With the SBI, the BUSY signal is output after the BUSY release directive until the next fall of the serial clock (SCK). When setting WUP = 1, it is necessary to confirm that the SB0 pin has been driven high after BUSY is released befo[...]

77 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Remarks 1. The operating mode can be selected according to the setting of CSIE and CSIM3. CSIE CSIM3 Operating Mode 0 × Operation-halted mode 1 0 3-wire serial I/O mode 1 1 SBI mode 2. The P10/SCK pin status depends on the setting of CSIE and CSIM0 as shown below. CSIE CSIM1 P10/SCK Pin Status 0 0 Input [...]

78 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (2) Serial bus interface control register (SBIC) The format of the serial bus interface control register (SBIC) is shown in Fig. 5-26. SBIC is an 8-bit register composed of bits which control the serial bus and flags which indicate various statuses of the input data from the serial bus, and is mainly used[...]

79 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-26 Serial Bus Interface Control Register (SBIC) Format (2/3) Bus release trigger bit (W) RELT The bus release signal (REL) trigger output control bit. The SO latch is set (1) by setting this bit (RELT = 1), after which the RELT bit is automatically cleared (0). Note SB0 must not be cleared during a[...]

80 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-26 Serial Bus Interface Control Register (SBIC) Format (3/3) Acknowledge enable bit (R/W) ACKE When set before end of transfer ACK is output is synchronization with the 9th SCK clock cycle. When set after end of transfer ACK is output in synchronization with SCK immediately after execution of the s[...]

81 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (3) Shift register (SIO) The configuration around the shift register is shown in Fig. 5-27. SIO is an 8-bit register which carries out parallel- to-serial conversion and performs serial transmission/reception (shift operations) in synchronization with the serial clock. A serial transfer is started by writ[...]

82 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (4) Slave address register (SVA) SVA is an 8-bit register used by the slave to set the slave address value (its own specification number). SVA is a write-only register which is manipulated by 8-bit manipulation instructions. After RESET signal input, the value of SVA is indeterminate. However, when RESET [...]

83 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.5.4 Operation-Halted Mode The operation-halted mode is used when no serial transfer is performed, allowing power dissipation to be reduced. In this mode, the shift register does not perform shift operations and can be used as an ordinary 8-bit register. When the RESET signal is input the operation-halte[...]

84 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Serial clock selection bit (W) The P01/SCK pin status depends on the CSIM1 setting as shown below. CSIM1 P01/SCK Pin Status 0 High impedance 1 High level The following procedure should be used to clear CSIE during a serial transfer. ➀ Clear the interrupt enable flag (IECSI) to set the interrupt disabled[...]

85 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (a) Serial operating mode register (CSIM) When the 3-wire serial I/O mode is used, CSIM is set as shown below (see 5.5.3 (1) “Serial operating mode register” for full details of CSIM). CSIM is manipulated by 8-bit memory manipulation instructions. Bit manipulation of bits 7, 6 and 5 is also possible. [...]

86 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Signal from address comparator (R) Clearing Conditions (COI = 0) Setting Condition (COI = 1) When slave address register (SVA) and shift register data do not match. COI * When slave address register (SVA) and shift register data match. Shift Register Operation Serial Clock Counter IRQCSI Flag SO/SB0 &[...]

87 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (b) Serial bus interface control register (SBIC) When the 3-wire serial I/O mode is used, SBIC is set as shown below (see 5.5.3 (2) “Serial bus interface control register” for full details of SBIC). SBIC is manipulated by bit manipulation instructions. Reset input clears the SBIC register to 00H. The [...]

88 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (2) Communication operation In the 3-wire serial I/O mode, data transmission/ reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Shift register shift operations are performed in synchronization with the fall of the serial clock (SCK). T[...]

89 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (3) Serial clock selection Serial clock selection is performed by setting bit 1 of the serial operating mode register (CSIM). Either of the following clocks can be selected. Table 5-6 Serial Clock Selection and Use (in 3-Wire Serial I/O Mode) Serial Clock CSIM 1 Source Serial Clock Masking Possible Timing[...]

90 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (5) Data transfer order The µ PD75402A 3-wire serial I/O mode differs from that of other 75X series products in that it is not possible to switch between MSB and LSB as the first bit. Serial transfer is performed MSB-first. Fig. 5-31 Shift Register (SIO) and Internal Bus Configuration (6) Start of transf[...]

91 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (7) 3-wire serial I/O mode applications (a) To transfer data MSB-first (master operation) using a 262 kHz transfer clock (when operating at 4.19 MHz). <Sample program> MOV XA, #10000010B MOV CSIM, XA ; Transfer mode setting MOV XA, TDATA ; TDATA is transfer data storage address MOV SIO, XA ; Transfe[...]

92 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (b) To transmit/receive MSB-first data using an external clock (slave operation). ➤ ➤ ➤ P01/SCK µ PD75402A SI SO/SB0 SCK SO SI Other Microcomputer <Sample program> Main routine MOV XA, #80H MOV CSIM, XA ; Serial operation stopped, external clock specification MOV XA, TDATA MOV SIO, XA ; Trans[...]

93 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.5.6 SBI Mode Operation The SBI (serial bus interface) is a high-speed serial interface which conforms to the the NEC serial bus format. The SBI is a single-master high-speed serial bus. Its format includes the addition of bus configuration functions to the clocked serial I/O method to enable communicati[...]

94 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (1) SBI functions Since conventional serial I/O methods have only data transfer functions, when a serial bus is configured with multiple devices connected a large number of ports and wires are required for Chip Select signal and command/ data differentiation, busy status recognition, etc. If these control[...]

95 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (2) SBI definition The SBI serial data format and the meaning of the signals used are explained in the following section. Serial data transmitted via the SBI is classified into three types: Commands, addresses and data. Serial data forms a frame with the configuration shown below. Address, command and dat[...]

96 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS SCK SB0 “H” The bus release signal indicates that the master is about to send an address to a slave. Slaves incorporate hardware to detect the bus release signal. (b) Command signal (CMD) The command signal indicates that the SB0 line has changed from high to low when the SCK line is high (wh[...]

97 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (c) Address An address is 8-bit data output by the master to slaves connected to the bus line in order to select a particular slave. Fig. 5-36 Address SCK SB0 Bus Release Signal Command Signal Address 1 2 3 4 5 6 7 8 A7 A6 A5 A4 A3 A2 A1 A0 Th[...]

98 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (d) Command & data The master performs command transmission to or data transmission/reception to/from the slave selected by address transmission. Fig. 5-38 Command SCK SB0 Command Signal Command 1 2 3 4 5 6 7 8 C7 C6 C5 C4 C3 C2 C1 C0 Fig. 5-[...]

99 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (e) Acknowledge signal (ACK) The acknowledge signal is used to confirm serial data reception between the sender and receiver. Fig. 5-40 Acknowledge Signal The acknowledge signal is a one-shot pulse synchronized with the fall of SCK after an 8-bit data transfer. Its position is arbitrary and it can be sync[...]

100 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (f) Busy signal (BUSY), ready signal (READY) The busy signal notifies the master that a slave is preparing for data transmission/reception. The ready signal notifies the master that a slave is ready for data transmission/reception. Fig. 5-41 Busy Signal & Ready Signal With the SBI a slave reports its[...]

101 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (3) Register setting When the device is used in the SBI mode, setting can be performed by means of the following two registers: • Serial operating mode register (CSIM) • Serial bus interface control register (SBIC) (a) Serial operating mode register (CSIM) When the SBI mode is used, CSIM is set as sh[...]

102 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Wake-up function specification bit (W) IRQCSI set at end of every serial transfer in SBI mode mask state. User only when functioning as a slave in SBI mode. IRQCSI is set only when the address received after bus release matches the slace address register data (wake-up status). SB0 is high impedance. 1 0 [...]

103 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (b) Serial bus interface control register (SBIC) When the SBI mode is used, SBIC is set as shown below (see 5.5.3 (2) “Serial bus interface control register” for full details of SBIC). SBIC is manipulated by bit manipulation instructions. Reset input clears the SBIC register to 00H. The shaded area i[...]

104 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Bus release detection flag (R) Clearing Conditions (RELD = 0) Setting Condition (RELD = 1) ➀ When a transfer start instruction is executed ➁ When RESET is input ➂ When CSIE = 0 (See Fig. 5-25) When SVA and SIO do not match when an address is received RELD When the bus release signal (REL) is de- te[...]

105 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Busy enable bit (R/W) 0 ➀ Disablin of automatic busy signal output ➁ Busy signal output is stopped in synchronization with the fall of SCK immediately after execution ofthe clearing instruction. The busy signal is output in synchronization with the fall or SCK following the acknowledge signal. 1 BSYE[...]

106 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (5) Signals The operation of signals and flags in SBIC in the SBI mode are shown in Figs. 5-42 to 5-47, and SBI signals are listed in Table 5-8. Fig. 5-42 RELT, CMDT, RELD & CMDD Operation (Master) Fig. 5-43 RELT, CMDT, RELD & CMDD Operation (Slave) Tramsfer Start Directive SIO SCK SB0?[...]

107 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-44 ACKT Operation Note ACKT must not be set before the end of a transfer. SCK SB0 ACKT When set in this interval ACK signal is output in 1  clock interval immediately  after ACKT is set. ACK D2 D1 D0 6 7 8 9[...]

108 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-45 ACKE Operation (a) When ACKE = 1 on completion of transfer (b) When ACKE is set after completion of transfer SCK SB0 ACKE When ACKE = 1 at this point ACK signal is output in 9th clock cycle. 1 2 7 8 9 D7 D6 D2 D1 D0 ACK SCK SB0 ACKE Wh[...]

109 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-46 ACKD Operation (a) When ACK signal is output in 9th SCK clock interval (b) When ACK signal is output after 9th SCK clock interval 6 Transfer Start Directive Start of Transfer SIO SCK SB0 ACKD 7 8 9 D2 D1 D0 ACK (c) Clearing timing when transfer start[...]

110 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Table 5-8 Signals in SBI Mode (1/2) Signal Name Output Device Timing Chart Definition Output Condition Effect on Flag Meaning of Signal — Outputs next CMD signal and indicates send data is address. i) After REL signal output send data is address. ii) send data with no REL signal output is command. Rece[...]

111 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Table 5-8 Signals in SBI Mode (2/2) Signal Name Output Device Timing Chart Definition Output Condition Effect on Flag Meaning of Signal Timing of signal output to serial data bus Address value of slave device on serial bus Directive, meddage, etc., to slave device. Data to ve processed by slave or master[...]

112 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (6) Pin configuration The configuration of the serial clock pin (SCK) and the serial data bus pin SB0 is as shown below. (a ) SC K .................... Pin for input/output of serial clock ➀ Master ........ CMOS, push-pull output ➁ Slave ........... Schmitt input (b ) S B0 .................... Serial[...]

113 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (7) Address match detection method In the SBI mode, master address communication is used to select a specific slave and start communication. Address match detection is performed by hardware. A slave address register (SVA) is provided, and IRQCSI is set only when the address sent from the master and the v[...]

114 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-49 Address Transmission form Master Device to Slave Device (WUP = 1) RELT Setting CMDT Setting Serial Transmit Operation Write  to SIO IRQCSI Gene- ration ACKD Setting SCK Stop- page Interrupt Servicing (Preparation for Next Serial Transfer) 1 [...]

115 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-50 Command Transmission from Master Device to Slave Device IRQCSI Genera- tion ACKD Setting SCK Stop- page CMDD Setting IRQCSI Genera- tion ACK Output BUSY Output Serial Receive Operation BUSY Clear- ance 1 2 3 4 5 6 [...]

116 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-51 Data Transmission from Master Device to Slave Device Program Processing Hardware Operation Master Device Processing (Transmission Side) Transfer Line SCK Pin SB0 Pin Slave Device Processing (Reception Side) Program  Processing Hardware Operation Seri[...]

117 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-52 Data Transmission from Slave Device to Master Device ★ Master Device Processing (Reception Side) Program Processing Hardware  Operation Transfer Line SCK Pin SB0 Pin Program Processing Hardware Operation BUSY Clear- ance Serial Transmit Operation?[...]

118 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (10) Start of transfer When the following two conditions are met a serial transfer is started by setting transfer data in the shift register (SIO). • The serial interface operatio enable/disable bit (CSIE) = 1. • After an 8-bit serial transfer, the internal serial clock is stopped or SCK is high. Not[...]

119 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS V DD SB0 (SB1) SCK SB0 (SB1) SCK SB0  SCK SB0 (SB1) SCK (12) SBI mode application This section presents examples of applications in which serial data communication is performed in SBI mode. In these application examples, the µ PD75402A is operated as a slave CPU on the serial [...]

120 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (b) Description of commands (i) Command types The following command types are used in these application examples. ➀ READ command : Performs data transfer from slave to master. ➁ WRITE command : Performs data transfer from master to slave. ➂ END command : Notifies slave of completion of WRITE comman[...]

121 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Remarks M : Output by master S : Output by slave After the slave receives the data length, if the transmissible data is equal to or greater than that data length, the slave returns ACK. If the data is insufficient, ACK is not returned and an error is generated. When a data transfer is performed, the slav[...]

122 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS After the slave receives the data length, if the area for storing the receive data is at least as large as that data length, the slave returns ACK. If the data storage area is too small, ACK is not returned and an error is generated. When all the data has been transferred, the master sends an END command[...]

123 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS ➂ STATUS command This command is used to read the status of the currently selected slave. Fig. 5-57 STATUS Command Transfer Format MS STATUS ACK Command S S Status ACK Data Remarks M : Output by master S : Output by slave The format of the status byte returned by the slave is shown below. Fig. 5-58 STA[...]

124 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS RESET command This command is used to change the currently selected slave to non-selected status. All slaves can be placed in non-selected status by sending the RESET command. Fig. 5-59 RESET Command Transfer Format MS RESET ACK Command Remarks M : Output by master S : Output by slave ➄ CHGMST command [...]

125 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (iv) Error occurrence Operation in the event of an error in communication is described below. A slave indicates the occurrence of an error by failing to return ACK to the master. When an error occurs, the status bit indicating the occurrence of an error is set and all command processing being executed is[...]

126 CHAPTER 6. INTERRUPT FUNCTIONS CHAPTER 6. INTERRUPT FUNCTIONS On the µ PD75402A there are 3 vectored interrupt sources and one testable input, enabling a wide variety of applications to be handled. Moreover, the µ PD75402A’s interrupt control circuit has the following special features, making possible extremely fast interrupt servicing. (a)[...]

127 CHAPTER 6. INTERRUPT FUNCTIONS Fig. 6-1 Interrupt Control Circuit Block Diagram  Internal Bus 3 IM0 Sampling Clock  Noise Elimination Circuit Analog Delay Noise Elimination Circuit Rising Edge Detection  Circuit INT0/P10 INT2/P12 INTCSI INT BT Edge Detection Circuit IRQBT IRQ0 IR[...]

128 CHAPTER 6. INTERRUPT FUNCTIONS 6.2 INTERRUPT SOURCE TYPES AND VECTOR TABLE The µ PD75402A’s interrupt source types and interrupt vector table are shown in Table 6-1 and Fig. 6-2. Table 6-1 Interrupt Request Source Types Vectored Interrupt Request Signal (Vector Table Address) Interrupt Request Generation Source Interrupt Priority * 1 Interna[...]

129 CHAPTER 6. INTERRUPT FUNCTIONS Interrupt Request Flag IRQBT IRQ0 IRQCSI IRQ2 6.3 INTERRUPT CONTROL CIRCUIT HARDWARE (1) Interrupt request flag & interrupt enable flag There are four interrupt request flags (IRQ ××× ) corresponding to the interrupt sources (interrupt: 3, test: 1) as follows. INT0 interrupt request flag (IRQ0) INT2 interru[...]

130 CHAPTER 6. INTERRUPT FUNCTIONS (2) External interrupt input pin hardware The configuration of INT0 and INT2 is shown in Fig. 6-3. Fig. 6-3 Configuration of INT0 and INT2 4 IM0 Input Buffer Input Buffer  with Hysteresis  Characteristics Internal Bus INT2/P12 INT0/P10 Sampling Clock Noise Elimina- tion Circuit?[...]

131 CHAPTER 6. INTERRUPT FUNCTIONS Fig. 6-4 INT0 Noise Elimination Circuit Input/Output Timing Remarks t SMP = t CY or 64/f XX Specification of the detected edge of the INT0 input and selection of the sampling clock is performed by the edge detection mode register (IM0). As signals are also input via the noise elimination circuit when the INT0 pin [...]

132 CHAPTER 6. INTERRUPT FUNCTIONS The format of the edge detection mode register (IM0) which is used to select the detected edge is shown in Fig. 6-6. IM0 is set by 4-bit memory handling instructions. On an RESET input, all bits of IM0 are cleared to 0 and the rising edge is specified for INT0. Fig. 6-6 Edge Detection Mode Register Format Note As [...]

133 CHAPTER 6. INTERRUPT FUNCTIONS (4) Interrupt status flag The interrupt status flag (IST0) is the flag which shows the status of the processing currently being executed by the CPU, and is contained in the PSW. The interrupt priority control circuit performs interrupt control according to the contents of this flag as shown in Table 6-3. IST0 cann[...]

134 CHAPTER 6. INTERRUPT FUNCTIONS 6.4 INTERRUPT SEQUENCE When an interrupt is generated, it is serviced by the procedure shown in Fig. 6-8. Fig. 6-8 Interrupt Servicing Procedure Interrupt (INT ××× ) generation IExxx set? NO NO NO IRQxxx set YES Corresponding VRQn generation YES YES IST0=0 IME=1 Save PC and PSW contents to stack memory; place d[...]

135 CHAPTER 6. INTERRUPT FUNCTIONS 6.5 MACHINE CYCLES BEFORE INTERRUPT SERVICING On the 75X, the machine cycles from the setting of the interrupt request flag (IRQn) until execution of the interrupt routine program are as shown below. (1) When IRQn is set during execution of an interrupt control instruction When IRQn is set during execution of an i[...]

136 CHAPTER 6. INTERRUPT FUNCTIONS (2) When IRQn is set during execution of an instruction other than an interrupt control instruction (a) When IRQn is set in the last machine cycle of the instruction being executed In this case, the interrupt routine program is executed after 3 machine cycles of interrupt servicing have been performed following ex[...]

137 CHAPTER 6. INTERRUPT FUNCTIONS 6.6 INTERRUPT APPLICATIONS When the interrupt function is used, the following setting are first carried out in the main program. ➀ The interrupt enable flag corresponding to the interrupt to be used is set to “1” (EI IE ××× instruction). ➁ If INT0 is used, the active edge is selected (IM0 setting). ➂ [...]

138 CHAPTER 6. INTERRUPT FUNCTIONS (2) Example using INTBT, INT0 (falling edge active), and INTCSI ➀ Reset ➁ MOV MOV CLR1 ➂ EI EI EI EI    ➄ RETI <INT0 Service Program> ➃ INT0 A, #1 IM0, A IRQ0 IEBT IE0 IECSI ; MBE = 0 Status 0 Status 1 Status 0 <Main Program[...]

139 CHAPTER 6. INTERRUPT FUNCTIONS (3) Pending interrupt execution - interrupt input in interrupt disabled state Reset ➂ INTCSI <INT0 Service Program> RETI RETI  <INTCSI Service Program> EI IE0 ➀ INT0 <Main program> ➁ EI ➃ EI IECSI ➀ Although INT0 is set in the interrupt disabled state[...]

140 CHAPTER 6. INTERRUPT FUNCTIONS (4) Pending interrupt execution Reset EI EI EI  ➀  IECSI IE0  <Main Program> INT0  INTCSI RETI ➁ RETI <INTCSI Service Program> <INT0 Service Program> <Main Program> ➀ If INT0 and INTCSI are generated simultaneously (during executio[...]

141 CHAPTER 7. STANDBY FUNCTION CHAPTER 7. STANDBY FUNCTION The µ PD75402A has a standby function which can reduce the system power consumption. The standby function has the following two modes: • STOP mode • HALT mode (1) STOP mode In this mode, the main system clock oscillator is stopped and the whole system stops. The CPU current drain is r[...]

142 CHAPTER 7. STANDBY FUNCTION 7.1 STANDBY MODE SETTING AND OPERATION STATES Table 7-1 Standby Mode Operation States STOP Mode HALT Mode Setting instruction HALT instruction CPU clock Φ only stopped oscillator (oscillation continues) Operation (IRQBT set at basic time interval) Operation possible Output other than CPU clock Φ possible Operation [...]

143 CHAPTER 7. STANDBY FUNCTION 7.2 STANDBY MODE RESET The STOP mode is reset only by RESET input. The HALT mode is reset by standby release signal by setting of an interrupt request flag enabled by the interrupt enable flag and by RESET input. The standby mode reset operation is shown in Fig. 7-1. Note When a standby mode (STOP/HALT) was reset by [...]

144 CHAPTER 7. STANDBY FUNCTION Fig. 7-1 Standby Mode Reset Operation (a) STOP mode reset by RESET input (b) HALT mode reset by RESET input HALT Instruction RESET Input Operating Mode Clock Oscillation HALT Mode Operating Mode STOP Instruction RESET Input Operating Mode Clock Oscillation STOP Mode Oscillation?[...]

145 CHAPTER 7. STANDBY FUNCTION 7.3 OPERATION AFTER STANDBY MODE RESET (1) When the standby mode was reset by RESET input, normal reset operation is executed. (STOP and HALT modes) (2) When the standby mode was reset by interrupt request generation, whether or not a vector interrupt is executed when the CPU resumes instruction execution is determin[...]

146 CHAPTER 8. RESET FUNCTION CHAPTER 8. RESET FUNCTION When low level is input to the RESET pin, system reset is applied and the hardware enters the state shown in Table 8-1. When the RESET input goes from low level to high level, the reset state is released. Then, the contents of the lower-order three bits of address 000H of the reset vector tabl[...]

147 CHAPTER 8. RESET FUNCTION Table 8-1 State of Hardware after Reset * The contents of data memory addresses 038H to 03DH are made undefined by RESET input. Hardware RESET Input standby mode RESET Input during operation Program counter (PC) PSW Low-order 3 bits of program memory address 000H set in PC10 to PC8 and contents of address 001H set in P[...]

148 CHAPTER 9. INSTRUCTION SET CHAPTER 9. INSTRUCTION SET The 75X series instruction set is an improved and expanded version of old µ PD7500 series instruction set. It is a revolutionary new instruction set which retains succession from the µ PD7500 series. The µ PD75402A instruction set is a 75X instruction subset, and has the following feature[...]

149 CHAPTER 9. INSTRUCTION SET 9.1 SPECIAL INSTRUCTIONS This section outlines the special instructions of the µ PD75402A instruction set. 9.1.1 Bit Manipulation Instructions µ PD75402A bit manipulation can be performed by various instructions, such as the following: (a) Bit set : SET1 mem. bit SET1 fmem. bit (b) Bit clear : CLR1 mem. bit CLR1 fme[...]

150 CHAPTER 9. INSTRUCTION SET 9.1.3 Base Correction Instructions Depending on the application, the result of addition of 4-bit data must be converted to decimal numbers or to base-6, such as time. Base correction instructions for converting the result of addition of 4-bit data to an arbitrary base are available with the µ PD75402A instruction set[...]

151 CHAPTER 9. INSTRUCTION SET 9.2 INSTRUCTION SET AND ITS OPERATION (1) Operation identifier and description The operands are described in the operand field of each instruction in accordance with the description for the operand identifier of the instruction. (See "RA 75X Assembler Package User's Manual Language Volume (EEU-730) for detai[...]

152 CHAPTER 9. INSTRUCTION SET (3) Description of addressing area field symbols * 1 MB = 0 * 2 MB = 0 (00H to 3FH) MB = 15 (80H to FFH) * 3 MB = 15, fmem = FB0H to FBFH, FF0H to FFFH * 4 addr = 000H to 77FH * 5 addr = (Current PC) – 15 to (Current PC) – 1, (Current PC) + 16 to (Current PC) + 2 * 6 caddr = 000H to 77FH * 7 faddr = 000H to 77FH R[...]

153 CHAPTER 9. INSTRUCTION SET A, #n 4 1 1 A ← n 4 Stack A XA, #n 8 2 2 XA ← n 8 Stack A HL, #n 8 2 2 HL ← n 8 Stack B A, @HL 1 1 A ← (HL) *1 MOV @HL, A 1 1 (HL) ← A* 1 A, mem 2 2 A ← (mem) *2 XA, mem 2 2 XA ← (mem) *2 mem, A 2 2 (mem) ← A* 2 mem, XA 2 2 (mem) ← XA *2 A, @HL 1 1 A ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *2 XA, mem 2 2 [...]

154 CHAPTER 9. INSTRUCTION SET mem. bit 2 2 (mem. bit) ← 1* 2 f mem. bit 2 2 (f mem.bit) ← 1* 3 mem. bit 2 2 (mem. bit) ← 0* 2 f mem. bit 2 2 (f mem. bit) ← 0* 3 mem. bit 2 2 + S Skip if (mem. bit) = 1 *2 (mem. bit) = 1 f mem. bit 2 2 + S Skip if (f mem. bit) = 1 *3 (f mem. bit) = 1 mem. bit 2 2 + S Skip if (mem. bit) = 0 *2 (mem. bit) = 0 [...]

155 CHAPTER 9. INSTRUCTION SET IN A, PORTn 2 2 A ← PORTn (n = 0 – 3, 5, 6) OUT PORTn, A 2 2 PORTn ← A (n + 2, 3, 5, 6) HALT 2 2 Set HALT Mode (PCC.2 ← 1) STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation Operation Bytes Skip Condition Addressing Area Machine Cycle Note 1. Instruction Group 2. I/O instructions Mnemonic Operand Note 1[...]

156 CHAPTER 9. INSTRUCTION SET R 1 R 0 reg 00 A 01 X 10 L 11 H 9.3 OPERATION CODE OF EACH INSTRUCTION (1) Description of operation code symbols P 1 reg-pair 0X A 1H L N 2 N 1 N 0 IE ××× 0 0 0 IEBT 1 0 1 IECSI 110 I E 0 111 I E 2 In : Immediate data for n4, n8 Dn : Immediate data for mem Bn : Immediate data for bit Nn : Immediate data for n, IE ?[...]

157 CHAPTER 9. INSTRUCTION SET Operation Code B 1 B 2 XCH MOV Note 1. Instruction Group 2. Accumulator operation instructions 3. Increment/decrement instructions 4. Compare instruction 01 11I 3 I 2 I 1 I 0 10001 0 P 1 1 11100 0 01 11101 0 00 10100 0 11 10100 0 10 10010 0 11 10010 0 10 11101 0 01 10110 0 11 10110 0 10 11011 0 R 1 R 0 11010 0 00 01 1[...]

158 CHAPTER 9. INSTRUCTION SET mem. bit f mem. bit mem. bit f mem. bit mem. bit f mem. bit mem. bit f mem. bit SKTCLR f mem. bit AND 1 CY, f mem. bit OR 1 CY, f mem. bit XOR 1 CY, f mem. bit BRCB ! caddr CALLF ! faddr RET RETS RETI PUSH rp POP rp IE ××× IE ××× IN A, PORTn OUT PORTn, A HALT STOP NOP Operation Code B 1 B 2 Operand Note 1. Instr[...]

159 CHAPTER 9. INSTRUCTION SET 9.4 INSTRUCTION FUNCTIONS AND APPLICATION 9.4.1 Move Instructions MOV A, #n4 Function: A ← n4; n4 = I 3 to I 0 : 0 to FH Moves 4-bit immediate data n4 to the A register (4-bit accumulator). This instruction has a stacking effect (group A). When placed after a MOV A, #n4 or MOV XA, #n8 instruction, stack instructions[...]

160 CHAPTER 9. INSTRUCTION SET MOV @HL, A Function: (HL) ← A Moves the contents of the A register to the data memory addressed by the contents of register pair HL. MOV A, mem Function: A ← (mem); mem = D 7 to D 0 : 00H to 3FH Moves the data memory contents addressed by 8-bit immediate data mem to the A register. MOV XA, mem Function: A ← (mem[...]

161 CHAPTER 9. INSTRUCTION SET XCH A, @HL Function: A ← (HL) Exchanges the contents of the A register and the contents of the data memory addressed by the contents of register pair HL. Application example: Exchange the data of data memory addresses 20H to 2FH and the data of addresses 30H to 3FH. MOV HL, #30H LOOP: XCH A, @HL ; A ↔ (3 × ) MOV [...]

162 CHAPTER 9. INSTRUCTION SET 9.4.2 Table Reference Instructions MOVT XA, @PCXA Function: XA ← ROM (PC 10 to PC 8 + XA) Moves the high-order three bits (PC 10 to PC 8 ) of the program counter (PC) and the low-order four bits of the table data in the program memory addressed by the contents of register pair XA to the A register and the high-order[...]

163 CHAPTER 9. INSTRUCTION SET 9.4.3 Arithmetic and Logic Instructions ADDS A, #n4 Function: A ← A + n4; Skip if carry; n4 = I 3 to I 0 : 0 to FH Binary adds 4-bit immediate data n4 to the contents of the A register and skips the next instruction if a carry is generated. The carry flag is not affected. When combined with an ADDC A, @HL instructio[...]

164 CHAPTER 9. INSTRUCTION SET OR A, @HL Function: A ← A ∨ (HL) ORs the contents of the A register and the data memory contents addressed by register pair HL and sets the result into the A register. XOR A, @HL Function: A ← A ∨ (HL) Exclusive-ORs the contents of the A register and the data memory contents addressed by register pair HL and s[...]

165 CHAPTER 9. INSTRUCTION SET 9.4.4 Accumulator Operation Instructions RORC A Function: CY ← A 0 An to A 1 ← An , A 3 ← CY (n = 1 to 3) Rotates the contents of the A register (4-bit accumulator), including the carry flag, to the right one bit at a time. 0 0 1 0 1 1 0 0 1 0 CY 3 2 1 0 A RORC A?[...]

166 CHAPTER 9. INSTRUCTION SET 9.4.5 Increment/Decrement Instructions INCS reg Function: reg ← reg + 1; Skip if reg = 0 Increments the contents of register reg (X, A, H, L). When the contents of register reg become 0 as the result of incrementing, skips the next instruction. INCS mem Functions: (mem) ← (mem) + 1; Skip if (mem) = 0, mem = D 7 to[...]

167 CHAPTER 9. INSTRUCTION SET 9.4.6 Compare Instructions SKE reg, #n4 Function: Skip if reg = n4; n4 = I 3 to I 0 : 0 to FH If the contents of register reg (X, A, H, L) equal 4-bit immediate data n4, skips the next instruction. SKE A, @HL Function: Skip if A = (HL) If the contents of the A register and the data memory contents addressed by registe[...]

168 CHAPTER 9. INSTRUCTION SET 9.4.7 Carry Flag Operation Instructions SET1 CY Function: CY ← 1 Sets the carry flag. CLR1 CY Function: CY ← 0 Clears the carry flag. SKT CY Function: Skip if CY = 1 When the carry flag is 1, skips the next instruction. NOT1 CY Function: CY ← CY Inverts the carry flag. If the carry flag is 0, it becomes 1 and if[...]

169 CHAPTER 9. INSTRUCTION SET 9.4.8 Bit Manipuration Instructions SET1 mem. bit Function: (mem. bit) ← 1; mem = D 7 to D 0 : 00H to 3FH, bit = B 1 to B 0 : 0 to 3 Sets the bit specified by 2-bit immediate data bit of the address specified by 8-bit immediate data mem. SET1 fmem. bit Function: (bit specified by operand) ← 1 Sets the data memory [...]

170 CHAPTER 9. INSTRUCTION SET SKF mem. bit Function: Skit if (mem. bit) = 0; mem = D 7 to D 0 : 00H to 3FH, bit = B 1 to B 0 : 0 to 3 If the bit specified by 2-bit immediate data bit of the address specified by 8-bit immediate data mem is 0, skips the next instruction. SKF fmem. bit Function: Skip if (bit specified by operand) = 0 If the contents [...]

171 CHAPTER 9. INSTRUCTION SET 9.4.9 Branch Instructions BR addr Function: PC 10 to PC 0 ← addr; addr = 000H to 77FH Branches to the address addressed by 11-bit immediate data addr. This instruction is an assembler pseudo instruction. During assembly, the assembler automatically replaces this instruction with the optimum instruction from among th[...]

172 CHAPTER 9. INSTRUCTION SET 9.4.10 Subroutine Stack Control Instructions CALLF !faddr Function: (SP-1) ← PC 7 to PC 4 , (SP-2) ← PC 3 to PC 0 , (SP-3) ← 0, 0, 0, 0 (SP-4) ← 0, PC 10 to PC 8 , SP ← SP-4, PC ← A 10 to A 0 faddr = A 10 to A 0 : 000H to 77FH Saves the contents of the program counter (PC; return address) to the data memor[...]

173 CHAPTER 9. INSTRUCTION SET PUSH rp Function: (SP-1) ← rp H , (SP-2) ← rp L , SP ← SP-2 Saves the contents of register pair rp (XA, HL) to the data memory (stack) addressed by the stack pointer (SP), then decrements the SP. The high-order side (rp H : X, H) of the register pair is saved to the stack addressed by (SP-1) and the low- order s[...]

174 CHAPTER 9. INSTRUCTION SET 9.4.11 Interrupt Control Instructions EI Function: IME ← 1 Sets the interrupt master enable flag (1), and enables interrupts. Whether or not interrupts are accepted is determined by each interrupt enable flag. EI IEXXX Function: IE ××× ← 1; ××× = N 2 to N 0 Sets the interrupt enable flag (IE ××× ) (1), an[...]

175 CHAPTER 9. INSTRUCTION SET 9.4.12 Input/Output Instructions IN A, PORTn Function: A ← PORTn; n = N 3 to N 0 : 0 to 3, 5, 6 Transfers the contents of the port specified by PORTn (n = 0 to 3, 5, 6) to the A register. Note Only 0 to 3, 5 or 6 can be specified at n. Output latch data (output mode) or pin data (input mode) is fetched according to [...]

176 CHAPTER 9. INSTRUCTION SET 9.4.13 CPU Control Instructions HAL T Function: PCC. 2 ← 1 Sets the HALT mode (This instruction sets bit 2 of the processor clock control register.). Note The instruction following the HALT instruction is made an NOP instruction. STOP Function: PCC. 3 ← 1 Sets the STOP mode (This instruction sets bit 3 of the proc[...]

177 APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLY APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLY Since EVAKIT-75X (75X series common evaluation board) supports the 75X series functions, it can execute the following instructions not available with the µ PD75402A. Since the µ PD75402A and µ PD75P402 cannot execute thes[...]

178 APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLY Mnemonic Operands DECS mem @HL SKE A, reg XA, rp’ XA, @HL @HL, #n4 A, mem SET1, CLR1, pmem. @L SKF, SKT, SKTCLR @H + mem. bit AND1, OR1 CY, pmem. @L CY, @H + mem. bit CY,/fmem. bit CY,/pmem. @L CY,/@H + mem. bit XOR1 CY, pmem. @L CY, @H + mem. bit Mnemonic Operands NOT1 fmem. bit pm[...]

179 APPENDIX B. DEVELOPMENT TOOLS APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for system development using the µ PD75402A: Language Processor Host Machine Ordering Code (Product Name) Supply Medium OS PC DOS TM (Ver. 3.1) ~ PC-9800 series MS-DOS TM 3.5-inch 2HD µ S5A13RA75X Ver. 3.30 Ver. 5.00 A * 5-inch 2HD µ S5A[...]

180 APPENDIX B. DEVELOPMENT TOOLS Debugging Tools The following in-circuit emulators (IE-75000-R and IE-75001-R) are available as the µ PD75402A program debugging tools. Their respective system configurations are as follows. IE-75000-R *1 The IE-75000-R is an in-circuit emulator for hardware/software debugging in develop- ment of an application sy[...]

181 APPENDIX B. DEVELOPMENT TOOLS Development Tool Configuration *1 . The IE-75001-R does not incorporate the IE-75000-R-EM (Sold separately) 2. EV-9200G-44 Host Machine PC-9800 Series IBM PC/AT (Symbolic Debugging Capability) Centronics I/F IE Control Program PG-1500 Controller RS-232-C Relocatable Assembl[...]

182 APPENDIX C. MASK ROM ORDERING PROCEDURE APPENDIX C. MASK ROM ORDERING PROCEDURE When completing the µ PD75402A program and ordering the mask ROM, proceed as follows: ➀ Mask ROM order reservation Provide us with the mask ROM ordering schedule through your dealer or our sales department (If we are not informed in advance, processing may be del[...]

183 APPENDIX D. INSTRUCTION INDEX (ALPHABETIC ORDER) APPENDIX D. INSTRUCTION INDEX (ALPHABETIC ORDER) ADDC A, @HL ADDS A, #n4 ADDS A, @HL AND A, @HL AND1 CY, fmem. bit BR addr BR $addr BRCB ! caddr CALLF ! faddr CLR1 CY CLR1 fmem. bit CLR1 mem. bit DECS reg DI DI IE ××× EI EI IE ××× HALT IN A, PORTn INCS mem INCS reg MOV A, mem MOV A, #n4 MOV[...]

184 APPENDIX E. HARDWARE INDEX (ALPHABETIC ORDER) APPENDIX E. HARDWARE INDEX (ALPHABETIC ORDER) Symbol Hardware Name Page Hardware Name Page Symbol IRQ2 INT2 interrupt request flag IRQBT BT interrupt request flag IRQCS Serial interface interrupt request flag IST0 Interrupt status flag PC Program counter PCC Processor clock control mode register PMG[...]