NEC uPD98502 Bedienungsanleitung

Preliminary User’s Manual µ µ µ µ PD98502 Network Controller Document No. S15543EJ1V0UM00 (1st edition) Date Published December 2001 NS C P(K) 2001 Printed in Japan[...]

Preliminary User’ s Manual S15543EJ1V 0UM 2 [MEMO][...]

Preliminary User’ s Manual S15543EJ1V 0UM 3 SUMMARY OF CONTENTS CHAPTER 1 INTRODUCTION ........................................................................................................ .......... 23 CHAPTER 2 V R 4120A ..........................................................................................................................[...]

Preliminary User’ s Manual S15543EJ1V 0UM 4 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly[...]

Preliminary User’ s Manual S15543EJ1V 0UM 5 V R 4100, V R 4102, V R 4111, V R 4120A, V R 4300, V R 4305, V R 4310, V R 4400, V R 5000, V R 10000, V R Series, V R 4000 Series, V R 4100 Series, and EEPROM are trademarks of NEC Corporation. Micro Wire is a trademark of National Semiconductor Corp. iAPX is a trademark of Intel Corp. DEC VAX is a trad[...]

6 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM PREFA CE Readers This ma nual i s intend ed for engin eers w ho need to b e famil iar with t he capa bility of the µ PD98502 in order to devel op appli cation system s based on it. Purpose The purpose o f this m anual is to help user s understa nd the hardware cap abilit ies (listed b elow) of th e[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 7 CONTENTS CHAPTER 1 INTRODUCTION ........................................................................................................ ....... 23 1.1 Features ................................................................................................................... ................... 23 [...]

8 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 2.1.6 Floating- point unit (FPU) ................................................................................................ ................64 2.1.7 CPU core memory ma nagement s ystem (MMU) ...........................................................................65 2.1.8 Translation lookasi[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 9 CHAPTER 3 SYSTEM CONTRO LLER ............................................................................................... 185 3.1 Overview ................................................................................................................... ................ 185 3.1.1 CPU interface .[...]

10 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.4.15 SDRAM refresh ........................................................................................................... .................219 3.4.16 Memory-to-CPU prefetch FIFO ............................................................................................. .......219 3.4.17 C[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 11 4.4.18 A_T1R (T1 Time Reg ister)................................................................................................ ........... 245 4.4.19 A_TSR (Time Stamp Re gister) ............................................................................................. ....... 245 4.4.20 A_IBB[...]

12 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 5.2.20 En_HT1 (Hash Tabl e Register 1).......................................................................................... .......290 5.2.21 En_HT2 (Hash Tabl e Register 2).......................................................................................... .......290 5.2.22 En_CAR1 (Ca[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 13 6.2.20 U_RP1IR (USB Rx Pool1 Inform ation Regis ter) .......................................................................... 327 6.2.21 U_RP1AR (USB Rx Pool1 Addres s Register) ............................................................................. 327 6.2.22 U_RP2IR (USB Rx Pool2 Inform a[...]

14 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M CHAPTER 7 PCI CONTROLL ER ...................................................................................................... ... 370 7.1 Overview ................................................................................................................... ................ 370 7.2 Bus Bri[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 15 8.3.4 UARTIER (UART Interrupt Enable R egister) ............................................................................... 41 6 8.3.5 UARTDLL (UART Divisor Lat ch LSB Regi ster) ........................................................................... 416 8.3.6 UARTDLM (UART Divisor Latch M [...]

16 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M LIST OF FIGUR ES (1/5) Figure No. Title Page 1-1 Example s of the µ PD98502 System Configurati on ........................................................................................24 1-2 Block Diagram of the µ PD98502 ........................................................................[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 17 LIST OF FIGUR ES (2/5) Figure No. Title Page 2-29 Supervisor Mode A ddress S pace .............................................................................................. .................. 108 2-30 Kernel Mode Ad dress Space ...................................................................[...]

18 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M LIST OF FIGUR ES (3/5) Figure No. Title Page 2-71 Instruction Ca che State Diagram ............................................................................................ .....................173 2-72 Data Check Flow o n Instructi on Fetch .....................................................[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 19 LIST OF FIGUR ES (4/5) Figure No. Title Page 4-19 Open_Channe l Command an d Indicati on ........................................................................................ ............ 258 4-20 Close_Channel C ommand and Indic ation ............................................................[...]

20 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M LIST OF FIGUR ES (5/5) Figure No. Title Page 6-16 Data Receiving in E ndPoint0, EndPoint 6 ..................................................................................... ................349 6-17 EndPoint2, EndPoi nt4 Rece ive Normal M ode.....................................................[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 21 LIST OF TABL ES (1/2) Table No. Title Page 2-1 System Control C oproce ssor (CP0) Regist er Definit ions ....................................................................... ........ 64 2-2 Number of Delay S lot C ycles Necess ary for L oad and S tore Instr uction s .............................[...]

22 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M LIST OF TABL ES (2/2) Table No. Title Page 3-1 Endian Configur ation Ta ble.................................................................................................. ........................202 3-2 Endian Transl ation Ta ble in Endia n Convert er............................................[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 23 CHAPTER 1 INTRODUCTION The µ PD98502 is a high performa nce control ler, w hich can pe rform the prot ocol con version betwe en IP Packets and ATM Cells, w hich i s especia lly suita ble for ADSL r outer . It includ es high performanc e MIPS  based 64-bit RISC processor V R 41 20A CPU core, ATM[...]

CHAPTER 1 I NTRODUCTION 24 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 1.3 System Con figuration The µ PD98502 can per form bridgin g and ro uting funct ion betw een ADSL/ATM interface and USB/E thernet interface and provid es thi s functi on in a si ngle ch ip. By selectin g user interfa ce, examples of sys tem config uration will be realize[...]

CHAPTER 1 I NTRODUCTION Preliminary User ’ s Manu al S155 43EJ 1V0UM 25 1.4 Block Diagr am (Summ ary) Figure 1-2. Bloc k Diagr am of the µ µ µ µ PD98502 SDRAM ATM Cell Proc esso r Full-Spee d USB Controller Ethernet Controller #1, # 2 System Controller V R 4120 A RIS C Proc esso r C or e JTA G PHY Management 16.5/25/33 MHz UTOPIA 2 3.3V MII R[...]

CHAPTER 1 I NTRODUCTION 26 Preliminary User ’ s Manu al S155 43EJ 1V0U M 1.5 Block Diagr am (Deta il) 1.5.1 V R 4120A RISC pro cessor core We will suppor t real-tim e OS ru nning on hi gh performan ce RISC p rocessor V R 41 20A core and can per form networ k protocols (TCP /IP, PPP, SNM P, HTTP etc) to r ealize ADSL router a nd modem. Mid dleware[...]

CHAPTER 1 I NTRODUCTION Preliminary User ’ s Manu al S155 43EJ 1V0UM 27 1.5.2 IBUS The IBUS is a 32-bit, 6 6-MHz high-s peed on -chip b us, whic h enables interco nnecti on each control ler block s. The IBUS supp orts the followin g bus pr otocol s; • Single read/write transfer • Burst read/wri te transf er • Slave lock • Retry and d isco[...]

CHAPTER 1 I NTRODUCTION 28 Preliminary User ’ s Manu al S155 43EJ 1V0U M 1.5.3 System control ler System Co ntroller is µ PD98502 ’ s interna l syst em control ler. Syst em Controller pro vides bridg ing function amon g the V R 4120A S ystem Bus “ SysA D ” , NEC origi nal hig h-speed on-ch ip bu s “ IBUS ” and m emory bus for SDRAM/PRO[...]

CHAPTER 1 I NTRODUCTION Preliminary User ’ s Manu al S155 43EJ 1V0UM 29 1.5.4 ATM cell proc essor By using N EC proprietar y 32-bit contro ller, we w ill reali ze ATM Cell processor Unit . ATM Cell processing by firmware realiz es mor e flexi bility tha n before. Features o f ATM Cell Proc essor ar e as fo llows; • Realize softw are SAR fun cti[...]

CHAPTER 1 I NTRODUCTION 30 Preliminary User ’ s Manu al S155 43EJ 1V0U M 1.5.5 Ethernet controller Ethernet Controll er s upports 2-channel 1 0 Mbps /100 Mbps Eth ernet M AC (Media A ccess Contr o l) functio n and M II (Media Indep endent I nterface) fun ction. Features o f Ethernet C ontroller are as f ollows; • Supports 10 M /100 M Etherne t [...]

CHAPTER 1 I NTRODUCTION Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 31 1.5.6 USB controller USB Controller pr ovide s Full Speed Functio n devi ce functio n define d in Uni versal S erial Bus. Features o f USB Contr oller are as follows; • Compliant to Univer sal Seri al Bus Sp ecificati on Rev. 1. 1 • Supports De vice cla ss func tion by s[...]

CHAPTER 1 I NTRODUCTION 32 Preliminary User ’ s Manu al S155 43EJ 1V0U M 1.5.7 PCI controller PCI Controller p rovide s PCI Bus funct ion def ined by PCI SIG. Th is block is brid ging betwe en IBUS and PCI. Features o f PCI Control ler are a s follows; • 32-bit PCI Int erface (up to 33 MHz) • 32-bit IBUS Int erface (u p to 33 MH z) • Suppor[...]

CHAPTER 1 I NTRODUCTION Preliminary User ’ s Manu al S155 43EJ 1V0UM 33 1.6 Pin Configuration (Bottom View) • 500-pin Tape BG A (Heat spread type) (40 × 40) µ PD98502N7-H6 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AF AE AD AC AB AA YW V U T R P N M L K J H G F E D C B A 30 29 28 27 AK AJ AH AG Inde x Mark[...]

CHAPTER 1 I NTRODUCTION 34 Preliminary User ’ s Manu al S155 43EJ 1V0U M Pin Name (1/3) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No . Pin Nam e Pin No . Pin Nam e A1 SMA13 B10 URSDO C19 NJTRST D28 PGTO2_B F27 GND A2 SMD0 B11 RMSL1 C20 IC-OPEN D29 PRQI 1_B F28 GND A3 SMD4 B12 MWDO C21 JDI D30 P AD0 F29 P AD 5 A4 SMD7 B13 POM3 C22 GND[...]

CHAPTER 1 I NTRODUCTION Preliminary User ’ s Manu al S155 43EJ 1V0UM 35 (2/3) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Nam e Pin No. Pin Nam e K26 GND P5 GND V4 IVDD AB3 IC-PU p AF2 MICRS K27 IVDD P26 GND V5 GND AB4 IC -PDn AF3 MIMCLK K28 P AD 14 P27 IVDD V26 P AD26 AB5 EVD D AF4 MITD3 K29 P AD15 P2 8 P AD16 V27 P AD25 AB2 6[...]

CHAPTER 1 I NTRODUCTION 36 Preliminary User ’ s Manu al S155 43EJ 1V0U M (3/3) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Nam e Pin No. Pin Nam e AG11 UDRD0 AH3 MICOL AH25 EVDD AJ 17 UDTD5 AK9 UDRD5 AG12 I VDD AH4 MI2RD0 AH26 IVDD AJ 18 GND AK 10 UDRD2 AG13 UDRA D1 AH5 MI2MD AH27 UMAD8 A J19 UMRD Y _B AK11 UDRCLK AG14 IVDD A H[...]

CHAPTER 1 I NTRODUCTION Preliminary User ’ s Manu al S155 43EJ 1V0UM 37 1.7 Pin Func tion Symbol of I/O column indicat es fol lowin g statu s in this section. I : Input O : Output I/O : Bidirect ion I/OZ : Bidirect ion (Inc lude Hi-Z state) I/OD : Bidirection (Open dr ain outp ut) OZ : O utput (Include Hi-Z stat e) OD : Output (Open dr ain) 1.7.1[...]

CHAPTER 1 I NTRODUCTION 38 Preliminary User ’ s Manu al S155 43EJ 1V0U M 1.7.4 System control interface Pin Name Pi n No . I/O Act ive Le vel Functi on SCLK V1 I Syste m clo ck (3 3 MHz) CLKSL U1 I Clock select (100 MHz/66 MHz) PSMD AA 3 I System PLL mode control (0: normal , 1: through) PSTBY AA 2 I Syst em PLL standb y mode control (0: active ,[...]

CHAPTER 1 I NTRODUCTION Preliminary User ’ s Manu al S155 43EJ 1V0UM 39 1.7.5 Memory int erface (1/2) Pin Name Pi n No . I/O Act ive Le vel Functi on SDCLK0 L1 O SDRAM clock SDCLK1 G3 O SDRAM clock SDCKE0 L3 O H SDRAM clock enable SDCKE1 F2 O H SDRAM clock enab le SDCS_B F3 O L Chi p select SDRAS_B E2 O L Row address st robe SDCAS_B G5 O L Col um[...]

CHAPTER 1 I NTRODUCTION 40 Preliminary User ’ s Manu al S155 43EJ 1V0U M (2/2) Pin Name Pi n No . I/O Act ive Le vel Functi on SMD11 R5 I/O Memory data SMD12 R2 I/O Memory data SMD13 P1 I/O Memo ry data SMD14 P2 I/O Memo ry data SMD15 P3 I/O Memo ry data SMD16 E7 I/O Memo ry data SMD17 B5 I/O Memo ry data SMD18 C6 I/O Memory data SMD19 A5 I/O Mem[...]

CHAPTER 1 I NTRODUCTION Preliminary User ’ s Manu al S155 43EJ 1V0UM 41 1.7.6 PCI interface (1/2) Pin Name Pi n No . I/O Act ive Le vel Func tion PSCLK V30 I PCI cloc k P ARBN D26 I PCI arbiter enable PMODE C27 I PCI mode select (L: host, H: NIC) PIDSEL U28 I H Initialization device select PDSEL_ B M29 I/OZ L De vice se lec t PER_B L30 I/O Z L Pa[...]

CHAPTER 1 I NTRODUCTION 42 Preliminary User ’ s Manu al S155 43EJ 1V0U M (2/2) Pin Name Pi n No . I/O Act ive Le vel Func tion P AD11 J28 I/OZ PCI address and data P AD12 J29 I/OZ PCI address and data P AD13 J30 I/OZ PCI address and data P AD14 K28 I/ OZ PCI address and data P AD15 K29 I/ OZ PCI address and data P AD16 P28 I/ OZ PCI address and d[...]

CHAPTER 1 I NTRODUCTION Preliminary User ’ s Manu al S155 43EJ 1V0UM 43 1.7.7 ATM interface 1.7.7.1 UTOPIA management interf ac e Pin Name Pi n No . I/O Act ive Le vel Functi on UMMD AG20 O Management mode s elect UMINT_B AH19 I L Interr upt from PHY UMRD_B AK21 O L Management read enable UMRD Y_B AJ19 I L Management data ready UMRST_B AK20 O L P[...]

CHAPTER 1 I NTRODUCTION 44 Preliminary User ’ s Manu al S155 43EJ 1V0U M 1.7.7.2 UTOPIA data interface Pin Name Pi n No . I/O Act ive Le vel Functi on CLKU SL0 T4 I UT OPI A clo c k sele ct CLKUSL1 T3 I (CLKUS L1/0 = L/L: 33 MHz, H/L: 25 MH z, L/H: 16. 5 MHz) UDRCLK AK11 O Rece ive cloc k UDRCL V AH9 I H Receive cell av ailable UDRE_B AJ8 O L Rec[...]

CHAPTER 1 I NTRODUCTION Preliminary User ’ s Manu al S155 43EJ 1V0UM 45 1.7.8 Ethernet interfac e 1.7.8.1 Ethernet interfac e (Chann el 1) Pin Name Pi n No . I/O Act ive Le vel Functi on MIMCLK AF3 O MII management clock MIMD AG1 I /O MII management MICOL AH3 I Collision MICRS AF2 I Carr ier sens e MIRCLK AD3 I Receive clock (2.5/25 MHz) MIRD V A[...]

CHAPTER 1 I NTRODUCTION 46 Preliminary User ’ s Manu al S155 43EJ 1V0U M 1.7.8.2 Ethernet interfac e (Chann el 2) Pin Name Pi n No . I/O Act ive Le vel Functi on MI2MCLK AJ2 O MII management clock MI2MD AH5 I/ O MII management MI2COL A G5 I Collision MI2CRS AG7 I Carri er sense MI2RCLK AK3 I Rec eive cloc k (2.5/25 MHz) MI2RD V AK4 I Receive data[...]

CHAPTER 1 I NTRODUCTION Preliminary User ’ s Manu al S155 43EJ 1V0UM 47 1.7.10 UART interface Pin Name Pi n No . I/O Act ive Le vel Functi on URCLK D9 I UAR T e xternal clock URCTS_B B8 I L UAR T clear to send URDCD_B A9 I L UAR T data carrier det ect URDSR_B A8 I L UAR T data set ready URDTR_B A10 O L UAR T data terminal ready URR TS_B C10 O L U[...]

CHAPTER 1 I NTRODUCTION 48 Preliminary User ’ s Manu al S155 43EJ 1V0U M 1.7.14 I.C. – open Pin Name Pin No . I/O Act ive Le vel Function IC-OPEN A17, A19, A20, A28, B16, B17, B18, B19, B26, C20, C24, D18, D20, E18, Y1, AA1, AB1, AB27, AB28, AC28 , A C29, AD29, AH12, AJ12 O 1.7.15 I.C.– pull down Pin Name Pin No . I/O Act ive Le vel Function [...]

CHAPTER 1 I NTRODUCTION Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 49 1.8 I/O Regist er Map Core Offset Register Length (Byte) Name A ccess by V R 4120A Descr ip tion ATM F000H 4 A_GMR R/W General Mode Regist er ATM F004H 4 A_GSR R General Status Regist er ATM F008H 4 A_IM R R/ W I nterrupt Mask Regist er ATM F00CH 4 A_RQU R Receive Queue Unde[...]

CHAPTER 1 I NTRODUCTION 50 Preliminary User ’ s Manu al S155 43EJ 1V0U M Core Offset Register Length (Byte) Name A ccess by V R 4120A Descr ip tion PCI 048H-04CH 4 N/A - Reserved for future use PCI 050H 4 P_BCNT R/W Bridge Cont rol Register PCI 054H 4 P_PPCR R/W Power Control Register PCI 058H 4 P_SWRR W Sof tware Reset Register PCI 05CH 4 P_P TM[...]

CHAPTER 1 I NTRODUCTION Preliminary User ’ s Manu al S155 43EJ 1V0UM 51 Core Offset Register Length (Byte) Name A ccess by V R 4120A Descr ip tion Ether 1D0H 4 En_TBCA R/W Trans mit Broadcast P acket Counter Ether 1D4H 4 En_TUCA R/W T ransmit Unicast Packet Counter Ether 1D8H 4 En_TXPF R/W Trans mit PAUSE control Frame Counter Ether 1DCH 4 En_TDF[...]

CHAPTER 1 I NTRODUCTION 52 Preliminary User ’ s Manu al S155 43EJ 1V0U M Core Offset Register Length (Byte) Name A ccess by V R 4120A Descr ip tion SYSCNT D8H 4 M ACAR1 R MAC Address Register 1 SYSCNT DCH 4 MACAR2 R MAC Address Register 2 SYSCNT E0H 4 MACAR3 R MAC Address Register 3 SYSCN T E4 H-FFH - N/A - Rese rved for fu ture use SYSCNT 100H 4[...]

CHAPTER 1 I NTRODUCTION Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 53 1.9 Memory M ap Using a 32 -bit addr ess, the proce ssor ph ysical a ddress spa ce enc ompasse s 4 Gb ytes. V R 4120A u ses this 4-Gbyte physical address space as show n in the fol lowi ng figure . Figure 1-10. M emory Map PC I Contr oll er (For P C I Window) RFU SDRAM 1000_[...]

CHAPTER 1 I NTRODUCTION 54 Preliminary User ’ s Manu al S155 43EJ 1V0U M 1.10 Reset Con figuration The falling e dge of Cl ock Control Unit (CCU) ’ s reset line (RST_B) s erves as the µ PD98502' s interna l reset. The System Control ler gener ates th e IBUS reset signal u sing RST_ B for the global r eset of the µ PD98502. After 4 IBUS c[...]

CHAPTER 1 I NTRODUCTION Preliminary User ’ s Manu al S155 43EJ 1V0UM 55 1.11 Interrupt s The controlle r suppor ts mas kable inter rupt s and Non-M ask able to t he CPU. Figure 1-12. I nterrupt Sig nal Connectio n USB Co nt r ol l er E th e rn e t C o n tro ll er # 1 ATM C el l Processo r Syst em Co nt rol l er V R 4120A S_I SR in tb [0 ] in tb [[...]

CHAPTER 1 I NTRODUCTION 56 Preliminary User ’ s Manu al S155 43EJ 1V0U M 1.12 Clock Con trol Unit This section d escrib e µ PD98502 ’ s internal clock is supplied by Clock Control Unit (CCU) with fo llowing figure. Figure 1-13. Blo ck Di agram of Clock Control Unit UA RT 25/16. 7 MHz PLL ( x6) 1/ 2 1/ 3 CCU ( CLOCK CO NTROL UNI T) ATM C e ll P[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 57 CHAPTER 2 V R 4120A Caution The µ µ µ µ PD98502 does n’t support M IPS16 instructi ons. This chapter descri bes an V R 4120A RISC Proces sor Cor e operation (M IPS instr uction, P ipelin e, etc.). Followin g in this Docum ent, it is call f or V R 4120A RISC Processor Core with “V R 4120A”[...]

CHAPTER 2 V R 4120A 58 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.1.1 Internal bloc k configuration 2.1.1.1 CPU CPU has hardw are resour ces t o process an integer ins truction . They are the 64-bit register fil e, 64-bit integer data bus, and mu ltiply- and-acc umulat e operation unit . 2.1.1.2 Coprocessor 0 (C P0) CP0 incorpor ates a m em[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 59 2.1.2 V R 4120A register s The V R 4120A h as the f ollowing regist ers.  general-pu rpose regi ster (GPR): 6 4 bits × 32 In addition, t he pr ocessor pr ovide s the fol lowing s pecial reg isters:  64-bit Program Co unter (PC )  64-bit HI reg ister, c ontaining t he i[...]

CHAPTER 2 V R 4120A 60 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.1.3 V R 4120A instru ction set ove rview For CPU instructio ns, ther e are onl y one type of instr uction s – 32-bit l ength in structi on (MIPS III). 2.1.3.1 MIPS III instruction All the CPU instru ctions are 32-bit length when execut ing MI PS III instruct ions, a nd they[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 61 2.1.4 Data formats an d addressin g The V R 4120A u ses followi ng four d ata formats: ✧ Doubleword (6 4 bits) ✧ Word (32 bits) ✧ Halfword (16 bits) ✧ Byte (8 bits) For the µ PD98502, byte ordering with in all of the larg er data formats - ha lfword, w ord, doub leword [...]

CHAPTER 2 V R 4120A 62 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M The follow ing spe cial instr uction s to loa d and store data that are not aligned on 4-byte (word) or 8-byte (doubleword) boundar ies: LWL LWR SWL SWR LDL LDR SDL SDR These instru ctions are use d in pa irs to pro vide an a ccess to misal igned data. Accessin g misalig ned da[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 63 2.1.5 Coprocessors (C P0) MIPS ISA defines 4 type s of copr ocessors (CP 0 to CP3) . • CP0 translat es virt ual addr esses to phy sical addr esses , switch es the o perating mode ( kernel, supervisor, or user mode), a nd mana ges exce ptions. It als o controls t he cac he sub [...]

CHAPTER 2 V R 4120A 64 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 2-1. S ystem Control Copr ocessor (CP0) Register D efinitions Register Number Register Name Descripti on 0 Index Programm able pointer to TLB array 1 Random Pseudo-random pointer to TLB array (read only) 2 EntryLo0 Low half of TLB entry for even VPN 3 EntryLo1 Low half of[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 65 2.1.7 CPU core me mory manag eme nt system (MM U) The V R 4120A h as a 32- bit phys ical add ressin g range of 4 Gbyte s. However, since it is r are for syst ems to implement a physical m emory s pace as large as that m emory spac e, the C PU provi des a l ogical ex pansio n of [...]

CHAPTER 2 V R 4120A 66 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.1.11 Instruction pip eline The V R 4120A has a 6-stage inst ruction p ipelin e. Un der normal c ircum stances, o ne instr uct ion is is sued ea ch cycle. A detailed de scripti on of pi peline is pro vided i n Section 2.3 Pip eline . 2.2 MIPS I II Instru ction S et Summ ary Th[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 67 2.2.2 Instruction cl asses The CPU in structions are cla ssified i nto fiv e classe s. 2.2.2.1 Load and st ore instructions Load and stor e are immediat e (I-type) instru ctions t hat move d ata betw een memory and gener al register s. The only add ressin g mode that load an d s[...]

CHAPTER 2 V R 4120A 68 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 2-3. Byt e Specification Re lated to Load and Store Instruction s Access ed Byte Low-Order Address Bit Little Endian Access Type (Value) 210 6 3 0 Doubleword (7) 0 0 0 7 6 5 4 3 2 1 0 7 - b y t e ( 6 ) 0 0 0 6543 210 00 17654 32 1 6-byte (5) 0 0 0 5 4 3 2 1 0 01 07654 32 [...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 69 Table 2-4. Load/Stor e Instruction Instruc tion Format and Descripti on Load Byte LB rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The bytes of the memory location spec ified by the address are sign[...]

CHAPTER 2 V R 4120A 70 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 2-5. Load/Stor e Instruction (E xtended ISA) Instruc tion Format and Descripti on Store Word Left SWL r t, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. Shifts to the right the contents of regist[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 71 2.2.2.2 Computational instructions Computati onal instru ctions perform arithmet ic, logic al, and shift op eration s on values in registers. Computat ional instruct ions can b e either in regi ster (R-type) format, in which both operands are registe rs, or in immediate (I-type [...]

CHAPTER 2 V R 4120A 72 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 2-7. ALU I mmediate Instruction (Ext ended ISA ) Instruc tion Format and Descripti on Doubleword Add Immediate DADDI rt, rs, im mediate The 16-bit immediate is sign extended to 64 bits and then added to the contents of register rs to form a 64-bit result. The result is st[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 73 Table 2-9. Thr ee-Operand Typ e Instr uction (Extended ISA ) Instruc tion Format and Descripti on Doubleword Add DADD rd, rt, rs The contents of register rs are added to that of register rt. The 64-bit result is stored into register rd. An exception occurs on the generati on of [...]

CHAPTER 2 V R 4120A 74 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 2-11. Shift In structio n (Extended ISA) Instruc tion Format and Descripti on Doubleword Shift Left Logical DSLL rd, rt, sa The contents of register rt are shifted l eft by sa bits and zeros are inserted into the emptied lower bits. The 64-bit result is stored into regi s[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 75 Table 2-12. Multiply/Divide Instructions Instruc tion Format and Descripti on Multiply MULT r s, rt The contents of registers rt and rs are multiplied, treating both operands as 32-bit signed integers. The 64-bit result is stored i nto special registers HI and LO. In the 64-bit [...]

CHAPTER 2 V R 4120A 76 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 2-13. Multiply/Divide Instruct ions (Extended ISA) Instruc tion Format and Descripti on Doubleword Multi ply DMULT rs, rt The contents of registers rt and rs are multiplied, treating both operands as si gned integers. The 128-bit result is stored into special registers HI[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 77 Table 2-14. Number of Stall C ycles in Multip ly and Divide In structions Instruc tion Number of Inst ruction Cycles MULT 1 MULTU 1 DIV 36 DIVU 36 DMULT 3 DMULTU 3 DDIV 68 DDIVU 68 MACC 0 DMACC 0 2.2.2.3 Jump and bra nch instructio ns Jump an d bra nch in structi ons chang e the[...]

CHAPTER 2 V R 4120A 78 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 2-16. Jump Instruction Instruc tion Format and Descripti on Jump JAL tar get The contents of 26-bit target address is shift ed left by two bits and combined with the high-order four bits of the PC. The program jumps to this calculated address wit h a delay of one instruct[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 79 There are spe cial s ymbols u sed in t he instr uction formats of Ta bles 2-17 t hrou gh 2-21. REGIMM : Op code Sub : Sub-operat ion code CO : Sub-operation identif ier BC : BC sub-oper ation c ode br : Branch cond ition id entifier op : Operation code Table 2-17. Branch Instruc[...]

CHAPTER 2 V R 4120A 80 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 2-18. Branch Instructions (Extend ed ISA) Instruc tion Format and Descripti on Branch On Equal Likely BEQL rs, rt, offset If the contents of regist er rs are equal to that of register rt, the program branches to the target address. If the branch condition is not met, the [...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 81 2.2.2.4 Special instru ctions Special ins truction s gener ate softwar e exce ptions . Their f ormats ar e R-type (S yscal l, Break). The Trap ins truction is availab le onl y for the V R 4000 S eries. A ll the o ther ins tructio ns are a vailab le for all V R Series. Table 2-19[...]

CHAPTER 2 V R 4120A 82 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 2-20. Speci al Instr uctions (Ext ended ISA) (2/2 ) Instruc tion Format and Descripti on Trap If Greater Than Or Equal Immediate TGEI rs, immediate The contents of register rs are compared with 16-bit sign-ex tended immediate data, treating both operands as signed int ege[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 83 Table 2-21. Syste m Control Co processor (C P0) Instructi ons (2/2) Instruc tion Format and Descripti on Read Indexed TLB Entry TLBR The TLB entry indexed by the index register is loaded into the entryHi, entryLo0, entryLo1, or page mask regist er. Write Indexed TLB Entry TLBWI [...]

CHAPTER 2 V R 4120A 84 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.3 Pipeline This secti on des cribes t he basi c opera tion of t he V R 4 120A Core p ipeline , whi ch includ es desc riptio ns of th e delay slots (instr uctions that follow a bra nch or load instru ction in the pip eline), interrupt s to the pipe line f low caus ed by interl[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 85 Figure 2-10. I nstruction Exec ution in th e Pipeline (Five stages) Current CPU cycle PCycle IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB 1 WB 2 IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB 1 WB 2 IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB 1 WB 2 IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB 1 WB 2 IF1 IF2 RF1 RF2 EX[...]

CHAPTER 2 V R 4120A 86 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 2-22. O peration in Eac h Stage of Pipeline (MIPS III) Cycle P hase Mnem onic Description IF Φ 1 IDC Instruc tion cache address decode ITLB Inst ruction address trans lation Φ 2 ICA Instr ucti on cache array a cce ss ITC Instruction tag check RF Φ 1 IDEC Instruc tion d[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 87 2.3.2 Branch delay During a V R 4120A's p ipeline op eration, a one-c ycle br anch dela y occur s when: • Target addr ess is c alculat ed by a Jump in structio n • Branch condit ion of br anch i nstruct ion is m et and then lo gical o peration st arts for br anch-destin[...]

CHAPTER 2 V R 4120A 88 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.3.4 Pipeline oper ation The operat ion of th e p ipeline is illus trated by the followi ng exam ples that describ e how typ ical i nstruct ions ar e executed. T he instr uction s descr ibed are si x: ADD, JALR, BEQ, TL T, LW, an d SW. Each instructi on is ta ken through the p[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 89 2.3.4.2 Jump and li nk register in stru ction (JA LR rd, r s) IF stage Same as the IF sta ge for th e ADD in structio n. IT stage Same as the IT sta ge for th e ADD in structio n. RF stage A register specified in the r s field is read from the file dur ing Φ 2 a t the R F stag [...]

CHAPTER 2 V R 4120A 90 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.3.4.3 Branch on equa l instruction (BEQ rs, rt, offset) IF stage Same as the IF sta ge for th e ADD in structio n. IT stage Same as the IT sta ge for th e ADD in structio n. RF stage During Φ 2, the r egister fil e is ad dressed w ith the r s and rt field s. A chec k is p er[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 91 2.3.4.4 Trap if less t han instructi on (TLT r s, rt) IF stage Same as the IF sta ge for th e ADD in structio n. RF stage Same as t he RF stag e for the AD D ins truction . EX stage ALU controls are set to do an A - B o peration. Th e operan ds flow i nto the A LU inputs , and t[...]

CHAPTER 2 V R 4120A 92 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.3.4.5 Load word instr uction (LW r t, offset (bas e)) IF stage Same as the IF sta ge for th e ADD in structio n. IT stage Same as the IT sta ge for th e ADD in structio n. RF stage Same as t he RF stag e for the AD D ins truction. Note tha t the ba se fiel d is in the same p [...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 93 2.3.4.6 Store word instru ction (SW r t, offs et (base)) IF stage Same as the IF sta ge for th e ADD in structio n. IT stage Same as the IT sta ge for th e ADD in structio n. RF stage Same as the RF stag e for the L W instr uct ion. EX stage Refer to the LW i nstruct ion for a c[...]

CHAPTER 2 V R 4120A 94 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.3.5 Interlock and exceptio n hand ling Smooth pi peline flow is interrupte d whe n ca che m isses or e xcepti ons occur, or whe n data depe ndenci es are detected. Int erruption s hand led usi ng hardwar e, such as cache miss es, are r eferred to as inte rlocks, while thos e [...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 95 Table 2-24. Pipeline Interlock Interlo ck D escrip tion ITM Instruction TLB Miss ICM Instruction Cac he Miss LDI Load Data Interlock MDI MD Busy Inter lock SLI Store-Load Interlock CP0 Coprocess or 0 Interlock DTM Dat a TLB Miss DCM Dat a Cache Miss DCB Dat a Cache Busy Table 2-[...]

CHAPTER 2 V R 4120A 96 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.3.5.1 Exception co nditions When an exc eption conditi on occurs, the rele vant in structi on and a ll tho se that follow it in th e pipeline are cancelled. According ly, any stall condit ions an d any l ater except ion co ndition s that m ay ha ve referen ced this instruct i[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 97 2.3.5.2 Stall conditions Stalls are us ed to st op the p ipeline for con ditions det ected a fter the RF stage. W hen a s tall occur s, the process or will re solve the condition and then the pipeli ne wi ll cont inue. F igure 2-21 shows a data c ache mis s stal l, and F igure 2[...]

CHAPTER 2 V R 4120A 98 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.3.5.3 Slip conditions During Φ 2 of the R F stage and Φ 1 of the EX stage, internal log ic will determ ine whether it is possib le to start the current instru ction i n this cycle. If all of the sour ce opera nds are availa ble (eit her from the regi ster file or via the in[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 99 Figure 2-24. M D Busy Inter lock 1 M FL O/M FH I Bypass De te ct M D bu sy inte rlock IF RF EX DC WB IF RF RF EX DC WB IF RF EX DC WB 1 Ge t targ e t data 2 2 MD Busy In terlock is detect ed in th e RF stage as sh own in Fig ure 2-24 and also the pipeline sl ips in the stage. MD[...]

CHAPTER 2 V R 4120A 100 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.3.6 Program compatibility The V R 4120A core is des igned taki ng into considerat ion program compatibilit y with other V R -Series pro cessor s. However, bec ause th e V R 4120A d iffers from other processor s in it s archit ecture, it may not be a ble to ru n some programs[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 101 2.4 Memory Management System The V R 4120A Core provid es a mem ory managem ent un it (MMU ) which use s a transla tion loo kaside buff er ( TLB) to translate vir tual addresse s into p hysical address es. Th is chap ter des cribes the virtual and ph ysica l addres s spa ces, t[...]

CHAPTER 2 V R 4120A 102 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.4.2 Virtual address space This se ction des cribes the virtual/ physi cal addr ess s pace an d the manne r in whic h virtu al addre sses ar e converte d or “translated” into ph ysica l addresse s in the TLB. The V R 4 120A vir tual add ress can b e either 32 or 64 bits w[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 103 2.4.2.1 Virtual-to-physi cal address translation Converting a virtual addre ss to a ph ysica l address b egins by com paring t he virtual address from the processor w ith the virtual a ddresses in the TLB; there i s a match wh en the v irtual page number (VPN) of the address is[...]

CHAPTER 2 V R 4120A 104 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.4.2.2 32-bit mode addr ess tran slat ion Figure 2-26 sh ows t he virtu al-to-ph ysical-ad dress tr anslation o f a 32-bi t mode addres s. The page s can have five different sizes betw een 1 Kbyte (1 0 bits) and 2 56 Kbyte s (18 bi ts), each b eing 4 tim es as large as the pr[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 105 2.4.2.3 64-bit mode addr ess tran slat ion Figure 2-2 7 sh ows t he virtual-to -phys ical-ad dress trans lation o f a 64-bi t mode address. Th is fig ure illu strates the two possi ble pag e size; a 1 -Kbyte pa ge (10 b its) and a 256-Kb yte page (18 bit s).  Shown at the t [...]

CHAPTER 2 V R 4120A 106 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.4.2.4 Operating modes The proce ssor has th ree opera ting mode s that fu nction in both 32- and 6 4-bit operati ons:  User mode  Supervisor mode  Kernel mode User and Kern el modes are com mon to all V R -Serie s pro cessors. Genera lly, Kernel m ode is u sed to e [...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 107 The User segm ent start s at add ress 0 and the curre nt active u ser pro cess resi des in either useg (in 32-bit mode) or xuseg (i n 64-bit m ode). T he TLB id entica lly maps all refer ences t o useg /xuseg from all mode s, and control s cach e accessib ility. The proce ssor [...]

CHAPTER 2 V R 4120A 108 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.4.2.6 Supervisor-mode virtual add re ssing Supervisor m ode show n in Figu re 2-29 i s designe d for la yered op erating systems in which a true kernel runs in Kernel mode, a nd the re st of the operating system runs in Sup ervisor mo de. The proce ssor operate s in Superv i[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 109 Table 2-28. 32-b it and 64-bit Supervisor Mode S egments Address Bit Status Register Bit Value Segment Addres s Range S ize Value KSU EXL ERL SX Name 32-bit A31 = 0 01 0 0 0 suseg 0000_0000H to 7FFF_FFFFH 2 Gbytes (2 31 byte s) 32-bit A(31:29) = 110 01 0 0 0 s seg C000_0000H to[...]

CHAPTER 2 V R 4120A 110 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.4.2.7 Kernel-mode vir tual a ddress ing If the Status reg ister s atisfies a ny of th e follow ing con ditions, th e proce ssor runs in Kern el mod e.  KSU = 00  EXL = 1  ERL = 1 The addressi ng width in Kernel m ode varies a ccording t o the st ate of th e KX bit o[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 111 Figure 2-30. Ker nel Mode A ddress S pace 32-bit mode Not e 1 0.5 Gbytes with TLB mapping 0.5 Gbytes with TLB mapping 0.5 Gbytes without TLB mapping uncacheable 64-bit mode DFFF_ FFFFH E000_ 0000H C000_ 0000H FFFF_ FFFFH FFFF_ FFFF_ FFFF_ FFFFH kuseg kseg0 kseg1 ksseg kseg3 7FF[...]

CHAPTER 2 V R 4120A 112 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 2-29. 32-b it Kernel M ode Segments Address Bit Status Register B it Value Segm ent Virtual Physical Si ze Value KSU E XL ERL KX Name Address Addres s A31 = 0 0 kuseg 0000_0000H to 7FFF_FFFFH TLB map 2 Gbytes (2 31 byte s) A(31:29) = 100 0 kseg0 8000_0000H to 9FFF_FFFFH [...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 113 (5) kseg3 (32-b it kernel mo de, kernel space 3) When KX = 0 in th e Status r egister and the m ost-sign ificant three bi ts of th e virtual ad dress space ar e 111, t he kseg3 virtu al addre ss sp ace is selected; it is t he curren t 512-M byte (2 29 -by te) kerne l virtua l s[...]

CHAPTER 2 V R 4120A 114 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M (7) xksseg (64-bit k ernel mode, current supervisor sp ace) When KX = 1 in th e Status r egister and bit s 63 an d 62 of th e virtual a ddress space are 0 1, the x ksseg ad dress space is selecte d; it i s the 1-Tbyte ( 2 40 bytes) current s upervis or addre ss space . The v i[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 115 (9) xkseg (64-bit ker nel mo de, physi cal spac es) When the KX = 1 in the Stat us regi ster and bits 63 and 62 of the virtua l addre ss spa ce are 11, th e virtua l addre ss space is called xk seg and select ed as either of the followin g: • Kernel virt ual space xkse g, the[...]

CHAPTER 2 V R 4120A 116 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.4.3 Physical addr ess space So V R 4120A core uses a 32-bit ad dress, t hat t he pr ocessor ph ysical a ddress space encom passes 4 G byte s. The V R 4120A uses th is 4-G byte phys ical a ddress space as show n in Fig ure 2-31. Figure 2-31. µ µ µ µ PD98502 Phy sical Addr[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 117 2.4.4 System control coprocesso r The System Con trol Copro cessor (CP 0) is im plemented as an integral part of the C PU, and s upports memor y management, addr ess translati on, except ion processin g, and o ther priv ileged operatio ns. The CP0 conta ins the registers and a [...]

CHAPTER 2 V R 4120A 118 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.4.4.1 Format of a TLB entry Figure 2-33 sh ows t he TLB entr y formats f or both 3 2- and 64-bi t modes. Each field of an entry has a correspon ding field in the E ntryHi , EntryLo 0, EntryLo 1, or PageM ask r egisters . Figure 2-33. F ormat of a TLB Entry 114 115 96 127 107[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 119 2.4.5 CP0 regist ers The CP0 regi ster s explaine d below are a ccess ed by t he memory m anagem ent syst em and softw are. The parenthesiz ed number th at follow s each r egister name i s the re gister num ber. 2.4.5.1 Index regist er (0) The Index reg ister i s a 32-bit, rea [...]

CHAPTER 2 V R 4120A 120 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.4.5.3 EntryLo0 (2) an d EntryLo1 ( 3) re gisters The Entr yLo reg ister co nsist s of two re gisters that have i dentic al form ats: EntryLo0 , used f or even virt ual pag es and EntryL o1, used for odd virt ual pag es. The EntryLo0 and EntryLo1 register s are both read-/wri[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 121 Table 2-32. Cache Algorithm C Bit Value Cache Algorit hm 0 Cached 1 Cached 2 Uncached 3 Cached 4 Cached 5 Cached 6 Cached 7 Cached 2.4.5.4 PageMask regist er (5) The PageM ask reg ister is a r ead/wr ite register used for r eading from or writ ing to t he TLB ; it hol ds a comp[...]

CHAPTER 2 V R 4120A 122 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.4.5.5 Wired register (6) The Wir ed r egister is a read/w rite regist er that s pecifi es the l ower bound ary of t he random en try of the TLB as shown in F igure 2-3 8. Wired entries cannot be overwr itten by a TLBWR instructi on. They can, howev er, be overwritten by a TL[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 123 2.4.5.6 EntryHi regist er (10) The Entr yHi r egister is write-acc essible. I t i s u sed t o acce ss the on-ch ip TLB. The EntryH i regist er hold s the hi gh- order bits of a TLB entry for T LB read and w rite op erations. If a TLB Mismatc h, TLB Invalid, or TLB Modified exce[...]

CHAPTER 2 V R 4120A 124 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.4.5.8 Config register (1 6) The Config r egister specif ies va rious configur ation o ptions select ed on V R 4120A pr ocess ors. Some conf igurati on optio ns, as defined by the EC and BE fie lds, are set by the hardwar e during C old Res et and are incl uded in the Co nfig[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 125 2.4.5.9 Load linked addr ess (L LAddr ) regist er (17) The read/w rite Lo ad Lin ked Address ( LLAd dr) register i s not u sed with th e V R 4120A pr oces sor except f or diagnost ic purpose , and s erves no fu nction during n ormal o peration. LLAddr regi ster is im plemen ted[...]

CHAPTER 2 V R 4120A 126 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.4.5.11 Virtual-to-physi cal address translation During virtual-t o-phys ical a ddress tran slation, the CPU com pares t he 8-bit ASID (w hen the Global bit , G, i s not se t to 1) of the vir tual address to the ASID of t he TLB entr y to see if ther e is a match. One of the [...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 127 Figure 2-46. T LB Addres s Translation Virtual ad dress ( input) VPN and ASID Except ion Exception Exception Exception Ph y sical Ad dr ess ( outp ut ) Exception No Yes Yes Yes No Yes Yes No Addr es s OK? Supervisor mode? User mode? Addr es s OK? Addr es s OK? No No Yes Yes Yes[...]

CHAPTER 2 V R 4120A 128 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.4.5.13 TLB instructions The instr uction s used for TLB control are des cribed below. (1) Translation lookas ide buffer probe (TLBP) The translati on lookas ide buff er probe (TLBP) in structi on loads the Index registe r with a TLB number that m atche s the content of the E[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 129 2.5 Excepti on Pro cessing This chapter describe s V R 4120A CPU ex ceptio n process ing, in cluding an explan ation of hardware t hat pr ocesses exceptions . 2.5.1 Exception proc essing op eration The proce ssor recei ves exce ptions f rom a n umber of sou rces, i nclud ing tr[...]

CHAPTER 2 V R 4120A 130 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.5.2 Precision of e xceptions V R 4120A CPU e xceptions are log ically pre cise; the ins truction tha t caus es an e xception a nd all those that follow it are aborted and can be re-exec uted aft er servici ng the e xception. When succ eeding in structions are dis carded, exc[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 131 2.5.3.1 Context register ( 4) The Context regist er is a read/wr ite regis ter cont aining the poin ter to an entry in the page ta ble entr y (PTE) array on the mem ory; this array is a t able th at stores virtual-to-p hysi cal addres s translations. When there is a TLB miss, t[...]

CHAPTER 2 V R 4120A 132 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.5.3.2 BadVAddr regis ter (8) The Bad Virtual Ad dress (B adVAddr) register is a read-o nly regist er that saves the most recent virt ual addr ess that failed to have a valid translat ion, or that had an address ing error. Figure 2-48 shows the format of the BadVAddr register[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 133 2.5.3.4 Compare re gister (11) The Compar e regist er causes a timer interrupt; it maintai ns a st able v alue tha t does n ot chan ge on it s own. When t he val ue of the C ount reg ister (se e Section 2 .5.3.3 Count register (9) ) e quals t he val ue of the Compare register, [...]

CHAPTER 2 V R 4120A 134 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.5.3.5 Status register ( 12) The Stat us r egister is a re ad/writ e reg ister that c ontain s the op erating mod e, interru pt enabl ing, and the diagno stic states of the processor. Figure 2-51 show s the form at of th e Status r egister . Figure 2-51. St atus Register Form[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 135 Figure 2-52. St atus Register Diagnost ic Stat us Field 16 17 18 19 20 21 22 23 24 0 BEV TS SR 0 CH CE DE 1 1 1 1 1 1 1 2 BEV : Specifie s the ba se addr ess of a TLB Refil l exce ption v ector an d comm on except ion ve ctor (0 → Normal, 1 → Boots trap). TS : Occurs the TL[...]

CHAPTER 2 V R 4120A 136 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M (7) Status after reset The contents of the Sta tus register are und efined a fter Cold re sets, e xcept for th e follow ing bit s in the diagnosti c status field . • TS and SR are cleared t o 0. • ERL and BEV are set t o 1. • SR is 0 after C old reset, a nd is 1 after So[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 137 Table 2-35. Caus e Register Exc eption Code Fi eld Excepti on Code Mnemonic Description 0 Int Interrupt exc eption 1 Mod TLB Modified exc eption 2 TLBL TLB Refill exception (load or fetch) 3 TLBS TLB Refill except ion (store) 4 AdEL Address E rror exception (load or fetch) 5 Ad[...]

CHAPTER 2 V R 4120A 138 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.5.3.7 Exception progra m counter (EPC ) register (1 4) The Excep tion Program Counte r (EPC) is a re ad/wri te register t hat cont ains th e addre ss at whi ch proces sing resumes after an ex ception has be en servic ed. Beca use the µ PD985 02 does not support t he MIPS1 6[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 139 2.5.3.8 WatchLo (18) and WatchHi (1 9) registers The V R 4120A proc essor pr ovide s a d ebuggi ng featur e to detec t reference s to a s elected ph ysic al addre ss; loa d and store in structio ns to th e locat ion sp ecifie d by the Wat chLo an d WatchHi register s cau se a W[...]

CHAPTER 2 V R 4120A 140 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.5.3.9 XContext register ( 20) The read/w rite XContext regi ster contai ns a point er to an e ntry in t he page tab le entry (P TE) array, a n operat ing system dat a struct ure that stores virtual-t o-physica l addre ss trans lation s. If a TLB miss occur s, the operating s[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 141 2.5.3.11 Cache err or regist er (27) The Ca che Err or regist er is a read able/w riteabl e register. Th is regi ster is defined to mai ntain softw are-compa tibilit y with the V R 410 0, and is n ot used in hardwar e beca use the V R 41 20A CPU has no parit y. Figure 2-59 sh o[...]

CHAPTER 2 V R 4120A 142 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.5.4 Details of excepti ons This secti on des cribes cause s, proce sses, and servi ces of t he V R 4120A's ex ception s. 2.5.4.1 Exception typ es This secti on give s sam ple ex ception handler operati ons for the f ollow ing ex ception types:  Cold Reset  Soft Re[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 143 Table 2-37. 32-B it Mode Exce ption Vector Base Addr esses Vector Base Address (Virtual) Vect or Offset Cold Reset Soft R ese t NMI BFC0_0000H (BEV b it i s au tomat ical ly se t to 1) 0000H TLB Refill (EXL = 0) 0000H XTLB Refill (EXL = 0) 0080H Other exceptions 8000_0000H (BEV[...]

CHAPTER 2 V R 4120A 144 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.5.4.3 Priority of exce ptions While more th an one e xception can oc cur for a single instru ction, onl y the ex ceptio n with the highest pri ority i s reported. Tabl e 2-38 li sts the prioriti es. Table 2-38. Exce ption Priority O rder High ↑        [...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 145 2.5.4.4 Cold reset ex ception (1) Cause The Cold Re set excepti on oc curs when the ColdR eset_B signa l (intern al) is ass erted and the n deas serted. T his exception i s not mas kable. The Rese t_B signal ( internal) m ust b e asser ted alo ng with th e ColdR eset_B sign al [...]

CHAPTER 2 V R 4120A 146 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.5.4.5 Soft reset exc eption (1) Cause A Soft Reset ( sometime s called Warm Reset) occurs w hen the C oldReset _B signal (i nternal) r emains de asserte d while the Re set_B s ignal (intern al) goe s from asser tion to deass ertion (for deta ils, see Section 2.6 In itia liza[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 147 2.5.4.6 NMI except ion (1) Cause The Nonma skable Inter rupt (NM I) excepti on oc curs when the NMI s ignal ( internal) becomes a ctive . This interr upt is not mas kable; it o ccurs re gardle ss of the se ttings of the EXL, ERL , and IE b its in t he Status reg ister (for deta[...]

CHAPTER 2 V R 4120A 148 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.5.4.7 Address er ror exception (1) Cause The Address Error except ion oc curs whe n an attempt is ma de to ex ecute one o f the fol lowing. T his e xception i s not maskab le. • Execution of the LW, L WU, SW, or C ACHE ins truction for w ord data t hat is n ot located on a[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 149 2.5.4.8 TLB exceptio ns Three types o f TLB ex ception s can occ ur: • TLB Refill e xception occurs wh en there is no TLB e ntry that m atche s a refer enced addre ss. • A TLB Invalid e xception occurs w hen a TLB entry th at matches a referen ced virtua l addres s is mark [...]

CHAPTER 2 V R 4120A 150 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M (2) TLB invalid e xception (a) Cause The TLB Inv alid exce ption o ccurs wh en the T LB entry t hat mat ches with the vir tual ad dress to be refere nced is invalid (the V bit is set to 0). This except ion is not mask able. (b) Processing The comm on exception vector is used f[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 151 (3) TLB modified e xception (a) Cause The TLB Modifi ed ex ception occurs w hen the TLB entry that m atche s with th e virtua l address r eference d by th e store instru ction i s valid (V b it is 1) but is n ot writeab le (D b it is 0). Th is ex ception is not m askable . (b) [...]

CHAPTER 2 V R 4120A 152 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.5.4.9 Bus error ex ception (1) Cause A Bus Error excep tion i s raised by board-le vel c ircuitry for e vents such a s bus t ime-out, lo cal bu s parity errors, a nd invalid physica l mem ory addres ses or acce ss typ es. Thi s exce ption is not m aska ble. A Bus Error excep[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 153 2.5.4.10 System call ex ception (1) Cause A System Call e xception occurs dur ing an at tempt to execute t he SYSCALL in struction. T his ex ception i s not maskable. (2) Processing The comm on exception vector is us ed for thi s except ion, and t he Sys code i n the Ex cCode f[...]

CHAPTER 2 V R 4120A 154 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.5.4.12 Coprocessor unusabl e excep tion (1) Cause The Coproce ssor Unu sable exception occur s when an attempt is mad e to execut e a cop roces sor instr uction for either:  a corresp onding copr oces sor unit t hat has not been m arked us able (St atus regist er bit, C U[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 155 2.5.4.13 Reserved instr uction exc epti on (1) Cause The Reserv ed Instr uction except ion occur s when an attempt is mad e to execut e one of the fol lowin g instructi ons: • Instruction w ith a n undefined m ajor o pcode ( bits 31 to 26) • SPECIAL instructio n with an und[...]

CHAPTER 2 V R 4120A 156 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.5.4.14 Trap excepti on (1) Cause The Trap exce ption occ urs when a TGE, TG EU, TLT, TLTU, TEQ, TNE, TGEI, TGEUI, T LTI, TLTUI, TEQI, or TNEI instruc tion result s in a TR UE con dition. This exce ption is not mas kable. (2) Processing The comm on exception vector is us ed f[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 157 2.5.4.16 Watch exception (1) Cause A Watch exce ption o ccurs whe n a loa d or stor e instru ction re ferences th e phys ical addre ss spe cified by the WatchLo/Watc hHi re gisters. Th e WatchL o/WatchH i regist ers spe cify whe ther a lo ad or st ore or bot h coul d have initi[...]

CHAPTER 2 V R 4120A 158 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.5.4.17 Interrupt except ion (1) Cause The Interrupt e xceptio n occur s when o ne of the eight i nterrupt conditi ons Note is assert ed. In th e V R 4120A CP U, interrupt reque sts from internal pe ripheral units f irst ent er the ICU an d are the n notifi ed to the CPU core[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 159 Figure 2-61. Co mmon Excep tion Han dling (1/2) (a) Handling Exception s other than Col d Reset, Soft Re set, NMI, and TLB/XTLB R efill (Hardware) BD bit ← 1 EPC ← PC − 4 EXL ← 1 Kernel mode is s et and int errup ts are disabl e d. = 0 (Normal) = 1 (boo tstrap) Che ck f[...]

CHAPTER 2 V R 4120A 160 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 2-61. Com mon Except ion Han dling (2/2) (b) Servicing Common Ex ceptions (Software) The proc ess or is re set. (In Kernel mode, int errupts are enabled. ) • Aft er EXL = 0 is set , al l exc ept ions are ena bled (al thou gh the Int errupt ex cept ion can be mas ked b[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 161 Figure 2-62. T LB/XTLB Refill Exception H andling (1/2 ) (a) Handling TLB/XTLB Refill E xcept ions (Hardwar e) BD bit ← 0 BD bit ← 1 EPC ← PC − 4 EXL ← 1 EPC ← PC Kerne l mode is s et and inte rrupts are di sab led. = 1 ( boo tstr ap) = 0 (N ormal) Check for mu ltip[...]

CHAPTER 2 V R 4120A 162 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 2-62. T LB/XTLB Refill Exception H andling (2/2 ) (b) Servicing TLB/XTLB Refill E xceptions (S oftware) • The occurrence of TLB Refill, TLB Invalid, and TLB Modified ex cepti ons is di sabled by us ing an unmapped spac e. • The occurrenc e of the Watc h and Interrup[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 163 Figure 2-63. Col d Reset Exception H andling (Har dware) PC ← FFFF FFFF BFC 0 0000H (Sof t ware) • The pro c essor pro vid e s no me an s of distingu ishing be twee n an NMI ex ceptio n a nd So f t Rese t e xce ptio n, so that this mus t be dete rmine d at th e sy ste m l e[...]

CHAPTER 2 V R 4120A 164 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 2-64. Soft Reset and N MI Exceptio n Handling BD bit ← 1 Erro rEPC ← PC − 4 Se t Sta tus re giste r BEV bit ← 1 TS b it ← 0 SR bit ← 1 ERL bit ← 1 BD bit ← 0 Erro rEPC ← PC (Hardware) So ft Reset o r NMI e x ce ptio n Yes ERL=1? No No Yes I nstr uction[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 165 2.6 Initialization Inte rface This secti on des cribes t he reset sequen ce of th e V R 4120A Cor e. For det ails a bout factors of reset or reset of the whole V R 4120A C ore. 2.6.1 Cold reset In the V R 412 0A Core, a c old reset s equenc e is executed in the C PU core in the[...]

CHAPTER 2 V R 4120A 166 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.6.3.1 Power modes The V R 4120A supports four power m odes: Fullspee d mode, Standby mo de, Susp end mod e, and Hi bernate mode . (1) Fullspeed mode This is the normal operatio n mode. The V R 4120A’ s default s tatus sets oper ation u nder Ful lspeed mo de. After th e pro[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 167 2.6.3.2 Privilege mod e The V R 4120A supports three sy stem modes: kernel ex panded addres sing mode, superv isor ex panded addr essing mode, and u ser expa nded addres sing m ode. Th ese three m odes ar e descr ibed be low. (1) Kernel expand ed addressi ng mode When the St at[...]

CHAPTER 2 V R 4120A 168 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.7 Cache M emory This secti on des cribes in detai l the cach e mem ory: its place in t he V R 41 20A Core m emory organ izatio n, and individual organi zation o f the ca ches. 2.7.1 Memory organizat ion Figure 2-65 sh ows t he V R 4 120A Core s ystem m emory hi erarchy. In t[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 169 2.7.2 Cache organi zation This secti on des cribes t he organ izatio n of the o n-chip data and in structi on cac hes. Figure 2-66 p rovid es a block diagram of th e V R 4120A C ore ca che and m emory mode l. Figure 2-66. Cache S upport V R 4120A CPU core Cache controller I-cac[...]

CHAPTER 2 V R 4120A 170 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 2-67. I nstruction C ache Lin e Format 22 21 V PTag 0 1 22 Data 0 Data Data Data 31 PTag : Physical tag ( bits 31 to 10 of physi cal ad dress) V: V a l i d b i t Data : Cache da ta 2.7.2.2 Organizat ion of the da ta cach e (D-cach e) Each lin e of D- cache data has an a[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 171 2.7.2.3 Accessing th e caches Figure 2-69 sh ows t he virtu al address (VA) index int o the c aches. The number of virtual address bit s used to index the instruct ion and data caches depends on the cac he size. (1) Data cache addressing Using VA (12: 4). The m ost-sig nificant[...]

CHAPTER 2 V R 4120A 172 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.7.3.1 Cache write policy The V R 4120A Cor e manag es its data ca che b y using a writ e-back pol icy; that is, it stores write dat a into the cache, instead of writing it dire ctly to mem ory Not e . Some tim e lat er this data is ind ependen tly writte n into m emory. In t[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 173 2.7.5 Cache state tr ansition di agrams The follow ing se ction de scribes the cac he state diagram s for the dat a and instr uct ion cache lin es. These state diagrams do not co ver the i nitial state of the sy stem, since t he init ial stat e is sys tem-depende nt. 2.7.5.1 Da[...]

CHAPTER 2 V R 4120A 174 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.7.6 Cache data i ntegrity Figures 2-72 t o 2-8 6 shows checking operati ons for various ca che ac cesse s. Figure 2-72. Dat a Check Flow on Instru ction Fetch Start Data Fe tch END Tag Check Refill (See Figure 2-85 ) Hit Miss Figure 2-73. Dat a Check Flow o n Load Operation [...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 175 Figure 2-74. Dat a Che ck Flow on Store O perations Start Write-back and Refill ( see Figure 2-86 ) END Hit V = 0 (invalid) or W = 0 (clean) Miss V bit, W bit V = 1 ( valid) and W = 1 (dirty) Refill ( see Figure 2-85 ) Tag Check Data W rite to Da ta C ache Figure 2-75. Dat a Ch[...]

CHAPTER 2 V R 4120A 176 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 2-76. Dat a Che ck Flow on Ind ex_Writ eback_In validate Oper ations = 0 ( Clean ) Start Write-back (see Figure 2- 84 ) END = 0 ( In valid ) W bi t = 1 (dirty) V bit Valid bit and W bit Clear = 1 ( Va lid ) Figure 2-77. Dat a Che ck Flow on Ind ex_Load_T ag Operati ons [...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 177 Figure 2-78. Dat a Che ck Flow on Ind ex_Store_Tag Operation s Start Tag W rite fro m Ta gLo END Figure 2-79. Dat a Che ck Flow on Cr eate_Dirt y Operati ons Start Write-back (see Figure 2- 84 ) END Miss or In valid V bit, W bit = 1 ( dirty ) Tag Check V bit and W bit set, Tag [...]

CHAPTER 2 V R 4120A 178 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 2-80. Dat a Che ck Flow on Hit_In validate O perations Start Valid bit Clear END Miss or Inv alid Tag Check Hit Figure 2-81. Dat a Che ck Flow on Hi t_Writebac k_Invalid ate Operat ions Start Write-back (see Figure 2-84 ) END Miss or In valid W b i t = 1 (dirty) Tag Che[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 179 Figure 2-82. Dat a Check Flow on Fill Operation s Start Refill ( see Figure 2-85 ) END Figure 2-83. Dat a Che ck Flow on Hi t_Writebac k Operation s Start Write-ba ck (see Figure 2- 84 ) END Miss or In valid W b i t = 1 (dirty) Tag Check Hit = 0 (Clean) W bit clear Data c ache [...]

CHAPTER 2 V R 4120A 180 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 2-84. Writ eback Fl ow EOD ? Yes No Wr i t e- ba ck t o me mory Figure 2-85. Ref ill Flow EOD ? Yes No W ri te da ta to C ach e Bus Error Exception Error bit Cache line Invalid OK Error[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 181 Figure 2-86. Writ eback & Refill Flow EOD ? Yes No Write-back to memo ry EOD ? Refill Star t Write data to cach e Error bit OK Bus Error Except ion Cache line Invalid Yes Error No Remark Write-back Pro cedure: On a store m iss writ e-back, data tag is ch ecked and data i s [...]

CHAPTER 2 V R 4120A 182 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.8 CPU Core Interrupts Four types of interrupt are ava ilable on the CP U core. These are:  one non-mas kable interr upt, NMI  five ordinar y interrupts  two software interrupt s  one timer int errupt For the interrupt request input t o the CP U core. 2.8.1 Non-ma[...]

CHAPTER 2 V R 4120A Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 183 2.8.5 Asserting inter rupts 2.8.5.1 Detecting hardw are interrup ts Figure 2-88 sh ows how the har dware interr upt s are readabl e throug h the C ause regis ter. The timer int errupt si gnal, IP7, is dir ectly reada ble as bit 15 o f the Cau se regis ter. Bits 4 to 0 of t he I[...]

CHAPTER 2 V R 4120A 184 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2.8.5.2 Masking interr upt signal s Figure 2-89 sh ows t he maski ng of the CPU core interrupt signa ls.  Cause regi ster bit s 15 to 8 (IP7 t o IP0) are AND -ORed wi th Status register interrupt mask bits 15 to 8 (IM7 to IM0) to mas k individu al interr upts.  Status re[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 185 CHAPTER 3 SYSTEM CONTROLLER 3.1 Overview Register m ap This block is an internal system c ontroll er for the µ PD985 02. Sy stem controll er provi des bridgi ng funct ion am ong the CPU syst em bus “SysAD”, NEC orig inal h igh-speed o n-chip bu s “IBUS” an d memory b us for SDRAM /PROM /f[...]

CHAPTER 3 S YSTEM CONTROLLER 186 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M • 66-MHz IBUS c lock rat e • Supports 266-M B/sec (3 2 bits @6 6 MHz) bur sts on IBUS. • Support endian conver sion b etween memory a nd IBUS sla ve I/F • Support endian conver sion b etween SyaAD bus and IBUS m aster I/F 3.1.4 UART • Universal Asynchron ous[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 187 3.1.9 System block di agram Sy stem Contr oll er IBU S Sy sAD TIM ER IBU S Mas ter- I F Flas h PRO M SDRAM RS-232C Fl as h- I F SDRAM- UART R egis t er Memo r y Arbi ter MI F HIF DSU Sy sAD -I F S y sA D -I F Pref etc h Buff e r Wr i t e Buff e r 64- wor d R ead Buff e[...]

CHAPTER 3 S YSTEM CONTROLLER 188 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.1.10 Data flow diagr am V R 4120A C o r e t o SD R AM I BUS t o S DRAM V R 4120A C o r e t o I B U S V R 41 2 0 A Cor e t o UART SysA D ME M FLASH -I F SDRAM- I F Mem o ry Arbiter MI F HIF Sys A D- IF Sy sAD- IF W P R W R IBUS M aster- I F IBUS S lave-I F IBU S SysA[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 189 3.2 Registers 3.2.1 Register map Following Table sum marize s the contro ller’s r egister set. The ba se address for the set is 1000 _0000H in the physical addre ss space . Offset Address Regist er Name R/W Acc ess Descripti on 1000_0000H S_GM R R/ W W/H/B General Mo[...]

CHAPTER 3 S YSTEM CONTROLLER 190 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Offset Address Regist er Name R/W Acc ess Descripti on 1000_00D8H MA CAR1 R W/H/ B MAC Address Register 1 1000_00DCH MACAR2 R W/H/ B MAC Address Regis ter 2 1000_00E0H MACAR3 R W/H/ B MAC Address Regis ter 3 1000_00E4H: 1000_00FCH N/A - - Reserved for futu re u se 100[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 191 3.2.2 S_GMR (G eneral Mode Regi ster) The genera l m ode register “S_GM R” is a read-writ e and 32-b it w ord-aligne d regist er. After ini tializin g, V R 412 0A sets the IAEN bit to enab le the IBU S arbite r. S_GMR is init ialized to 0 at res et and cont ains th[...]

CHAPTER 3 S YSTEM CONTROLLER 192 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.2.4 S_ISR (Interrupt Status Reg ister) The interru pt s tatus regis ter “S_ISR” is a read-clear and 32-b it wor d-aligned re gister. S_ ISR indicate s the interruption s tatus from S ysAD/IBUS interfac es, tim er, UART and so on. If corresp onding bit in S_IMR ([...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 193 3.2.5 S_IMR (Interrupt M ask Regis ter) The interrupt m ask regis ter “S_IMR” i s a read-wr ite and 32-bit word-aligned regist er. S_IMR masks interr uption for each corr esp onding incid ent. A ma sk bit, whic h locates in the s ame b it locat ion to a corres pond[...]

CHAPTER 3 S YSTEM CONTROLLER 194 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.2.6 S_NSR (NMI Status R egister ) The interrupt s tatus regis ter “S_NSR” i s a read-cl ear and 32-bit word-aligned regist er. S_NSR indicate s the non- maskable interrupti on “NMI” s tatus from S ysAD/IBUS i nterface s, external NMI, mem ory interface and s[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 195 3.2.7 S_NER (NMI Enable R egister ) The NM I enable reg ister “S_NER” is a r ead-wri te and 3 2-bit wo rd-aligned re gister . S_NER en ables NM I for ea ch correspondin g i ncident . A enabl e bit, w hich lo cates i n the same bit loc ation to a corre sponding b it[...]

CHAPTER 3 S YSTEM CONTROLLER 196 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.2.9 S_IOR (IO Port R egister) The IO port reg ister “S_IO R” is a r ead-write a nd 32-bi t word-ali gned register. IO port reg ister i s used to indicate the status of software. E ach bit of the foll owing POM_OU T fields is co nnecte d to the externa l IO port [...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 197 3.2.10 S_WRCR (Warm Reset Control Register) The warm reset contr ol regi ster “S_WRCR” is a writ e-only a nd 32-bi t word-ali gned register. S_WRCR generate s warm-reset reque st to USB C ontroller, Eth ernet Contro ller, ATM Cell Processor, UART, and PCI Controlle[...]

CHAPTER 3 S YSTEM CONTROLLER 198 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.2.11 S_WRSR (Warm R eset Statu s Re gister) The warm reset status regi ster “S _WRSR” is a re ad-only and 32-bi t word-al igned re gister. S_WR SR indicate s the response from U SB Contr oller, Ethernet Contr oller, ATM C ell Proces sor, UART, and PCI Contr olle[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 199 3.2.12 S_PWCR (Power Contr ol Reg ister) The pow er contro l re gister “S_PWC R” is a read-write and 32-bit wor d-aligned re gister. S_PWCR r equest s to ke ep the idle state for USB C ontroller, Ethernet Co ntroller, ATM Cell Pr ocessor, a nd PCI Control ler by se[...]

CHAPTER 3 S YSTEM CONTROLLER 200 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.2.13 S_PWSR (Power Statu s Regis ter) The pow er st atus regist er “S_PWSR” is a read-on ly and 32-b it word-al igne d regist er. The IDLE fie ld in S_PWSR indicates the status that it is ready to sus pend. The WKU P filed in S_PWSR indicate s the wak eup requ e[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 201 3.3 CPU Interf ace The system co ntroller provide s the direct i nterface for the V R 41 20A usin g the 32-bi t SysAD bus operated at 100 MHz or 66 MHz. 3.3.1 Overview • Connects t o the V R 41 20A CPU bu s “SysAD bus” dire ctly. • Supports all V R 4120A bus cy[...]

CHAPTER 3 S YSTEM CONTROLLER 202 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 3-1. Endian Co nfiguration Ta ble BIG pin ENDCE N pin Status regist er RE field in V R 4120A Endian in V R 4120A Endian in syste m co ntroller Endian conv erter operation 0 0 0 LITTLE LITTLE Transparent 0 1 0 LITTLE LITTLE Transparent 1 0 0 BIG LITTLE Data swap [...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 203 3.3.6 I/O performan ce The follow ing tabl e indicate s the I/O performan ce acces sing fr om the V R 4120A th rough the sy stem control ler. W/R Target area Burst length Acc ess latency [V R 4120A clocks] R IBUS target 1 24 R IBUS target 2 24-1 R IBUS target 4 27-1-1-[...]

CHAPTER 3 S YSTEM CONTROLLER 204 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.4 Memory Int erface The V R 4120A a ccesses m emory at tached to th e contro ller in the normal wa y, by addre ssing the m emory sp ace. 3.4.1 Overview • 66 MHz or 100 MHz mem ory bu s • Supports up to 32 MB ba se memory range for SDRAM • Supports up to 8 MB w[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 205 3.4.3 Memory signal connections µ µ µ µ PD98502 SMD[31 :0] SRMOE_ B SRMCS_ B SDRAS_ B SDCS_B SDCAS_ B SDWE_B SDCLK[1:0] SMA[20 :0] SDQM[3 :0] SDCKE[ 1:0] (SDQM=SMA[17:14] ) Flash PROM OE_B WE_B CS_B A[20:0] D[31: 0] SDRAM RAS_B CS_B CAS_B WE_B DQM[3:0] CKE CLK[1:0][...]

CHAPTER 3 S YSTEM CONTROLLER 206 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.4.4 Memory perfor mance The latency of mem ory acces ses i s determine d by m emory typ e, speed and prefetch scheme. Fol lowin g lists some examples of acce ss lat encies. 66-M Hz or 1 00-MHz m emory-bu s clock is req uired for each transfer of a 4-word (16- byte) [...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 207 3.4.5 RMMD R (ROM M ode Register) The ROM m ode regist er “RMMD R” is a read-w rite an d 32-bit word-al igned register. RM MDR is used to setup the PROM/flash m emory interf ace. R MMDR is initia lized t o 0 at reset and con tains t he foll owing fie lds: Bits Fiel[...]

CHAPTER 3 S YSTEM CONTROLLER 208 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M in v a lid SM A SDCLK No r m a l ROM Rea d Cy c l e SM D FAT(=4) SRM C S_B SRM OE_B SDWE_B H V al i d R ead Ad d r ess T0 T1 T2 T3 T4 T0 Hi - Z R ead D ata T1 T2 T3 T4 T5 T6 F L A S H M e m o r y W r ite C yc le H V a lid W rite A d d re s s Wr i t e Da t a FAT(=6) RO[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 209 3.4.7 SDMDR (SDRAM Mode Register) The SDRAM m ode regist er “SDMDR ” is a read-wr ite and 32-bit word-ali gned reg ister. SDMDR is used to setup the SDRAM interfac e. SDMD R is init ialize d to 330H at reset and contai ns the f ollow ing fields : Bits Field R/ W De[...]

CHAPTER 3 S YSTEM CONTROLLER 210 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.4.8 SDTSR (SDRAM Type Sele ction Re gister) The SDRAM type se lection regist er “SD TSR” is a r ead-write a nd 3 2-bit word-al igned regi ster. SDTSR is used t o setup the ty pe of SDR AM. SDTSR is initiali zed to 0 at rese t and c ontains the followin g field s[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 211 3.4.9 SDPTR (SDRAM Precha rge Timing Register) The SDRAM prec harge timin g regist er “SDPTR” is a r ead-write and 32-bi t word-aligned register. SDPTR is used to set the pr echarge timing for t he SDRAM control ler. SDPTR is initializ ed to 142H at reset and conta[...]

CHAPTER 3 S YSTEM CONTROLLER 212 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.4.11 SDRCR (SDRAM Refresh Timer Count R egister) The SDRAM refresh tim er count re gister “SDRCR” i s a read-on ly an d 32-bit w ord-aligned r egister. SDRCR is a 16- bit timer that cause s an SDRAM refresh whe n it expire s. The SDR AM refresh c ontroller autom[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 213 3.4.13 Boot ROM The sys tem control ler sup ports up to 8 MB of bo ot mem ory. Th is mem ory must be popula ted with e ither of t he following two type s of memory devi ces: PRO M/flash m emory. 3.4.13.1 Boot ROM configur ation and address ran ges Boot ROM can be popu [...]

CHAPTER 3 S YSTEM CONTROLLER 214 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 3-7. Co mmand Sequ ence (a) Program Command Seque nce (4 Write Cycles) 1st Write 2nd Wri te 3rd Write 4th Writ e 5t h Write 6th Write A 1FC0_2AA8H A 1FC0_1554H A 1FC0_2AA8H A PA* A A D AAAA_AAAAH D 5555_5555H D A0A0_A0A0H D PD* D D (b) Chip Erase Comm and Sequen[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 215 3.4.1.4 Boot ROM signal connections SMD [ 31: 0] SRM OE _B SDW E_B SRM C S_B Exam pl e ( 8 M B PR O M ) SMA [ 20: 0] SM D[31: 0] µ PD98502 (System C ontr ol ler ) µ PD98502 (System C ontr ol ler ) FLA S H / RO M C onf i gur at i on SMD [ 31: 0] SRM OE _B SDW E_B SRM [...]

CHAPTER 3 S YSTEM CONTROLLER 216 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.4.14 SDRAM 3.4.14.1 SDRAM address range System m emory can be populat ed w ith SD RAM chips, and it mus t have an acc ess time of 10 ns or l ess. Th e system contro ller support s 16-Mb it or 64-Mbit and 128-M bit SDR AM at lo cations 0 000_000 0H through 01FF_FFFFH[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 217 3.4.1.4 SDRAM word ordering Following table indi cates t he word-a ddress ord er for a 4-w ord i nstruct ion-cache lin e fill from SDRAM. This order is determined b y the SDR AM chips’ burst t ype, w hich is pr ogramm ed during the mem ory initializat ion procedur e.[...]

CHAPTER 3 S YSTEM CONTROLLER 218 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M RAS_B SDCAS_B SMA [ 1 3: 0] SMD[3 1: 0] 1 M x 16 SDRAM A[ 11 : 0] DQ [1 5: 0] RAS_B CS_B µ PD98502 ( Syst em Con t r ol l er ) µ PD98502 ( Syst em Con t r ol l er ) µ PD98502 ( Syst em Con t r ol l er ) µ PD98502 ( Syst em Con t r ol l er ) SDCAS_B SDRAS_B SDW E_B[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 219 3.4.15 SDRAM refresh The sys tem co ntroller supports CAS-Befor e-RAS (CBR) D RAM refr esh to a ll SDRAM addr ess ra nges. Th e refresh clock is derived from the system clock ; its rate is determined by programming the RCR filed in the SDRAM Refresh Mode Register “SD[...]

CHAPTER 3 S YSTEM CONTROLLER 220 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.4.18 SDRAM mem ory initialization The follow ing se ctions describe th e conf iguratio n seque nce us ed in this ini tializ ation. 3.4.1.1 Power-on initializ ation sequ ence by memory controller The follow ing sequen ce to c onfigure m emory i s done autom atic ally[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 221 3.5 IBUS Interfa ce 3.5.1 Overview • IBUS Master and t arget ca pabilit y • 64-word (256-byte) IBUS Slave T xFIFO (IBUS r ead data from IBUS) • 64-word (256-byte) IBUS Slave R xFIFO (IBUS writ e data to IBUS) • 4-word (16-byte) IBUS M aster TxFIFO (V R 41 20A r[...]

CHAPTER 3 S YSTEM CONTROLLER 222 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 31 0 78 56 34 12 31 0 78 56 34 12 2 bytes Outline figure of Endi an converter 31 0 78 56 34 12 31 0 78 56 34 12 1 byte 31 0 78 56 34 12 31 0 78 56 34 12 word 31 0 78 56 34 31 0 78 56 34 31 0 56 34 12 31 0 56 34 12 3 bytes Big Endian: offset 0H · · Little Endian: 0H [...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 223 3.5.4 ITCNTR (IBUS Timeout Time r Control Register) The IBUS Tim eout Timer c ontrol reg ister “ITCNTR ” is a read-wr ite and word-aligned 32-bi t register. ITCNTR is used to enab le use of the IBUS Tim eout T imer. ITCNTR is init ialize d to 0H at r eset an d cont[...]

CHAPTER 3 S YSTEM CONTROLLER 224 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.6 DSU (Deadman ’s SW Unit) 3.6.1 Overview The DSU det ects wh en the V R 4120A i s in run away (end less loop) st ate and r eset s the V R 412 0A. The use of the DSU to minim ize run away tim e effect ively m inimizes data lo ss that can oc cur due to software -re[...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 225 3.6.5 DSUTIMR (D SU Elapsed Time R egister) This regi ster ind icates the elapsed t ime for t he curre nt Deadm an’s Sw itch timer. DSUTIMR is a read-only and 32-b it word-al igned re gister. Defau lt i s 0H. Bits Field R/ W Default Description 31:0 CRTTIM R 0 Curren[...]

CHAPTER 3 S YSTEM CONTROLLER 226 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 3.7 Endian Mode Softw are Iss ues 3.7.1 Overview The native e ndian m ode for MIPS pr ocess ors, li ke Motorola and IBM 370 processor s, is big endia n. However, the native m ode for Intel (whi ch deve loped t he PCI standard) a nd VAX pro cessor s is littl e endian. [...]

CHAPTER 3 S YSTEM CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 227 Figure 3-1. Bit and Byte Order of Endi an Modes BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 4 0 MSB LS B 31 0 MSB = Most Significant Byte LSB = Least Significant Byte Big-Endian Big End Little End BYTE3 BYTE2 BYTE1 BYTE0 BYTE7 BYTE6 BYTE5 BYTE4 4 0 MSB LS B 31 0 Li[...]

CHAPTER 3 S YSTEM CONTROLLER 228 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M However, w hen makin g ha lf-word acce sses i nto a dat a array co nsi sting of w ord data, access t o the more- significan t ha lf word require s the ad dress corre spondi ng to the less signif icant half w ord (and vice ver sa). Suc h code is not endia n-indep enden[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 229 CHAPTER 4 ATM CELL PROCESSOR 4.1 Overview This section des cribes func tional spe cificatio ns of ATM cell processor unit. 4.1.1 Function feat ures Features o f ATM Cell Proc essor wit h out Firmw are (F/W) is as foll ows: • Data Transmis sion Cap acity Aggregated tran smis sion capac ity is 50 [...]

CHAPTER 4 ATM CELL PROCESSOR 230 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.1.2 Block diagram of ATM cel l pr ocessor Figure 4-1. Bloc k Diagr am of ATM Cell Processor ATM Cell Processor V R 4120A RISC Processor System Controller Ethernet Controller #1, #2 USB Controller UTOPIA BUS Controller RISC Core SAR REGS Work RAM Data RAM I cache IRA[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 231 4.1.2.3 UTOPIA bus co ntroller This block has so me H/W resources – DMA con troller, FIFOs, CRC calculato rs/checkers. Its features are as follows: • Scatter /Gather-DMA c ontroller t hat ca n operate the distributed data accordin g to descriptor tables, w ithout F[...]

CHAPTER 4 ATM CELL PROCESSOR 232 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.1.2.4 Other bloc ks Work-RAM is 12 K- byt e memory. T ables a nd Pool De script ors are l ocated in this RAM . It is shared between MCU and UTOPIA Bu s Controll er bloc k. It al so can be acces sed by V R 412 0A RISC Proc essor, usin g Indir ect-Acce ss. 4.1.3 ATM c[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 233 4.1.3.1 AAL-5 SAR subl ayer functio n When ATM Ce ll Processor transm its a cell in AAL-5 m ode, it a dds a trai ler to the variable-len gth data, as well as padding, so that its overal l lengt h becomes a mult iple of 48 by tes, t hereby g eneratin g an AAL-5 PDU . Wh[...]

CHAPTER 4 ATM CELL PROCESSOR 234 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 4-4. ATM Cell VCI GFC Segment 48 byte VPI VPI PTI HEC CLP header 1 2 3 4 5 6 7 8 bit The funct ion of each field i n the he ader is as fol lows: (a) GFC (General F low Con trol) fie ld: Used f or flow co ntrol. At tr ansmi ssion, the value set in the packet des[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 235 (3) Cell scheduling ATM Cell Proces sor use s Scheduli ng Tabl e, Cell Tim er and Tx VC table for the cell scheduling . Before the V R 4120A starts tra nsmitt ing a packet, it sets the r ate inform ation in Tx VC t able. ATM Cell Proc essor cal culate s cell transmissi[...]

CHAPTER 4 ATM CELL PROCESSOR 236 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.2 Memory Space Although the R ISC Core in the ATM Ce ll Proce ssor is a 3 2-bit MPU, its phy sical m emory spac e is 24-bit width. Figure 4-6. M emory Spac e from V R 4120A and RISC Cor e Wo r k R A M & Re gi st e r Sp ace Instr ucti on space A_IBBAR :I Bus dat [...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 237 4.2.1 Work RAM and r egister s pace Work RAM and Regi ster Spa ce are s hown in F igure 4-7. The ca pacity of W ork RAM is 16 KB ma x. In ord er to access Work RAM, the user has to us e “Indire ct Access C omm and”. In regi ster sp ace, A_GM R (gener al mode regist[...]

CHAPTER 4 ATM CELL PROCESSOR 238 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.4 Registers f or ATM C ell Pr ocess ing Registers in ATM Cell Pro cessor block ca n be cl assif ied into 3 group s: SAR regis ters, DM A register s and FIFO Control regi sters. T hese reg isters c an be acce ssed bot h V R 4120A a nd RISC Cor e in ATM C ell Proce ss[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 239 Offset Address Regist er Name R/W Acc ess Descripti on 1001_F0C8H A_TSR R/ W W T ime Stamp Register 1001_F0CCH: 1001_F1FCH N/A - - Reserved for futu re u se 1001_F200H: 1001_F2FCH N/A - - Can not access from V R 4120A RISC Core. This area is used for an internal functi[...]

CHAPTER 4 ATM CELL PROCESSOR 240 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.4.2 A_GMR (G eneral Mode Regi ster) A_GMR is us ed to se lect op eration mod e of thi s block, e nables /disab les ATM SAR oper ations. A fter reset , V R 4120A mus t wr ite this re gister f or initi alization. M odifi cation of A_GMR after star ting Tx/Rx o peratio[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 241 4.4.4 A_IMR (Interrupt Mask Regis ter) A_IMR m asks inte rruption for e ach corr espond ing ev ent. A Ma sk bit, w hich l ocates in the same b it location to a correspondin g b it i n A_GS R, m asks interrupti on. I f a bit o f this re gister is rese t to a ‘0’, th[...]

CHAPTER 4 ATM CELL PROCESSOR 242 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.4.5 A_RQU (Receivin g Queue Underr un Register) A_RQU shows t he status of each poo l. When a pool has no free b uffers, th e correspon ding bi t is se t. ATM Cel l Processor detect s a pool em pty when it rece ives a cell a nd try to send the cell to buffer. Whenev[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 243 4.4.10 A_MSA0 to A_M SA3 (Mailbox Star t Address R egister) A_MSA0 to A_MSA3 shows star t addre ss of R eceive M ailbox (M ailbox 0 and Mail box1) a nd Transmit M ailb ox (Mailbox2 a nd Mai lbox3) r espect ively. Initial value is all zer o. Bits Field R/ W Default Desc[...]

CHAPTER 4 ATM CELL PROCESSOR 244 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.4.13 A_MWA0 to A_MWA 3 (Mailbo x Write Address Register) A_MWA0 to A_MWA3 shows write ad dress o f Recei ve Mailbo x (Mail box0 and M ailbox 1) and Transm it Ma ilbox (Mailbox2 a nd Mai lbox3) r espect ively. Initial value is zer o. Bits Field R/W Default Descri pti[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 245 4.4.18 A_T1R (T1 Time Register ) A_T1R s hows t ime which user all ows ATM C ell Proce ssor to s pend t o receive a whole of one pac ket. In itial v alue is “0000_FFFFH”. Bits Field R/ W Default Description 31 Reserv ed R/ W 0 Reserv ed for future use. Write ‘0?[...]

CHAPTER 4 ATM CELL PROCESSOR 246 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.4.22 A_ UMCMD (UTOPIA Management Interface Command Register) A_UMCM D selects op eration mod e of UTOPIA M anagemen t Interfa ce. After re set, RISC C ore must w rite this register to co nfigure UTO PIA Man agement Int erface. When BM bit i s set to ‘0 ’, it mea[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 247 4.5 Data St ructur e ATM Cell Proces sor has Tx/R x buffer structur e similar t o that of E thernet Co ntroller and U SB Controller. 4.5.1 Tx buffer structur e The follow ing figure shows Tx buffer struct ure used by ATM Cell Proce ssor. It co nsist s of a pa cket d es[...]

CHAPTER 4 ATM CELL PROCESSOR 248 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 4-9. Tx Buffer Elements - Tx buffer di rect ory Tx buf fer di rect ory Addr ess - Tx li nk point er 0 31 0 31 0 Tx buf fer de sciptor 0 Tx buf fer de sciptor 1 Tx buf fer de sciptor 2 Tx buf fer de sciptor 3 Tx buf fer de sciptor 4 Tx buf fer de sciptor N T x l[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 249 4.5.1.1 Packet des criptor A packet des criptor contain s two words shown a s Figure 4-10. It s address i s word al igned. Figure 4-10. T x Packet De scriptor -Tx packet descriptor 31 0 16 15 Attribute CPCS-UU CPI 8 7 16 GFC 28 CLPM 27 PTI 26 24 23 19 18 17 20 IM C10 A[...]

CHAPTER 4 ATM CELL PROCESSOR 250 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.5.1.2 Tx buffer direct ory Tx buffer dire ctory c ontains some buff er descr iptor s, up to 255 , and a link p ointer. It s addre ss is word aligned. T he end of buf fer directory must b e a link p ointer. Buf fer des criptors mu st be rea d and serv ed from the top[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 251 Figure 4-12. Rx Pool Stru cture R x b u ffe r d e s c . Dat a B u ffe r Dat a B u ffe r Dat a B u ffe r Dat a B u ffe r Dat a B u ffe r Dat a B u ffe r Rx li nk poi n t er Dat a B u ffe r Dat a B u ffe r Dat a B u ffe r R x b u ffe r d irec to ry Rx pool0 descr i pt or[...]

CHAPTER 4 ATM CELL PROCESSOR 252 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 4-13. Rx Pool Descr iptor/Rx Buffer Direct ory/Rx Buffer D escriptor/R x Link Pointer -Rx buffer directory Rx buffer directory Address -Rx link pointer Attribute 31 0 31 0 Rx buffer desciptor 0 Rx buffer desciptor 1 Rx buffer desciptor 2 Rx buffer desciptor 3 R[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 253 4.5.2.1 Rx pool descri ptor A pool descri ptor con tains tw o word s shown a s Figure 4-1 4. Its ad dress is word al igned. Figure 4-14. Rx Pool Descr iptor - R x pool descr i p t or 31 30 0 16 15 R x bu ff er di r ectory A ddress Rem ai ni ng # of di r. i n t he pool [...]

CHAPTER 4 ATM CELL PROCESSOR 254 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 4-15. Rx Buffer Des criptor/ Link Poi nter -Rx link pointer -Rx buffer descriptor 31 30 0 16 15 Attribute Size L Buffer Address 31 0 1 31 30 0 16 15 Reserved 0 Directory Address 31 0 0 4.5.2.4 Rx data buffer Rx Data buffer contai ns act ual rec eived cel l data[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 255 4.6 Initialization This ATM Cell Proce ssor is in itiali zed by firm ware that is bas ed RISC i nstruct ion. 4.6.1 Before starting R ISC core RISC Core ha s 1 MB of Instruc tion sp ace and 8 KB of phys ical I nstruct ion RAM an d 8 KB of i nstruct ion ca che. The Instr[...]

CHAPTER 4 ATM CELL PROCESSOR 256 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.6.2 After RISC core’s F/W is star ting RISC C ore st arts its operatio n from addre ss xx 00_000 0H. When it starts f etchin g an in structio n locat ed in a ddress xx00_0000H , a de dicated H /W will s top RISC C ore and w ill copy a blo ck of i nstruct ions. Th [...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 257 4.7 Commands Here, basi c comm ands use d in AAL-5 opera tion are descri bed. O ther commands used in AAL-2, OAM and cell switchin g function s are de scribed in µ µ µ µ PD98502 Appli cation Note (to be planne d) . ATM Cell Proces sor provide s V R 4120A w ith the [...]

CHAPTER 4 ATM CELL PROCESSOR 258 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.7.1 Set_Link_Rate command This com mand is used to set the lin k rate of ATM PHY inter face. Aft er initi alizing ATM Cell Proc essor, thi s command ha s to be issue d once, before a ny packet i s tran smitted. Figure 4-18. S et_Link_Rate Comm and [Set_Li nk_Rate co[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 259 4.7.3 Close_Channel command The Close _Channel command is use d to close a send or recei ve channel. Upo n accepti ng this command, A TM Cell Processor retur ns the VC t able to VC T able po ol. The indicat ion that ATM Cell Pro cesso r returns for this command has the[...]

CHAPTER 4 ATM CELL PROCESSOR 260 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.7.4 Tx_Ready c ommand The Tx_Rea dy com mand is u sed by the V R 412 0A to noti fy ATM Cel l Processor that a transmit packet has been added for a specifie d chan nel (a new packet descr iptor ha s been se t in s ystem m emory queue) . Upon receiving thi s command, [...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 261 4.7.5 Add_Buffers com mand The Add_Buffers comm and is u sed to add unused buffer d irectorie s to a single r eceiv e free buf fer pool. In this command, when ATM Cell Processor detects some errors, it write s E bit i n A_CMR. Thi s comm and has the following format: F[...]

CHAPTER 4 ATM CELL PROCESSOR 262 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.7.6 Indirect_Acce ss comm and The Indirect_A cces s command is us ed to perf orm read/w rite acces s to Wor k RAM. Figure 4-23. I ndirect _Access Co mmand [Indirect _Access c ommand] CMR 0R / W B3 B2 B1 B0 Addre ss 0 31 29 28 27 26 25 24 23 210 CER Data 31 0 Indirec[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 263 Figure 4-24. W ork RAM Usage P a c k e t In f o S tru c tu r e Pool (4 W ords x 64) Free Bl ock Pool /fo r V C T a b le/ (16 W ord s x 6 4) Tem porar y Dat a 4096 by t es 1024 by t es 64 by te s Fl ow T abl e Pool (4 W ords x 64) 1024 by t es Pool D escri pt or (2 W o [...]

CHAPTER 4 ATM CELL PROCESSOR 264 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.8.2.1 Transmissio n procedure (a) Setting transmitti ng data Before transmit ting a p acket, V R 4 120A pl aces a pa cket dat a to be sent in system memory and set s the packet descriptor. (b) Opening the se nd channel If V R 4120A ne eds a n ew channe l for tran sm[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 265 4.8.2.2 Transmit que ue Tx_Ready command has to be issu ed in or der to tran smit a packe t. However, V R 4120A doesn’t h ave to w ait Tx indication befor e issuing next T x_Ready comm and for th e same VC . When V R 4120A iss ues Tx_Read y comm and before compl etin[...]

CHAPTER 4 ATM CELL PROCESSOR 266 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M (2) Packet descriptor Figure 4-27. Tr ansmit Q ueue Pack et Descriptor 10 ENC CLPM PTI GFC IM C 1 0 AAL MB CPCS-UU CPI 31 30 29 28 27 26 24 23 20 19 18 17 16 15 8 7 0 Buff er Directory Address 31 0 Encapsulati on mode is indic ated. 1 LLC encap sulation ENC 0 No encap[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 267 (3) Tx VC table Figure 4-28. T x VC Table Word 0 V ENC CLPM PTI GFC IM C 1 0 AAL M B CPSS- UU CPI 31 30 29 28 27 26 24 23 20 19 18 17 16 15 8 7 0 Word 1 L 0 PRIORIT Y VPI/VCI 31 30 27 26 24 23 0 Word 2 No. OF B YTES TRANS MITTED IN THIS PAC KET REMAINI NG BYTES IN CURR[...]

CHAPTER 4 ATM CELL PROCESSOR 268 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Word0 Identica l to the content s of Word0 in the pa cket de scriptor in sy stem mem ory. The initial value mus t be al l zeros. ATM Cell copie s the Wor d0 in the pack et descr iptor into this fie ld. L This bit is used i nternall y for SAR pro cessi ng. The init ial[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 269 (2) Raw cell tran smission When host sends the non AAL-5 tr affic p acket wh ich i s not OAM F5 cell, hos t sets “AAL” bit in the packet descriptor to a 0 and “P TI” field “0 xx” whi ch indic ates user da ta. In th is ca se, ATM Cell Pro cessor doesn’t ca[...]

CHAPTER 4 ATM CELL PROCESSOR 270 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.8.2.6 LLC encapsul ation If LLC enca psulation is indica ted in Tx VC ta ble, ATM Cell Proc essor adds the LLC h eader to t he top o f the IP packet. ATM Ce ll Proce ssor always encapsul ates CPC S-PDU as Intern et IP PDU. Figure 4-31. L LC Encapsulation For mat LLC[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 271 (1) Rx VC table Figure 4-32. Re ceive VC Tab le Word 0 CL P BF A 0 RID DD DP 0 CI OD A /R MB POO L No. UINFO 31 30 29 28 27 26 25 24 23 22 21 20 16 15 0 Word 1 T1 TIM E STAMP MAX. No. OF BYTE S 31 16 15 0 Word 2 REMAINING WORDS IN CURRE NT BUFFER CURRENT COUNT OF BYTES[...]

CHAPTER 4 ATM CELL PROCESSOR 272 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M CLP S et to a 1 i f the CLP i n the header of at least one cel l of the packets being received i s equal to a 1. BFA Set to a 1 if the free buff er assigne d to this VC e xists. RID Set to a 1 i f an error occurs whil e a pac ket is being rece ived. Then, the subseque[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 273 Figure 4-33. Raw Cell Data F ormat WORD0 CELL HEADER WORD 1 BYTE2 BYTE1 BYT E0 HEC : : : WORD 12 BYTE46 BYTE4 5 BYTE4 4 BYTE43 WORD 13 UINFO 0 BYTE47 WORD 14 TIME ST AMP WORD15 1 V C NUMBER CE 0 Cell Header Header of the cell except HEC. HEC HEC field patt ern of the c[...]

CHAPTER 4 ATM CELL PROCESSOR 274 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 4-34. Re ceive Ind ication Form at UINFO PACKE T SIZE 31 16 15 0 TIME ST AMP 31 0 PACKE T START A DDRESS 31 0 1 VC Number ERR CI CL P 0 ERR STA TUS 0 POOL No. 31 30 16 15 14 13 12 11 8 7 5 4 0 UINFO Pattern set by the host in the UINFO f ield in the VC tabl e P[...]

CHAPTER 4 ATM CELL PROCESSOR Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 275 (2) Max No. of bytes violation This error oc curs if t he last cell o f a pac ket has not been re ceived when the number of cells re ceive d has re ached the user-spe cified "Max. No. of byte s" Whe n the ne xt cel l is recei ved, the RID bit is set and a rec[...]

CHAPTER 4 ATM CELL PROCESSOR 276 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 4.8.4 Mailbox ATM Cell Pro cessor use s mailbo xes as ring buf fers in sy stem mem ory. The structur e of a mailbox and the defined addresses ar e as fo llows. Mailbox st art addre ss (A_M SA[3:0]) :The start addr ess of t he mailbo x Mailbox bo ttom addres s (A_MBA[3[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 277 CHAPTER 5 ETHERNET CONTROLLER 5.1 Overview This secti on des cribes Et hernet Contr oller b lock. T his Etherne t Co ntroller block compri ses of a 10/100 Mbps Ethernet MA C (Media A ccess C ontrol), d ata tran smit/recei ve FIFO s, DMA and internal bu s interf ace. The µ PD98502 implemen ts 2-ch[...]

CHAPTER 5 E THERNET CONTROLLER 278 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 5-1. Bloc k Diagr am of Ethernet Contr oller TPO+ TPO– TPI+ TPI– T ransceiv er MII I/O buffer MAC Core Ether net Cont roll er Block FIFO Cont. Tx FIFO Rx FIFO DM A Master I/F Slave I/F IBUS µ µ µ µ PD985 02[...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 279 5.2 Registers Registers of this blo ck are categor ized followi ng four categorie s as shown in Table 5-1 . V R 4120A contr ols follow ing reg ister s. The µ PD98502 has 2- channel Ethernet Co ntroller, #1 contr oller ’s base addr ess is 1000_2 000H, #2 contr olle[...]

CHAPTER 5 E THERNET CONTROLLER 280 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Offset Address Register Name R/W Access D escrip tion 1000_m0A8H: 1000_m0C4H N/A - - Reserved for futu re u se 1000_m0C8H En_AFR R/W W Addres s Filtering Register 1000_m0CCH En_HT1 R/W W Hash Table Register 1 1000_m0D0H En_HT2 R/W W Hash Table Register 2 1000_m0D4H:[...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 281 Table 5-3. St atistics Count er Register Map Offset Address Register Name R/W Access De scrip tion 1000_m140H En_RB YT R/W W Rec eive Byte Counter 1000_m144H En_RP KT R/W W Rec eive Packet Count er 1000_m148H En_RFCS R/W W Receive FCS Error Counter 1000_m14CH En_RMCA[...]

CHAPTER 5 E THERNET CONTROLLER 282 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Offset Address Register Name R/W Access D escrip tion 1000_m1C4H En_TPCT R/W W T ransmit Pack et Counter 1000_m1C8H En_TF CS R/W W Transm it CRC Error Packet Counter 1000_m1CCH En_TMCA R/W W Trans mit Multicast Packet Counter 1000_m1D0H En_TBCA R/W W Trans mit Broad[...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 283 5.2.1.3 DMA and FIFO manage ment registers These regist ers con trol to tra nsfer re ceive and tr an smit data by i nternal DM AC of this block. Table 5-4. DMA and FIFO Manag ement Regist ers Map Offset Address Register Name R/W Access De scrip tion 1000_m200H En_TXC[...]

CHAPTER 5 E THERNET CONTROLLER 284 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 5.2.1.4 Interrupt and configurati on r egisters These regist er contro l interrupt o ccur an d confi guration for this block. Table 5-5. Interrupt a nd Configuration R egisters M ap Offset Address Register Name R/W Access De scrip tion 1000_m234H En_CCR R/W W Config[...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 285 5.2.2 En_MACC1 (MAC Configuration Register 1) Bits Field R/W Default Descrip tion 31:12 Reserved R/W 0 Res erved for future use. Write 0s. 11 TXFC R/W 0 Trans mit flow c ontrol enabl e: Setting this bit to a ‘1’ enables to transmit t he pause control frame. 10 RX[...]

CHAPTER 5 E THERNET CONTROLLER 286 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 5.2.3 En_MACC2 (MAC Configuration Register 2) Bits Field R/W Default Descrip tion 31:11 Reserved R/W 0 Res erved for future use. Write 0s. 10 MCRS T R/W 0 MAC Control Bl ock software res et: Settin g th is bit to a ‘1’ for ces M AC Co ntro l Blo ck to a s oftw a[...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 287 5.2.6 En_CLRT (Collision R e gister) Bits Field R/W Default Descrip tion 31:14 Reserved R/W 0 Res erved for future use. Write 0s. 13:8 LCOL R/W 38H Late collision window: This field sets collision wi ndow size. The formula for the collisi on window size is: collisi o[...]

CHAPTER 5 E THERNET CONTROLLER 288 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 5.2.11 En_PTVR (Pause Ti mer Valu e Rea d Register ) Bits Field R/W Default Descrip tion 31:16 Reserved R 0 Reserved for future use. 15:0 PTCT R 0 Pause timer counter: This field indicates the current paus e timer value. 5.2.12 En_VLTP (VLAN Type Re gist er) Bits Fi[...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 289 5.2.15 En_MADR (MII Address Reg ister) Bits Field R/W Default Descrip tion 31:13 Reserved R/W 0 Res erved for future use. Write 0s. 12:8 FIAD R/W 0 MI I PHY address: This field sets PHY address to be selected duri ng the management access. 7:5 Reserv ed R/W 0 Reserve[...]

CHAPTER 5 E THERNET CONTROLLER 290 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 5.2.19 En_AFR (Addres s Filtering R eg ister) Bits Field R/W Default Descrip tion 31:4 Reserved R/W 0 Res erved for future use. Write 0s. 3 PRO R/ W 0 Promisc uous mode: When this bit is set to a ‘1’, all receive packets are accept ed. Please refer to 5.3.6 . 2 [...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 291 5.2.22 En_CAR1 (Carry Register 1) The bits of this r egister indicate that an overflow event has o ccurr ed in st atistics counter s. Each bit corr espond s to a counter, and the bit is set to a ‘1 ’ when the corr esponding statis tics counter overf low even t oc[...]

CHAPTER 5 E THERNET CONTROLLER 292 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 5.2.23 En_CAR2 (Carry Register 2) The bits of this r egister indicate that an overflow event has o ccurr ed in st atistics counter s. Each bit corr espond s to a counter, and the bit is set to a ‘1 ’ when the corr esponding statis tics counter overf low even t o[...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 293 5.2.24 En_CAM1 (Car ry Register 1 M ask Regis ter) This regi ster mask s the In terrupt tha t is generat ed fr om the se tting of the b its in t he En_CAR1 reg ister. Each mask b it can be enab led ind ependen tly. Bits Field R/W Default Descrip tion 31:16 Reserved R[...]

CHAPTER 5 E THERNET CONTROLLER 294 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 5.2.25 En_CAM2 (Car ry Register 2 M ask Regis ter) This regi ster mask s the In terrupt tha t is generat ed fr om the se tting of the b its in t he En_CAR2 reg ister. Each mask b it can be enab led ind ependen tly. Bits Field R/W Default Descrip tion 31 M2X D R/ W 0[...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 295 5.2.27 En_TXFCR (Transmit FIFO C ontrol Reg ister) Bits Field R/W Default Descrip tion 31:16 TPT V R/W FFFFH Transmit Pause Timer Value : 15:10 TX_DRTH R/W 10H Transmit Drain Threshold Level: This threshold is enable to the transmit data to the MAC Control Block f or[...]

CHAPTER 5 E THERNET CONTROLLER 296 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 5.2.28 En_TXDPR (Transmit De scri ptor Poi nter) Bits Field R/W Default Descrip tion 31:2 XMTDP R/W 0 Transmit Desc riptor Please see the Section 5.3.4 1:0 Reserv ed R/W 0 Reserved for future use. Write 0s. 5.2.29 En_RXCR (Recei ve Configu r ation Regist er) Bits Fi[...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 297 5.2.30 En_RXFCR (Recei ve FIFO C ontrol Register) Bits Field R/W Default Descrip tion 31:26 UWM [7:2] R/W 30H Upper Water Mark: This pointer is used with Auto Flow Control Enable bit in En_TXCR. When the receiving data fil l level exceeds this pointer, the transmit m[...]

CHAPTER 5 E THERNET CONTROLLER 298 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 5.2.32 En_RXPDR (Recei ve Pool D escri ptor Pointer) Bits Field R/W Default Descrip tion 31 Reserv ed R/ W 0 Reserv ed for future use. Write a 0. 30:28 AL[2:0 ] R/W 0 Alert Le vel 27:16 Reserved R/W 0 Res erved for future use. Write 0s. 15:0 RNOD [15:0] R/W 0 Remai [...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 299 5.2.35 En_MSR (Mask Serv es Regi st er) Each interr upt sour ce is ma skable . En_MSR reg ister s hows w hich in terrupts are enab le. Default va lue is all “0” wh ich m eans all in terrupt s ources are disa ble. Bits Field R/W Default Descrip tion 31:16 Reserved[...]

CHAPTER 5 E THERNET CONTROLLER 300 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 5.3 Operation 5.3.1 Initializat ion After a power on re set or a software re set, V R 4120A ha s to se t the follow ing regist ers: i) Interrupt Mask Regist ers ii) Configuration Re gisters iii) MII Management R egister s iv) Pool/Buffer De scriptor Regi sters 5.3.2[...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 301 5.3.3 Buffer descriptor format The Transmit D escript or format is show n in Figure 5-5 and the des criptio n is show n in Table 5-6. Figure 5-5. Tran smit D escriptor For mat 31 16 15 0 Word 0 Attribute Size Word 1 Buffer Address Po inter Table 5-6. Attrib ute for T[...]

CHAPTER 5 E THERNET CONTROLLER 302 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table 5-7. Attrib ute for Receiv e Descriptor Attribu te & Si ze Bit N ame Statu s 31 L Last Descript or 30 D/L Data Buffer / Link Point er 29 OWN Owner bit 1:Ethernet Cont roller 0: V R 4120A Ethernet Controll er sets this bit after it began to transfer data in[...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 303 Short frames are automatic ally p added by th e transmit logic if PADEN bit in E n_MACC1 regist er is set. If the transmit frame length exce eds 1518 bytes, Eth ernet C ontroller will assert an interr upt. However, th e entire frame will be transmitte d (no trun cati[...]

CHAPTER 5 E THERNET CONTROLLER 304 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 5-7. Tran smit Pro cedure V R 4120A Ethernet Controller External PHY Device Initialize Registers Initialize Auto Negotiation Link Configuration Prepare Buffer Descriptors and T ransmit Data mem Set T ransmit Descript or address Set XMDP Set T ransmit Enable S[...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 305 Operation flow for tr ansmit pac ket i) Prepares transmit data in data buffer ii) Initialize s regist ers (XM DP, TX E) iii) Reads buffer de scriptor for tr ansmiss ion from SDRAM iv) Reads tran smit data from data buffer by us ing m aster DMA bu rst oper ation v) Wa[...]

CHAPTER 5 E THERNET CONTROLLER 306 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M When the re ceive fram e is com plete, Eth ernet Contr oller se ts th e L-bit in the Re ceive Descript or, writes the fram e status bits into the Receiv e Descriptor, and set s the O WN-bit. Ether net C ontroller gen erates a maskable interrup t, indicating t hat a [...]

CHAPTER 5 E THERNET CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 307 Operation flow for r eceive pa cket i) Prepares the recei ve buffer descriptor s ii) Initialize s regist ers (R XVDP, RXE) iii) Reads the rece ive buf fer des criptor iv) Waits for ex ceeding of receive drain thr eshold (RXDRTH ) v) Writes recei ve data t o data b uf[...]

CHAPTER 5 E THERNET CONTROLLER 308 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M (3) Broadcast ad dress filtering All of receiv ed pac kets with broadcast destin ation addre ss are recei ved when ABC bit in E n_AFR re gister is set to a ‘1’. (4) Promiscuous mod e Setting PRO bit in En_AFR register to a ‘1’ c aused all of rece ive d packe[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 309 CHAPTER 6 USB CONTROLLER 6.1 Overview The USB Contr oller h andles the data communi cation t hrough U SB. The f ollowing lists the feat ures of USB Controller. 6.1.1 Features • Conforms to U niversal S erial B us Spe cificat ion Rev 1.1 • Supports operat ion co nforming to t he USB Comm unicat[...]

CHAPTER 6 USB CONTROLLER 310 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.1.2 Internal bloc k diagram USB Controller i nternal block d iagram is as sh own below. Figure 6-1. USB Controller Intern al Configuration SI E EPC IB U S D+ D- USB BUS I / F R x FI FO Ma s t er I/F Sl ave I/F I/O Bu f sl av e decode r Tx FI FO DMAC MCONT USB CONTROLL E[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 311 6.2 Registers This secti on expl ains th e mapping of thos e regist ers that can b e acces sed from IBUS. USB base addres s is 1000_1000H 6.2.1 Register map Offset Address Regist er Name R/W Acc ess Descripti on 1000_1000H U_GMR R/W W/H/ B USB General Mode Register 1000_10[...]

CHAPTER 6 USB CONTROLLER 312 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 2. All internal re gisters are 32-b it word-aligne d regist ers. 3. The bur st acce ss to the i nte rn al re gis ter is p rohi bit ed. If such burst acce ss has been occu rred, IR ERR bit in N SR is s et and NM I will as sert to CPU . 4. Read acce ss to t he reser ved are[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 313 6.2.2 U_GMR (USB General Mode Register) This r egister is used for setting the op eration of USB Contr oller . The l ow-order si xteen b its excep t for RR b it can be written onl y when the devi ce is b eing in itialized. If th e values o f these bits are chang ed while t[...]

CHAPTER 6 USB CONTROLLER 314 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.2.4 U_GSR1 (USB Gener al Status Reg ister 1) This regi ster ind icates the current status of USB Control ler. Bits Field R/ W Default Description 31 GSR2 RC 0 If some bits of General Status Register 2 are set to ‘1’s and the corresponding bit s in Interrupt Mask Reg[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 315 Bits Field R/ W Default Description 8 EP1FU RC 0 EP1 FIFO Err or: Bit that indicates that an underrun has occurred f or the FIFO of EndPoint1 (Isochronous IN). When the FIFO empties while EndPoint1 is performi ng a transa ction, thi s bit is set to a ‘1’. This bit is r[...]

CHAPTER 6 USB CONTROLLER 316 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.2.5 U_IMR1 (USB Interrupt Mask Register 1) This regi ster is used to m ask int errupts. When a bit in this reg ister i s set to a ‘ 1’ and t he corre sponding bit i n the USB G eneral Sta tus Regi ster 1 (Address: 10H) is set to a ‘1’, a n interru pt is issu ed.[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 317 Bits Field R/ W Default Description 4 EP3TF R/W 0 EP3 Tx Finished: 1 = unmask. 0 = mask. 3 EP 2RF R/W 0 EP2 Rx Finished: 1 = unmask. 0 = mask. 2 EP1TF R/W 0 EP1 Tx Finished: 1 = unmask. 0 = mask. 1 EP 0RF R/W 0 EP0 Rx Finished: 1 = unmask. 0 = mask. 0 EP0TF R/W 0 EP0 Tx Fi[...]

CHAPTER 6 USB CONTROLLER 318 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.2.6 U_GSR2 (USB G eneral Status R egister 2) This regi ster ind icates the current status of USB Cont roller. Re ading th is regi ster cl ears al l bits in this r egister . Bits Field R/ W Default Description 31:21 Reserved R 0 Reserved for future use 21 FW RC 0 Frame N[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 319 6.2.7 U_IMR2 (USB Interrupt Mask Register 2) This regi ster is used to m ask int errupts. When a bit in this reg ister i s set to a ‘ 1’ and t he corre sponding bit i n the USB G eneral Sta tus Regi ster 2 (Address: 18H) is set to a ‘1’, GS R2 bit in the U_GSR1 wil[...]

CHAPTER 6 USB CONTROLLER 320 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.2.8 U_EP0CR (USB EP0 Control Register) This regi ster is us ed for s etting th e operation of EndPoint 0. If the value in the MAXP field is rewritte n during transm itting or receiv ing oper ation, t he operat ion of USB Cont roller may become un predictabl e. Therefor [...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 321 6.2.9 U_EP1CR (USB EP1 Control Register) This regi ster is us ed for s etting th e operation of EndPoint 1. If the value in the M AXP field is rewr itten dur ing tran smittin g operat ion, the operation of USB Controller may become unpredi ctable. There fore, the MAXP can [...]

CHAPTER 6 USB CONTROLLER 322 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.2.11 U_EP3CR (USB EP3 Control R egister) This regi ster is us ed for s etting th e operation of EndPoint 3. If the value in the M AXP field is rewr itten dur ing tran smittin g operat ion, the operation of USB Controller may become unpredi ctable. There fore, the MAXP c[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 323 6.2.12 U_EP4CR (USB EP4 Control R egister) This regi ster is us ed for s etting th e operation of EndPoint 4. If the value in the M AXP field is rewr itten dur ing r eceiving opera tion, t he operation of USB Controller may becom e unpredictabl e. Theref ore, the M AXP can[...]

CHAPTER 6 USB CONTROLLER 324 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.2.13 U_EP5CR (USB EP5 Control R egister) This regi ster is us ed for s etting th e operation of EndPoint 5. If the value in the M AXP field is rewr itten dur ing tran smittin g operat ion, the operation of USB Controller may become unpredi ctable. There fore, the MAXP c[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 325 6.2.15 U_CMR (USB Command Register) This regi ster is us ed for i ssuing Tx reque st or ad ding Rx Bu ffer Dir ectorie s to Poo l. The V R 4120A writ es com mands into th is regi ster. Whenever B bit (B it 31) i s set, t he value wil l not chang e even i f th e V R 4120A w[...]

CHAPTER 6 USB CONTROLLER 326 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.2.17 U_TEPSR (USB Tx EndPoint Status Regi ster) This regi ster is us ed for in dicate the stat us of th e EndPoint bein g use d for data tran smitti ng. Bits Field R/ W Default Description 31:26 Reserved R 0 Reserved for future use 25:24 EP5TS R 0 EP5 Tx Stat us: Regist[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 327 6.2.19 U_RP0AR (USB Rx Pool0 Ad dress R e gister) This regi ster ind icates the start ad dress of Buffer Dire ctory w hi ch is curr ently u sed. The way to set up Rx Pool i s descr ibed at S ection 6 .6.3 Rece ive p ool setting s . Bits Field R/ W Default Description 31:0 [...]

CHAPTER 6 USB CONTROLLER 328 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.2.22 U_RP2IR (USB Rx Pool 2 Infor mation R egister) This regi ster ind icates the inform ation of R eceive Pool2. The V R 4120A wr ites to this r egister only wh en the d evice is be ing i nitialize d. Bits Field R/ W Default Description 31 Reserv ed R/ W 0 Reserv ed fo[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 329 6.2.27 U_TMWA (USB Tx M ailBox Wr it e Address Reg ister) Bits Field R/ W Default Description 31:0 Address R 0 Regist er that indicates the address i n the transmit MailBox area to which USB Con trolle r will write nex t time . 6.2.28 U_RMSA (USB R x MailBox St art Addres [...]

CHAPTER 6 USB CONTROLLER 330 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.3 USB Attach ment Seq uenc e This secti on des cribes t he sequ ence th at is foll owed wh en the µ PD98 502 is attached to a USB hub. Figure 6-2. USB Attach ment Sequence V R 4120A USB C ont rol l er Connect t o a H U B Host PC reset s t he Port that t he new devi ce [...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 331 6.4 Initialization After USB Controll er has b een rese t, the V R 41 20A must set se ver al USB Control ler regi sters. The initi alizat ion sequence i s list ed below . (1) A desired mode i s set into t he USB Gen eral Mode R egister. (2) The receive pools are p laced in[...]

CHAPTER 6 USB CONTROLLER 332 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.4.1 Receive poo l settings For details of the rec eive p ool setting s, see S ection 6. 6.3 Rec eive p ool setting s . 6.4.2 Transmit/rece ive MailBo x set tings After USB Controll er transm its a d ata segme nt, it in dicate s the statu s by writin g a tran smit indi c[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 333 Figure 6-3. Mailbo x Configuration 31 0 U_TMSA(U_RMSA) U_TMWA(U_RMWA) U_TMBA(U_RMBA) U_TMRA(U_RMRA) When USB Control ler wri tes an ind ication, th e write poi nter (U_TM WA or U _RMWA) i s incremen ted. Ever y time that USB Con troller wr ites an indicat ion, it also s et[...]

CHAPTER 6 USB CONTROLLER 334 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.5 Data Transmit Function This secti on expl ains USB Con troller' s data tran smit fu nction. 6.5.1 Overview of tra nsmit pr ocessing USB Controller d ivide s the data s egment s in syst em m emory, in to USB pa ckets, the n transm its th em to the H ost PC. The V [...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 335 Figure 6-5. Tx Buffer Confi guration Buffer descriptor Buffer descriptor Buffer descriptor Data Buffer Data Buffer Buffer desc.(L=1) Data Buffer Data Buffer Link pointer Buffer descriptor Data Buffer Tx Packet Buffer Directory A transmit pa cket i s configured by bre aking[...]

CHAPTER 6 USB CONTROLLER 336 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 6-6. Confi guration of Transmit Buff er Director y -T x B u ffer D irec to ry Dir ector y Addr ess -Tx Li nk Poi nter Res er ve d 31 0 0 B u ffe r D e s c ripto r N B u ffe r D e s c ripto r 4 B u ffe r D e s c ripto r 3 B u ffe r D e s c ripto r 2 B u ffe r D e s [...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 337 6.5.3 Data transmit m odes USB Controller supports two transmit m odes. These mod es diff er only in whether a zero-leng th USB packet is transmitted after the last USB packe t of a data s egment. In a ll other aspec ts, the y are identi cal. The transm it mode is switched[...]

CHAPTER 6 USB CONTROLLER 338 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.5.4 V R 4120A processing at data tr ansmitting This secti on expl ains the pr ocessing perform ed by the V R 4120 A w hen tran smitting data. Figure 6-7. V R 41 20A Proc essing at Da ta Transmitti ng Prepare Tx dat a in t he memory Reads U SB Tx EndPoint St atus Regist [...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 339 (1) First, the V R 4120A prep ares the data to be transm itted in sy stem mem ory. (2) The V R 4120A reads the USB Comm and Register . (3) The V R 4120A che cks whether t he Busy bit of th e USB Comm and Regis ter is set. I f the Bus y bit is s et, it indicates t hat USB C[...]

CHAPTER 6 USB CONTROLLER 340 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 6-9. Tran smit Status R egister 31 15 EP3 0 16 23 8 EP5 EP0 7 EP1 24 USB Tx EndPoint Status Register (48H) Corresponding to each EndPoint 00: Idle 01: Sending one data 10: Sending two data (Busy)[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 341 6.5.5 USB controller processing a t dat a transmitting This secti on prese nts al l of the pr oces sing perf ormed by USB Contr oller at data tra nsmitting. Figure 6-10. US B Control ler Transmit O peration F low Char t Tx c om m and i s set Copies t he com m and t o i nt [...]

CHAPTER 6 USB CONTROLLER 342 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Numbers (1) to (15) do not ind icate the or der in whi ch USB Cont roller m ust p erform proce ssing. Inst ead, the se numbers corr espond to those in the f ollowin g expla nation. (1) USB Controller starts tra nsmit proc essin g upon rece iving a tran smit comm and from [...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 343 6.5.6 Tx indicati on For every data segment to be transm itted, USB Contr oller writ es a Tx indica tion in to the Tx M ailBox. Af ter writ ing a Tx indicati on, USB Co ntroller set s the tra nsmit completio n bit of USB Gen eral Statu s Regis ter1 to 1 and, provided it is[...]

CHAPTER 6 USB CONTROLLER 344 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.6 Data Receive Function This secti on expl ains USB Con troller' s data r eceive fu nction. 6.6.1 Overview of re ceive proc essi ng USB Controller re ceives USB pa ckets from the U SB, stores th em i nto system memory, and then assembles a single data segm ent. The[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 345 6.6.2 Rx Buffer configur ation Data recei ved from the USB is stor ed into a recei ve pool in syst em m emory. USB Controller u ses thr ee receive pools. The con figurati on of the recei ve pools i s shown below. Figure 6-13. Re ceive Buffer Configuratio n B u ffe r d e s [...]

CHAPTER 6 USB CONTROLLER 346 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 6-14. Receiv e Descriptor Configuration -R x B uffer D irec tory Buff er Dir ector y A ddress -Rx Li nk Poi nt er 0 31 0 | B u ffe r D e s c ipto r N B u ffe r D e s c ipto r 4 B u ffe r D e s c ipto r 3 B u ffe r D e s c ipto r 2 B u ffe r D e s c ipto r 1 B u ffe[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 347 6.6.3 Receive poo l settings USB Controller u ses three re ceive pools. Pool0 For EndPoint0 (Control) and EndPoint6 (I nterrupt) Pool1 For EndPoint2 (Isochronous) Pool2 For EndPoint4 (Bulk) The data in ea ch of th ese three pools i s writt en into t he corresp ondi ng regi[...]

CHAPTER 6 USB CONTROLLER 348 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M (a) If any unuse d Buffer Dire ctories remain in the poo l (when the R NOD field in t he Pool I nformation Reg ister i s set to grat er than 0) , USB Controll er adds t he num ber in the N OD f ield of the command to the RNOD field of the Pool Information Register. (b) Wh[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 349 (1) Reception in En dPoint0, EndPoint 6 Same proces sing is e xecuted w ithout relat ions in receive m ode in EndPo int0, EndPo int6 every time. Figure 6-16. Dat a Receiving in En dPoint0, EndPoint 6 D0 µ PD98502 Bu f f er Di r e ct or y D1 D2 D3 D0 D1 D2 R x In di ca tio[...]

CHAPTER 6 USB CONTROLLER 350 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M (3) EndPoint2, EndPoint 4, assemble mode The proce ssing in En dPoint2, E ndPoint4 receive As semble m ode is exp lained bel ow. Figure 6-18. En dPoint2, EndPoint4 Rec eive Asse mble Mode D0 µ PD98502 Bu f f er Di r e ct or y D1 D2 D1 D2 D2 R x In di ca tio n D0 D0 D1 D3[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 351 6.6.5 V R 4120A re ceive proc essing This secti on expl ains th e proce ssing that the V R 4120A must perform whe n data i s bein g received. Figure 6-20. V R 4 120A R eceive Proc essing S e ts P o o l initializatio n Reads U SB Gen eral Stat us Regi st er ( I f necessar y[...]

CHAPTER 6 USB CONTROLLER 352 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.6.6 USB controller r ecei ve proce ssing This secti on prese nts al l of the pr ocessing perform ed by USB Contr oller at data recei ving. 6.6.6.1 Normal mode The follow ing figur e illustrat es the re ceive operati ons perf ormed b y USB Contr oller in N ormal Mod e. F[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 353 Numbers (1) to (9) do not indicat e the ord er in whi ch USB Control ler must perform processi ng. Instead, the se numbers corr espond to those in the f ollowin g expla nation. (1) USB Controller is in the st atus wher e it waits to rece ive dat a (USB Pa ckets) fr om the [...]

CHAPTER 6 USB CONTROLLER 354 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.6.6.2 Assemble m ode The follow ing figur e illu strates t he receive operati ons perf orme d by USB Contr oller i n Assemble Mode. Figure 6-22. US B Control ler Receive Operation s (Assemble Mode) St or es t he data f r om U SB t o rece ive F IFO Receiv es dat a fro m [...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 355 Numbers (1) to (11) do not ind icate t he order in w hich USB Co ntro ller must p erform proce ssing. Inst ead, the se numbers corr espond to those in the f ollowin g expla nation. (1) USB Controller is in the st atus wher e it waits to rece ive dat a (USB Pa ckets) fr om [...]

CHAPTER 6 USB CONTROLLER 356 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.6.6.3 Separate mod e The follow ing figur e illustrat es the re ceive operati ons perf ormed b y USB Contr oller in Sep arate Mo de. Figure 6-23. US B Control ler Receive Operation S equence (S eparate M ode) St or es t he data f rom USB to rece ive F IFO Receiv es dat [...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 357 Numbers (1) to (12) do not ind icate the or der in whi ch USB Con troller m ust p erform proce ssing. Inst ead, the se numbers corr espond to those in the f ollowin g expla nation. (1) USB Controller is in the st atus wher e it waits to rece ive dat a (USB Pa ckets) fr om [...]

CHAPTER 6 USB CONTROLLER 358 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.6.7 Detection of error s on USB USB Controller h as some fu nction s which detect some err ors on t he USB. Errors shown in figur e below ar e related to Isochro nous EndPo int and SOF pa cket. Figure 6-24. USB Timing Errors SOF SOF ISO. ISO. SOF ISO. SOF ISO. SOF ISO. [...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 359 data to USB an d will set EP1ND b it (Bit 2) i n USB General Status Register 2. • Extra Token on EndPoint1: If IN TOKEN packet for En dPoint2 comes whic h between two SOFs, USB Controller wil l set EP1ET bit (Bit 3) in USB General Statu s Regist er 2. In th is case, U SB[...]

CHAPTER 6 USB CONTROLLER 360 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.6.8 Rx data corruption on I sochron ous EndPoint On Isochron ous Rx En dPoint (EP2), one data pa cket c omes pe r one fr ame. If any Isochr onous data pa cket do esn’t c ome betw een two SOF pack et, it is assumed that Isochr onous data is corrupted. In the case of co[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 361 Figure 6-25. E xample of Buff ers In cluding Cor rupted Data B u ffe r d es c riptor B u ffe r d es c riptor B u ffe r d es c riptor V a lid Dat a V a lid Dat a V a lid Dat a V a lid Dat a Li nk poi nter B u ffe r d es c riptor V a lid B u ffe r d es c .(L= 1 ) Corr upt ed[...]

CHAPTER 6 USB CONTROLLER 362 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M (b) Rx assembl e mode USB Controller sets EP2FO (EndP oint2 No D ata) bit (Bit 9) in USB Gener al Status Regi ster 2. USB Control ler writ es dumm y data to D ata Buffer (In fact, USB Control ler onl y increment pointer whi ch addresse s Data Buffer b y Max Pack et Size. [...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 363 When set t o a ‘1’, in dicate s that a buffer overrun occurr ed. This bit is set onl y wh en receivi ng the d ata from the EndPoint1. Bit21: Reserved. Bit20: When set to a ‘0’ , indicate s that a CRC err or has not o ccurred. When set to a ‘1’, in dicates that [...]

CHAPTER 6 USB CONTROLLER 364 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.7 Power Man agement USB Controller h as a bu ilt in featur e that al lows it t o use interru pts to inform the V R 4120A o f it s having re ceive d Suspend or Resume si gnalin g from a Ho st PC. When the V R 41 20A rec eives a Suspe nd or a Resum e, it must perform the [...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 365 The V R 4120A is n ot p ermitted to w rite to other than USB C ontro ller's USB G eneral Mo de Regist er and USB Interrupt M ask R egister 2 w hile USB C ontroller is in t he Suspe nd status. O therwi se, after USB C ontroller en ters th e Resume st atus, its operatio[...]

CHAPTER 6 USB CONTROLLER 366 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.7.3 Remote wake up The Remote Wake Up sequence i s shown below . Figure 6-29. Re mote Wake Up Sequence V R 4120A USB C ont r ol l er Ho s t PC Rec ei v es t h e data f r om S e ts R R b it ( B it0 ) i n US B G eneral Mode Regi ster St a r t s K- s t at e si gnal i n g 2[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 367 6.8 Receiving SOF P acket USB Controller can rece ive SOF Pac kets, a nd che ck if Fr ame N umber is i ncremented corr ectly. In addition, U SB Control ler can det ect t he timing skew of SO F Pack et. 6.8.1 Receiving SOF Pa cket and u pdatin g the Frame N umber After USB [...]

CHAPTER 6 USB CONTROLLER 368 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 6.9 Loopback Mode USB Controller fe atures a built-i n loopbac k funct ion for te st purpo ses. To enable the loopba ck fun ction, set t he LE bit (Bit 1) of the US B General Mode Reg ister to 1. Once the lo opbac k funct ion has bee n activ ated, USB C ontrolle r ge ts t[...]

CHAPTER 6 USB CONTROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 369 6.10 Example of Connection USB Controller i s connect ed to the µ PD98502 internal USB I /O buffer a s shown in th e followi ng Figure 6-32 . Figure 6-32. E xample of C onnecti on OSE C onnect t o HUB + 3.3 V A µ PD 98502 D+ D- USB Con t r ol l er D+ B u ffe r OEN IS E Y[...]

370 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M CHAPTER 7 PCI CONTROLLER 7.1 Overview The PCI Control ler sup ports both N IC mode and Host m ode. With t he NIC m ode, the PC I Controll er does not is sue configur ation cyc le and t he arbitra tion fun ction is n ot enab led. With the Host m ode, t he PCI Controller can issue configur ation cy[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 371 7.2 Bus Bridge Functions 7.2.1 Internal bus t o PCI transacti on 7.2.1.1 Window size The PCI Control ler can have a 2-M B length a ccess window in internal memory space. The V R 412 0A ca n acce ss external PCI devic es through th e acc ess window . The a ccess wind ow c[...]

CHAPTER 7 PCI CONTROLLER 372 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.2.1.3 Write issue from internal bu s t o PCI (1) Posted write tr ansaction If IPWRD bit in P _BCNT reg ister i s ‘0’, the PCI C ontroller us es “Posted Write Tran sacti on” rule for w rite transaction s from th e internal b us-side to PCI-s ide. T he rule is a s[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 373 (2) Non posted wr ite transactio n If IPWRD bit in P _BCNT registe r is ‘1’, th e PCI Con troller uses “Non Post ed Write Tr ansact ion” rul e for wr ite transaction s from In ternal bus-s ide to PCI-s ide. In thi s mode , burst transfers are disco nnected at eve[...]

CHAPTER 7 PCI CONTROLLER 374 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.2.1.4 Read issue fro m internal bu s to PCI (1) Delayed read tr ansaction When IDRTD bit in P_BC NT regi ster is ‘ 0’, the PC I Controll er uses “De layed R ead Transac tion” rul e for read transaction s from i nternal bus-s ide to PCI-s ide. T he rule is as fol[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 375 (2) Non delayed re ad transactio n When IDRTD bit in P_BCNT re gister is ‘1’, the PCI C ontroller u ses “Non D elayed Re ad Transact ion” rule for read transaction s from In ternal bus-s ide to PCI-s ide. In thi s mode , burst transfers are disco nnected at every[...]

CHAPTER 7 PCI CONTROLLER 376 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.2.2 PCI to internal bu s transacti on 7.2.2.1 Window size The PCI Control ler sup ports a 2-MB a ddress space as the acc ess win dow from PCI-side to Internal bu s-side in PCI memory space. The base addre ss f or the win dow is wr itten t o Window M emory Bas e Address [...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 377 7.2.2.3 Write issue fro m PCI to Inter nal bus (1) Posted write transa ction If PPWRD bit in P_BC NT regi ster is ‘0’, the PC I Controll er uses “Pos ted Write Transactio n” rule for write transaction s from Interna l bus-s ide to PCI-sid e. The rule i s as follo[...]

CHAPTER 7 PCI CONTROLLER 378 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M (2) Non posted write trans action When PPWRD bit in P_BCN T r egister is ‘1’, the PCI Controll er uses “No n Posted Writ e Transa ction” ru le for writ e transaction s from In ternal bus-s ide to PCI-s ide. In thi s mode , burst transfers are disco nnected at ever[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 379 7.2.2.4 Read issue fro m PCI to inter nal bus (1) Delayed read tr ansaction When PDRTD b it in P_BCNT re gister is ‘0’, the PC I Contro ller us es “Dela yed Read Tr ansaction” ru le for read transaction s from Interna l bus-s ide to PCI-sid e. The rule i s as fol[...]

CHAPTER 7 PCI CONTROLLER 380 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M (2) Non delayed re ad transactio n When PDRTD bit in P_BCNT register is ‘1’, the PCI C ontroller uses “N on Del ayed Read Tran sacti on” rule f or read transaction s from In ternal bus-s ide to PCI-s ide. In thi s mode , burst transfers are disco nnected at every [...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 381 7.2.3 Abnormal Termination 7.2.3.1 On PCI bus (1) Detecting parity error When t he acc ess to the PCI Co ntroller is issue d on PCI bu s and t he PCI Co ntroller dete cts the addres s parity error as a target, th e PCI Con troller iss ues a tar get abort to terminat e th[...]

CHAPTER 7 PCI CONTROLLER 382 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M In the case t hat t he value e xcept f or ‘0’ i s set to P_R TMR register , the PCI Controller abando ns the access when the number of target retr y which t he PCI Co ntroller is receiv ed for the same access goes over the valu e in P_RTMR register. Thi s function is [...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 383 7.3 PCI Powe r Man agement I nte rface The PCI Control ler has the mechan ism for power m anagement c ompliant to PCI Power Manageme nt Interface (PPMI) Rev.1.1 as a PCI-de vice. The PCI Contro ller doe s not c ontrol th e power st ate of th e chip, but issue s sig nals [...]

CHAPTER 7 PCI CONTROLLER 384 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.3.4 Power state tr ansition 7.3.4.1 Transition by issue from PC I- Host An example o f the tran sition sequen ce is as foll ows: 1. When PCI-Host wa nts to c hange t he power st ate of t he chip, it w rite s the state code to Power State field in PMCSR register. 2. The [...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 385 7.3.4.2 Transition by power ma nagem ent event The sequenc e is as fo llows: 1. When Power Mana gement E vent occurs , the V R 41 20A writes a ‘1’ to PMERQ bit in P_PPCR register . 2. The PCI Controller a sserts PME_B if PM E_En bit in PMCSR regi ster is enabled. 3. [...]

CHAPTER 7 PCI CONTROLLER 386 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.4 Functions in Host-mode The funct ions desc ribed i n this sec tion are avail able when PMOD E is set to low. 7.4.1 Generating config uration cy cle 7.4.1.1 How to generate Confi gurati on Cycle The PCI Control ler can generate s Configu ration Cy cle on PCI b us b y a[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 387 7.4.1.3 PCI Configuration Data Register (P_PCDR) When bit31 in the PCAR regi ster is set to ‘1’, access to PCDR regi ster gen erates Config uration Cycl e. Read acce ss to P_PCDR regis ter generate s Configur ation Read Cy cle on PCI bus . Write a ccess to P_PCDR reg[...]

CHAPTER 7 PCI CONTROLLER 388 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Figure 7-14. An E xample How to Connect A D [31:1 6] Signal Line to ID SEL Port AD[ x] AD[3 1: 0] ID S E L PCI dev i ce Figure 7-15. Addr ess St epping for IDSEL Cl ock FRA M E# AD I DSEL IR D Y # TRDY# DEVSEL # Address Data 7.4.2 PCI bus arbiter The PCI Control ler has a[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 389 Figure 7-16. Arbitrat ion in Alternating M ode PCI C ontr ol l er GNT# 0 GNT# 3 GNT# 1 GNT# 2 R o ta tin g Al t er nat i ng 7.4.2.2 Rotating mode Priority rotate s among all PCI m aster de vices in cludin g the PCI Contr oller i n this m ode. When all REQ _B inp ut signa[...]

CHAPTER 7 PCI CONTROLLER 390 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.5 Registers 7.5.1 Register map R/W Of fset Address Register Name Intern al bus PCI Acces s Descr ip tion 1000_4000H P_P LBA R/W R/W W/H/B PCI Lower Base Address Register 1000_4004H N/A --- Reserved 1000_4008H P_I BBA R/W R/ W W/ H/B Internal Bus B ase Address Register 1[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 391 7.5.2 P_PLBA (PCI Lower B ase A ddress Regi ster) When the PCI Co ntroller issues 32-bit PCI address, t his reg ister conta ins PCI base address. Whe n the access from Internal b us-sid e to PCI- side com es, the PCI C ontroller replaces the upper 10 bits of the address [...]

CHAPTER 7 PCI CONTROLLER 392 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.5.5 P_PCAR (PCI Configuration Address Register) PCAR regist er i s u sed to set the informati on for C onfigur ation Cy cle. How to generate Configura tion C ycle is described i n 7.4.1 G enerating configuration cycle . The PCI Control ler can executes Co nfigurat ion C[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 393 7.5.7 P_IGSR (Internal Bus-side G ener al Status Register ) IGSR register s hows the interrupt status of the PCI C ontroller t o the V R 412 0A. When a n event that trigger s interruption occurs, the PCI Co ntroller sets a bit in thi s register c orrespon ds to the e ven[...]

CHAPTER 7 PCI CONTROLLER 394 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.5.8 P_IIMR (Internal Bus Inter rupt M ask Regist er) IIMR register masks the interrupti on f or each corresponding event. A mask bit, whic h locat es in t he same bi t position to a c orrespondin g bit in IGSR, control s interruptio n trigger ed by th e event. Whe n a b[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 395 7.5.9 P_PGSR (PCI-side Gen eral Stat us Regi ster) PGSR register shows t he interr upt stat us of th e PCI Controll er to PCI-si de (wh ich means PCI-Host). Wh en an event that tri ggers in terruptio n occur s, the PCI C ontroller set s a bit in PGSR corresponds to the t[...]

CHAPTER 7 PCI CONTROLLER 396 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.5.10 P_IIMR (Internal Bus Inter rup t Mask R egister ) IIMR register masks the interrupti on f or each corresponding event. A mask bit, whic h locat es in t he same bi t position to a c orrespondin g bit in IGSR, control s interruptio n trigger ed by th e event. Whe n a[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 397 7.5.11 P_PIMR (PCI Interrupt M ask Regis ter) PIMR register mas ks interr uption s. A mask b it, which locates i n the sam e bit position to a corre spondi ng bit in PGSR, can mas k the interru ption. Wh en a bit of this reg ister is reset to ‘0 ’, the c orresponding[...]

CHAPTER 7 PCI CONTROLLER 398 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.5.12 P_HMCR (Host M ode Contro l Reg ister) This regi ster is us ed to co ntrol the PCI-Host functions . R/W Bits Field Intern al bus PCI Default Desc ription 31 PRSTO R/W R 0 Reset Ou t. PCI reset output as Host. The PCI Controller asserts PRSTO during this bit is ‘1[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 399 7.5.15 P_BCNT (Bridge Control Register) This regi ster is us ed to co ntrol the PCI-interna l bus br idge fu nction. R/W Bits Field Intern al bus PCI Default Desc ription 31 INIT D R/W R 0 I nitialize done. The V R 4120A should set this bit to ‘1’ after the initializ[...]

CHAPTER 7 PCI CONTROLLER 400 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.5.16 P_PPCR (PCI Power Contr ol Register) This regi ster is us ed to co ntrol the power sta te for PPM I. See 7.6 Inform ation for Softwar e for furth er details. R/W Bits Field Intern al bus PCI Default Desc ription 31 PMRDY R/W R 0 Power Management Ready. ‘1’ indi[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 401 7.5.18 P_RTMR (Retry Tim er Regist er) This regi ster is us ed to se t the lim itatio n of the number of retry repeti tion. ‘0 ’ disable s this functi on. See 7.2.3.1 (5) Received target retry a s PCI-master for further d etails. R/W Bits Field Intern al bus PCI Defa[...]

CHAPTER 7 PCI CONTROLLER 402 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Offset Address Register Name Size (byte) Intern al bus PCI De scrip tion 1000_4100H Vendor ID 2 R R Vendor ID for NEC = 1033H 1000_4102H Device ID 2 R R Devic e Specific ID 1000_4104H Command 2 R/W R/W PCI Command 1000_4106H Status 2 R/W R/W PCI St atus 1000_4108H Revisio[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 403 7.5.19.2 Vendor ID register This regi ster ide ntifies the manufa cturer of the devic e. The i dentifier for NEC i s ‘1033H ”. R/W Bits Field Intern al bus PCI Default Desc ription 15:0 Vendor ID R R 1033H Hardwired t o ‘1033H’, which means t he Vendor ID of NEC [...]

CHAPTER 7 PCI CONTROLLER 404 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.5.19.4 Command regis ter This r egister pro vides coar se cont rol over a device’s abi lity to g enerate and res pond to PCI cycl es. Thi s register i s valid in H ost-mode. T he V R 4120A should set the register . R/W Bits Field Intern al bus PCI Default Desc ription[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 405 7.5.19.5 Status register This regi ster is used to sh ow PCI bu s relat ed events status. These b its are set w hen events rela ted to the status on PCI bus and r eset to ‘0’ by wr iting ‘1’. In Host-mo de, any bit in this register is not set ev en if corres pond[...]

CHAPTER 7 PCI CONTROLLER 406 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.5.19.6 Revision ID r egister This regi ster sp ecifie s a device spec ific re vision id entifier. R/W Bits Field Intern al bus PCI Default Desc ription 7:0 Revisi on ID R R 01H Hardwired to ‘01H’ that shows the revision number of the chi p. 7.5.19.7 Class code r egi[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 407 7.5.19.10 Header type r egister This regi ster ide ntifie s the layou t of the second part of th e predef ined he ader and also whe ther or not the device contain s multiple functi ons. R/W Bits Field Intern al bus PCI Default Desc ription 7:0 Header Type R R 0 Hardwired[...]

CHAPTER 7 PCI CONTROLLER 408 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.5.19.14 Subsystem ID r egister This regi ster is used to un iquely identif y the expa nsion board or subsystem where the PCI de vice resi des. R/W Bits Field Intern al bus PCI Default Desc ription 15:0 Subsystem I D R/ W R 0 The V R 4120A should set the identifier to th[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 409 7.5.19.19 Max_Lat register This regi ster sp ecifie s how ofte n the de vice n eeds to get the PCI bus u sage. R/W Bits Field Intern al bus PCI Default Desc ription 7:0 Max _Lat R/W R 0 The value should be set by the V R 4120A. 7.5.19.20 Cap_ID regi ster This regi ster i[...]

CHAPTER 7 PCI CONTROLLER 410 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 7.5.19.23 PMCSR register This regi ster is us ed to m anage the PC I funct ion’s pow er managem ent state as well a s to ena ble/monitor PME. R/W Bits Field Intern al bus PCI Default Desc ription 15:10 PME_Staus R R/ W 0 This bit is set when the PCI Controller ass erts [...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 411 7.6 Informatio n for Softw are 7.6.1 NIC mode 7.6.1.1 Initializat ion (1) Initialization by t he V R 4120A The PCI Control ler issue s “retry” to all acce sses fr om PCI-side until INITD bit in P_BCNT regi ster is set to ‘1’. Therefore, I nitializat ion of t he c[...]

CHAPTER 7 PCI CONTROLLER 412 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M - Sets a ‘1’ to PM E_En bit in PMCSR reg ister, if needed Then, the PCI-Ho st dev ice in itializes interna l regist ers. - Sets the val ue of ba se addres s in P _IBBA register, i f needed - Enables ma sk bit s in P_PIMR register , if nee ded - Sets Retry Tim er regis[...]

CHAPTER 7 P CI CONT ROLLER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 413 - Sets a ‘1’ to “B us Ma ster Enab le” bit i n comm and regist er, if the chip e xecutes tra nsact ion as PCI-mas ter - Sets a ‘1’ to “M emor y Write an d Inva lidate Enabl e” bit in comm and r egister, if needed - Sets a ‘1’ to “P arit y Error Resp[...]

414 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M CHAPTER 8 UART 8.1 Overview UART is a ser ial inte rface that confo rms to the R S-232C c ommun icatio n stand ard and i s equipped with tw o one- channel interfa ces, on e for tran smiss ion and one for r eception. This uni t is fun ctionall y com patible wi th the NS16550D. 8.2 UART Block Diagr[...]

CHAPTER 8 UART Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 415 8.3 Registers This control ler use s the NEC NA16550L Me ga-Funct ion as its int ernal UART. This UART is func tional ly identic al to the Nat ional Semicond uctor NS16550D . Re fer t o the N EC “User’ s Manual. M ega Fu nctionNA16 550L” for m ore information a nd program ming[...]

CHAPTER 8 UART 416 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 8.3.2 UARTRBR (UART Receiver data Buffer Re gister) This regi ster hol ds rec eive data. It is on ly ac cessed w hen the D ivi sor Lat ch Acce ss bit (D LAB) is c leared in the UARTLCR. Bits Field R/ W Default Description 31:8 Reserved R 0 Hardwired to 0. 7:0 UDATA R - UART receiv [...]

CHAPTER 8 UART Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 417 8.3.6 UARTDLM (UART Divis or Latch MSB Register) This regi ster is us ed to se t the di visor (div ision r ate) for th e baud rate genera tor. The d ata in t his reg ister an d the lower 8-bit data in UAR TDLL reg ister are together handled a s 16-bit data. Bits Field R/ W Default D[...]

CHAPTER 8 UART 418 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 8.3.7 UARTIIR (UART Interrupt ID Register) This regi ster ind icates pri ority le vels f or interru pts and exist ence of pending interrup t. From highest to lowest priority, the se interru pts are r eceive li ne stat us, rece ive dat a ready, chara cter timeout, tr an smit hold in[...]

CHAPTER 8 UART Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 419 8.3.8 UARTFCR (UART FIFO Control Register) This regi ster is us ed to co ntrol the FIFOs: ena ble FIFO , clear FIFO, a nd set th e rece ive FIFO trigger le vel. Bits Field R/ W Default Description 31:8 Reserved W 0 Hardwired to 0. 7:6 URFTR W 00 UART Receive FIFO Trigger level. When[...]

CHAPTER 8 UART 420 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 8.3.9 UARTLCR (UART Line Control Register) This r egister is used to spec ify the form at for as ynchro nous com mun ication and ex change and to set t he div isor latch acce ss bit. Bit 6 is used to send the b reak st atus to t he rece ive s ide’s UAR T. When bit 6 = 1, the seri[...]

CHAPTER 8 UART Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 421 8.3.10 UARTMCR (UART Modem Control R egister) This register controls t he state of external URDTR_B and URRTS_B mo dem-control signa ls and of the loop-back test. Bits Field R/ W Default Description 31:5 Reserved R/W 0 Hardwired t o 0. 4 LOOP R/W 0 Loop-Bac k Test. 1 = loop-back. 0 [...]

CHAPTER 8 UART 422 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 8.3.11 UARTLSR (UART Line Status Register) This regi ster repor ts the current s tate of the tra nsmitt er and rec eiver logic. Bits Field R/ W Default Description 31:8 Reserved R/W 0 Hardwired t o 0. 7 RFE RR R/W 0 Rec eiver F IFO Error. 1 = parity, framing, or break error in rece[...]

CHAPTER 8 UART Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 423 8.3.12 UARTMSR (UART Modem Status Register) This regi ster repor ts the current s tate of a nd chan ges in var ious contro l signal s. Bits Field R/ W Default Description 31:8 Reserved R/W 0 Hardwired t o 0. 7 DCD R/W 0 Data Carri er Detect. 1 =URDCD_B state activ e. 0 = URDCD_B sta[...]

424 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M CHAPTER 9 TIMER 9.1 Overview There are two Timers. The tim ers are clocked at the s ystem clock rate. All two tim ers are read/write able b y the CPU. Timers c an be re ad by the C PU whi le they are countin g. They can be automat ically relo aded with the “Timer Set Count Reg ister” v alue a[...]

CHAPTER 9 TIMER Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 425 9.3 Registers 9.3.1 Register map Offset Address Regist er Name R/W Acc ess Descripti on 1000_00B0H TMMR R/W W/H/B Ti mer Mode Regi ster 1000_00B4H TM0CSR R/W W/ H/B Timer CH0 Count Set Regist er 1000_00B8H TM1CSR R/W W/ H/B Timer CH1 Count Set Regist er 1000_00BCH TM0CCR R W/ H/B T[...]

CHAPTER 9 TIMER 426 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 9.3.3 TM0CSR (Timer CH 0 Count Set Register) The Timer CH0 Count Set Regist er “TM0CSR” i s a read-wr ite and 3 2-bit word-al igned register. C PU (V R 412 0A) loads a value in i t and the counter starts counti ng down from the (TM 0CSR –1) value. When it r eache s 0000_ 000[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 427 CHAPTER 10 MICRO WIRE 10.1 Overview This EEPROM interfa ce is com patible with t he Mi cro Wire serial interf ace. Connection to the “NM93C46” serial EEPROM, manufacture d by Nati onal Semic onductor, i s recomm ended. Serial EEPROM memory area is accessed in-directly throghout Micro Wire-ma c[...]

CHAPTER 10 MICRO WIRE 428 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 10.2 Operation s 10.2.1 Data read at th e power up load After reset relea se, power up load processe s start s. In case of th e valu e from EEPROM address 00H i s: 1. A5A5H System Controller sets the EEPROM data (a ddress: 01H to 06H) in the internal registers (MACAR1, MACAR[...]

CHAPTER 10 MICRO WIRE Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 429 10.3 Registers 10.3.1 Register map Offset Address Regist er Name R/W Acc ess Descripti on 1000_00D0H ECCR W W/ H/B E EPROM Command Control Register 1000_00D4H ERDR R W/ H/B EEPROM Read Data Register 1000_00D8H MA CAR1 R W/H/ B MAC Address Register 1 1000_00DCH MACAR2 R W/H/ B[...]

CHAPTER 10 MICRO WIRE 430 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M 10.3.6 MACAR3 (MAC Address Reg ister 3) Bits Field R/ W Default Description 31:16 SERIAL EEPRO M 06 H ADDRESS R 0 S tored Serial EEPROM data of address 05H, 06H. 15:0 SERIAL EEPRO M 05 H ADDRESS R0[...]

Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 431 APPENDIX A MIPS III INSTRUCTIO N SET DETAILS This ch apter provid es a det ailed des cription of the o peration of each in structi on in bo th 32- an d 64-bit mo des. Th e instruct ions are li sted in alphab etical order. A.1 Instruction Notation Con vention s In this chapter, all variable subfi e[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 432 Preliminary User ’ s Manu al S155 43EJ 1V0U M Table A-1. CPU Instruction O peration Not ations Symbol Desc ription ← Assignment || Bit string conc atenation x y Replicat ion of bit value x into a y -bit string. x is always a single-bit value xy:z Sel ection of bits y through z of bit string x [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 433 (1) Instruction notation e xamples The follow ing examp les il lustrate the app lication of some of the in structi on notat ion conve ntion s: Example 1: GPR [rt] ← immediat e || 0 16 Sixteen zero bits are conca tenated w ith an im mediat e value (ty pi[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 434 Preliminary User ’ s Manu al S155 43EJ 1V0U M As shown i n Table A- 3, the Acc ess T ype field indica tes the size of the data item to be loaded or stored. Regardles s of acce ss t ype or b yte-numberi ng order ( endian), t he addr ess sp ecifie s the byt e that has the smallest byte address in [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 435 A.4 System Control Coprocessor (CP0) Instructions There are som e spec ial limit ations impos ed on op erations in volvi ng CP0 t hat is in corpor ated with in the CPU. Although load and sto re instr uction s to transfer data to/from coprocess ors and to [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 436 Preliminary User ’ s Manu al S155 43EJ 1V0U M ADD Add ADD rs SPECI AL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 ADD 1 0 0 0 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: ADD rd, rs, rt Description: The contents of gener al regi ster rs and the c ontents of genera l register rt are added to form the [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 437 ADDI Add Imm edi at e ADDI rs ADDI 0 0 1 0 0 0 rt imm ediate 31 26 25 21 20 16 15 0 65 5 1 6 Format: ADDI rt, rs, imm ediate Description: The 16-bit immediat e is sign-exte nded an d added to the c ontents of g eneral re gister rs to form the result. The [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 438 Preliminary User ’ s Manu al S155 43EJ 1V0U M ADDIU A dd Immediate Unsi g ned ADDIU rs ADDIU 0 0 1 0 0 1 rt imm ediate 31 26 25 21 20 16 15 0 65 5 1 6 Format: ADDIU rt, rs, immediate Description: The 16-bit immediat e is sign-exte nded an d added to the c ontents of g eneral re gister rs to form[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 439 ADDU A d d Unsigned ADDU rs SPECI AL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 ADDU 1 0 0 0 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: ADDU rd, rs, rt Description: The contents of gener al regi ster rs and the c ontents of genera l register rt are added to[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 440 Preliminary User ’ s Manu al S155 43EJ 1V0U M AND An d AND rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 AND 1 0 0 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: AND rd, rs, rt Description: The contents of gener al regi ster rs are comb ined w ith the content s of gen eral reg ister rt in a [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 441 ANDI And Imm edi at e ANDI rs ANDI 0 0 1 1 0 0 rt imm ediate 31 26 25 21 20 16 15 0 65 5 1 6 Format: ANDI rt, rs, imm ediate Description: The 16-bit immediat e is zero-ex tended and combi ned w ith the content s of gen eral regi ster rs in a bit-wis e log[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 442 Preliminary User ’ s Manu al S155 43EJ 1V0U M BC0F Branch On Coprocessor 0 False BC0F BC 0 1 0 0 0 COPz 0 1 0 0 X X N ote BCF 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 65 5 1 6 Format: BC0F offset Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc tion [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 443 BC0FL Branch On Co p rocessor 0 False Likel y ( 1/2 ) BC0FL BC 0 1 0 0 0 COPz 0 1 0 0 X X N ote BCFL 0 0 0 1 0 offse t 31 26 25 21 20 16 15 0 65 5 1 6 Format: BC0FL offset Description: A branch tar get addr ess is com puted from the sum of the addres s of[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 444 Preliminary User ’ s Manu al S155 43EJ 1V0U M BC0FL Branch On Co p rocessor 0 False Likel y ( 2/2 ) BC0FL Opcode Table: 31 0 30 1 29 0 28 0 27 0 26 0 25 0 24 1 23 0 22 0 21 0 20 0 19 0 18 0 17 1 16 0 0 BC0FL Opcode Coprocessor number BC sub-opcod e Branch condition[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 445 BC0T Branch On Coprocessor 0 True BC0T BC 0 1 0 0 0 COPz 0 1 0 0 X X N ote BCT 0 0 0 0 1 of fset 31 26 25 21 20 16 15 0 65 5 1 6 Format: BC0T offset Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc tion in th[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 446 Preliminary User ’ s Manu al S155 43EJ 1V0U M BC0TL Branch On Coprocessor 0 True L ikely ( 1/2) BC0TL BC 0 1 0 0 0 COPz 0 1 0 0 X X Note BCTL 0 0 0 1 1 of fset 31 26 25 21 20 16 15 0 65 5 1 6 Format: BC0TL offset Description: A branch tar get addr ess is com puted from the sum of the addres s of[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 447 BC0TL Branch On Coprocessor 0 True L ikely ( 2/2) BC0TL Opcode Table: 31 0 30 1 29 0 28 0 27 0 26 0 25 0 24 1 23 0 22 0 21 0 20 0 19 0 18 0 17 1 16 1 0 BC0TL Opcode Coprocessor number BC sub-opcod e Branch condition[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 448 Preliminary User ’ s Manu al S155 43EJ 1V0U M BEQ Branch On Equ al BEQ rs BEQ 0 0 0 1 0 0 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: BEQ rs, rt, offse t Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc tion in the delay slo t and the 16-bit [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 449 BEQL Branch On Equal Like ly BEQL rs BEQL 0 1 0 1 0 0 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: BEQL rs, rt, offs et Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc tion in the delay slo t and the 1[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 450 Preliminary User ’ s Manu al S155 43EJ 1V0U M BGEZ Branch On Greater Th an Or Equa l To Zero BGEZ rs REGIM M 0 0 0 0 0 1 BGEZ 0 0 0 0 1 offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: BGEZ rs, offset Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 451 BGEZAL Bran ch On Grea ter Tha n Or Eq ual To Zer o And Link BGEZAL rs REGIM M 0 0 0 0 0 1 BGEZAL 1 0 0 0 1 offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: BGEZAL rs, offset Description: A branch tar get addr ess is com puted from the sum of the addres s [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 452 Preliminary User ’ s Manu al S155 43EJ 1V0U M BGEZALL Branch O n Greater T han O r Equal T o Z ero And Link Likely BGEZALL rs REGIM M 0 0 0 0 0 1 BGEZALL 1 0 0 1 1 offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: BGEZALL rs, offs et Description: A branch tar get addr ess is com puted from the sum[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 453 BGEZL Branch On Greater Th an Or Equa l To Zero L ikely BGEZL rs REGIM M 0 0 0 0 0 1 BGEZL 0 0 0 1 1 offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: BGEZL rs, offset Description: A branch tar get addr ess is com puted from the sum of the addres s of the i[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 454 Preliminary User ’ s Manu al S155 43EJ 1V0U M BGTZ Branch On Great er Than Zero BGTZ rs BGTZ 0 0 0 1 1 1 0 0 0 0 0 0 offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: BGTZ rs, offset Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc tion in the delay s[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 455 BGTZL Branch On Greater Th an Ze ro Likely BGTZL rs BGTZL 0 1 0 1 1 1 0 0 0 0 0 0 offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: BGTZL rs, offs et Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc tion in the[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 456 Preliminary User ’ s Manu al S155 43EJ 1V0U M BLEZ Branch On Less T han Or Equal To Zero BLEZ rs BLEZ 0 0 0 1 1 0 0 0 0 0 0 0 offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: BLEZ rs, offset Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc tion in th[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 457 BLEZL Bran ch On Less Than Or Equal To Zero Lik ely BLEZL rs BLEZL 0 1 0 1 1 0 0 0 0 0 0 0 offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: BLEZL rs, offset Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc tio[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 458 Preliminary User ’ s Manu al S155 43EJ 1V0U M BLTZ Bra nch On Les s Tha n Ze r o BLTZ rs REGIM M 0 0 0 0 0 1 BLTZ 0 0 0 0 0 offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: BLT Z r s, o ffs et Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc tion in [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 459 BLTZAL Bra nch O n Les s Than Zer o And Link BLTZAL rs REGIM M 0 0 0 0 0 1 BLTZAL 1 0 0 0 0 offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: BLTZAL rs, offset Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc t[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 460 Preliminary User ’ s Manu al S155 43EJ 1V0U M BLTZALL Branch On Less Than Zero A nd Link Likely BLTZALL rs REGIMM 0 0 0 0 0 1 BLTZ ALL 1 0 0 1 0 offse t 31 26 25 21 20 16 15 0 65 5 1 6 Format: BLTZALL rs, offs et Description: A branch tar get addr ess is com puted from the sum of the addres s of[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 461 BLTZL Branch On Less Than Zero Like ly BLTZL rs REGIM M 0 0 0 0 0 1 BLTZL 0 0 0 1 0 offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: BLT Z r s, o ffs et Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc tion in[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 462 Preliminary User ’ s Manu al S155 43EJ 1V0U M BNE Branch On N ot Equ al BNE rs BNE 0 0 0 1 0 1 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: BNE rs, rt, offset Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc tion in the delay slo t and the 16-[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 463 BNEL Branch On Not Equal Like ly BNEL rs BNEL 0 1 0 1 0 1 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: BNEL rs, rt, offset Description: A branch tar get addr ess is com puted from the sum of the addres s of the instruc tion in the delay slot and the[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 464 Preliminary User ’ s Manu al S155 43EJ 1V0U M BREAK Breakpoin t BREAK code SPECIAL 0 0 0 0 0 0 BREAK 0 0 1 1 0 1 31 26 25 6 5 0 62 06 Format: BREAK Description: A breakpoint tr ap occ urs, im mediately and un conditi onally tran sferring control to the e xception h andler. The code field is a va[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 465 CACHE Cache (1/4) CACHE base CACHE 1 0 1 1 1 1 op of fset 31 26 25 21 20 16 15 0 65 5 1 6 Format: CACHE op, off set (bas e) Description: The 16-bit offset is sign-extend ed and added to the content s of general register base t o form a virt ual addr ess. [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 466 Preliminary User ’ s Manu al S155 43EJ 1V0U M CACHE Cache (2/4) CACHE Write back from a cache goes t o main m emory. The main m emory addre ss to be writte n is spec ified b y the cache tag and not the phys ical addre ss translat ed using TLB. TLB Refill a nd TLB In valid exce ption s can occ ur[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 467 CACHE Cache (3/4) CACHE Code Cache Name Operation 0 I Index_Invalidate S et the cache state of the cache block to Invalid. 0 D Index_Writ e_ Back_I nvalidate Examine the cache state and W bit of the primary data cache block at the index specified by the v[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 468 Preliminary User ’ s Manu al S155 43EJ 1V0U M CACHE Cache (4/4) CACH E Operation: 32, 64 T: v Addr ← ((offset 15 ) 48 || offset 15...0 ) + GPR [base] (pAddr, uncached) ← AddressTranslation (vAddr, DA TA) CacheOp (op, vAddr, pAddr) Exceptions: Coprocessor u nusabl e exce ption TLB Refill exc [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 469 DADD Doubl ew or d Add DADD rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DADD 1 0 1 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DADD rd, rs, rt Description: The contents of gener al regi ster rs and the c ontents of genera l register rt are added [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 470 Preliminary User ’ s Manu al S155 43EJ 1V0U M DADDI Doubleword A dd Imm ediate DA DDI rs DADDI 0 1 1 0 0 0 rt imm ediate 31 26 25 21 20 16 15 0 65 5 1 6 Format: DADDI rt, rs, immediate Description: The 16-bit immediat e is sign-exte nded an d added to the c ontents of g eneral re gister rs to fo[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 471 DADDIU Doubl ew or d Add Imme diat e Uns ign ed DA DDIU rs DADDI U 0 1 1 0 0 1 rt imm ediate 31 26 25 21 20 16 15 0 65 5 1 6 Format: DADDIU rt, rs, immediate Description: The 16-bit immediat e is sign-exte nded an d added to the c ontents of g eneral re g[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 472 Preliminary User ’ s Manu al S155 43EJ 1V0U M DADDU Doubleword A dd U nsign ed DADDU rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DADDU 1 0 1 1 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DADDU rd, rs, rt Description: The contents of gener al regi ster rs and the c ontents of genera l regi[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 473 DDIV Do ublew o rd D ivide DDIV rs SPECIAL 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 DDIV 0 1 1 1 1 0 31 26 25 21 20 16 15 6 5 0 65 5 1 0 6 Format: DDIV rs, rt Description: The contents of gener al regi ster rs are di vided by the contents of gener al regi ste[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 474 Preliminary User ’ s Manu al S155 43EJ 1V0U M DDIVU Doublew ord Divi de Unsigned DDIVU rs SPECI AL 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 65 5 1 0 DDIVU 0 1 1 1 1 1 65 6 Format: DDIVU rs, rt Description: The contents of gener al regi ster rs are di vided by the contents of g[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 475 DIV Divide DIV rs SPECIAL 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 65 5 1 0 DIV 0 1 1 0 1 0 65 6 Format: DIV rs, rt Description: The contents of gener al regi ster rs are divid ed by t he cont ents of general r egister rt, tre ating bot[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 476 Preliminary User ’ s Manu al S155 43EJ 1V0U M DIVU Divide Unsi gned DIVU rs SPECI AL 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 65 5 1 0 DIVU 0 1 1 0 1 1 65 6 Format: DIVU rs, rt Description: The contents of gener al regi ster rs are di vided by the contents of gener al regi ste[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 477 DMACC Doublew ord M ultiply and Accumulate (1 /3) D MACC rs SPECI AL 0 0 0 0 0 0 rt 1 31 26 25 21 20 16 15 0 65 5 DMACC 1 0 1 0 0 1 65 6 rd sat us 0 0 0 1 53 11 10 9 7 Format: DMACC rd, rs, rt DMACCU rd, rs, rt DMACCS rd, rs, rt DMACCUS rd, rs, rt Descrip[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 478 Preliminary User ’ s Manu al S155 43EJ 1V0U M DMACC Doubleword Multiply and Accumulate (2/3) DMACC • When saturati on processing is not executed ( sat = 0): DMACC, DM ACCU instructions The contents of gener al regi ster rs is mult iplied by the cont ents of general regi ster rt . If both opera[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 479 DMACC Doubleword Multiply and Accumulate (3/3) DMACC Operation: 64, sat=0, us=0 (DM ACC instruction) T: temp1 ← ((GPR[rs] 31 ) 32 || GPR [rs]) * ((GPR[rt] 31 ) 32 || GPR [rt]) temp2 ← temp1 + LO LO ← temp2 GPR[rd] ← LO 64, sat=0, us =1 (DMACCU ins[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 480 Preliminary User ’ s Manu al S155 43EJ 1V0U M DMFC0 Doubl eword Mov e From Sy stem Con tr ol Cop roce ssor DMFC0 DMF 0 0 0 0 1 COP0 0 1 0 0 0 0 rt rd 31 26 25 21 20 16 15 0 6 555 0 0 0 0 0 0 0 0 0 0 0 0 11 10 11 Format: DMFC0 rt, rd Description: The contents of copr ocessor reg ister rd of the C[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 481 DMTC0 Doublew ord Move To System Control Cop rocessor DMTC0 DMT 0 0 1 0 1 COP0 0 1 0 0 0 0 rt rd 31 26 25 21 20 16 15 0 6 555 0 0 0 0 0 0 0 0 0 0 0 0 11 10 11 Format: DMTC0 rt, rd Description: The contents of gener al register rt are loa ded into coproces[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 482 Preliminary User ’ s Manu al S155 43EJ 1V0U M DMULT Doub lew ord Multiply DMULT rs SPECIAL 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 65 5 1 0 DMULT 0 1 1 1 0 0 65 6 Format: DMULT rs, rt Description: The contents of gener al regi sters rs and rt are multi plied, tr eating b oth [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 483 DMULTU Doub lew ord Multiply Uns igned DMU LTU rs SPECIAL 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 65 5 1 0 DMULTU 0 1 1 1 0 1 65 6 Format: DMULTU rs, rt Description: The contents of gener al regi ster rs and the c ontents of genera l r[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 484 Preliminary User ’ s Manu al S155 43EJ 1V0U M DSLL Doubl ew ord S hi ft Le ft Logi cal DSLL 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSL L 1 1 1 0 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DSLL rd, rt, sa Description: The contents of gener al regi ster rt are shifted left by sa bits,[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 485 DSLLV Doublew o rd S hif t Le ft Logic al Var ia ble DSLLV rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DSLLV 0 1 0 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DSLLV rd, rt, rs Description: The contents of gener al register rt are shifted left by [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 486 Preliminary User ’ s Manu al S155 43EJ 1V0U M DSLL32 Doublew o rd S hif t Le ft Log ic al + 32 DSLL32 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSLL32 1 1 1 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DSLL32 rd, rt, sa Description: The contents of gener al regi ster rt are shifted lef[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 487 DSRA Doub lew ord Shift Right A r ithmetic DSRA 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSRA 1 1 1 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DSRA rd, rt, sa Description: The contents of gener al regi ster rt are sh ift ed ri gh t by sa bits[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 488 Preliminary User ’ s Manu al S155 43EJ 1V0U M DSRAV Doubleword Shift Right A rithmetic Variab le DSRA V rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DSRA V 0 1 0 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 555 6 Format: DSRAV rd, rt, rs Description: The contents of gener al regi ster rt are shifted r[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 489 DSRA32 Doubleword Shift Right A rithmetic + 32 DSRA 32 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSRA 32 1 1 1 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DSRA32 rd, rt, sa Description: The contents of gener al regi ster rt are sh ift ed ri ght[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 490 Preliminary User ’ s Manu al S155 43EJ 1V0U M DSRL Doubl ew o rd S hif t Ri ght Logi cal DSRL 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSRL 1 1 1 0 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DSRL rd, rt, sa Description: The contents of gener al regi ster rt are sh ift ed ri ght by sa [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 491 DSRLV Doubl ew o rd S hif t Ri ght Logi cal Va ri able DSRLV rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DSRL V 0 1 0 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DSRLV rd, rt, rs Description: The contents of gener al regi ster rt are shifted righ[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 492 Preliminary User ’ s Manu al S155 43EJ 1V0U M DSRL32 Doubl ew o rd S hif t Ri ght Logic al + 32 DSRL32 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSRL 32 1 1 1 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DSRL32 rd, r t, sa Description: The contents of gener al regi ster rt are shif te [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 493 DSUB Doubl ew o rd S ubt rac t DSUB rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DSUB 1 0 1 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DSUB rd, rs, rt Description: The contents of gener al regi ster rt are subtract ed from the content s of genera[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 494 Preliminary User ’ s Manu al S155 43EJ 1V0U M DSUBU Doubl ew or d Sub tra ct Un sign ed DSUBU rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DSUB U 1 0 1 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DSUBU rd, rs, rt Description: The contents of gener al regi ster rt are subtract ed from the[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 495 ERET Exception Return ERET CO 1 COP0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERET 0 1 1 0 0 0 31 26 25 24 6 5 0 61 1 9 6 Format: ERET Description: ERET is the i nstruct ion for ret urning fr om an interru pt, ex ception, or error tra p. Unlik [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 496 Preliminary User ’ s Manu al S155 43EJ 1V0U M HIBERNATE Hi bernate HIBERNATE CO 1 COP0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIBERNATE 1 0 0 0 1 1 31 26 25 24 6 5 0 61 1 9 6 Format: HIBERNATE Description: HIBERNATE instr uction starts m ode transit ion from Fullspeed m ode t o Hibe[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 497 J Jump J J 0 0 0 0 1 0 target 31 26 25 0 62 6 Format: J target Description: The 26-bit target address is shif ted left two bits and combi ned with the high-or der four bits of the address of the delay slot. The progr am un conditiona lly jum ps to thi s c[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 498 Preliminary User ’ s Manu al S155 43EJ 1V0U M JAL Jum p And Link JAL JAL 0 0 0 0 1 1 target 31 26 25 0 62 6 Format: JAL target Description: The 26-bit target address is shif ted left two bits and combi ned with the high-or der four bits of the addres s of the delay slot. The progr am un conditio[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 499 JALR Jump A nd Link Register JALR rs SPECIAL 0 0 0 0 0 0 0 0 0 0 0 0 rd 0 0 0 0 0 0 JALR 0 0 1 0 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: JALR rs JALR rd, rs Description: The program un condit ionall y jump s to the address c ontaine d in gen[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 500 Preliminary User ’ s Manu al S155 43EJ 1V0U M JALX Jump A nd Link Exchange JALX JALX 011101 31 26 25 0 62 6 target Format: JALX target Description: When a MIPS16 i nstruct ion can be exe cuted, a 26-bit t arget is shifted to left by 2 bits and then added to higher 4 bits of the d elay s lot&apos[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 501 JR Jump R egist er JR rs SPECIAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 0 65 1 5 JR 0 0 1 0 0 0 65 6 Format: JR rs Description: The program un condit ionall y jump s to the addr ess contained in general regist er rs , with a delay of o[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 502 Preliminary User ’ s Manu al S155 43EJ 1V0U M LB Load Byte LB base LB 1 0 0 0 0 0 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: LB rt, offset (ba se) Description: The 16-bit offset is sign-extend ed and added to the content s of general register base to form a virtual addres s. The contents[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 503 LBU Load Byte Unsigned LBU base LBU 1 0 0 1 0 0 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: LBU rt, offset ( base) Description: The 16-bit offset is sign-extend ed and added to the content s of general register base to form a virtual addres s. The [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 504 Preliminary User ’ s Manu al S155 43EJ 1V0U M LD Load Do ublew o rd LD base LD 1 1 0 1 1 1 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: LD rt, offset ( base) Description: The 16-bit offset is sign-extend ed and added to the content s of general register base to form a virtual addres s. The[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 505 LDL Load Doublew ord Left (1/3) LDL base LDL 0 1 1 0 1 0 rt offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: LDL rt, offset (ba se) Description: This in structio n c an be u sed in com binatio n with the LDR in structi on to lo ad a register with eight con[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 506 Preliminary User ’ s Manu al S155 43EJ 1V0U M LDL Load Doublew ord Left (2/3) LDL The contents of gener al regi ster rt are inter nally byp assed within th e process or so tha t no NOP i s needed b etween an imm ediatel y pre ceding load i nstruct ion whic h spec ifies r egister rt and a f ollow[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 507 LDL Load Doublew ord Left (3/3) LDL Given a do ubleword i n a regi ster and a doubl eword in m emory, the operati on of LD L is as f ollow s: B C D E F G A H J K L M N O I P Register Mem o r y LDL vAddr2..0 Dest ination Type Offset (LEM) 0 1 2 3 4 5 6 7 P[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 508 Preliminary User ’ s Manu al S155 43EJ 1V0U M LDR Load Doublew ord Right (1/3) LDR base LDR 0 1 1 0 1 1 rt offset 31 26 25 21 20 16 15 0 65 5 1 6 Format: LDR rt, offset ( base) Description: This instru ction c an be u sed in combinat ion wit h the LDL instruct ion to load a register wit h eight [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 509 LDR Load Doublew ord Right (2/3) LDR The contents of gener al regi ster rt are inter nally byp assed within th e process or so that no N OP is n eeded betw een an imm ediatel y pre ceding load i nstruct ion whic h spec ifies r egister rt and a f ollowing [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 510 Preliminary User ’ s Manu al S155 43EJ 1V0U M LDR Load Doublew ord Right (3/ 3) LDR Given a do ubleword i n a regi ster and a doubl eword in m emory, the operati on of LDR is as fol lows: B C D E F G A H J K L M N O I P Register Mem o r y LDR vAddr2..0 Destination Ty pe Offset (LEM) 0 1 2 3 4 5 [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 511 LH Load H alfw ord LH base LH 1 0 0 0 0 1 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: LH rt, offset ( base) Description: The 16-bit offset is sign-extend ed and added to the content s of general regist er base to form a virtual addres s. The conten[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 512 Preliminary User ’ s Manu al S155 43EJ 1V0U M LHU Load Halfw ord Un signe d LHU base LHU 1 0 0 1 0 1 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: LHU rt, offset ( base) Description: The 16-bit offset is sign-extend ed and added to the content s of general register base to form a virtual ad[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 513 LUI Loa d Upp er Immediate LUI 0 0 0 0 0 0 LUI 0 0 1 1 1 1 rt imm ediate 31 26 25 21 20 16 15 0 65 5 1 6 Format: LUI rt, immedi ate Description: The 16-bit immediat e is s hifted l eft 16 bits a nd con catenat ed to 16 bits of zeros. The res ult is p lace[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 514 Preliminary User ’ s Manu al S155 43EJ 1V0U M LW Load W ord LW base LW 1 0 0 0 1 1 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: LW rt, offset (ba se) Description: The 16-bit offset is sign-extend ed and added to the content s of general register base to form a virtual addres s. The content[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 515 LWL Load Word Left (1/3) LWL base LW L 1 0 0 0 1 0 rt offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: LWL rt, offset (b ase) Description: This in structio n c an b e used in combin ation wit h the LWR instr uction to load a register w ith fo ur consecu ti[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 516 Preliminary User ’ s Manu al S155 43EJ 1V0U M LWL Load Word Left (2/3) LWL The contents of gener al regi ster rt are inter nally byp assed within th e process or so that no N OP is n eeded betw een an imm ediatel y pre ceding load i nstruct ion whic h spec ifies r egister rt and a f ollowing LWL[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 517 LWL Load Word Left (3/3) LWL Given a do ubleword i n a regi ster and a doubl eword in m emory, the operati on of LWL is as follows: B C D E F G A H J K L M N O I P Register Mem o r y LWL vAddr2..0 Destination Type Offs et (LEM) 0 1 2 3 4 5 6 7 S SSSPF G H[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 518 Preliminary User ’ s Manu al S155 43EJ 1V0U M LWR Load Word Right (1/ 3) LWR base LW R 1 0 0 1 1 0 rt offset 31 26 25 21 20 16 15 0 65 5 1 6 Format: LWR rt, offset (base) Description: This instru ction c an be u sed in com binatio n with the LWL instru ction to load a register w ith four consecu[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 519 LWR Load Word Right (2/ 3) LWR The contents of gener al regi ster rt are inter nally bypas sed with in the proce ssor so tha t no NOP i s need ed between an imm ediatel y pre ceding load i nstruct ion whic h spec ifies r egister rt and a foll owing LWR (o[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 520 Preliminary User ’ s Manu al S155 43EJ 1V0U M LWR Load Word Right (3/3) LW R Given a word in a reg ister an d a wor d in mem ory, the op eration of LWR is as fol lows: B C D E F G A H J K L M N O I P Register Mem o r y LWR vAddr2..0 Desti nation Type Offs et (LEM) 0 1 2 3 4 5 6 7 SS S S M N O P [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 521 LWU Load Word Unsigned LWU base LW U 1 0 1 1 1 1 rt offset 31 26 25 21 20 16 15 0 65 5 1 6 Format: LWU rt, offset (base) Description: The 16-bit offset is sign-extend ed and added to the content s of general register base to form a virtual addres s. The c[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 522 Preliminary User ’ s Manu al S155 43EJ 1V0U M MACC Multiply and Accumulate (1/5) MACC rs SPECI AL 0 0 0 0 0 0 rt 1 31 26 25 21 20 16 15 0 65 5 MACC 1 0 1 0 0 0 65 6 rd sat us 0 0 1 51 11 10 9 7 hi 2 8 Format: MACC rd, rs, rt MACCU rd, rs, rt MACCHI rd, rs, rt MACCHIU rd, rs, rt MACCS rd, rs, rt [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 523 MACC Multiply and Accumulate (2/5) MACC • When saturati on processing is not executed ( sat = 0): MACC, M ACCU, MACCHI, M ACCHIU instructions The contents of gener al regi ster rs is mult iplied t o the conte nts of g eneral regi ster rt . If both o per[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 524 Preliminary User ’ s Manu al S155 43EJ 1V0U M MACC Multiply and Accumulate (3/5) MACC Operation: 32, sat=0, hi=0, us=0 (MAC C instruction) T: temp1 ← GPR[rs] * GPR[rt] temp2 ← temp1 + (HI || LO) LO ← temp2 63..32 HI ← temp2 31..0 GPR[rd] ← LO 32, sat=0, hi=0 , us=1 (MACCU instruction) [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 525 MACC Multiply and Accumulate (4/5) MACC 32, sat=1, hi=1 , us=0 (MACCHIS instruction) T: temp1 ← GPR[rs] * GPR[rt] temp2 ← saturation(temp1 + (HI || LO)) LO ← temp2 63..32 HI ← temp2 31..0 GPR[rd] ← HI 32, sat=1, hi=1 , us=1 (MACCHIUS instruction[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 526 Preliminary User ’ s Manu al S155 43EJ 1V0U M MACC Multiply and Accumulate (5/5) MACC 64, sat=1, hi=0, us=0 (MAC CS instruction) T: temp1 ← ((GPR[rs] 31 ) 32 || GPR[rs]) * ((GPR[rt] 31 ) 32 || GPR[rt]) temp2 ← saturation(temp1 + (HI 31..0 || LO 31..0 )) LO ← ((temp2 63 ) 32 || temp2 63..32[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 527 MFC0 Move F rom Sy stem Co ntro l Cop roces sor MFC0 MF 0 0 0 0 0 COP0 0 1 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 6 555 11 10 11 rd Format: MFC0 rt, rd Description: The contents of copr ocessor reg ister rd of the C P0 are l oaded i nto[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 528 Preliminary User ’ s Manu al S155 43EJ 1V0U M MFHI M ove From HI MFHI 0 0 0 0 0 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 31 26 25 11 10 16 15 0 61 0 5 6 rd 0 0 0 0 0 0 MFHI 0 1 0 0 0 0 5 65 Format: MFHI rd Description: The contents of spe cial regist er HI are l oaded into g eneral reg ister rd . To ensu[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 529 MFLO M ove Fro m LO MFLO 0 0 0 0 0 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 31 26 25 11 10 16 15 0 61 0 5 6 rd 0 0 0 0 0 0 MFLO 0 1 0 0 1 0 5 65 Format: MFLO rd Description: The contents of spe cial regist er LO are lo aded into g ener al register rd . To ensure p[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 530 Preliminary User ’ s Manu al S155 43EJ 1V0U M MTC0 Move To Coprocessor0 MTC0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 31 26 25 11 10 16 15 0 6 11 5 5 rt rd MT 0 0 1 0 0 5 21 20 Format: MTC0 rt, rd Description: The contents of gener al register rt are loa ded into coproces sor register rd of copr[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 531 MTHI Move To HI rs SPECI AL 0 0 0 0 0 0 MTHI 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 6 5 0 65 6 15 MTHI Format: MTHI rs Description: The contents of gener al register rs are lo aded int o special regist er HI . If a MTHI op eration is e[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 532 Preliminary User ’ s Manu al S155 43EJ 1V0U M MTLO Move To LO MTLO rs SPECI AL 0 0 0 0 0 0 MTLO 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 6 5 0 65 6 15 Format: MTLO rs Description: The contents of gener al register rs are lo aded int o special regist er LO. If an M TLO operat io[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 533 MULT Mult ip ly MULT rs SPECIAL 0 0 0 0 0 0 MULT 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 6 5 0 65 6 10 rt 5 16 15 Format: MULT rs, rt Description: The contents of gener al regi sters rs and rt are multi plied, tr eating b oth oper ands a s signed[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 534 Preliminary User ’ s Manu al S155 43EJ 1V0U M MULTU Mult ip ly Uns ig ned MULTU rs SPECIAL 0 0 0 0 0 0 MULT U 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 6 5 0 65 6 10 rt 5 16 15 Format: MULTU rs, rt Description: The contents of gener al regi ster rs and the c ontents of genera l register r[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 535 NOR Nor NOR rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 NOR 1 0 0 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: NOR rd, rs, rt Description: The contents of gener al regi ster rs are comb ined w ith the content s of gen eral reg ister rt in a bit-w [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 536 Preliminary User ’ s Manu al S155 43EJ 1V0U M OR Or OR rs SPECI AL 000000 rt rd 0 00000 OR 1 0 0 1 0 1 31 26 25 21 20 16 15 11 10 6 5 0 65 5 5 56 Format: OR rd, rs, rt Description: The contents of gener al regi ster rs are comb ined w ith the cont ents of general register rt in a bit-w ise logic[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 537 ORI Or Immediate ORI rs ORI 0 0 1 1 0 1 rt imme diate 31 26 25 21 20 16 15 0 65 5 1 6 Format: ORI rt, rs, imm ediate Description: The 16-bit immediat e is zero-ex tended and combi ned w ith the content s of gen eral regi ster rs in a bit-wis e logica l OR[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 538 Preliminary User ’ s Manu al S155 43EJ 1V0U M SB Store By te SB base SB 1 0 1 0 0 0 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: SB rt, offset (bas e) Description: The 16-bit offset is sign-extend ed and added to the content s of general register base to form a virtual address. The least-s[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 539 SD Store Do ubleword SD base SD 1 1 1 1 1 1 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: SD rt, offset (bas e) Description: The 16-bit offset is sign-extend ed and added to the content s of general register base to form a virtual addres s. The conte[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 540 Preliminary User ’ s Manu al S155 43EJ 1V0U M SDL Store Doublew ord Left (1/3) SDL base SDL 1 0 1 1 0 0 rt offset 31 26 25 21 20 16 15 0 65 5 1 6 Format: SDL rt, offset ( base) Description: This instru ction c an be u sed with t he SDR in structi on to st ore the content s of a regist er into ei[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 541 SDL Store Doubleword Left (2/3) SDL An address error exception is not occurr ed that specif y address i s not l ocated in doub leword bou ndary. This oper ation is d efined i n 64-bit mo de or in 32-bit k ernel mode. Execut ion of th is instru ction in 32[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 542 Preliminary User ’ s Manu al S155 43EJ 1V0U M SDL Store Doublew ord Left (3/3) SDL Given a do ubleword i n a regi ster and a doubl eword in m emory, the operati on of SDL i nstructi on is as foll ows: B C D E F G A H J K L M N O I P Register Mem o r y SDL vAddr2..0 Destination Ty pe Offset (LEM)[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 543 SDR Store Doublew ord Right (1/3) SDR base SDR 1 0 1 1 0 1 rt offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: SDR rt, offset (base) Description: This in structio n c an be u sed with t he SDL ins tructio n to stor e the co ntents of a regi ster into eig h[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 544 Preliminary User ’ s Manu al S155 43EJ 1V0U M SDR Store Doubl eword Ri ght (2/ 3) SDR An address error exception is not occurr ed that specif y address i s not l ocated in doub leword bou ndary. This oper ation is d efined i n 64-bit mo de or in 32-bit k ernel mode. Execut ion of th is instru ct[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 545 SDR Store Doubl eword Ri ght (3/ 3) SDR Given a do ubleword i n a regi ster and a doubl eword in m emory, the operati on of SDR instructio n is a s follow s: B C D E F G A H J K L M N O I P Register Mem o r y SDR vAddr2..0 Destination Ty pe Offset (LEM) 0[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 546 Preliminary User ’ s Manu al S155 43EJ 1V0U M SH Store Hal fw ord SH base SH 1 0 1 0 0 1 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: SH rt, offset (bas e) Description: The 16-bit offset is sign-extend ed and added to the contents of general register base to form a n unsig ned effe ctive a[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 547 SLL Shift Left Logi cal SLL SPECI AL 0 0 0 0 0 0 rt rd sa SLL 0 0 0 0 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 0 0 0 0 0 0 Format: SLL rd, rt, sa Description: The contents of gener al register rt are shifted left by sa bits, in sertin g zeros int o t[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 548 Preliminary User ’ s Manu al S155 43EJ 1V0U M SLLV Shift Left Logical Vari able SLLV SPECI AL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SLLV 0 0 0 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 rs Format: SLLV rd, rt, rs Description: The contents of gener al register rt are shifted left the number o f bits[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 549 SLT Set On L ess Th an SLT rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SLT 1 0 1 0 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: SLT rd, rs, rt Description: The contents of gener al regi ster rt are subtract ed from the cont ents of general reg ister[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 550 Preliminary User ’ s Manu al S155 43EJ 1V0U M SLTI Set On Less Than Immediate SLTI rs SLTI 0 0 1 0 1 0 rt imm ediate 31 26 25 21 20 16 15 0 65 5 1 6 Format: SLTI rt, rs, imm ediate Description: The 16-bit immediat e is s ign-extende d and s ubtracted from the c ontents of g eneral re gister rs. [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 551 SLTIU Set On L ess Th an Immed iate Uns igned SLTIU rs SLTIU 0 0 1 0 1 1 rt imm ediate 31 26 25 21 20 16 15 0 65 5 1 6 Format: SLTIU rt, rs, immedi ate Description: The 16-bit immediat e is s ign-extende d and s ubtracted from the c ontents of g eneral re[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 552 Preliminary User ’ s Manu al S155 43EJ 1V0U M SLTU Set On L ess Th an Un signe d SL TU rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SLTU 1 0 1 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: SLTU rd, rs, rt Description: The contents of gener al regi ster rt are subtract ed from the cont ents[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 553 SRA Shift Right A rithme tic SRA 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa SRA 0 0 0 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: SRA rd, rt, sa Description: The contents of gener al register rt are sh ift ed ri ght by sa bits, sig n-extendin g [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 554 Preliminary User ’ s Manu al S155 43EJ 1V0U M SRAV Shift Right A rithmetic Variable SRAV rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SRAV 0 0 0 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 65 5 5 56 Format: SRAV rd, rt, rs Description: The contents of gener al regi ster rt are shifted right b y the numbe[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 555 SRL Shift Right Lo gical SRL 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa SRL 0 0 0 0 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: SRL rd, rt, sa Description: The contents of gener al register rt are sh ift ed ri ght by sa bits, ins erting zero s int[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 556 Preliminary User ’ s Manu al S155 43EJ 1V0U M SRLV Shift Right Lo gical Vari able SRLV rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SRLV 0 0 0 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: SRLV rd, rt, rs Description: The contents of gener al regi ster rt are shifted right b y the num ber [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 557 STANDBY Standb y STANDBY 0 00 0 0 000 0000 000 0 00 00 COP0 0 1 0 0 0 0 STANDBY 1 0 0 0 0 1 31 26 25 6 5 0 61 9 6 CO 1 1 24 Format: STANDBY Description: STANDBY instruct ion start s mode transit ion from Ful lspeed mode to Stan dby m ode. When the STANDBY[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 558 Preliminary User ’ s Manu al S155 43EJ 1V0U M SUB Subtract SUB rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SUB 1 0 0 0 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: SUB rd, rs, rt Description: The contents of gener al regi ster rt are subtract ed from the content s of general register rs to[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 559 SUBU Subt ract Un signed SUBU rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SUBU 1 0 0 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: SUBU rd, rs, rt Description: The contents of gener al register rt are subtract ed from the content s of gen eral reg [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 560 Preliminary User ’ s Manu al S155 43EJ 1V0U M SUSPEND Suspen d SUSPEND 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 SUSPEN D 1 0 0 0 1 0 31 26 25 6 5 0 61 9 6 CO 1 1 24 Format: SUSPEND Description: SUSPEND instru ction start s mode tr ansiti on from Fullspeed m ode to S uspend mode. [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 561 SW Store Word SW base SW 1 0 1 0 1 1 rt off set 31 26 25 21 20 16 15 0 65 5 1 6 Format: SW rt, offset (ba se) Description: The 16-bit offset is sign-extend ed and added to the content s of general register base to form a virtual addres s. The contents of [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 562 Preliminary User ’ s Manu al S155 43EJ 1V0U M SWL Store Word Left (1/3) SWL base SW L 1 0 1 0 1 0 rt offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: SWL rt, offset (ba se) Description: This instru ction c an be u sed with t he SWR inst ruct ion to store the co ntents o f a regi ster into f our c[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 563 SWL Store Word Left (2/3) SWL Operation: 32 T: vAddr ← ((offset 15 ) 16 || offset 15...0 ) + GPR [base] (pAddr, uncached) ← AddressTranslation (vAddr, DA TA) pAddr ← pAddr PSIZE - 1...3 || (pAddr 2...0 x or ReverseEndian 3 ) if BigEndianMem = 0 then[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 564 Preliminary User ’ s Manu al S155 43EJ 1V0U M SWL Store Word Left (3 /3) SWL Given a do ubleword i n a regi ster and a doubl eword in m emory, the operati on of SWL is as fo llows: B C D E F G A H J K L M N O I P Register Mem o r y SWL vAddr2..0 Destination Type Of fset (LEM) 0 1 2 3 4 5 6 7 IJ [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 565 SWR Store Word Right (1/3 ) SWR base SW R 1 0 1 1 1 0 rt offs et 31 26 25 21 20 16 15 0 65 5 1 6 Format: SWR rt, offset ( base) Description: This in structio n c an b e used w ith t he SWL instru ction to store th e conte nts of a reg ister int o four c o[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 566 Preliminary User ’ s Manu al S155 43EJ 1V0U M SWR Store Word Right (2/3) SWR Operation: 32 T: vAddr ← ((offset 15 ) 16 || offset 15...0 ) + GPR [base] (pAddr, uncached) ← AddressT ranslation (vAddr, DAT A) pAddr ← pAddr PS IZE - 1...3 || (pA ddr 2...0 xor R everseEndian 3 ) if BigEndianMem[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 567 SWR Store Word Right (3/3) SWR Given a do ubleword i n a regi ster and a doubl eword in m emory, the operati on of SWR in structi on is a s follow s: B C D E F G A H J K L M N O I P Register Mem o r y SWR vAddr2.. 0 Destin at ion Type Off set (LEM) 0 1 2 [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 568 Preliminary User ’ s Manu al S155 43EJ 1V0U M SYNC Sy nchro ni ze SYNC SPECIAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 6 5 0 62 0 SYNC 0 0 1 1 1 1 6 Format: SYNC Description: The SYNC instru ction i s execute d as a NOP on the V R 4121. Th is oper ation main tains compat i[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 569 SYSC ALL S y stem Call SY SCALL SPECI AL 0 0 0 0 0 0 Code 31 26 25 6 5 0 62 0 SYSC ALL 0 0 1 1 0 0 6 Format: SYSCALL Description: A system c all except ion oc curs, im mediatel y and u ncondi tionally tr ansferring control to the ex ception handler . The [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 570 Preliminary User ’ s Manu al S155 43EJ 1V0U M TEQ Trap If Equal TEQ rs SPECI AL 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 65 5 1 0 TEQ 1 1 0 1 0 0 6 65 Format: TEQ rs, rt Description: The contents of gener al regi ster rt are com pared to general regist er rs . If t he cont ents of gener al r e[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 571 TEQI Trap If Eq ual Immed iate TEQI rs REGIM M 0 0 0 0 0 1 TEQ I 0 1 1 0 0 immediat e 31 26 25 21 20 16 15 0 65 5 1 6 Format: TEQI rs, immedi ate Description: The 16-bit immediat e is sign-exte nded and com pared to t he cont ents of g eneral r egister rs[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 572 Preliminary User ’ s Manu al S155 43EJ 1V0U M TGE Tra p If Gr ea ter Than O r Eq ual TGE rs SPECIAL 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 65 5 1 0 TGE 1 1 0 0 0 0 6 65 Format: TGE rs, rt Description: The conte nts of g eneral re gister rt are com pared to the co ntents o f genera l regist e[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 573 TGEI Trap I f Gre a ter Tha n Or Equa l Im me dia te TGEI rs REGIM M 0 0 0 0 0 1 TGE I 0 1 0 0 0 immediat e 31 26 25 21 20 16 15 0 65 5 1 6 Format: TGEI rs, immedi ate Description: The 16-bit immediat e is sign-ex tended an d com pared to t he cont ents o[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 574 Preliminary User ’ s Manu al S155 43EJ 1V0U M TGEIU T rap I f Gre ater Th an Or Equal I mmedi ate Un sign ed TGEIU rs REGIM M 0 0 0 0 0 1 TGE IU 0 1 0 0 1 immediat e 31 26 25 21 20 16 15 0 65 5 1 6 Format: TGEIU rs, imm ediate Description: The 16-bit immediat e is sign-ex tended an d com pared t[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 575 TGEU Trap If Greater Than Or Equal Unsi gned TGEU rs SPECI AL 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 65 5 1 0 TGE U 1 1 0 0 0 1 6 65 Format: TGEU rs, rt Description: The conte nts of g eneral re gister rt are com pared to the co ntents o f genera l re[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 576 Preliminary User ’ s Manu al S155 43EJ 1V0U M TLBP Probe T LB For Matching Entry TLBP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 TLB P 0 0 1 0 0 0 31 26 25 6 5 0 61 9 6 CO 1 1 24 Format: TLBP Description: The Index reg ister i s loade d with the addres s of the T LB entry wh ose co[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 577 TLBR Read I nde xed TLB En tr y TLBR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 TLB R 0 0 0 0 0 1 31 26 25 6 5 0 61 9 6 CO 1 1 24 Format: TLBR Description: The EntryHi and EntryL o regist ers are loaded wi th the c ontents of t he TLB entr y[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 578 Preliminary User ’ s Manu al S155 43EJ 1V0U M TLBWI Write Indexed TL B Entry TLBWI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 TLB W I 0 0 0 0 1 0 31 26 25 6 5 0 61 9 6 CO 1 1 24 Format: TLBWI Description: The TLB entr y p ointed at by the contents o f the TLB Inde x regist er is lo[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 579 TLBWR Wri te Random TLB E ntr y TLBWR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 TLB W R 0 0 0 1 1 0 31 26 25 6 5 0 61 9 6 CO 1 1 24 Format: TLBWR Description: The TLB entr y point ed at by the content s of the TLB Ra ndom regis ter is load [...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 580 Preliminary User ’ s Manu al S155 43EJ 1V0U M TLT Trap If Le ss Tha n TLT rs SPECIAL 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 65 5 1 0 TLT 1 1 0 0 1 0 6 65 Format: TLT rs, rt Description: The contents of gener al regi ster rt are com pared to general register rs . Con siderin g both qua ntitie[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 581 TLTI T rap If Less T han Imme diate TLT I rs REGIM M 0 0 0 0 0 1 TLTI 0 1 0 1 0 immediat e 31 26 25 21 20 16 15 0 65 5 1 6 Format: TLTI rs, immedia te Description: The 16-bit immediat e is sign-ex tended an d com pared to t he cont ents of gener al r egis[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 582 Preliminary User ’ s Manu al S155 43EJ 1V0U M TLTIU Trap If Less T han Immediat e Unsig ned TLTIU rs REGIM M 0 0 0 0 0 1 TLTI U 0 1 0 1 1 immediat e 31 26 25 21 20 16 15 0 65 5 1 6 Format: TLTIU rs, im mediate Description: The 16-bit immediat e is sign-ex tended an d com pared to t he cont ents [...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 583 TLTU T rap If Less T han Uns igned TLTU rs SPECIAL 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 65 5 1 0 TLTU 1 1 0 0 1 1 6 65 Format: TLTU rs, rt Description: The contents of gener al regi ster rt are com pared to general regist er rs . Con sidering both q[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 584 Preliminary User ’ s Manu al S155 43EJ 1V0U M TNE Trap If Not Equal TNE rs SPECI AL 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 65 5 1 0 TNE 1 1 0 1 1 0 6 65 Format: TNE rs, rt Description: The contents of gener al register rt are com pared to general regist er rs . If t he cont ents of general r[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 585 TNEI Trap If Not Eq ual Immediate TNEI rs REGIM M 0 0 0 0 0 1 TNE I 0 1 1 1 0 immediat e 31 26 25 21 20 16 15 0 65 5 1 6 Format: TNEI rs, immedi ate Description: The 16-bit immediat e is sign-exte nded and com pared to t he cont ents of g eneral r egister[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 586 Preliminary User ’ s Manu al S155 43EJ 1V0U M XOR Excl usive O r XOR rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 XOR 1 0 0 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: XOR rd, rs, rt Description: The contents of gener al regi ster rs are comb ined w ith the content s of gen eral regist e[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 587 XORI Excl usi ve OR I mm ediat e XORI rs XORI 0 0 1 1 1 0 rt imm ediate 31 26 25 21 20 16 15 0 65 5 1 6 Format: XORI rt, rs, immedi ate Description: The 16-bit immediat e is zero-ex tended and combi ned w ith the content s of gen eral regi ster rs in a bi[...]

APPEND IX A MIPS II I INS T RUCTION SET DETAILS 588 Preliminary User ’ s Manu al S155 43EJ 1V0U M A.6 CPU Instruction Opcode Bit Encoding Figure A-1 list s the V R 4120A Op code Bit En codin g. Figure A-1. V R 412 0A Opcode B it Encoding (1/2) 28...26 O pcode 31...29 01234567 0 SPECIAL REG IMM J JAL BEQ BNE BLEZ BGTZ 1 ADDI ADDIU S LTI SLT IU AND[...]

APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User ’ s Manu al S155 43EJ 1V0UM 589 Figure A-1. V R 412 0AOpcode Bit Encodi ng (2/2) 23...21 COP0 rs 2 5 , 2 4 01234567 0M F D M F εγ γ MT DMT εγ γ 1B C γγγγ γγγ 2C O 3 18...16 COP0 rt 20...19 01234567 0 B CF B CT B CFL BCTL γγγγ 1 γγγγγγγγ 2 γγγγγγγγ 3 γγ[...]

590 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M APPENDIX B V R 4120A COPROCESSO R 0 HAZARD S The V R 4120A core avo ids conte ntion of its int ernal re source s by ca using a pi peline i nterlo ck in such case s as when the contents of the d estinat ion regi ster of a n instru ction are used as a sour ce in th e succ eeding instruct ion. T her[...]

APPEND IX B V R 4120A COPROCESSOR 0 HAZARDS Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 591 Table B-1. V R 41 20A CPU Copr ocessor 0 Hazards Operation Sourc e Destination Source Name No. of Cycle s Destination Nam e No. of Cycle s MTC0 cpr rd 5 MFC0 cpr rd 3 TLBR Index, TLB 2 PageMask, Entry Hi, EntryLo0, EntryLo1 5 TLBWI TLBWR Index or Random,[...]

APPEND IX B V R 4120A COPROCESSOR 0 HAZARDS 592 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Remarks 1 . The instr uction f ollowin g MTC0 m ust not b e MFC0. 2. The five in structio ns foll owing M TC0 to Statu s regist er that chan ges KSU and sets EXL and ERL may be exe cuted i n the new m ode, a nd not kerne l mode. This can be avoided by s[...]

APPEND IX B V R 4120A COPROCESSOR 0 HAZARDS Prelimi nary Us er’s Ma nual S 155 43EJ1V 0UM 593 (10) Instruction Fetch Source: The conf irmation of the o perating mode and T LB nece ssary fo r instru ction f etch. Examples 1. When changi ng the operat ing mod e from Us er to Kerne l and fetch ing instru ctions after the KSU, EXL, and ERL b its of t[...]

APPEND IX B V R 4120A COPROCESSOR 0 HAZARDS 594 Prelimi nary Us er’s Ma nual S 155 43EJ1V 0U M Table B-2 indi cates e xampl es of cal culatio n. Table B-2. Calc ulation Exam ple of CP0 H azard a nd Number of In struction s Inserted Destination Sourc e Contending Intern al Resource Number of Instruc tions Inser ted Formula TLBWR/TLBWI TLBP TLB Ent[...]

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