Nexus 21 NEX DDR3INTR THIN Bedienungsanleitung

DDR3THIN-MN-XXX 1 Doc. Rev. 1.11 NEX-DDR3INTR-THIN DDR3 800/1066MT/s Interposer For use with the TLA7BB4 Logic Analyzer Modules Including these Software Support packages: B_DDR3D_2D (Single/Dual/Quad Rank, single slot with Selective Clocking) *B_DDR3D_2G (2 or 3 DIMM slots, two Rank @ 800MT/s) *B_DDR3D_3A (2 DIMM slots, two Rank @ 1066MT/s) * Optio[...]

DDR3THIN-MN-XXX 2 Doc. Rev. 1.11 Product Warranty Due to wide variety of possible customer target implementations, this product has a 30 day acceptance period by the customer from the date of receipt. If the customer does not contact Nexus Technology within 30 days of the receipt of the product, it will be said that the customer has accepted the pr[...]

DDR3THIN-MN-XXX 3 Doc. Rev. 1.11 License Agreement In return for payment for this product, Nexus Technology grants the Customer a SINGLE user LICENSE in the software subject to the following: Use of the Software: - Custom er may use the software on only one Tektronix mainframe logic analysis system at any given time - Custom er may make copies or a[...]

DDR3THIN-MN-XXX 4 Doc. Rev. 1.11 TABLE OF CONTENTS 1.0 OVERVIEW ................................................................................................................. .......... 9 1.1 General Information ...................................................................................................... ...... 9 1.2 Software Package de[...]

DDR3THIN-MN-XXX 5 Doc. Rev. 1.11 B.3 TLA7BB4 Module to module skew .................................................................................. 75 APPENDIX C – 240-pin DDR3 DIMM Pinout ........................................................................... 76 APPENDIX D –Data Flow Through the Probes (coax cable to channel) ...........[...]

DDR3THIN-MN-XXX 6 Doc. Rev. 1.11 TABLE OF FIGURES Figure 1 – Drawing of Interposer with probes attached ............................................................... 15 Figure 2 – Samtec connector on the LEASH probe...................................................................... 16 Figure 3 – LEASH probe to NEX-PRB1X/2X connection ...[...]

DDR3THIN-MN-XXX 7 Doc. Rev. 1.11 TABLE OF TABLES Table 1 - B_DDR3D_2D (<=1066MT/s Read and Write) TLA Channel Grouping .................... 19 Table 2 - B_DDR3D_2G (<=1066MT/s Read and Write) TLA Channel Grouping .................... 25 Table 3 - B_DDR3D_3A (<=1066MT/s Read and Write) TLA Channel Grouping .................... 31 Table 4 - [...]

DDR3THIN-MN-XXX 8 Doc. Rev. 1.11[...]

DDR3THIN-MN-XXX 9 Doc. Rev. 1.11 1.0 OVERVIEW 1.1 General Information The DDR3 Interposer Products are designed for ease of use. Interposers extra signal trace length, also an extra connector that might affect the quality of the system operation in some systems. • This Product is designed for capture of 1066MT/s or slower, and may only be used wi[...]

DDR3THIN-MN-XXX 10 Doc. Rev. 1.11 NEX-DDR3INTR-THIN Interposer products. This support can be used with Single Rank and Dual Rank DIMMs. Note that this manual uses some term s generically. For instance, references to the TLA700/7000 apply to all suitable TLA700/7000 Logic Analyzers, or PCs being used to control the TLA. NEX-DDR3INTR-THIN refers to t[...]

DDR3THIN-MN-XXX 11 Doc. Rev. 1.11 1.3 Eye size required The Eye size (stable data) required at the input resistor to the Nexus passive probes (NEX- PRB1X(-T) & NEX-PRB2X(-T)) is 330ps, and 0.2V. Capture accuracy may be affected if a stable eye can not meet this requirement. . The eye is a perfectly shaped diam ond with each side equal distant f[...]

DDR3THIN-MN-XXX 12 Doc. Rev. 1.11 3.0 CONNECTING to the NEX-DDR3INTR-THIN INTERPOSER 3.1 General Care should be taken to support the weight of th e acquisition probes so that the Logic Analyzer Interposer board and/or target socket are not damaged. 3.2 B_DDR3D_2D Support To acquire DDR3 Read and Write data at speeds up to 1066MT/s requires two merg[...]

DDR3THIN-MN-XXX 13 Doc. Rev. 1.11 TLA Master Connect the NEX-PRB1X-T “C” probe head to DDR3 Interposer’s LEASH (soldered-on coax cable) that is attached to “M_C” position on the Interposer. Connect the NEX-PRB2X-T A3/2 & A1/0 probe head to DDR3 Interposer’s LEASH that is attached to “M_ A3/2 A1/0” position on the Interposer. Con[...]

DDR3THIN-MN-XXX 14 Doc. Rev. 1.11 TLA Slave1 Connect the NEX-PRB2X-T A3/2 & A1/0 probe head to DDR3 Interposer’s LEASH that is attached to “S_ A3/2 A1/0” position on the Interposer. Connect the NEX-PRB2X-T “C3/2” & “E3/2” probe head to DDR3 Interposer’s LEASH that is attached to “S_C3/2 E3/2” position on the Interposer. [...]

DDR3THIN-MN-XXX 15 Doc. Rev. 1.11 3.5 Short “LEASH” probes The standard product includes 4 “LEASH” probes connected to this Interposer product. These short probes are soldered directly onto the interposer and interface the Interposer to the Passive probes that connect to the logic analyzer. These “LEASH” probes are to allow the user to [...]

DDR3THIN-MN-XXX 16 Doc. Rev. 1.11 The strain relief on the LEASH to NEXPRB1X/2X interface, while designed for bench handling, can be damaged by twisting the coax cables. Bends of over 45 degrees in this area should be avoided. The coax connection points, under any circumstances, are not to be bent. 3.5.1 Samtec connector on the LEASH probe pins Fig[...]

DDR3THIN-MN-XXX 17 Doc. Rev. 1.11 3.5.2 LEASH probe to NEX-PRB1X/2X connection Figure 3 – LEASH probe to NEX-PRB1X/2X connection 3.5.3 Alternate use of NEX-PRB1X or NEX-PRB2X probes The NEX-PRB1X or NEX-PRB2X can be used in place of the “-T” probes but will have to be secured for long term connection by tie-wraps. Two each plastic Spacers Scr[...]

DDR3THIN-MN-XXX 18 Doc. Rev. 1.11 3.6 Slot Numbering The Interposer must be installed in the furthest slot from the m emory controller. For 1066MT/s support only the two furthest slots may be used. Slots are named as shown below: Slot naming for a three slot system Memory controller Slot C Slot B Slot A S0-3# CLKE0- bS0-1# bCLKE0-1 (from NEX- PRBCO[...]

DDR3THIN-MN-XXX 19 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input RdA_DatHi RD_A_DQ63 234 S_A2:0 RdA_DatLo RD_A_DQ31 156 M_A0:6 (Hex) RD_A_DQ62 233 S_A2:1 (Hex) RD_A_DQ30 155 M_A0:3 RD_A_DQ61 228 S_A2:5 RD_A_DQ29 150 S_C2:0 RD_A_DQ60 227 S_CK0 RD_A_DQ28 149 S_C2:1 RD_A_DQ59 115 S_A2:2 RD_A_DQ2[...]

DDR3THIN-MN-XXX 20 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin# TLA Input Group Name Signal Name DDR3 Pin# TLA Input RdB_DatHi RD_B_DQ63 234 S_A2:0^1 RdB_DatLo RD_B_DQ31 156 M_A0:6^1 (Hex) RD_B_DQ62 233 S_A2:1^1 (Hex) RD_B_DQ30 155 M_A0:3^1 RD_B_DQ61 228 S_A2:5^1 RD_B_DQ29 150 S_C2:0^1 RD_B_DQ60 227 S_CK0^1 RD_B_DQ28 149 S_C2:1^1 RD_B_DQ59 115 S[...]

DDR3THIN-MN-XXX 21 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input WrA_DatHi WR_A_DQ63 234 S_D2:0 WrA_DatLo WR_A_DQ31 156 M_D0:6 (Hex) WR_A_DQ62 233 S_D2:1 (Hex) WR_A_DQ30 155 M_D0:3 WR_A_DQ61 228 S_D2:5 WR_A_DQ29 150 S_C0:0 WR_A_DQ60 227 S_Q1 WR_A_DQ28 149 S_C0:1 WR_A_DQ59 115 S_D2:2 WR_A_DQ27[...]

DDR3THIN-MN-XXX 22 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input WrB_DatHi WR_B_DQ63 234 S_D2:0^1 WrB_DatLo WR_B_DQ31 156 M_D0:6^1 (Hex) WR_B_DQ62 233 S_D2:1^1 (Hex) WR_B_DQ30 155 M_D0:3^1 WR_B_DQ61 228 S_D2:5^1 WR_B_DQ29 150 S_C0:0^1 WR_B_DQ60 227 S_Q1^1 WR_B_DQ28 149 S_C0:1^1 WR_B_DQ59 115 [...]

DDR3THIN-MN-XXX 23 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input RdAChkBits RD_A_CB7 165 M_A1:5 WrAChkBits 4 WR_A_CB7 165 M_D1:5 (OFF) RD_A_CB6 164 M_A1:4 (OFF) WR_A_CB6 164 M_D1:4 RD_A_CB5 159 M_A1:0 WR_A_CB5 159 M_D1:0 RD_A_CB4 158 M_A0:7 WR_A_CB4 158 M_D0:7 RD_A_CB3 46 M_A1:6 WR_A_CB3 46 M[...]

DDR3THIN-MN-XXX 24 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input Control 2 CKE1 169 M_A3:2 Address 2 BA2 52 M_A3:0 (SYM) CKE0 50 M_A3:1 (Hex) BA1 190 M_C3:7 S3# 49 M_C2:5 BA0 71 M_C1:6 S2# 48 M_C3:0 A15 171 M_CK0 S1# 76 M_C3:4 A14 172 M_A2:5 S0# 193 M_C3:3 A13 196 M_CK3 BA2 52 M_A3:0 A12/BC# [...]

DDR3THIN-MN-XXX 25 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input RdA_DatHi RD_A_DQ63 234 S_A2:0 RdA_DatLo RD_A_DQ31 156 M_A0:6 (Hex) RD_A_DQ62 233 S_A2:1 (Hex) RD_A_DQ30 155 M_A0:3 RD_A_DQ61 228 S_A2:5 RD_A_DQ29 150 S_C2:0 RD_A_DQ60 227 S_CK0 RD_A_DQ28 149 S_C2:1 RD_A_DQ59 115 S_A2:2 RD_A_DQ2[...]

DDR3THIN-MN-XXX 26 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin# TLA Input Group Name Signal Name DDR3 Pin# TLA Input RdB_DatHi RD_B_DQ63 234 S_A2:0^1 RdB_DatLo RD_B_DQ31 156 M_A0:6^1 (Hex) RD_B_DQ62 233 S_A2:1^1 (Hex) RD_B_DQ30 155 M_A0:3^1 RD_B_DQ61 228 S_A2:5^1 RD_B_DQ29 150 S_C2:0^1 RD_B_DQ60 227 S_CK0^1 RD_B_DQ28 149 S_C2:1^1 RD_B_DQ59 115 S[...]

DDR3THIN-MN-XXX 27 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input WrA_DatHi WR_A_DQ63 234 S_D2:0 WrA_DatLo WR_A_DQ31 156 M_D0:6 (Hex) WR_A_DQ62 233 S_D2:1 (Hex) WR_A_DQ30 155 M_D0:3 WR_A_DQ61 228 S_D2:5 WR_A_DQ29 150 S_C0:0 WR_A_DQ60 227 S_Q1 WR_A_DQ28 149 S_C0:1 WR_A_DQ59 115 S_D2:2 WR_A_DQ27[...]

DDR3THIN-MN-XXX 28 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input WrB_DatHi WR_B_DQ63 234 S_D2:0^1 WrB_DatLo WR_B_DQ31 156 M_D0:6^1 (Hex) WR_B_DQ62 233 S_D2:1^1 (Hex) WR_B_DQ30 155 M_D0:3^1 WR_B_DQ61 228 S_D2:5^1 WR_B_DQ29 150 S_C0:0^1 WR_B_DQ60 227 S_Q1^1 WR_B_DQ28 149 S_C0:1^1 WR_B_DQ59 115 [...]

DDR3THIN-MN-XXX 29 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input RdAChkBits RD_A_CB7 165 M_A1:5 WrAChkBits 4 WR_A_CB7 165 M_D1:5 (OFF) RD_A_CB6 164 M_A1:4 (OFF) WR_A_CB6 164 M_D1:4 RD_A_CB5 159 M_A1:0 WR_A_CB5 159 M_D1:0 RD_A_CB4 158 M_A0:7 WR_A_CB4 158 M_D0:7 RD_A_CB3 46 M_A1:6 WR_A_CB3 46 M[...]

DDR3THIN-MN-XXX 30 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input Control 2 cCKE1 From Slot C M_E3:5 Address 2 BA2 52 M_A3:0 (SYM) cCKE0 From Slot C M_E3:4 (Hex) BA1 190 M_C3:7 bCLK1 From Slot B M_Q2 BA0 71 M_C1:6 bCLK0 From Slot B M_E1:7 A15 171 M_CK0 CKE1 169 M_A3:2 A14 172 M_A2:5 CKE0 50 M_[...]

DDR3THIN-MN-XXX 31 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input RdA_DatHi RD_A_DQ63 234 S_A2:0 RdA_DatLo RD_A_DQ31 156 M_A0:6 (Hex) RD_A_DQ62 233 S_A2:1 (Hex) RD_A_DQ30 155 M_A0:3 RD_A_DQ61 228 S_A2:5 RD_A_DQ29 150 S_C2:0 RD_A_DQ60 227 S_CK0 RD_A_DQ28 149 S_C2:1 RD_A_DQ59 115 S_A2:2 RD_A_DQ2[...]

DDR3THIN-MN-XXX 32 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin# TLA Input Group Name Signal Name DDR3 Pin# TLA Input RdB_DatHi RD_B_DQ63 234 S_A2:0^1 RdB_DatLo RD_B_DQ31 156 M_A0:6^1 (Hex) RD_B_DQ62 233 S_A2:1^1 (Hex) RD_B_DQ30 155 M_A0:3^1 RD_B_DQ61 228 S_A2:5^1 RD_B_DQ29 150 S_C2:0^1 RD_B_DQ60 227 S_CK0^1 RD_B_DQ28 149 S_C2:1^1 RD_B_DQ59 115 S[...]

DDR3THIN-MN-XXX 33 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input 1_RdA_DatHi 1_RD_A_DQ63 234 S2_A0:0 1_RdA_DatLo 1_RD_A_DQ31 156 S2_D2:6 (Hex) 1_RD_A_DQ62 233 S2_A0:1 (Hex) 1_RD_A_DQ30 155 S2_D2:3 1_RD_A_DQ61 228 S2_A0:5 1_RD_A_DQ29 150 S2_E2:0 1_RD_A_DQ60 227 S2_CK1 1_RD_A_DQ28 149 S2_E2:1 1[...]

DDR3THIN-MN-XXX 34 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin# TLA Input Group Name Signal Name DDR3 Pin# TLA Input 1_RdB_DatHi 1_RD_B_DQ63 234 S2_A0:0^1 1_RdB_DatLo 1_RD_B_DQ31 156 S2_D2:6^1 (Hex) 1_RD_B_DQ62 233 S2_A0:1^1 (Hex) 1_RD_B_DQ30 155 S2_D2:3^1 1_RD_B_DQ61 228 S2_A0:5^1 1_RD_B_DQ29 150 S2_E2:0^1 1_RD_B_DQ60 227 S2_CK1^1 1_RD_B_DQ28 1[...]

DDR3THIN-MN-XXX 35 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input WrA_DatHi WR_A_DQ63 234 S_D2:0 WrA_DatLo WR_A_DQ31 156 M_D0:6 (Hex) WR_A_DQ62 233 S_D2:1 (Hex) WR_A_DQ30 155 M_D0:3 WR_A_DQ61 228 S_D2:5 WR_A_DQ29 150 S_C0:0 WR_A_DQ60 227 S_Q1 WR_A_DQ28 149 S_C0:1 WR_A_DQ59 115 S_D2:2 WR_A_DQ27[...]

DDR3THIN-MN-XXX 36 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input WrB_DatHi WR_B_DQ63 234 S_D2:0^1 WrB_DatLo WR_B_DQ31 156 M_D0:6^1 (Hex) WR_B_DQ62 233 S_D2:1^1 (Hex) WR_B_DQ30 155 M_D0:3^1 WR_B_DQ61 228 S_D2:5^1 WR_B_DQ29 150 S_C0:0^1 WR_B_DQ60 227 S_Q1^1 WR_B_DQ28 149 S_C0:1^1 WR_B_DQ59 115 [...]

DDR3THIN-MN-XXX 37 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input RdAChkBits RD_A_CB7 165 M_A1:5 WrAChkBits 4 WR_A_CB7 165 M_D1:5 (OFF) RD_A_CB6 164 M_A1:4 (OFF) WR_A_CB6 164 M_D1:4 RD_A_CB5 159 M_A1:0 WR_A_CB5 159 M_D1:0 RD_A_CB4 158 M_A0:7 WR_A_CB4 158 M_D0:7 RD_A_CB3 46 M_A1:6 WR_A_CB3 46 M[...]

DDR3THIN-MN-XXX 38 Doc. Rev. 1.11 Group Name Signal Name DDR3 Pin # TLA Input Group Name Signal Name DDR3 Pin # TLA Input Control 2 CKE1 169 M_A3:2 Address 2 BA2 52 M_A3:0 (SYM) CKE0 50 M_A3:1 (Hex) BA1 190 M_C3:7 S3# 49 S2_C2:5 BA0 71 M_C1:6 S2# 48 S2_C3:0 A15 171 M_CK0 S1# 76 M_C3:4 A14 172 M_A2:5 S0# 193 M_C3:3 A13 196 M_CK3 BA2 52 M_A3:0 A12/BC[...]

DDR3THIN-MN-XXX 39 Doc. Rev. 1.11 3.7 Display Groups not in Tables 1,2 or 3 There are several groups in the List window that are not documented in the tables as these groups are used only by the post-processing display software. To ensure correct data display these groups must not be modified. These groups are: • DataHi • DataLo • ChekBits ?[...]

DDR3THIN-MN-XXX 40 Doc. Rev. 1.11 4.0 CLOCK SELECTION 4.1 B_DDR3D_2D Clocking Selections There are two clocking option fields available when using the B_DDR3D_2D support package. These select fields permit the user to setup the TLA acquisition as follows: SDRAM Clocking: – Permits selecting the Clocking Mode to be used to acquire DDR3 data. It is[...]

DDR3THIN-MN-XXX 41 Doc. Rev. 1.11 Latency of <= 5 cycles the support software will store a total of 13 clock cycles worth of data after the Read or Write Comm and appears on the bus. Refresh Cycles: – Permits choosing whether Refresh Cycles will be stored or not. The field choices are: Acquire (default) – Refresh Cycles will be stored. Do No[...]

DDR3THIN-MN-XXX 42 Doc. Rev. 1.11 C:____B:_0__A:___0 0r1r1r – bS0# in the slot between the Interposer and the memory controller and S0# in the Interposer slot are active, equivalent to two Single Rank DIMMs. C:____B:_0__A:__10 0r1r2r – bS0#, S0# and S1# are active, equivalent to one Single Rank DIMM and one Dual Rank DIMM. C:____B:10__A:___0 0r[...]

DDR3THIN-MN-XXX 43 Doc. Rev. 1.11 4.3 B_DDR3D_3A Clocking Selections There is one clocking option field available when using the B_DDR3D_3A support package. This select field sets up the TLA acquisition as follows: SDRAM DDR CLK0 Clocking: – Permits selecting the Clocking Mode to be used to acquire DDR3 data. Only one choice is available: Every R[...]

DDR3THIN-MN-XXX 44 Doc. Rev. 1.11 5.0 CONFIGURING FOR RE AD / WRITE DATA ACQUISITION Prior to configuring your NEX-DDR3INTR-THIN support package it is strongly recomm ended that Appendix A (“How DDR Data is Clocked” ), section 5.4 (“Selecting DDR Read Sample Points”) and section 5.5. (“Selecting DDR Write Sample Points”) be read. This b[...]

DDR3THIN-MN-XXX 45 Doc. Rev. 1.11 Group Name Signal Name TLA Input Group Name Signal Name TLA Input Data_H i DQ63 S_A2:0 Data_L o DQ31 M_A0:6 DQ62 S_A2:1 DQ30 M_A0:3 DQ61 S_A2:5 DQ29 S_C2:0 DQ60 S_CK0 DQ28 S_C2:1 DQ59 S_A2:2 DQ27 M_A0:4 DQ58 S_A2:3 DQ26 M_A0:1 DQ57 S_A2:7 DQ25 S_C2:2 DQ56 S_A3:0 DQ24 S_C2:3 DQ55 S_A3:2 DQ23 S_C2:4 DQ54 S_A3:3 DQ22 [...]

DDR3THIN-MN-XXX 46 Doc. Rev. 1.11 Group Name Signal Name TLA Input Group Name Signal Name TLA Input DataByte 7 DQ63 S_A2:0 DataByte 3 DQ31 M_A0:6 DQ62 S_A2:1 DQ30 M_A0:3 DQ61 S_A2:5 DQ29 S_C2:0 DQ60 S_CK0 DQ28 S_C2:1 DQ59 S_A2:2 DQ27 M_A0:4 DQ58 S_A2:3 DQ26 M_A0:1 DQ57 S_A2:7 DQ25 S_C2:2 DQ56 S_A3:0 DQ24 S_C2:3 DataByte 6 DQ55 S_A3:2 DataByte 2 DQ2[...]

DDR3THIN-MN-XXX 47 Doc. Rev. 1.11 Group Name Signal Name TLA Input Group Name Signal Name TLA Input CheckBit s CB7 M_A1:5 DataMasks DM7 S_A2:4 CB6 M_A1:4 DM6 S_A3:6 CB5 M_A1:0 DM5 S_A1:0 CB4 M_A0:7 DM4 M_C2:0 CB3 M_A1:6 DM3 M_A0:2 CB2 M_A1:3 DM2 S_CK3 CB1 M_CK1 DM1 S_E3:5 CB0 M_A0:5 DM0 S_E2:6 Strobes 2 DQS8 M_A1:2 Address 2 BA2 M_A3:0 DQS7 S_A2:6 [...]

DDR3THIN-MN-XXX 48 Doc. Rev. 1.11 Group Name Signal Name TLA Input Group Name Signal Name TLA Input Data_H i DQ63 S_A2:0 Data_L o DQ31 M_A0:6 DQ62 S_A2:1 DQ30 M_A0:3 DQ61 S_A2:5 DQ29 S_C2:0 DQ60 S_CK0 DQ28 S_C2:1 DQ59 S_A2:2 DQ27 M_A0:4 DQ58 S_A2:3 DQ26 M_A0:1 DQ57 S_A2:7 DQ25 S_C2:2 DQ56 S_A3:0 DQ24 S_C2:3 DQ55 S_A3:2 DQ23 S_C2:4 DQ54 S_A3:3 DQ22 [...]

DDR3THIN-MN-XXX 49 Doc. Rev. 1.11 Group Name Signal Name TLA Input Group Name Signal Name TLA Input DataByte 7 DQ63 S_A2:0 DataByte 3 DQ31 M_A0:6 DQ62 S_A2:1 DQ30 M_A0:3 DQ61 S_A2:5 DQ29 S_C2:0 DQ60 S_CK0 DQ28 S_C2:1 DQ59 S_A2:2 DQ27 M_A0:4 DQ58 S_A2:3 DQ26 M_A0:1 DQ57 S_A2:7 DQ25 S_C2:2 DQ56 S_A3:0 DQ24 S_C2:3 DataByte 6 DQ55 S_A3:2 DataByte 2 DQ2[...]

DDR3THIN-MN-XXX 50 Doc. Rev. 1.11 Group Name Signal Name TLA Input Group Name Signal Name TLA Input Data_Hi_1 1_DQ63 S2_A0:0 Data_Lo_ 1 1_DQ31 S2_D2:6 1_DQ62 S2_A0:1 1_DQ30 S2_D2:3 1_DQ61 S2_A0:5 1_DQ29 S2_E2:0 1_DQ60 S2_CK1 1_DQ28 S2_E2:1 1_DQ59 S2_A0:2 1_DQ27 S2_D2:4 1_DQ58 S2_A0:3 1_DQ26 S2_D2:1 1_DQ57 S2_A0:7 1_DQ25 S2_E2:2 1_DQ56 S2_A1:0 1_DQ2[...]

DDR3THIN-MN-XXX 51 Doc. Rev. 1.11 Group Name Signal Name TLA Input Group Name Signal Name TLA Input DataByte7_ 1 1_DQ63 S2_A0:0 DataByte3_ 1 1_DQ31 S2_D2:6 1_DQ62 S2_A0:1 1_DQ30 S2_D2:3 1_DQ61 S2_A0:5 1_DQ29 S2_E2:0 1_DQ60 S2_CK1 1_DQ28 S2_E2:1 1_DQ59 S2_A0:2 1_DQ27 S2_D2:4 1_DQ58 S2_A0:3 1_DQ26 S2_D2:1 1_DQ57 S2_A0:7 1_DQ25 S2_E2:2 1_DQ56 S2_A1:0 [...]

DDR3THIN-MN-XXX 52 Doc. Rev. 1.11 Group Name Signal Name TLA Input Group Name Signal Name TLA Input ChkBits CB7 M_A1:5 ChkBits_1 1_CB7 S2_D3:5 CB6 M_A1:4 1_CB6 S2_D3:4 CB5 M_A1:0 1_CB5 S2_D3:0 CB4 M_A0:7 1_CB4 S2_D2:7 CB3 M_A1:6 1_CB3 S2_D3:6 CB2 M_A1:3 1_CB2 S2_D3:3 CB1 M_CK1 1_CB1 S2_Q0 CB0 M_A0:5 1_CB0 S2_D2:5 Strobes 2 DQS8 M_A1:2 Strobes_1 2 1[...]

DDR3THIN-MN-XXX 53 Doc. Rev. 1.11 5.3 Adjusting Input Thresholds for Proper Data Acquisition The Interposer DDR3 support was designed to work with the new Nexus Low Profile Distributed probes. To maximize the electrical characteristics of the acquired waveform s the probe input resistors values were placed at 510 ohms. This value results in a divid[...]

DDR3THIN-MN-XXX 54 Doc. Rev. 1.11 Figure 4 - Read Data Latency = CAS Latency + CAS Additive Latency + RDIMM (5+0+1) = 6 cycles) 5.6 Selecting B_DDR3D_XX Write Data Sample Points Unlike valid DDR Read data, valid Write data is bisected by the Strobes. Since valid DDR3 Write data is bisected by the Strobes (see Figure 5) the Setup & Hold sample p[...]

DDR3THIN-MN-XXX 55 Doc. Rev. 1.11 The B_DDR3D_XX supports acquire two samples of valid Write data on each rising edge of the DDR3 clock. So to acquire both pieces of data the WrA_DatHi/Lo data groups must have their sample point set to that shown by Sample Pt. #1 in the Figure, and the W rB_DatHi/Lo data groups must have their sample point set to t[...]

DDR3THIN-MN-XXX 56 Doc. Rev. 1.11 Figure 7 - Measuring B_DDR3D_XX RdA_DatHi / Lo Read Data Setup & Hold Zoom in further to determine the Setup and Hold sam ple point necessary to acquire valid data at that point (Figure 7) and use the cursors to measure the time from the clock edge to the start of valid Read data. In this example the delay from[...]

DDR3THIN-MN-XXX 57 Doc. Rev. 1.11 Figure 8 - Measuring B_DDR3D_XX RdB_DatHi / Lo Read Data Setup & Hold Now the sample point positions must be set for the RdA_DatHi, RdA_DatLo, RdB_DatHi and RdB_DatLo capture groups in the Setup window (see Figure 9). This window is found by going to the LA Card’s Setup window, then clicking on the More butto[...]

DDR3THIN-MN-XXX 58 Doc. Rev. 1.11 Setting the Setup & Hold values for acquiring Write data is a similar process. To determ ine the Write Data group sample points first m ake an a ppropriate acquisition of Write data by triggering on a Write Comm and. Then, as above, create a timing window display of MagniVu data and display the Data_Hi and Data[...]

DDR3THIN-MN-XXX 59 Doc. Rev. 1.11 Figure 11 - Measuring B_DDR3D_XX WrA_Da tHi / Lo Write Data Setup & Hold Now the sample point for the WrB_DatHi and W rB_DatLo groups must be determined (see Figure 12). The next valid Write data (after the cycle measured above) occurs approxim ately 500ps after the rising edge of DDRCK0, so a suitable Setup &a[...]

DDR3THIN-MN-XXX 60 Doc. Rev. 1.11 used as Data Masks then the WrtMasks group should have a Setup & Hold value that matches that of the Write Data groups. Figure 13 - Setting B_DDR3D_XX WrA_DatHi / Lo and WrB_DatHi / Lo Sample Points Because of the speeds of DDR3 data it may be necessary to program Setup & Hold values for each of the 8-bit g[...]

DDR3THIN-MN-XXX 61 Doc. Rev. 1.11 Figure 14 - Viewing Indivi dual 8-bit Read Data Groups Figure 15 - Setting Individual Setup & Hold Values for the 8-bit Read Data Groups Note: Values shown are for illustration purposes only[...]

DDR3THIN-MN-XXX 62 Doc. Rev. 1.11 5.8 Setting B_DDR3D_3A Read Data Sample Points The same procedure outlined above for setting Read Data sample points should be used to determine the sample points for Read Data from teh second DIMM slot. Set the sample points for the groups named RdA_DatHi_1, RdA_DatLo_1, RdB_DatHi_1 and RdB_DatLo_1.[...]

DDR3THIN-MN-XXX 63 Doc. Rev. 1.11 6.0 VIEWING DATA 6.1 Viewing B_DDR3D_XX Data When using the NEX-DDR3INTR-THIN support pack ages the raw Address and Data groups are suppressed and are replaced with post-processed data in new groups. This data is displayed in new groups that have the support package name preceding it (i.e., B_DDR3D_XX Address, B_DD[...]

DDR3THIN-MN-XXX 64 Doc. Rev. 1.11 To change the display it is necessary to bring up the window’s Properties window (perform a right mouse-click in the State display window) and select the Disassembly tab. This will bring up the configuration window shown in Figure 17. Figure 17 - Disassembly Properties There are several select fields available in[...]

DDR3THIN-MN-XXX 65 Doc. Rev. 1.11 DM Signal Use - permits setting Data Mask functionality to W rite Masks (default) or Strobes. When set to Write Mask the DM signals will be used to m ask Write Data to show which data bytes were valid in the cycle. In addition to these Disassembly Properties selections, changing the settings in the Show field resul[...]

DDR3THIN-MN-XXX 66 Doc. Rev. 1.11 data are displayed. Note that the timestamp is updated to reflect the tim e between displayed cycles. 6.2 Viewing Raw DDR3 Data using B_DDR3D_XX Supports In order to make the display of DDR3 data more user-friendly the raw data from the Address, all Data and other groups is suppressed in the B_DDR3D_2D Listing disp[...]

DDR3THIN-MN-XXX 67 Doc. Rev. 1.11 Table 7 gives a brief description of each of the text lines displayed in the B_DDR3D_2G post- processing software display. Mnemonic Description ACT – BANK ACTIVATE (Sx# / bS# / cS#) Bank: Active comma nd – activate a row in a bank for subsequent access (Slot A, B or C; Chi p Select 0-3; Bank x) DESL - IGNORE CO[...]

DDR3THIN-MN-XXX 68 Doc. Rev. 1.11 Figure 19 - B_DDR3D_XX MagniVu Display on TLA[...]

DDR3THIN-MN-XXX 69 Doc. Rev. 1.11 7.0 HINTS & TIPS 7.1 Symbolic Triggering on a Command using B_DDR3D_XX Supports A Symbol Table has been included for the Control data groups defined in each of the support packages. The Symbol Table for the B_DDR3D_2D / 3A supports is shown in Table 8; the Symbol Table for the B_DDR3D_2G support is shown in Tab[...]

DDR3THIN-MN-XXX 70 Doc. Rev. 1.11 Symbol Definition cccc ssssssss = xxxxx1 1110 for S0# cccc ssssssss = xxxx1x 1101 for S1# cccc ssssssss = xxxxx1 1011 for S2# cccc ssssssss = xxxx1x 0111 for S3# cccc ssssssss = xxxxx1 1110 for bS0# cccc ssssssss = xxxx1x 1101 for bS1# cccc ssssssss = xxxxx1 1011 for cS0# cccc ssssssss = xxxx1x 0111 for cS1# x in D[...]

DDR3THIN-MN-XXX 71 Doc. Rev. 1.11 Figure 20 - B_DDR3D_2D MRS Trigger In the trigger example a Storage condition has been created so that only MRS cycles will be stored. In testing, multiple MRS cycles were seen during the boot process, and the example triggers shown will ensure that all of the MRS cycles will be acquired, an example of which is sho[...]

DDR3THIN-MN-XXX 72 Doc. Rev. 1.11 the differential pair by removed. The added capacitance of the logic analyzer compensates for this missing capacitor. 7.5 Thresholds Analog waveforms and their associated thresholds viewed using the Tektronix Analog Mux will display amplitudes and thresholds that are not an exact representation of the actual analog[...]

DDR3THIN-MN-XXX 73 Doc. Rev. 1.11 APPENDIX A – How DDR Data is Clocked A.1 Background Demultiplexing means that the TLA’s Logic Analyzer card can have one data probe connected to the target yet store incoming data in two or four separate data sections of the card. For instance, the A3 data section (8-bits) can be connected to the target and dat[...]

DDR3THIN-MN-XXX 74 Doc. Rev. 1.11 A.3 B_DDR3D_2D / 2G / 3A Data Acquisition These supports requires two (2) merged 136-channel with 1.4G state option TLA7BB4 acquisition cards used in a TLA7XX logic analyzer. Data is acquired using the rising edge of the DDR clock. A_Data information is earlier (older) data than the inform ation stored in B_Data. D[...]

DDR3THIN-MN-XXX 75 Doc. Rev. 1.11 APPENDIX B - Considerations B.1 NEX-DDR3INTR-THIN Bus Loading It must be noted that the NEX-DDR3INTR-THIN In terposer is designed to minim al effect on the user’s circuit. The acquired signals are sampled at top edge connector, and then passed through isolation resistors to the probe. There will be an effective 6[...]

DDR3THIN-MN-XXX 76 Doc. Rev. 1.11 APPENDIX C – 240-pin DDR3 DIMM Pinout Front Side (left 1-60) Back Side (right 121-180 Fr ont Side (left 61-120) Back Side (right 181-240) Pin # X64 Non- Parity X72 ECC Pin # X64 Non-Parity X72 ECC Pin # X64 Non- Parity X72 ECC Pin # X64 Non- Parity X72 ECC 1 VREF VREF 121 VSS VSS 61 A2 A2 181 A1 A1 2 VSS VSS 122 [...]

DDR3THIN-MN-XXX 77 Doc. Rev. 1.11 APPENDIX C - 240-pin DDR3 DIMM Pinout (cont’d.) Front Side (left 1-60) Back Side (right 121-180 Fr ont Side (left 61-120) Back Side (right 181-240) Pin # X64 Non- Parity X72 ECC Pin # X64 Non-Parity X72 ECC Pin # X64 Non- Parity X72 ECC Pin # X64 Non- Parity X72 ECC 41 VSS VSS 161 DM8 DQS17 DM8 DQS17 101 VSS VSS [...]

DDR3THIN-MN-XXX 78 Doc. Rev. 1.11 APPENDIX D –Data Flow Through the Probes (coax cable to channel) Data flow Slave1 C3/2 & E3/2 Master A3/2 & Master Slave1 A3/2 & A1/0 Slave1 C3/2/1/0 Slave1 E3/2/1/0 Master A3/2 D3/2 Master A1/0 D1/0 Master C3/2/1/0 Slave1 A3/2 D3/2 Slave1 A1/0 D1/0 J15-x Coax on top J16-x Coax on Samtec Connectors pl[...]

DDR3THIN-MN-XXX 79 Doc. Rev. 1.11 APPENDIX D - Data Flow Through the Probes (cont’d.) Coax wire PIN M_C Channel M_A3/2 A1/0 Channel S_A3/2 A1/0 Channel S_C3/2 E3/2 Channel J16-2 C2:0 A0:0 A0:0 E2:0 J16-5 C2:5 A0:5 A0:5 E2:5 J16-8 C3:3 A1:3 A1:3 E3:3 J16-11 C1:5 A3:5 A3:5 C3:5 J16-14 C1:0 A3:0 A3:0 C3:0 J16-17 C0:3 A2:3 A2:3 C2:3 J16-4 C2:4 A0:4 A[...]

DDR3THIN-MN-XXX 80 Doc. Rev. 1.11 APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot 0 Samtec Pin Coax Pin TLA Channe l DDR3 Signal Samte c Pin Coax Pin TLA Channe l DDR3 Signal 15 J15-6 CK1 CB1 46 J16-6 CK3+ A13 29 J15-10 A1:7 NC 32 J16-10 C3:7 BA1 25 J15-9 A1:6 CB3 36 J16-9 C3:6 RAS# 28 J16-11 A1:5 CB7 33 J15-11 C3:5 CAS# 24 J16-12 A1:4 CB6 37 J[...]

DDR3THIN-MN-XXX 81 Doc. Rev. 1.11 APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot 0 (Cont’d.) Samtec Pin Coax Pin TLA Channel DDR3 Signal Samtec Pin Coax Pin TLA Channel DDR3 Signal 15 J15-6 CK1 DQS5 46 J15-6 Q3 DQ3 29 J15-10 A1:7 DQ49 32 J15-10 E3:7 DQ10 25 J15-9 A1:6 DQ48 36 J15-9 E3:6 DQS1 28 J16-11 A1:5 DQ52 33 J16-11 E3:5 DM1 24 J16-12 A[...]

DDR3THIN-MN-XXX 82 Doc. Rev. 1.11 APPENDIX F – B_DDR3_2G Support Pinout , DIMM Slot 0 Auxiliary Signals Samte c Pin Coax Pin TLA Channe l DDR3 Signal 46 J16-6 NC 32 J16-10 E3:7 NC 36 J16-9 E3:6 NC 33 J15-11 E3:5 cCLKE1 LEAD-6 37 J15-12 E3:4 cCLKE0 LEAD-5 40 J16-8 E3:3 NC 42 J16-7 E3:2 NC 41 J15-13 E3:1 LEAD-4 45 J15-14 E3:0 LEAD-3 49 J15-15 E2:7 [...]

DDR3THIN-MN-XXX 83 Doc. Rev. 1.11[...]

DDR3THIN-MN-XXX 84 Doc. Rev. 1.11 APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 Samte c Pin Coax Pin TLA Channe l DDR3 Signal Samte c Pin Coax Pin TLA Channe l DDR3 Signal 15 J15-6 Q0+ CB1 46 J16-6 CK3+ A13 29 J15-10 D3:7 NC 32 J16-10 C3:7 BA1 25 J15-9 D3:6 CB3 36 J16-9 C3:6 RAS# 28 J16-11 D3:5 CB7 33 J15-11 C3:5 CAS# 24 J16-12 D3:4 CB6 37 [...]

DDR3THIN-MN-XXX 85 Doc. Rev. 1.11 APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 (cont’d.) Samtec Pin Coax Pin TLA Channe l DDR 3 Signa l Samte c Pin Coax Pin TLA Channe l DDR 3 Signa l 15 J15-6 CK2+ DQS5 15 J15-6 Q2+ DQ3 29 J15-10 D1:7 DQ49 29 J15-10 E1:7 DQ10 25 J15-9 D1:6 DQ48 25 J15-9 E1:6 DQS1 28 J16-11 D1:5 DQ52 28 J16-11 E1:5 DM1 24[...]

DDR3THIN-MN-XXX 86 Doc. Rev. 1.11 APPENDIX H – Data Group / Data Byte / Strobe Cross-Reference 32-bit Data Group 8-bit Data Group Strobe Data Bits RdADatHi RdADatB7 DQS7 63,62,61,60,59,58,57,56 RdADatB6 DQS6 55,54,53,52,51,50,49,48 RdADatB5 DQS5 47,46,45,44,43,42,41,40 RdADatB4 DQS4 39,38,37,36,35,34,33,32 RdADatLo RdADatB3 DQS3 31,30,29,28,27,26[...]

DDR3THIN-MN-XXX 87 Doc. Rev. 1.11 APPENDIX I – NEX-DDR3INTR-THIN Silkscreen Front Silk-screen[...]

DDR3THIN-MN-XXX 88 Doc. Rev. 1.11 APPENDIX J – Keep out area[...]

DDR3THIN-MN-XXX 89 Doc. Rev. 1.11 APPENDIX K – Simulation Model Double this if you are using two Interposers on the same mem ory channel[...]

DDR3THIN-MN-XXX 90 Doc. Rev. 1.11 APPENDIX L - References JEDEC PC3-6400/PC3-8500-10660 DDR3 SDRAM U nbuffered DIMM Design Specification Revision 0.1 March 20, 2006. Tektronix TLA7000 Series Installation Manual Tek part number 071-1747-03 Tektronix TLA7000 Series Technical Reference Manual Tektronix part number 071-1764-00 Nexus Low Profile Distrib[...]

DDR3THIN-MN-XXX 91 Doc. Rev. 1.11 APPENDIX M - Support About Nexus Technology, Inc. Established in 1991, Nexus Technology, Inc. is dedicated to developing, marketing, and supporting Bus Analysis applications for Tektronix Logic Analyzers. We can be reached at: Nexus Technology, Inc. P.O. Box 6575 Nashua, NH 03063 TEL: 877-595-8116 FAX: 877-595-8118[...]