Omega Engineering DAQ-12 Bedienungsanleitung

INTERFACE CARDS FOR PERSONAL COMPUTERS DAQ-12 Data Acquisition Adapter For 16 bit ISA compatible machines Users Manual OMEGA ENGINEERING, INC. TEL: (203) 359-1660 One Omega Drive FAX: (203) 359-7700 P.O. Box 4047 Toll free: 1-800-826-6342 Stamford, CT 06907-4047 E-mail: das@omega.com http://www.dasieee.com[...]

WARRANTY/DISCLAIMER OMEGA ENGI NEERING, INC. , w arrants this unit to be free of def ects in materials and w orkmanship for a perio d of 13 mont hs from the date of purchase. OMEGA w arranty adds an ad ditional one (1) month grace period to the normal one (1 ) year pr oduct w arr anty to co ver shipping and handling time. This ensures that OMEGA’[...]

Declaration of Conf orm ity Manufacturer's Name: Omega Engineering, Inc. Manufacturer’s Address: One Omega Drive Stamford, CT 06907-0047 Application of Council Directive: 89/336/EEC Standards to which Conformity is Declared: * EN50081-2 (EN55022, EN60555-2, EN60555-3) * EN50082-1 (IEC 801-2, IEC 801-3, & IEC 801-4) Type of Equipment: Inf[...]

OMEGAnet  On-line Service: Internet e-mail: http://www.omega.com info@omega.com Servicing North America : USA : One Omega Drive, Box 4047 E-mail: info@omega.com ISO 9001 Certified Stamford, CT 06907-0047 Tel: (203) 359-1660 FAX: (203) 359-7700 Canada : 976 Bergar E-mail: info@omega.com Laval (Quebec) H7L 5A1 Tel: (514) 856-6928 FAX: (514) 856-68[...]

United Kingdom : One Omega Drive, River Bend Technology Drive ISO 9002 Certified Northbank, Irlam, Manchester M44 5EX, England Tel: 44 (161) 777-6611 FAX: 44 (161) 777-6622 Toll Free in England: 0800-488-488 E-mail: info@omega.co.uk It is the policy of OM EGA to comply with al l worl dwide safety and EM C/EMI regulations that apply. OMEGA is consta[...]

Table of Contents 29 4.2 Programming the 8254 Counter/Timer ............................ 28 4.1.9 8254 Control Word/Status Register ................................... 28 4.1.8 Multi-Function Timer Register ....................................... 28 4.1.7 Clock Rate Register (high word) ..................................... 28 4.1.6 Clock Rate Regi[...]

List of Figures and Tables 25 Table 4-1. DAQ-12 Address Map ............................................... 15 Table 2-3. D/A Converter Mode Selection Options ................................ 14 Table 2-2. A/D Conversion Format Examples .................................... 12 Table 2-1. Recommended Input Ranges and Gain Settings ...................[...]

1. Introduction The DA Q-1 2 is a high s peed dat a ac quisit ion adap ter for IBM AT a nd comp atible m ach ines off eri ng ei ght d if fer ential anal og i nput channel s with 16- bit r esol ution, two anal og output channel s with 12-b it r esoluti on and four di gi tal i nput/output lines. Other f eature s of the DAQ-12 include: Analog to Digit[...]

1.2 DAQ-12 Specifications DACK 5, 6 , 7 DRQ 5, 6 , 7 DMA Levels: IRQ 2, 3, 4. 5, 6, 7, 10, 11, 12, 14, 15 Interrupt Levels: 0000H - FFFFH I/O Address Range: ISA 16-bit Bus Interface: 491.4mA 374.9 mA +12 volts --- --- -12 volts 1204.9mA 1069.0 mA +5 volts --- --- -5 volts I(ms) I(t) Power Supply Power Requirements: I(t) = Typical Current / I(ms) = [...]

2. Circuit Board Description and Configuration The ba se addres s of t he DA Q-1 2 is sele ct ed using s witch es SW1 and SW 2. The op erat ing mo de of t he DAQ-12 is co nt rolled by jump ers J1 th rough J7 , while DMA an d interru pt sele ctions ar e set with jumpe rs J8 through J 11. Connections to exter nal e quipmen t are ma de through the hig[...]

The a mpli fi er stag e of the A/D conver ter circui t perf orms tw o functi ons: (1) a mpli fi es low leve l input signa ls and (2) c onv ert s this in put s ignal int o a vo lta ge ran ge acc ept able to the A/D c onve rter. Sev en ga in levels a re so ftware selec table for the a mplifie r st age of th e A/D circu it. To su ppo rt high lev el in[...]

Table 2-1 deta ils the availa ble gain s ettin gs a nd resultin g inpu t range s for t he vario us input conf ig urations. Note that the 'gai n byte' f ie ld i n Tabl e 2- 1 is the va lue wri tten to the DAQ-12's gain control register. (* indicates unipolar mode not available with gain of ½ ). 83 2-3 4 +2.5/ ±1.25 82 2-3 2 +5/ ±2.[...]

The final stage of the A/D converter circuit is the A/D converter IC . The co nverter must be co nfigur ed for unipo lar or bipo lar input vo ltages a s sho wn in Figu re 2-3. Whe n co nfigured for uni pola r ope ration, the anal og input mul tipl ied by the gai n setti ng must b e in the r ange of 0 volts (analog ground) to +10 volts. When configu[...]

n/a 0000 1111 1111 1111 10 0000 0111 1111 1111 0000 1000 0000 0000 5 0000 0100 0000 0000 0000 0100 0000 0000 2.5 0000 0000 0000 0000 0000 0000 0000 0000 0 1111 1100 0000 0000 n/a -2.5 1111 1000 0000 0000 n/a -5 Code Code Bipolar Unipolar Voltage Table 2-2. A/D Conversion Format Examples NOTE: The ' vo lta ge' c olumn is the vo ltage a ppl[...]

The D /A converte r channel s may al so be operated i n unipolar mode: 0 to +5 volts, or b ipol ar mo de: -5 to +5 vo lts. The ou tput m ode is selec ted us ing jump er J5 as sh own in Figu re 2-5. In addit ion , a gain sele ction jumpe r is pro vided t o sele ct an outp ut gain of 1 or 2 . When u sing an exte rnal voltag e ref erence , thi s gai n[...]

2.3 Digital Input/Output The DAQ- 12 of fer s four b its of di gi tal output and four b its of di gi tal i nput f or co ntrol/ mon ito ring o f extern al digit al dev i ce s. The four digital ou tput lines a re LS TTL co mpat ible an d will init ialize low (0 vo lts) on power-u p. The four digit al inp ut s are als o LS TTL co mpat ible. There is n[...]

2.5 Clock Selection The D AQ-1 2 is e quipped wi th a progr ammab le cl ock ci rcui t to pr oduce d ata sampl in g rate s independ ent from the clock rate o f the host co mputer. An onboard 8254 programmabl e inte rval time r, wi th a 10 MHz clock input and ei ther tw o or thr ee cascad ed 16-b i t timer s, provi des the sa mpli ng rate. Thi s enab[...]

2.5.1 Internal Clock Sampling rates for the internal clock can be calculated using the following equation: t = 100ns * [N1*N2] or f = 10MHz / [N1*N2] wher e N1 is the low 1 6-b its of the clock di vid er and N2 is the high 1 6-b its of the clock divider. The following criteria must be met when selecting values for N1 and N2: 2 < N1 < 65,535 2[...]

Whe n co nfigured fo r a 48-bit div ider, the first s ampling p eriod will be slightly lo nger th an the other s because the fi rst cl ock per iod is r equi red to l oad the i ni tial val ue of the multi-function timer. The following equation calculates the additional time of the first period: t = 100ns * [N1 * N2] add To m inimiz e the a moun t of[...]

When the mul ti- functi on time r is use d as a pr e-d i vid er, the fr equency of the ex ternal cl ock input may be var ied fr om DC to 10 MHz as l ong as the hi gh porti on of the cl ock is at l east 30ns and the low porti on is at least 5 0ns. E xcept f or the fi rst peri od, the sampl in g rate of the DAQ-1 2 will be the e xte rnal clock fre qu[...]

2.7 Direct Memory Access Di rect Me mory Acce ss (D MA) tra nsfe rs provi de a way of transf er ri ng da ta fr om the DAQ- 12's A/D conver ter into the persona l computer 's memory wi thout using the Central Pro cessin g Unit (C PU). DMA c apability e nables oth er syst em so ftware to be execu ted while data is being input from the DAQ-1[...]

2.8 Interrupts The DAQ-12 is capable of generating an interrupt from one of four sources: 1. End of conversion signal 2. DMA terminal count 3. Multi-function timer output 4. External interrupt input The i nterrupt source is softwar e selected through the D AQ-12 contr ol word r egi ster. The interrupt level is selected using the jumpers J10 and J11[...]

3. External Connections The DAQ-12 is equipped with a high density 62-pin connector as shown in Figure 3-1. 2 - CH1+ 4 - CH2- (CH10+) 6 - CH 4+ 8 - CH5- (CH13 +) 10 - CH7+ 12 - AOUT0 14 - DOUT0 6 - DOUT3 18 - EXT TRIG 20 - DIN1 22 - CH0+ 24 - CH1- (CH9+) 26 - CH3+ 28 - CH4- (CH12+) 30 - CH6+ 32 - CH7- (CH15+) 34 - AOUT1 36 - DOUT1 38 - EXT INT 40 -[...]

CHx-, C Hx+ : Ana l o g inpu ts t o t he ana l o g to digital co nvert er. When us ing different ial input mo de, eight input ch annels are a vailable (C H0+ to C H7+). When usin g s ingle-en ded inputs, 16 channels are avai labl e (CH0+ t o CH15+). The first eight channels are input through the connections mark ed C H 0+ to CH7+ and the second ei [...]

4. Register Description and Programming The DAQ-12 uses 16 con secut ive I/O address locat ions in the range 0 to FFFFH. The c ard ut ilizes thes e addre ss es fo r the regist ers list ed in Table 4-1 . (* indicat es regis ters loca te d in 8254 counter). Read/Write 8-bit 8254 Control Word/Status Register Base F * Read/Write 8-bit Multi-function Ti[...]

INT2, INT1 and INT0 control the DAQ-12 interrupt source. INT2 INT1 INT0 DESCRIPTION 0 0 0 Interrupt disabled 1 0 0 Interrupt timer 2 1 0 1 Interrupt on terminal count 1 1 0 External interrupt 1 1 1 Interrupt on end of conversion DMAEN - enables / disables DMA. When set, logic 1, DMA transfers are enabled. DMAC T - e nable s t he m ulti-c hanne l DM[...]

VALID - when s et, lo gic 1 , indic ate s at le ast one da ta sam ple was los t becau se it wa s rea d by the personal computer befor e the nex t sample was conver ted. Data was l ost because the sampli ng rate w as too fa st f or the computer to acq uir e the d ata. VALI D is rese t by w ri ting to the start conversion register. CHSL 2, CHSL 1, CH[...]

4.1.4 D/A Converter 0 Register An output to this re giste r cause s the lower twel ve b its of data to be conve rted to an analog output on D/A conver ter channe l 0. The f our most sig nif ica nt bi ts of d ata are i gnor ed. Thi s register is 16-bit write only. 4.1.5 D/A Converter 1 Register An output to this re giste r cause s the lower twel ve [...]

4.2 Programming the 8254 Counter/Timer This section provides programmi ng information for the 8254 count er/timer as implemented on the DAQ-12. For more details on the 8254, consult the Intel Micro-processor and Peripheral Handbook. To program any of the counters contained in the 8254 counter/timer, three steps are required: 1. Write the configurat[...]

Counter 1 - Clock rate register (high word) operating mode: 2 minimum count value: 2 configuration byte: 0 / 1 / 1 / 1 / 0 / 1 / 0 / 0 = 74H Example: Program the value 13A4H into the high word of the clock rate register. output 74H to base_address + 0FH output A4H to base_address + 0DH output 13H to base_address + 0DH Example: Program the value FFF[...]

DAQ-12 Users Manual Version 2.20 January 28, 1999 Part No. 940-0030-220[...]