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Sun Microsystems SME5224AUPA-400 Bedienungsanleitung

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Inhaltsverzeichnis der Gebrauchsanleitungen

  • Seite 1

    DA T ASHEET 1 SME5224A UP A-400 UltraSP ARC ™ -II CPU Module 400 MHz CPU, 4.0 MB E-Cache M ODULE D ESCRIPTION The UltraSP ARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUP A-400) delivers high performance computing in a compact design. Based on the UltraSP ARC™-II CPU, this module is designed using a small form factor board with an integr[...]

  • Seite 2

    2 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc CPU D ESCRIPTION UltraSP ARC-II CPU The UltraSP ARC™-II CPU is the second generation in the UltraSPARC™ s-series microprocessor family. A complete implementation of the SP ARC  V9 architecture, it has binary compatibility with all prev[...]

  • Seite 3

    3 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc D ATA B UFFER D ESCRIPTION UltraSP ARC-II Data Buf fer (UDB-II) The UltraSP ARC™-II module has two UltraSP ARC-II data buffers (UDB-II) - each a 256 pin BGA device - for a UP A Interconnect system bus width of 128 Data + 16[...]

  • Seite 4

    4 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc M ODULE C OMPONENT O VER VIEW The UltraSP ARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUP A-400), (see Figure 1 ), consists of the following components: • UltraSP ARC™-II CPU at 400 MHz • UltraSP ARC-II Data Buffer (UDB-II) • [...]

  • Seite 5

    5 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc S YSTEM I NTERF A CE Figure 2 shows the major components of a UP A based uniprocessor system. The system controller [1] for the UP A bus arbitrates between the UltraSP ARC™–II, 400 MHz CPU, 4.0 Mbyte module, and the I/O b[...]

  • Seite 6

    6 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc Module ID Module IDs are used to configur e the UP A address of a module. The UP A_PORT_ID[4:3] ar e hardwir ed on the module to “0”. UP A_POR T_ID[1:0] are br ought out to the connector pins. Each module is hardwir ed in the system to a[...]

  • Seite 7

    7 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc S IGNAL D ESCRIPTION [1] System Interface Signal T ype Name and Function UP A_ADDR[35:0] I/O P ack et s witched transaction request b us. Maximum of three other masters and one system controller can be connected to this bus .[...]

  • Seite 8

    8 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc JT A G/Debug Interface Signal T ype Name and Function TDO O IEEE 1149 test data output. A three-state signal driven only when the T AP controller is in the shift-DR state. TDI I IEEE 1149 test data input. This pin is internally pulled to logi[...]

  • Seite 9

    9 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc UP A AND CPU C LOCKS Module Clocks The module receives three differ ential pair low voltage PECL (L VPECL) clock signals (CPU_CLK, UP A_CLK0 and UP A_CLK1) from the systemboar d and terminates them. The CPU_CLK is unique in t[...]

  • Seite 10

    10 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc . LOW VOL T AGE PECL T wo trace signals compose each clock: one positive signal and one negative signal. Each signal is 180-degrees out of phase with the other . Signal timing is referenced to when the positive L VPECL signal transitions fro[...]

  • Seite 11

    11 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc E LECTRICAL C HARA CTERISTICS Absolute Maximum Ratings [1] 1. Operation of the device at v alues in excess of those listed above will result in deg radation or destruction of the device . All voltages are defined with respe[...]

  • Seite 12

    12 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc Module P ower Consumption This UltraSP ARC-II module requires two supply voltages. The requir ed voltages (provided to the module) for the V DD and V DD_CORE , are r espectively 3.30V and 2.6V . The estimated maximum power consumption of the[...]

  • Seite 13

    13 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc UP A Data Bus SPICE Model A typical circuit for the UP A data bus and ECC signals is illustrated in Figure 4 :. Figure 4. Module System Loading: Example for UP A_DA T A, UP A_ECC 3.1 nH 1.0 pF Edge Connector UDB-II Driver T [...]

  • Seite 14

    14 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc U P AA CT IMING S PECIFICA TIONS The UP A AC T iming Specifications are refer enced to the UP A connector . The timing assumes that the clocks are corr ectly distributed, (see the section "System Clock Distribution," on page 9). T[...]

  • Seite 15

    15 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc The following table, "Propagation Delay , Output Hold T ime Specifications," specifies the propagation delay and output hold times for the UltraSP ARC™–II, 400 MHz CPU, 4.0 Mbyte module with a 4 Mbyte E-cache[...]

  • Seite 16

    16 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc M ECHANICAL S PECIFICA TIONS The module components and dimensions are specified in Figure 6 , Figur e 7 , Figure 8 and Figure 9 . Figure 6. CPU Module Components Figure 7. CPU Module (Component Dimensions) Module Ejectors CPU/V oltage Regul[...]

  • Seite 17

    17 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc Figure 8. CPU Module Side View Figure 9. CPU Module Side View Dimensions NOTE: A minimum backside clearance is requir ed for airflow cooling of the backside heatsink. Module Shroud Bidirectional Airflow Backside SRAM Heat s[...]

  • Seite 18

    18 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc T HERMAL S PECIFICA TIONS The maximum CPU operating frequency and I/O timing is r educed when the junction temperature (Tj) of the CPU device is raised. Airflow must be directed to the CPU heatsink to keep the CPU device cool. Corr ect air-[...]

  • Seite 19

    19 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc Thermal Definitions and Specifications T erm Definition Specification Comments Tj Maximum device junction temperature 85 ° C, The Tj can't be measured directly by a thermo-couple probe. It must always be estimated [...]

  • Seite 20

    20 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc T emperature Estimating and Measuring Methods The following methods can be used to estimate air cooling requir ements and calculate junction temperature based on thermo-couple temperature measur ements. Airflow Cooling Measurement Method Th[...]

  • Seite 21

    21 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc Case T emperature Measuring Method The relationship between case temperatur e and junction temperature is described in the following thermal equation. If T c is known, then Tj can be calculated: Tj = T c + (Pd x θ jc) Note:[...]

  • Seite 22

    22 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc JT A G T EST ABILITY The UltraSP ARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUP A-400), implements the IEEE 1 149.1 standard to aid in boar d level testing. Boundary Scan Description Language (BSDL) files are available for all the [...]

  • Seite 23

    23 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc JT A G (IEEE 1149.1) T IMING Figure 10. V oltage W avef orms - Setup and Hold Times Data Input t H 1.5V V IH V IL Clock t SU 2.0V V IH V IL 1.5V Figure 11. V oltage W avef orms - Pr opagation Dela y Times Clock t PD In-Phase[...]

  • Seite 24

    24 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc UP A C ONNECT OR P IN A SSIGNMENTS (T OP V IEW ) Pin 1 (Pin 4) UP A_ADDR[1] (Pin 1) UP A_ADDR[0] (Pin 10) UP A_ADDR[3] (Pin 7) UP A_ADDR[2] UP A_ADDR[4] UP A_ADDR[6] UP A_ADDR[16] UP A_ADDR[18] UP A_ADDR[20] UP A_ADDR[22] UP A_ADDR[32] UP A_[...]

  • Seite 25

    25 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc UP A C ONNECT OR P IN A SSIGNMENTS (B OT TO M V IEW ) UP A_ADDR[9] (Pin 6) UP A_ADDR[8] (Pin 3) UP A_ADDR[11] (Pin 12) UP A_ADDR[10] (Pin 9) UP A_ADDR[12] UP A_ADDR[14] UP A_ADDR[24] UP A_ADDR[26] UP A_ADDR[28] UP A_ADDR[30][...]

  • Seite 26

    26 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc H ANDLING CPU M ODULES CAUTION : Handle a module by carefully holding it by its edges and by the lar ge CPU heatsink. Do not bump or handle the SRAM heatsinks because this action can cause unseen damage to the solder connections. Always hand[...]

  • Seite 27

    27 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc O RDERING I NFORMA TION [1] 1. T o order the data sheet for this device use the document part number: 805-6390-05 Part Number CPU Speeds Description SME5224A UP A-400 400 MHz CPU The UltraSP ARC™–II, 400 MHz CPU, 4.0 Mb [...]

  • Seite 28

    ©1999 Sun Microsystems, Inc. All Rights reserved. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED “AS IS” WITHOUT ANY EXPRESS REPRESENTATIONS OF WARRANTIES. IN ADDITION, SUN MICROSYSTEMS, INC. DISCLAIMS ALL IMPLIED REPRESENTATIONS AND WARRANTIES, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRING[...]

  • Seite 29

    DA T ASHEET 1 SME5224A UP A-400 UltraSP ARC ™ -II CPU Module 400 MHz CPU, 4.0 MB E-Cache M ODULE D ESCRIPTION The UltraSP ARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUP A-400) delivers high performance computing in a compact design. Based on the UltraSP ARC™-II CPU, this module is designed using a small form factor board with an integr[...]

  • Seite 30

    2 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc CPU D ESCRIPTION UltraSP ARC-II CPU The UltraSP ARC™-II CPU is the second generation in the UltraSPARC™ s-series microprocessor family. A complete implementation of the SP ARC  V9 architecture, it has binary compatibility with all prev[...]

  • Seite 31

    3 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc D ATA B UFFER D ESCRIPTION UltraSP ARC-II Data Buf fer (UDB-II) The UltraSP ARC™-II module has two UltraSP ARC-II data buffers (UDB-II) - each a 256 pin BGA device - for a UP A Interconnect system bus width of 128 Data + 16[...]

  • Seite 32

    4 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc M ODULE C OMPONENT O VER VIEW The UltraSP ARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUP A-400), (see Figure 1 ), consists of the following components: • UltraSP ARC™-II CPU at 400 MHz • UltraSP ARC-II Data Buffer (UDB-II) • [...]

  • Seite 33

    5 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc S YSTEM I NTERF A CE Figure 2 shows the major components of a UP A based uniprocessor system. The system controller [1] for the UP A bus arbitrates between the UltraSP ARC™–II, 400 MHz CPU, 4.0 Mbyte module, and the I/O b[...]

  • Seite 34

    6 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc Module ID Module IDs are used to configur e the UP A address of a module. The UP A_PORT_ID[4:3] ar e hardwir ed on the module to “0”. UP A_POR T_ID[1:0] are br ought out to the connector pins. Each module is hardwir ed in the system to a[...]

  • Seite 35

    7 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc S IGNAL D ESCRIPTION [1] System Interface Signal T ype Name and Function UP A_ADDR[35:0] I/O P ack et s witched transaction request b us. Maximum of three other masters and one system controller can be connected to this bus .[...]

  • Seite 36

    8 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc JT A G/Debug Interface Signal T ype Name and Function TDO O IEEE 1149 test data output. A three-state signal driven only when the T AP controller is in the shift-DR state. TDI I IEEE 1149 test data input. This pin is internally pulled to logi[...]

  • Seite 37

    9 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc UP A AND CPU C LOCKS Module Clocks The module receives three differ ential pair low voltage PECL (L VPECL) clock signals (CPU_CLK, UP A_CLK0 and UP A_CLK1) from the systemboar d and terminates them. The CPU_CLK is unique in t[...]

  • Seite 38

    10 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc . LOW VOL T AGE PECL T wo trace signals compose each clock: one positive signal and one negative signal. Each signal is 180-degrees out of phase with the other . Signal timing is referenced to when the positive L VPECL signal transitions fro[...]

  • Seite 39

    11 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc E LECTRICAL C HARA CTERISTICS Absolute Maximum Ratings [1] 1. Operation of the device at v alues in excess of those listed above will result in deg radation or destruction of the device . All voltages are defined with respe[...]

  • Seite 40

    12 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc Module P ower Consumption This UltraSP ARC-II module requires two supply voltages. The requir ed voltages (provided to the module) for the V DD and V DD_CORE , are r espectively 3.30V and 2.6V . The estimated maximum power consumption of the[...]

  • Seite 41

    13 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc UP A Data Bus SPICE Model A typical circuit for the UP A data bus and ECC signals is illustrated in Figure 4 :. Figure 4. Module System Loading: Example for UP A_DA T A, UP A_ECC 3.1 nH 1.0 pF Edge Connector UDB-II Driver T [...]

  • Seite 42

    14 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc U P AA CT IMING S PECIFICA TIONS The UP A AC T iming Specifications are refer enced to the UP A connector . The timing assumes that the clocks are corr ectly distributed, (see the section "System Clock Distribution," on page 9). T[...]

  • Seite 43

    15 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc The following table, "Propagation Delay , Output Hold T ime Specifications," specifies the propagation delay and output hold times for the UltraSP ARC™–II, 400 MHz CPU, 4.0 Mbyte module with a 4 Mbyte E-cache[...]

  • Seite 44

    16 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc M ECHANICAL S PECIFICA TIONS The module components and dimensions are specified in Figure 6 , Figur e 7 , Figure 8 and Figure 9 . Figure 6. CPU Module Components Figure 7. CPU Module (Component Dimensions) Module Ejectors CPU/V oltage Regul[...]

  • Seite 45

    17 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc Figure 8. CPU Module Side View Figure 9. CPU Module Side View Dimensions NOTE: A minimum backside clearance is requir ed for airflow cooling of the backside heatsink. Module Shroud Bidirectional Airflow Backside SRAM Heat s[...]

  • Seite 46

    18 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc T HERMAL S PECIFICA TIONS The maximum CPU operating frequency and I/O timing is r educed when the junction temperature (Tj) of the CPU device is raised. Airflow must be directed to the CPU heatsink to keep the CPU device cool. Corr ect air-[...]

  • Seite 47

    19 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc Thermal Definitions and Specifications T erm Definition Specification Comments Tj Maximum device junction temperature 85 ° C, The Tj can't be measured directly by a thermo-couple probe. It must always be estimated [...]

  • Seite 48

    20 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc T emperature Estimating and Measuring Methods The following methods can be used to estimate air cooling requir ements and calculate junction temperature based on thermo-couple temperature measur ements. Airflow Cooling Measurement Method Th[...]

  • Seite 49

    21 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc Case T emperature Measuring Method The relationship between case temperatur e and junction temperature is described in the following thermal equation. If T c is known, then Tj can be calculated: Tj = T c + (Pd x θ jc) Note:[...]

  • Seite 50

    22 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc JT A G T EST ABILITY The UltraSP ARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUP A-400), implements the IEEE 1 149.1 standard to aid in boar d level testing. Boundary Scan Description Language (BSDL) files are available for all the [...]

  • Seite 51

    23 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc JT A G (IEEE 1149.1) T IMING Figure 10. V oltage W avef orms - Setup and Hold Times Data Input t H 1.5V V IH V IL Clock t SU 2.0V V IH V IL 1.5V Figure 11. V oltage W avef orms - Pr opagation Dela y Times Clock t PD In-Phase[...]

  • Seite 52

    24 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc UP A C ONNECT OR P IN A SSIGNMENTS (T OP V IEW ) Pin 1 (Pin 4) UP A_ADDR[1] (Pin 1) UP A_ADDR[0] (Pin 10) UP A_ADDR[3] (Pin 7) UP A_ADDR[2] UP A_ADDR[4] UP A_ADDR[6] UP A_ADDR[16] UP A_ADDR[18] UP A_ADDR[20] UP A_ADDR[22] UP A_ADDR[32] UP A_[...]

  • Seite 53

    25 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc UP A C ONNECT OR P IN A SSIGNMENTS (B OT TO M V IEW ) UP A_ADDR[9] (Pin 6) UP A_ADDR[8] (Pin 3) UP A_ADDR[11] (Pin 12) UP A_ADDR[10] (Pin 9) UP A_ADDR[12] UP A_ADDR[14] UP A_ADDR[24] UP A_ADDR[26] UP A_ADDR[28] UP A_ADDR[30][...]

  • Seite 54

    26 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc H ANDLING CPU M ODULES CAUTION : Handle a module by carefully holding it by its edges and by the lar ge CPU heatsink. Do not bump or handle the SRAM heatsinks because this action can cause unseen damage to the solder connections. Always hand[...]

  • Seite 55

    27 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc O RDERING I NFORMA TION [1] 1. T o order the data sheet for this device use the document part number: 805-6390-05 Part Number CPU Speeds Description SME5224A UP A-400 400 MHz CPU The UltraSP ARC™–II, 400 MHz CPU, 4.0 Mb [...]

  • Seite 56

    ©1999 Sun Microsystems, Inc. All Rights reserved. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED “AS IS” WITHOUT ANY EXPRESS REPRESENTATIONS OF WARRANTIES. IN ADDITION, SUN MICROSYSTEMS, INC. DISCLAIMS ALL IMPLIED REPRESENTATIONS AND WARRANTIES, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRING[...]