Agilent Technologies HDMP-3001 manual

Agilent HDMP-3001 Ethernet over SONET Mapper IC Device Specification Data Sheet Table of Contents 1. Introduction ............................................................................................... 5 1.1 Internal Functional Blocks .............................................................. 5 1.2 HDMP-3001 Features List ..............[...]

2 3.9 SONET/SDH Processing ................................................................. 24 3.9.1 Transmit SONET/SDH Processing Overview ...................... 24 3.9.2 Receive SONET/SDH Processing Overview ........................ 25 3.9.3 Transmit SONET/SDH Processing Details ........................... 25 3.9.4 Receive SONET/SDH Processing D[...]

3 List of Figures Figure 1. Functional Block Diagram ......................................................... 5 Figure 2. HDMP-3001 applications ............................................................ 6 Figure 3. HDMP-3001 pin assignments ..................................................... 7 Figure 4. GFP Payload Bit Order .................[...]

4 List of Tables Table 1. Line Side Interface Pins Description ........................................... 8 Table 2. MII Interface Pins Description ..................................................... 9 Table 3. Transport Overhead Pins Description ...................................... 10 Table 4. Microprocessor Interface Pins Description .......[...]

5 1. Introduction The Agilent HDMP-3001 is a highly integrated VLSI device that provides mapping of Ethernet en- capsulated packets into STS-3c payloads. The HDMP-3001 sup- ports full-duplex processing of SONET/SDH data streams with full section, line, and path over- head processing. The device supports framing pattern, scrambling/descrambling, ala[...]

6 • Implemented in 0.25 micron CMOS with 1.8 V core, 3.3 V I/O power and LVCMOS compatible I/Os. • Provides a 16-bit general pur- pose I/O (GPIO) register. • Device power-up initialization optionally through 2-wire EEPROM interface. • Configurable by hardware to be connected to either a PHY or a MAC from the system connectivity viewpoint. 1[...]

7 2. Pinout 2.1 Pin Assignments Figure 3. HDMP-3001 Pin Assignments 125 115 110 75 70 130 GND VDD TX_LDCC_DA T A TX_LDCC_CLK TX_FRAME_SFP TX_E1_DA T A TX_E2_DA T A TX_F1_DA T A TX_E1E2F1_CLK DGND VDD TX_8K_CLK TX_SONETCLK TX_DA T A[7] TX_DA T A[6] TX_DA T A[5] TX_DA T A[4] TX_DA T A[3] DVDD DGND GND VDD TX_DA T A[2] TX_DA T A[1] TX_DA T A[0] RX_8K_[...]

8 Signal name Pin # Type(I/O) Signal description RX_DATA[0] 25 I RECEIVE DATA: Byte-wide STS-3c data input stream. RX_DATA[1] 26 RX_DATA [7] is the MSB, and RX_DATA [0] the LSB. RX_DATA[2] 27 Data is sampled on the rising edge of RX_SONETCLK. RX_DATA[3] 28 RX_DATA[4] 29 RX_DATA[5] 32 RX_DATA[6] 33 RX_DATA[7] 34 RX_FRAME_IN 23 I RECEIVE FRAME INDICA[...]

9 Signal name Pin # Type(I/O) Signal description TX_FRAME_SFP 125 O TRANSMIT FRAME POSITION OUTPUT INDICATOR: Frame position indication signal is active high and indicates the SONET frame position on the TX_DATA [7:0] bus. Updated on the rising edge of TX_SONETCLK. This signal is also used for the outer board to start sending the first bit (MSB) of[...]

10 Signal name Pin # Type(I/O) Signal description MDIO 113 I/O MII management input/output serial data. When this interface is unused, connect this pin high. If HDMP-3001 is attached to a MAC via the mechanical interface specified in IEEE 802.3, clause 22.6, an external pull-up of 1.5 kohm ± 5% is required. MDC 114 I MII management clock, up to 2.[...]

11 Signal name Pin # Type(I/O) Signal description TX_E1_DATA 126 I TRANSMIT E1 DATA: Local orderwire channel data byte (E1) to be inserted by the HDMP-3001 into the outgoing SONET data stream. TX_E2_DATA 127 I TRANSMIT E2 DATA: Express orderwire channel data byte (E2) to be inserted by the HDMP-3001 into the outgoing SONET data stream. TX_F1_DATA 1[...]

12 Signal name Pin # Type(I/O) Signal description ADDR[0] 56 I ADDRESS BUS: Allows host microprocessor to perform ADDR[1] 57 register selection within the HDMP-3001. ADDR[2] 58 ADDR[3] 63 ADDR[4] 64 ADDR[5] 65 ADDR[6] 66 ADDR[7] 67 ADDR[8] 68 APS_INTB 83 O (O/D) APS INTERRUPT: Active-low output triggered by an APS event. APS_INTB is an open-drain o[...]

13 Signal name Pin # Type(I/O) Signal description INT 86 O (T/S) INTERRUPT: Configurable interrupt output. Refer to Table 18 for a detailed description of how INT is configured. In open-drain configurations, an external pull-up is required. In open-source configurations, an external pull-down is required. To prevent undesired interrupts before conf[...]

14 Signal name Pin # Type(I/O) Signal description SCL 92 I/O EEPROM bus clock. If no EEPROM is present, connect this pin to ground. Refer to EEPROM application notes for board pull-up requirements. SDA 89 I/O EEPROM bus data. If no EEPROM is present, connect this pin to ground. Refer to EEPROM app notes for board pull-up requirements. Table 6. Two-[...]

15 Signal name Pin # Type(I/O) Signal description DGND 10, 11, 20, Driver GROUND: These pins should be connected to the I/O 40, 50, ground plane. 70, 80, 90, 100, 110, 120, 130, 140, 150, 160 VDD 2, 22, Logic POWER: These pins should be connected to the 1.8 V 42, 51, power supply for logic. 62, 82, 91, 102, 122, 131, 142 DVDD 19, 39, Driver POWER: [...]

16 2.3 I/O Buffer Types This section lists the types of some particular I/Os used in the HDMP-3001 chip. Table 8. Buffer types Buffer Type I/O Name Comment O/D APS_INTB Need external P/U Output TS P_RXD_M_TXD[0] Controlled by the “ Isolate MII ” register bit Output P_RXD_M_TXD[1] P_RXD_M_TXD[2] P_RXD_M_TXD[3] P_RX_DV_M_TX_EN P_RX_ER_M_TX_ER INT[...]

17 3. Functional Description 3.1 Introduction The HDMP-3001 performs full- duplex mapping of Ethernet frames into a SONET STS-3c / SDH STM-1 payload using the LAPS or GFP protocol. All SONET/SDH framing functions are included. A TOH interface provides direct add/drop capability for E1, E2, F1, and both Section and Line DCC channels. SONET or SDH mo[...]

18 3.2.5 SONET/SDH Interface This interface is 8 bits wide and runs at 19.44 MHz. The Serial SONET/SDH overhead channels are clocked in and out of the IC through low-speed serial ports. 3.3 Initialization 3.3.1 Hardware reset The HDMP-3001 hardware reset, RSTB, is asynchronous and must be active for at least 200 SONET clock cycles (>10 µ s) wit[...]

19 3.4.2 LAPS Mode In LAPS mode the FCS is calcu- lated LSB first and the FCS sum is transmitted in reversed bit order within each byte. See Figure 6 and Figure 7. 3.5 Performance Monitoring For performance monitoring pur- poses, the HDMP-3001 contains a number of delta bits, event bits and error counters. Delta bits are set by the HDMP- 3001 when [...]

20 Summary delta event bits provide a consolidated view of the various individual delta event bits, grouped either by function or SONET tributary. Summary delta events are therefore a function of the other delta events bits in the register maps. The summary bits are read only, and will only be cleared when all delta event bits that contribute to th[...]

21 3.6.2 JTAG The HDMP-3001 supports the IEEE 1149.1 Boundary Scan stan- dard. The Test Access Port consists of 5 pins as defined in Table 10. Signals TDI, TMS and TRSTSB are all pulled up to logic one when not driven. The HDMP-3001 TAP supports the mandatory EXTEST, SAMPLE/ PRELOAD, and BYPASS instruc- tions along with the optional CLAMP and HIGHZ[...]

22 EOS_D_SUM group indicates that at least one of the delta sig- nals below is unmasked and set. NEW_RX_MIN_ERR, NEW_RX_MAX_ERR, NEW_RX_OOS_ERR, NEW_RX_FORM_DEST_ERR, NEW_RX_FIFO_UR_ERR, NEW_RX_FIFO_OF_ERR, NEW_RX_FCS_HEC_ERR, NEW_TX_FIFO_UR_ERR, NEW_TX_FIFO_OF_ERR, NEW_TX_ER_ERR, NEW_TX_MII_ALIGN_ERR 3.7.4 APS_INTB RX_APS_INT interrupt message for[...]

23 3.8.1.1 FCS Polynomial for LAPS Processing The HDMP-3001 supports CRC-32 Frame Check Sequence (FCS) generation and checking. The polynomial used to generate and check the FCS is X 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1. The FCS field is calculated over all bits of the Address, Control, Payload, [...]

24 MSB PLI '+' 0xB6 NUMBER OF BYTES IN THE GFP P A YLOAD LSB PLI '+' 0xAB MSB cHEC '+' 0x31 LSB cHEC '+' 0xE0 MSB TYPE PROGRAMMABLE LSB TYPE PROGRAMMABLE MSB tHEC LSB tHEC MSB eHEC LSB eHEC MSB FCS[31:24] 1) 32-BIT CRC POL YNOMIAL FCS[23:16] 2) ON PRE-SCRAMBLED DA T A FCS[15:8] 3) COVERS THE GFP P A YLOAD DA [...]

25 • Pointer Bytes, H1, H2, H3 • BIP-96/24, B2 • APS bytes, K1, K2 • Synchronization Status, S1 • Line/MS REI, M1 • Transmits undefined TOH/SOH as fixed all zeros. • Scrambles payload using SONET/SDH frame synchronous descrambler, polynomial (X 7 + X 6 +1). 3.9.2 Receive SONET/SDH Process- ing Overview The Receive SONET/SDH Proces- so[...]

26 3.9.3.2 POH There are nine bytes of path over- head. The first byte of the path overhead is the path trace byte, J1. Its location with respect to the SONET/SDH TOH/SOH is indi- cated by the associated STS/AU pointer. The following sections define the transmitted values of the POH bytes. Where the byte names differ between SONET and SDH, the SONE[...]

27 PRDI_AUTO PRDI_ENH RX_PAIS RX_UNEQ RX_PLM G1 Bits 5, 6, and 7 RX_LOP 0 x x x x TX_G1[2:0] 101 x x 1 0 0 0x x0 0 0 1 1 x x 101 01 x1 1 0 00 10 1 0 00 00 0 1 Table 11. Path RDI bit values 3.9.3.2.9 POH AIS Generation Normal generation of SONET/ SDH payload is suspended during transmission of the Line (Multi- plex Section or MS) Alarm Indication Si[...]

28 Row Column 1 2-3 4 5-6 7 8-9 1 A1[1] A1[2,3] A2[1] A2[2,3] J0[1] Z0[2,3] 2B 1 E 1 F 1 3D 1 D 2 D 3 4 H1[1] H1[2,3] H2[1] H2[2,3] H3[1] H3[2,3] 5 B2[1] B2[2,3] K1 K2 6D 4 D 5 D 6 7D 7 D 8 D 9 8 D10 D11 D12 9 S1 Z1[2,3] 1 Z2[1] 1 Z2[2] 1 , M1 E2 Table 12. STS-3c/STM-1 TOH/SOH 3.9.3.3.4 Section Growth/Spare (ZO) Section Trace The Z0 bytes are trans[...]

29 Non-AIS Generation. The first H1-H2 byte pair is transmitted as a normal pointer with: • NDF = 0110 • SS (SONET/SDH) = 0 • Pointer Value = 10_0000_1010 All other H1-H2 byte pairs are transmitted as concatenation indi- cation bytes, with • NDF =1001 • SS = 0 • Pointer Value = 11_1111_1111. See Figure 14. 3.9.3.3.9 Line/MS BIP-24 (B2) [...]

30 scrambles the entire SONET/SDH frame except for the first row of TOH/SOH. For testing purposes, the scrambler can be disabled through the SCR_INH bit in the register map. 3.9.4 Receive SONET/SDH Processing Details 3.9.4.1 LOC The RX_SONETCLK input is monitored for loss of clock using the TCLK input. If no transitions are detected on RX_SONETCLK [...]

31 3.9.4.2.9 APS Monitoring If the K1 byte and the four MSBs of the K2 byte, which are used to send APS requests and channel numbers, are received identically for three consecutive frames, their values are written to RX_K1[7:0] and RX_K2[7:4]. Ac- cepted values are compared to the previous contents of these regis- ters, and when a new 12-bit value [...]

32 • If PTR_STATE[1:0] = 00 and {LOP2,AIS2} = 11 and {LOP3,AIS3} = 11, which is the normal case, then RX_PAIS = 0 and RX_LOP = 0. • If PTR_STATE[1:0] = 01 and {LOP2,AIS2} = 01 and {LOP3,AIS3} = 01, then RX_PAIS = 1 and RX_LOP = 0. • If PTR_STATE[1:0] = 10 and {LOP2,AIS2} = 01 and {LOP3,AIS3} = 10, then RX_PAIS = 0 and RX_LOP = 1. The RX_PAIS [...]

33 cates that the VC-4 starts three bytes after the K2 byte. In addition, 8-bit counters are pro- vided for counting positive and negative justification events, as well as NDF events. Status bits are provided for indicating the de- tection of negative justification, positive justification, NDF, invalid LOPC CONC Nx inv_point 3x AIS_ind 3x AIS_ind A[...]

34 Norm_point: Normal NDF AND match of ss bits AND offset value in range. NDF_enable: NDF enabled AND match of ss bits AND offset value in range. AIS_ind: 11111111 11111111. Incr_ind: Normal NDF AND match of ss bits AND majority of I bits inverted AND no majority of D bits inverted AND previous NDF_enable, incr_ind or decr_ind more than three frame[...]

35 can result in from 0 to 8 mis- matches (B3 bit errors). This value can be inserted into the Transmit Side G1 byte from bit one to bit four as a Path REI. The HDMP-3001 contains a 16-bit B3 error counter that counts every B3 bit error. When the perfor- mance monitoring counters are latched (LATCH_EVENT transi- tions high), the value of this count[...]

36 high-speed device that locates frame, does byte de-interleaving, and performs serial-to-parallel conversion of an STS-3c/STM-1 signal. 3.9.4.11 Framer Enabled Details If the framer is enabled (RX_FRMR_INH = 0), the HDMP-3001 device performs the framer processing as follows. When the framer state machine is out-of-frame (RX_OOF = 1), it searches [...]

37 3.9.4.14 B1 Monitor In both modes, the HDMP-3001 checks the received B1 bytes for correct Bit Interleaved Parity 8 (BIP-8) values. Even parity BIP-8 is calculated over all bytes of each frame before descrambling. This value is then compared to the re- ceived B1 value in the following frame after descrambling. The comparison can result in 0 to 8 [...]

38 4. Application Information 4.1 Chip setup and configuration 4.1.1 EEPROM Detection After reset, HDMP-3001 will probe the SDA pin. If tied to ground, no boot EEPROM is present and nor- mal operation will resume. If connected to an EEPROM, SDA is pulled high by an internal resistor and HDMP-3001 will start to load its configuration from the EEPROM[...]

39 Interrupt Output Int Active Description Mode[1:0] Configured Level Type 00 Open-Drain 0 Interrupt output INT is asserted with 0 and de-asserted with Z (Default) (O/D) externally. An external resistive pull-up is needed. Output buffer OEN is driven by an inversion of the internally maskable active-high interrupt signal. Output buffer ’ s input [...]

40 4.3 Firmware and System Design Information 4.3.1 Board level pull-ups and pull-downs Many of the HDMP-3001 input and tristateable outputs have internal pull-ups. Refer to the pin descrip- tion for detailed information on where external pull-ups are re- quired. 4.3.2 Motorola MPC860 Microprocessor Interface The recommended setup of the interface [...]

41 MII Signal HDMP-3001 pin HDMP-3001 pin (PHY Mode) (MAC Mode) TXD [3:0] P_TXD[3:0]/M_RXD[3:0] P_RXD[3:0]/M_TXD[3:0] TX_EN P_TX_EN/M_RX_DV P_RX_DV/M_TX_EN TX_ER P_TX_ER/M_RX_ER P_RX_ER/M_TX_ER TX_CLK P_TX_CLK/M_RX_CLK P_RX_CLK/M_TX_CLK RXD [3:0] P_RXD[3:0]/M_TXD[3:0] P_TXD[3:0]/M_RXD[3:0] RX_DV P_RX_DV/M_TX_EN P_TX_EN/M_RX_DV RX_ER P_RX_ER/M_TX_ER[...]

42 5. Register Definitions The HDMP-3001 contains two reg- ister maps. One is the MII Management (MDIO) register map, which can only be accessed through the MDIO port. The other register map is the chip register map which can be accessed through the MDIO, microproces- sor and EEPROM ports. 5.1 MII Management Register Map The MII Management register[...]

43 Address Bit Type Bit Name Default value Description 8 R Extended Status Fixed 0 No extended status information in register 15. 7 R Reserved Fixed 0 6 R MF Preamble Suppression Fixed 0 PHY does not allow preamble to be suppressed in management frames. 5 R Auto-Negotiation Complete Fixed 0 Not supported. 4 R Remote Fault Fixed 0 Not supported. 3 R[...]

44 Address Register Name Common Registers 0x000 Reset and Performance Latch Control 0x001 Test Modes 0x002 Reserved 0x003 Microprocessor Interrupt Pin Mode 0x004 Chip Revision 0x005 PHY Address 0x006 Interrupt Status 0x007 Event Summary 0x008 Summary Interrupt Mask 0x009 Mode of Operation 0x00A Rx Event Summary Mask 0x00B SONET/SDH Configuration 0x[...]

45 Address Register Name SONET/SDH Transmit Registers 0x0B4 Transmit G1 Control 0x0B5 Reserved 0x0B6-0x0F5 Transmit J1 Bytes (64) 0x0F6 Reserved 0x0F7 POH Error Generation 0x0F8 Transmit C2 Byte SONET/SDH Receive Registers 0x0F9 Receive LOH Monitor Delta 0x0FA Receive SOH Monitor Delta 0x0FB Reserved 0x0FC Receive LOH Monitor Masks 0x0FD Receive SO[...]

46 Address Register Name 0x122 Receive Pointer Interpreter Mask 0x123-0x125 Reserved 0x126 Receive Pointer Interpreter Delta 0x127 Reserved 0x128 Receive Pointer Status (1) 0x129 Reserved 0x12A Receive Pointer Status (2) 0x12B-0x12C Reserved 0x12D Receive J1 Reading Control 0x12E Receive J1 Mode Control 0x12F Receive RDI Monitor 0x130 Receive J1 De[...]

47 Address Register Name 0x182 Transmit Control/Type_L Field 0x183 Transmit Rate Adaptation/Type_H Field 0x184-0x185 Transmit FIFO Threshold 0x186 Transmit LAPS mode 0x187 GFP Mode 0x188 TX SAPI LSB / Spare Byte 0x189 TX_SAPI_MSB 0x18A-0x18B Reserved 0x18C-0x18F Transmit MII Frames Received OK Counter 0x190-0x193 Transmit MII Alignment Error Counte[...]

48 Address Register Name 0x1CF Receive Spare Field Byte 0x1D0 Receive Pre-Sync States 0x1D1-0x1D2 Receive SAPI Field 0x1D3 Reserved 0x1D4-0x1D7 Receive MII Frames Transmitted OK 0x1D8-0x1DB Receive FCS and HEC Error Counter 0x1DC-0x1DF Receive Format and Destination Error Counter 0x1E0-0x1E3 Receive Out of Sync Error Counter 0x1E4-0x1E7 Receive FIF[...]

49 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved LATCH_ Reserved STATE_ GLOBAL_ CNT RESET RESET R/W — ——— R/W — R/W WSR Value 0 000 0 0 0 0 after reset ADDR=0x000: Reset and Performance Latch Control Bits 7-4: Reserved Bit 3: LATCH_CNT is set to transfer performance monitor counters to regist[...]

50 Bits 7-6: Reserved Bit 5: SDA_PU_DIS disables the internal SDA pull-up when high. Bit 4: SCL_PU_DIS disables the internal SCL pull-up when high. Bits 3-2: Reserved Bits 1-0: INT_MODE specifies the Microprocessor Interrupt Pin Mode which configures the INT (tristate) output pin to support one of four modes: (1) 00: Default mode, Open-Drain, INT a[...]

51 ADDR = 0x005: PHY Address[4:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved PHY_ADDR[4:0] R/W — —— R/W Value 0 0 0 0x1B after reset Bits 7-5: Reserved Bits 4-0: PHY_ADDR specifies the PHY address for the HDMP-3001 chip. The chip uses the PHY address to respond to the Management Entity when addressed t[...]

52 ADDR=0x007: Event Summary Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name TOH_D_SUM Reserved PTR_D_SUM POH_D_SUM Reserved EOS_D_SUM Reserved Reserved R/W R — RRR R —— Value 0 0 000 00 0 after reset Bit 7: TOH_D_SUM is set to indicate at least one of the TOH/SOH delta bits (RX_LOS_D, RX_OOF_D, RX_LOF_D, RX_LAIS_D, RX_LRDI_D, J0_OOF[...]

53 ADDR=0x009: Mode of Operation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved ISOLATE_ SONET/SDH PHY/MAC GFP/LAPS MII R/W —— — — R/W R/W R/W R/W Value 0 0 00 10 0 0 after reset Note that this register only should be programmed when STATE_RESET is active. Bits 7-4: Reserved Bit 3: ISOLATE_MII i[...]

54 ADDR=0x00B: SONET/SDH Configuration Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved TX_UNEQ Reserved Reserved TX_SONET RX_SONET_DSCR Reserved _SCR_INH _INH R/W —— R/W —— R/W R/W — Value 0 0 000 0 0 0 after reset Bits 7-6: Reserved Bit 5: TX_UNEQ is set to generate all zeros in its SPE/VC bytes to create unequ[...]

55 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Value 1 1 111 11 1 after reset ADDR=0x00E: GPIO [7:0] Data Bits 7-0: GPIO[7:0] : General purpose I/O bits 7:0, and they are defaulted as inputs. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name GPIO[...]

56 This is a BIP calculating control register. Bits 7-3: Reserved Bit 2: TX_B1_INV is set to calculate B1 by odd parity (for testing purposes). Bit 1: TX_B2_INV is set to calculate B2 by odd parity (for testing purposes). Bit 0: TX_B3_INV is set to calculate B3 by odd parity (for testing purposes). 5.3 SONET/SDH Transmit Registers ADDR=0x09C: Trans[...]

57 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name TX_J0[0]_[7:0] • • • TX_J0[15]_[7:0] R/W R/W Value 0 0 0 0 0 000 after reset ADDR=0x09F – 0x0AE: Transmit J0 Bytes 1 – 16 Bits 7-0: TX_J0[0:15]_[7:0]: Transmit J0 (Section Trace) – When enable, the HDMP-3001 will continuously transmit in the 16-byte pattern in these registers i[...]

58 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name TEST_K1[7:0] R/W R/W Value 0 0 00 00 0 0 after reset ADDR=0x0B1: Transmit K1 Byte TX_K1[7:0]: These bits are automatic protection switching (APS) signaling. The HDMP-3001 inserts TX_K1[7:0] into the transmitted K1 byte, and TX_K2[7:3] into the five MSBs of the transmitted K2 byte. The thre[...]

59 Table 20. G1 values PRDI_ PRDI_ RX_PAIS || RX_UNEQ RX_PLM G1 Bits 5, 6, & 7 AUTO ENH RX_LOP 0x x x x TX_G1[2:0] 1 0 1 x x 100 0 x x 000 1 1 x x 101 0 1 x 110 0 0 1 010 0 0 0 001 When Transmit J1 (Path Trace) enabled, 1. When SONET/SDH = 1, the J1 byte is transmitted repetitively as the 16-byte sequence in TX_J1[15]_[7:0] down to TX_J1[0]_[7:[...]

60 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved TX_G1 [2:0] Reserved Reserved Reserved TX_PAIS R/W — R/W —— — R/W Value 0 0 00 00 0 0 after reset ADDR=0x0F7: POH Error Generation Bit 7: Reserved Bits 6-4: TX_G1[2:0] When PRDI_AUTO = 0, the values transmitted in bits 7-5 of G1 are taken from these three bits. Bits 3-1: R[...]

61 Bit 7: J0_OOF_D – J0_OOF delta bit Bit 6: Reserved Bit 5: RX_LAIS_D – RX_LAIS delta bit Bit 4: RX_LRDI_D – RX_LRDI delta bit Bit 3: RX_K1_D – RX_K1 delta bit Bit 2: K1_UNSTAB_D – K1_UNSTAB delta bit Bit 1: RX_K2_D – RX_K2 delta bit Bit 0: Reserved Receive LOH Monitor Delta Bits: If one, there is a change in state of the corresponding[...]

62 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name J0_OOF_ Reserved RX_LAIS_ RX_LRDI_ RX_K1_D K1_UNSTAB RX_K2_D Reserved D_MASK D_MASK D_MASK _ MASK _D_MASK _ MASK R/W R/W — R/W R/W R/W R/W R/W — Value 1 111 11 11 reset ADDR=0x0FC: Receive LOH Monitor Masks Bit 7: J0_OOF_D_MASK – J0_OOF delta bit mask Bit 6: Reserved, always write as[...]

63 ADDR=0x0FF: Receive TOH Monitor Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name K2_CONSEC_NUM[3:0] RX_LOS_ RX_LOS_ RX_FRAM_ RX_LOF_ LEVEL INH INH ALG R/W R/W R/W R/W R/W R/W Value 0 1 0 1 0000 after reset Bits 7-4: K2_CONSEC_NUM[3:0]: This 4 bit register is used to keep track of the number of consecutive occurrences of LAIS and [...]

64 Table 21. STS-3c/STM-1 configuration for RX_FRAME_POSITION [3:0] Data on RX_DATA[7:0] RX_FRAME_POSITION[3:0] last byte of frame 0000 first A1 byte 0001 second A1 byte 0010 third A1 byte 0011 first A2 byte 0100 second A2 byte 0101 third A2 byte 0110 J0 byte 0111 first Z0 byte 1000 last Z0 byte 1001 first byte after last Z0 byte 1010 second byte a[...]

65 Bit 0: J0_OOF: J0_OOF = 0 when the most significant bits of all J0 bytes are zero except for the MSB of the frame start marker byte. The J0 monitor framer searches for 15 consecutive J0 bytes that have a zero in their MSB and followed by a J0 byte with a zero in its MSB. J0_OOF = 1 once the J0 monitor framer is in frame. It remains in frame unti[...]

66 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name RX_J0 [0]_[7:0] • • • RX_J0 [15]_[7:0] R/W R Value 0 after reset ADDR=0x104 – 0x113: Receive J0 Bytes 0 – 15 Bits 7-0: RX_J0 [0:15]_[7:0]: (Section Trace) The received 16 J0 bytes. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved RX_S1[[...]

67 Bits 7-0: RX_K1[7:0]: (APS Signaling) The received K1 byte. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name RX_K1 [7:0] R/W R Value 0000 0 0 0 0 after reset ADDR=0x117: Receive K1 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name B1_ERRCNT[7:0] R/W R Value 0000 0 0 0 0 after reset ADDR=0x118: Receive B1 Error Count Bits 7-0:[...]

68 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name B2_ERRCNT[7:0] R/W R Value 0000 0 0 0 0 after reset ADDR=0x11B: Receive B2 Error Count Bits 7-0: B2_ERRCNT[15:8] Bits 7-0: B2_ERRCNT[7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name B2_ERRCNT[15:8] R/W R Value 0000 0 0 0 0 after reset ADDR=0x11C: Receive B2 Error Count Bit 7 B[...]

69 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name M1_ERRCNT[7:0] R/W R Value 0000 0 0 0 0 after reset ADDR=0x11F: Receive M1 Error Count Bits 7-0: M1_ERRCNT[7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name M1_ERRCNT[15:8] R/W R Value 0000 0 0 0 0 after reset ADDR=0x120: Receive M1 Error Count Bits 7-0: M1_ERRCNT[15:8] Bit 7 B[...]

70 ADDR=0x122: Receive Pointer Interpreter Mask Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved Reserved Reserved RX_LOP_D RX_PAIS_ _MASK D_MASK R/W — ——— — — R/W R/W Value 0 000 0 0 1 1 after reset Bits 7-2: Reserved Bit 1: RX_LOP_D_MASK: RX_LOP delta bit mask Bit 0: RX_PAIS_D_MASK: RX_PAIS [...]

71 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved P_STATE[1:0] RX_LOP RX_PAIS R/W ———— RR R Value 0000 0 0 1 1 after reset ADDR=0x128: Receive Pointer Status(1) Bits 7-3: Reserved Bits 3-2: P_STATE_[1:0]: These bits are used to monitor the first pair of H1/H2 bytes in the received SONET/SDH fram[...]

72 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name J1_READ Reserved Reserved Reserved Reserved Reserved Reserved Reserved R/W R/W — ——— ——— Value 00 000 000 after reset ADDR=0x12D: Receive J1 Reading Control Bit 7: J1_READ: When J1_READ transitions from 0 to 1, the HDMP-3001 will latch the 64-byte string it received in the J1[...]

73 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name G1_CONSEC_NUM[3:0] Reserved Reserved Reserved RX_PRDI5 R/W R/W — —— R/W Value 01 010 000 after reset ADDR=0x12F: Receive RDI Monitor Bits 7-4: G1_CONSEC_NUM [3:0]: These 4 bit registers specify the number of consecutive received G1 bytes which will be monitored to determine if a Path[...]

74 ADDR=0x131: Receive J1 Mask Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved Reserved Reserved J1_AVL_ J1_OOF_D_ MASK MASK R/W — ——— — — R/W R/W Value 00 0 0 001 1 after reset Bits 7-2: Reserved Bit 1: J1_AVL_MASK: J1_AVL mask bit. Bit 0: J1_OOF_D_MASK: J1_OOF delta bit mask. These bits are[...]

75 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved Reserved Reserved Reserved J1_OOF R/W —— ——— —— R Value 00 000 001 after reset ADDR=0x133: Receive J1 OOF Bits 7-1: Reserved Bit 0: J1_OOF: The J1 monitor framer searches for 15 consecutive J1 bytes that have a zero in their MSB, followed b[...]

76 ADDR=0x174: Receive Path Delta Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved RX_C2_D RX_G1_D RX_UNEQ_ RX_PLM_D Reserved D R/W — —— W1C W1C W1C W1C — Value 0 000 0 0 0 — after reset Bits 7-5: Reserved Bit 4: RX_C2_D: RX_C2 delta bit. It is set when a new value is stored in RX_G1 [2:0]. Bit 3: RX_G1_[...]

77 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved RX_G1[2:0] RX_UNEQ RX_PLM Reserved R/W —— R RR — Value 00 0 000 after reset ADDR=0x178: Receive UNEQ Monitor Bits 7-6: Reserved Bits 5-3: RX_G1[2:0]: When a consistent G1 monitor is received, bits 5,6, and 7 of G1 are written to RX_G1[2:0]. Bit 2: RX_UNEQ: It contri[...]

78 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name B3_ERRCNT[15:8] R/W R Value 0x00 after reset ADDR=0x17C: B3 Error Count Bits 7-0: B3_ERRCNT [15:8]: A 16-bit counter that counts every BIP-8 (B3) error. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name G1_ERRCNT[7:0] R/W R Value 0x00 after reset ADDR=0x17E: G1 Error Count Bits 7-0:[...]

79 5.5 Ethernet Transmit Registers ADDR = 0x180: GFP/LAPS control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved Reserved TX_SCR_ TX_FCS_ TX_FCS_ INH CORR INH R/W — ——— — R/W R/W R/W Value 00 0 0 000 0 after reset Bits 7-3: Reserved Bit 2: TX_SCR_INH is set to inhibit the Ethernet TX scramblin[...]

80 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name TX_CNT_TYPE_L[7:0] R/W R/W Value 0x03 after reset ADDR = 0x182: Transmit Control/Type_L Byte Bits 7-0: TX_CNT_TYPE_L[7:0] specifies the Control Byte for LAPS mode and the LSB of the TYPE field for GFP mode, which is the Payload Identifier. This byte will be sent out in the encapsulated LAP[...]

81 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name TX_FIFO_THRESHOLD[7:0] (LSB) R/W R/W Value 0x88 after reset ADDR = 0x184: Transmit FIFO Threshold[7:0] (LSB) TX_FIFO_THRESHOLD[7:0] specifies the LSB of the TX FIFO Threshold which is used by the INFO FIELD TX FIFO Controller to determine when it starts to read the data from the TX FIFO. F[...]

82 ADDR = 0x186: Transmit LAPS mode Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved TX_ADR_ TX_CNT_ TX_SAPI_ TX_ABORT TX_RA_ INH INH INH _INH INH R/W — —— R/W R/W R/W R/W R/W Value 00 0 0 000 0 after reset Bits 7-5: Reserved Bit 4: TX_ADR_INH is set to inhibit the insertion of the programmed address byte in[...]

83 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name TX_SAPI_L_SPARE[7:0] R/W R/W Value 0x01 after reset ADDR = 0x188: Transmit SAPI LSB / Spare Byte Bits 7-0: TX_SAPI_L_SPARE[7:0] is the LSB of the SAPI field in LAPS mode and the spare field byte in GFP frame. In LAPS mode it is sent as part of the header unless the TX_SAPI_INH bit is set. [...]

84 TX_MII_FRAMES_REC_OK[23:0] is the Transmit MII Frames Received OK counter. It is non-resetable except that a hard or soft reset will clear it. After reaching its max value the counter starts over from zero again. This counter is incremented for each frame that was properly byte aligned, did not cause a FIFO error and was received with the TX_ER [...]

85 ADDR = 0x194-0x197: TX_ER Error Counter ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name 0x194 TX_ER_ERR [7:0] 0x195 TX_ER_ERR [15:8] 0x196 TX_ER_ERR [23:16] 0x197 Fixed 0 R/W RO Value 0 after reset TX_ER_ERR is the TX_ER Error counter. It is non-resetable except that a hard or soft reset will clear it. After reaching its max value [...]

86 ADDR = 0x19C-F: TX FIFO Underrun Error ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name 0x19C TX_FIFO_UR_ERR [7:0] 0x19D TX_FIFO_UR_ERR [15:8] 0x19E Fixed 0 0x19F Fixed 0 R/W RO Value 0 after reset TX_FIFO_UR_ERR is the TX_FIFO Underrun Error counter. It is non-resetable except that a hard or soft reset will clear it. After reaching[...]

87 ADDR = 0x1A1: Ethernet Transmit Interrupt Mask Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved NEW_TX_ NEW_TX_ NEW_TX_ NEW_TX_ FIFO_UR_ FIFO_OF_ ER_MASK MII_ALIGN MASK MASK _MASK R/W — ——— R/W R/W R/W R/W Value 00 0 0 111 1 after reset Bits 7-4: Reserved Bit 3: NEW_TX_FIFO_UR_MASK is set to su[...]

88 Bits 7-3: Reserved Bit 2: RX_DES_INH is set to inhibit the descrambling (X 43 +1) of the RX Payload Data sent from the SPE/VC Extractor in the SONET/SDH portion. Removal of the GFP core header DC balancing is still performed. Bit 1: RX_FCS_INH is set to inhibit the checking of the LAPS/GFP 32-bit FCS field. In GFP mode, the optional FCS is assum[...]

89 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved Reserved RX_FIFO_THRESHOLD[10:8] R/W —— ——— R/W Value 00 000 0 x 1 after reset ADDR = 0x1C3: RX FIFO Transmit Threshold[10:8] Bits 7-3: Reserved Bits 2-0: RX_FIFO_THRESHOLD[10:8] are the three MSBs of the previous register. Bit 7 Bit 6 Bit 5 Bi[...]

90 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved Reserved HI_IFG_WATER_MARK[10:8] R/W —— ——— R/W Value 00 000 0 x 6 after reset ADDR = 0x1C5: High Inter-Frame-Gap Water Mark Bits 7-3: Reserved Bits 2-0: HI_IFG_WATER_MARK[10:8] are the three MSBs of the previous register. Bit 7 Bit 6 Bit 5 Bit[...]

91 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved Reserved LO_IFG_WATER_MARK[10:8] R/W —— ——— R/W Value 00 000 0 x 2 after reset ADDR = 0x1C7: Low Inter-Frame-Gap Water Mark Bits 7-3: Reserved Bits 2-0: LO_IFG_WATER_MARK[10:8] are the three MSBs of the previous register. Bit 7 Bit 6 Bit 5 Bit [...]

92 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved LOW_IFG[4:0] R/W —— — R/W Value 0 0 0 0x0A after reset ADDR = 0x1C9: Low Inter-Frame-Gap Bits 7-5: Reserved Bits 4-0: LOW_IFG[4:0] specifies the Low Inter-Frame-Gap which is used by the MII RX interface to insert the minimum number of idle cycles between tw[...]

93 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name RX_CNT_TYPE_H [7:0] R/W R/W Value 0x03 after reset ADDR = 0x1CB: Receive Control/TYPE_H Bits 7-0: RX_CNT_TYPE_H [7:0] specifies the expected Control when in LAPS mode or the expected MSB of the Type field when in GFP mode, which consists of the Extension Header Identification, Payload FCS [...]

94 ADDR = 0x1CD: LAPS Mode Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved RX_ADR_ RX_CNT_ RX_SAPI_ RX_ADR_ RX_CNT_ RX_SAPI_ REM_INH REM_INH REM_INH CHECK_ CHECK_ CHECK_ INH INH INH R/W —— R/W R/W R/W R/W R/W R/W Value 00 0 0 000 0 after reset Bits 7-6: Reserved Bit 5: RX_ADR_REM_INH is set to inhibit the removal of t[...]

95 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name RX_EXT_ RX_TYPE_ RX_EHEC RX_THEC RX_TYPE RX_SPARE RX_DP_ RX_SP_ HDR_REM HDR_REM _CHECK_ _CHECK_ CHECK_ _CHECK CHECK_ CHECK_ _INH _INH INH INH INH _INH INH INH R/W R/W R/W R/W R/W R/W R/W R/W R/W Value 0 000 00 00 reset ADDR = 0x1CE: GFP Mode Bit 7: RX_EXT_HDR_REM_INH is set for GFP null he[...]

96 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved Reserved Reserved Reserved RX_PRESYNC[3:0] R/W —— —— R/W Value 00 000 x 1 after reset ADDR = 0x1D0: Receive Pre-Sync States Bits 7-4: Reserved Bits3-0: RX_PRESYNC specifies the number of Pre-Sync states the GFP RX Processor performs before it transits to the Sync state dur[...]

97 ADDR = 0x1D4-7: Receive MII Frames Transmitted OK ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name 0x1D4 RX_MII_FRAMES_XMIT_OK [7:0] 0x1D5 RX_MII_FRAMES_XMIT_OK [15:8] 0x1D6 RX_MII_FRAMES_XMIT_OK [23:16] 0x1D7 Fixed 0 R/W RO Value 0 after reset RX_MII_FRAMES_XMIT_OK is the RX MII Frames Transmitted OK counter. It is non-resetable ex[...]

98 ADDR = 0x1DC-F: Receive Format and Destination Error Counter ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name 0x1DC RX_ FORM_DEST_ERR [7:0] 0x1DD RX_ FORM_DEST_ERR [15:8] 0x1DE RX_ FORM_DEST_ERR [23:16] 0x1DF Fixed 0 R/W RO Value 0 after reset RX_FORM_DEST_ERR is the RX Format and Destination Error counter. It is non-resetable excep[...]

99 ADDR = 0x1E4-E7: Receive FIFO Overflow Error ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name 0x1E4 RX_FIFO_OF_ERR [7:0] 0x1E5 RX_FIFO_OF_ERR [15:8] 0x1E6 Fixed 0 0x1E7 Fixed 0 R/W RO Value 0 after reset RX_FIFO_OF_ERR is the RX FIFO Overflow Error counter. It is non-resetable except that a hard or soft reset will clear it. After re[...]

100 ADDR = 0x1EC: Ethernet Receive Interrupt Event Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name Reserved NEW_RX_ NEW_RX_ NEW_RX_ NEW_RX_ NEW_RX_ NEW_RX_ NEW_RX_ MIN_ERR MAX_ERR OOS_ERR FORM_ FIFO_UR_ FIFO_OF_ FCS_HEC_ DEST_ERR ERR ERR ERR R/W — R/W R/W R/W R/W R/W R/W R/W W1C W1C W1C W1C W1C W1C W1C Value 00 0 0 000 0 after reset Bits[...]

101 Bits 7: Reserved Bit 6: NEW_RX_MIN_MASK is set to suppress the new RX Min Error from setting the EOS_D_SUM Summary Interrupt bit. This interrupt mask bit does not affect the corresponding interrupt event bit. Bit 5: NEW_RX_MAX_MASK is set to suppress the new RX Max Error from setting the EOS_D_SUM Summary Interrupt bit. This interrupt mask bit [...]

102 ADDR = 0x1EF: Receive Minimum Frame Size Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name RX_MIN RX_MIN_SIZE[6:0] ENFORCE R/W R/W R/W Value 0 0x40 after reset Bit 7: RX_MIN_ENFORCE enables the enforcing of a minimum frame size. When high, frames with fewer bytes are discarded. When low, no minimum frame size is enforced. Bits 6-0: RX_MI[...]

103 ADDR = 0x1F4-7: Receive Minimum Frame Size Violations [23:0] ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit name 0x1F4 RX_MIN_ERR [7:0] 0x1F5 RX_MIN_ERR [15:8] 0x1F6 RX_MIN_ERR [23:16] 0x1F7 Fixed 0 R/W RO Value 0 after reset RX_MIN_ERR is the RX minimum frame size violation counter. It is non-resetable except that a hard or soft rese[...]

104 6. Package Specification Package marking and outline drawings for the HDMP-3001 28x28mm, 160 pin PQFP. Figure 25. Top View of Package HDMP-3001 LLLLLLLLL-NNN G YYWW R.R CCCCC LLLLLLLLL - W AFER LOT NUMBER NNN - W AFER NUMBER G - SUPPLIER CODE YY - LAST TWO DIGITS OF YEAR WW - TWO DIGIT WORK WEEK R.R - DIE REVISION NUMBER CCCCC - COUNTRY OF ORIG[...]

105 Figure 26. Bottom View of Package Figure 27. Side View of Package Figure 28. Detailed View of Pin 12 2 H L BASE PLANE A1 A2 DET AIL "B" 0 - 7 ° C C 0.25 GAGE PLANE R 0.13/0.30 0 ° MIN. 0.40 MIN. 0.13 R MIN. 1.60 REF . 11 11 9 10 10 11 10 11 10 b b 1 BASE MET AL SECTION C-C WITH LEAD FINISH 0.11/0.19 0.11/0.23 DA TUM PLANE SEA TING P[...]

106 Symbol Min Nom Max Comment A - 3.7 4.1 Seated height A 1 0.25 0.33 0.5 Stand off A 2 3.2 3.37 3.6 Body thickness D 31.20 Bsc 4 D 1 28.00 Bsc Package length D 2 25.35 Bsc E 31.20 Bsc E 1 28.00 Bsc Package width E 2 25.35 Bsc L 0.73 0.88 1.03 N 160 Lead count e 0.65 Bsc Lead pitch b 0.22 - 0.40 Plated lead width b 1 0.22 0.3 0.36 ccc 0.13 Coplana[...]

107 Table 23. Absolute Maximum Ratings Parameter Min Max Units Supply Voltage (VDD) -0.5 2.5 Volts Supply Voltage (DVDD) -0.5 4.5 Volts Junction Temperature 0.0 110 ° C Storage Temperature -40 125 ° C ESD 2 KV Caution: Exceeding the values stated above could permanently damage the device. Prolonged exposure to absolute maximum ratings may affect [...]

108 7.5 AC Electrical Characteristics The specifications in this section are valid for the range of operating conditions defined in Table 24. 7.5.1 General AC specifications Table 28. Clock requirements and switching characteristics Parameter Min Max Units Conditions Clock Frequency 25 – 100 ppm 25 + 100 ppm MHz P_TX_CLK_M_RX_CLK, P_RX_CLK_M_TX_C[...]

109 7.5.2 MII specifications Table 29. MII AC Specification Parameter Min Max Units Conditions PHY mode output Setup time 10 ns P_RXD_M_TXD, P_RX_DV_M_TX_EN, P_RX_ER_M_TX_ER, ↑ P_RX_CLK_M_TX_CLK PHY mode output hold time 10 ns P_RXD_M_TXD, P_RX_DV_M_TX_EN, P_RX_ER_M_TX_ER, ↑ P_RX_CLK_M_TX_CLK MAC mode output Setup time 15 ns P_RXD_M_TXD, P_RX_D[...]

110 8. Timing Diagrams 8.1 Microprocessor Bus Timing - Write Cycle Figure 29. Microprocessor Write Cycle Timing. * RDYB is re-clocked twice by the microprocessor clock in addition to the timing shown. This adds an additional delay of between one and two microprocessor clock cycles. V ALID V ALID NEW V ALUE t 1 t 2 t 6 Hi - Z t 3 t 4 t 5 Hi - Z Hi -[...]

111 8.2 Microprocessor Bus Timing - Read Cycle. Figure 30. Microprocessor Read Cycle Timing. * RDYB is re-clocked twice by the microprocessor clock in addition to the timing shown. This adds an additional delay of between one and two microprocessor clock cycles. V ALID t 7 t 10 t 9 INV ALID VALID CAPTURED Hi - Z Hi - Z Hi - Z Hi - Z A[8:0] CSB WRB [...]

112 8.3 Microprocessor Bus Timing Table Table 30. Timing of microprocessor bus Parameter Description Min (ns) Max (ns) t 1 CS_N active to RDYB driven to inactive state 0 15 t 2 CS_N, WRB and RDB valid to A and D captured 90 270 t 3 1 CS_N, WRB and RDB valid to RDYB active 140 1 220 1 t 4 BUSMODE 0: WRB inactive to RDYB inactive 0 15 BUSMODE 1: RDB [...]

113 RX_SONETCLK RX_DA T A[7:0] RX_FRAME_IN t HRDFC t HFIFC t SRDTC t SFITC Label Parameter Min Max Units RX_SONETCLK RX_SONETCLK frequency 19.44-20ppm 19.44+20ppm MHz t SRDTC Setup RX_DATA to RX_CLK high 5 ns t HRDFC Hold RX_DATA from RX_CLK high 5 ns t SFITC Setup RX_FRAME_IN to RX_CLK high 5 ns t HFIFC Hold RX_FRAME_IN from RX_CLK high 5 ns 8.5 T[...]

114 8.6 TOH Interface E1/E2/F1 Receive Timing RX_E1E2F1_CLK RX_E1_DA T A RX_E2_DA T A RX_F1_DA T A t VE1FC t HE2FC t HF1FC Label Parameter Min Typ. Max Units RX_E1E2F1_CLK TX_E1E2F1_CLK frequency 64 kHz t VE1FC Transition RX_E1_DATA from RX_E1E2F1_CLK low 30 70 ns t HE2FC Transition RX_E2_DATA from RX_E1E2F1_CLK low 30 70 ns t HF1FC Transition RX_F[...]

115 RX_SDCC_CLK RX_LDCC_CLK RX_SDCC_DA T A RX_LDCC_DA T A t VSDCFC t VLDCFC Label Parameter Min Typ. Max Units RX_SDCC_CLK RX_SDCC_CLK frequency 192 kHz t VSDCFC Transition RX_SDCC_DATA from RX_SDCC_CLK low 30 70 ns RX_LDCC_CLK RX_LDCC_CLK frequency 576 kHz t VLDCFC Transition RX_LDCC_DATA from RX_LDCC_CLK 30 70 ns 8.9 JTAG Interface Timing TCK TDI[...]

116 8.10 Reset specification The HDMP-3001 reset pin (RSTB) is an asynchronous pin that must be active for at least 200 SONET clock cycles (>10 µ s) with stable power. TX_CLK TX_D[3:0], TX_EN, TX_ER RX_D[3:0], RX_DV , RX_ER RX_CLK t TX 0 ns MIN., 25 ns MAX. t RXS 10 ns MIN. t RXH 10 ns MIN. V ALID V ALID Figure 38. MII timing as defined by IEEE[...]

117 Table 31. MII signal clocking Mode Direction Pin name In/Out Note PHY TX P_TXD[3:0]/M_RXD[3:0], I n Clocked in by P_TX_EN/M_RX_DV, P_TX_CLK/M_RX_CLK P_TX_ER/M_RX_ER P_TX_CLK/M_RX_CLK Out RX P_RXD[3:0]/M_TXD[3:0], Out Clocked out by MII_RX. P_RX_DV/M_TX_EN, P_RX_ER/M_TX_ER P_RX_CLK/M_TX_CLK Out Inverted version of MII_RX. MAC TX P_RXD[3:0]/M_TXD[...]

118 8.13 EEPROM Port Timing Table 32. EEPROM Interface Timing Parameters Parameter MIN MAX UNITS SCL clock frequency 97.2 kHz SCL high period 4.9 µ s SCL low period 4.9 µ s Setup time for reSTART 4.9 µ s Hold time for START/reSTART 4.9 µ s Setup time for STOP 4.9 µ s Bus free between STOP & START 4.9 µ s SDA setup time, HDMP-3001 driving [...]

119 FOUR CONSECUTIVE FRAMES CONT AINING FRAMING P A TTERN ERRORS A1 A1 A1 A2 A2 A2 A1 A1 A1 A2 A2 A2 A1 A1 A1 A2 A2 A2 A1 A1 A1 A2 A2 A1/A2 ERROR A1/A2 ERROR A1/A2 ERROR A1/A2 ERROR A2 C1 C1 C1 RX_DA T A[7:0] RX_SONETCLK OOF The out of frame declaration timing diagram (Figure 40) illustrates the declaration of out of frame. In an STS-3 (STM-1) stre[...]

120 Figure 43. Transmit Overhead Clock and Data Alignment The transmit overhead clock and data alignment timing diagram (Figure 43) shows the relationship between the TX_E1_DATA, TX_E2_DATA and TX_F1_DATA serial data inputs and their associated clock TX_E1E2F1_CLK. It is a 72 kHz 50% duty cycle clock that is gapped to produce a 64 kHz nominal rate [...]

121 APPROX. 750 ns E1, E2, F1 B1 B2 B3 B4 B5 B6 B7 B8 RX_FRAME_SFP RX_SONETCLK RX_E1E2F1_CLK Figure 44. Receive Overhead Clock and Data Alignment The receive overhead alignment timing diagram (Figure 44) shows the relationship between the RX_E1_DATA, RX_E2_DATA and RX_F1_DATA serial data outputs and their associated clock RX_E1E2F1_CLK. It is a 72 [...]

122 APPROX. 2M TX_LDCC_CLK BURSTS ROW 1 BYTES ROW 2 BYTES ROW 3 BYTES ROW 4 BYTES ROW 5 BYTES ROW 6 BYTES ROW 7 BYTES ROW 8 BYTES ROW 9 BYTES B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 TX_FRAME_SFP TX_SDCC_CLK TX_SDCC_DA T A TX_LDCC_CLK TX_LDCC_DA T[...]

123 ROW 1 BYTES ROW 2 BYTES ROW 3 BYTES ROW 4 BYTES ROW 5 BYTES ROW 6 BYTES ROW 7 BYTES ROW 8 BYTES ROW 9 BYTES B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 RX_FRAME_SFP RX_SDCC_CLK RX_SDCC_DA T A RX_LDCC_CLK RX_LDCC_DA T A APPROX. 2M RX_LDCC_CLK RX_L[...]

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