Apple PowerPC G5 manual

Po w erPC G5 T he W orld’ s F irst 64-Bit Desktop P roce ssor White P aper July 2003[...]

Co nte n t s P age 3 Introduction P age 4 The World’ s First 64-Bit Desktop P rocessor An Exponential Leap in C omputing P ower M emory Addressing up to 1 8 Exabytes High-Precision C alculations in a Single Clock Cycle Clock Speeds up to 2GHz Industry-Leading 1GHz Fron tside Bus F ull Support for Symmetric Multiprocessing Native Compatibility wit[...]

In troduction T he revolutionary P owerPC G5 changes everything you know about personal computing. Suddenly , the next generation of high-performance applications for design and graphics, media production, and scientific research is possible and practical on the desktop . That’ s because the P owerPC G5 brings a 64-bit architecture to the Mac pla[...]

T he W orld’ s F irst 64-Bit De sktop P roc essor T he P owerPC G5 marks the arrival of 64-bit per formance to the personal computer market. With 6 4-bit-wide data paths and registers , this groundbreak ing new processor can address vast amoun ts of main memor y and handle multiple large in teger and floating-point math calculations in a single c[...]

High-Pr ecision Calculations in a Single Clock C ycle With 64-bit-wide data paths and registers, the P owerPC G5 can execute instructions on 64 bits of data in a single clock cycle—mak ing it possible to perform huge integer calculations and highly precise floating-point mathematics. In contrast, a 32-bit pr o- cessor would hav e to split up any [...]

Native C ompatibilit y with 3 2-Bit Application Code On other platforms, switching to a 64-bit computer requires migrating t o a 64-bit operating system (and purchasing 64-bit applications) or running a 3 2-bit operating system in a slow emulation mode. With the P owerPC G5, the transition to a 64-bit system is seamless: Current 3 2-bit code—such[...]

Next-G enera tion P ow erPC Archit ec ture T he P owerPC G5 is a highly parallel implementation of the P owerPC architecture , capable of handling multiple assorted tasks at the same time. It ’ s based on the execu- tion core of IBM’ s 64-bit POWER4 processor—recipient of the M icropr ocessor Report ’s 20 01 Analyst ’ s Choice Awar d for [...]

Highly P arallel Execution Core At the heart of the Pow erPC G5 is an entirely new superscalar , superpipelined execution core, composed of 1 2 functional units that execute differ ent types of instructions con- currently for massiv e data throughput. Before instructions are dispatched into the functional units, they are arranged into groups of up [...]

Optimized 1 28-Bit V elocit y Engine T he P owerPC G5 uses a dual-pipelined V elocity Engine optimized with two independent queues and dedicated 1 28-bit regist ers and data paths f or efficient instruction and data flow . This 1 28-bit vector processing unit accelerat es data manipulation by applying a sin- gle instruction to multiple data at the [...]

C ondition Register Th is special 3 2-bit register summarizes the stat es of the floating-point and integer units . T he condition register also indicate s the results of comparison operations and provides a means for testing them as branch conditions . B y bridging information betw een the branch unit and other functional units, the condition regi[...]

Industr y-Leading Pe rf ormance Ultrafast clock speeds and a highly parallel 64-bit architecture make the P owerPC G5 ideal for next-generation multimedia, graphics, and scientific applications. Integer and floating-point math calculations are faster than ev er thanks to 64-bit-wide registers and data paths. To demonstrate the per formance adv anta[...]

SPECint_base2000 and SPECfp_base2 000 measure the speed of a single task—either an integer calculation or a floating-point calculation—ex ecuting on a single processor . Each test measures ho w long the processor takes to complete the benchmark set of single tasks relative to a SPEC-defined baseline score . SPECint_base2000 is composed of eleve[...]

F or comparisons that more accurately demonstrate the performance of a dual proces- sor system, VeriT est used the “SPEC rate ” metrics, which recognize multiple processors. With SPECint_rate_base2000 and SPECfp_rat e_base2000, the benchmark code is compiled and multiple copies are run concurre nt ly , allowing both processors to work in parall[...]

T echnical Specifica tions 64-bit P owerPC proc essor architecture •V ir tual address range: 64 bits, or 1 8 exabyt es •P hy sical address range: 42 bits, or 4 terabytes •F ull 64-bit data paths and registers •N ative support for 32-bit application code •6 4K L1 instruc tion cache; 32K L1 data cache • 51 2K internal L2 cache •D edicat[...]

Thr ee-component branch prediction logic •S peculative superscalar inner core organization •F ast, selective flush of incorrect speculative instructions and results •P r edic tion of up to two branche s per cycle • Support for up to 1 6 predicted branches in flight •P r edic tion hints added to branch instructions •P r edic tion support[...]