Cypress Semiconductor enCoRe CY7C63310 manual

CY7C63310, CY7C638xx enCoRe™ II Low S peed USB Periph eral Controller Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document 38-08035 Rev . *K Revised December 08 2008 1. Features ■ USB 2.0-USB-IF certified (TID # 40000085) ■ enCoRe™ II USB - “enhanced Component Red uction” ❐ C[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 2 of 83 Inter nal 24 MH z Oscill at or 3.3V Regulat or Cloc k Con tr o l POR / Low - Voltage Det ec t Watchdog Timer RAM U p to 256 Byt e M8C CPU Fla sh Up to 8K Byt e U p to 14 Extended IO P i ns Low-Speed USB/ PS2 Transcei ver and Pull up Up t o 6 GPI O pins Wa k e u p Timer 16-bi t Free runni [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 3 of 83 3. Introduction Cypress has reinvented its leadership po sition in the low speed USB market with a new family of i nnovative microcontrollers. Introducing enCoRe II USB - “enhanced Component Redu ction.” Cypress has leveraged its design experti se in USB solutions to advance its famil[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 4 of 83 5. Pinout s Figure 5-1. Pin Diagrams 1 2 3 4 5 6 9 11 15 16 17 18 19 20 22 21 NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 P0.0 P2.0 P1.5/SMOSI P1.3/SSEL P3.1 P3.0 V CC P1.2/VREG P1.1/D– P1.0/D+ 14 P1.4/SCLK 10 P2.1 NC V SS 12 13 7 8 INT0/P 0.2 P0.1 24 23 P1.7 P1.6/SMISO 24-Pin QSOP [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 5 of 83 Figure 5-2. CY7C63823 Die Form Die s tep = 1792 .98 μ m x 22 72.998 μ m Die si ze = 1727 μ m x 2187 μ m Bon d pad op eni n g = 70 μ m x 70 μ m Die thi c k n ess = 14 mi l s Legend 1 2 4 3 5 6 8 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Cypress L ogo X Y T ab le 5-1 . Die Pad Sum[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 6 of 83 T ab le 5-2 . Pin Descr ip tio n 32 QFN 24 QSOP 24 SOIC 18 SIOC 18 PDIP 16 SOIC 16 PDIP Name Description 21 19 18 P3.0 GPIO Port 3 . Co nfigured as a group (byte). 22 20 19 P3.1 91 1 1 1 P 2 . 0 GPIO Port 2 . Co nfigured as a group (byte). 81 0 1 0 P 2 . 1 14 14 13 10 15 9 13 P1.0/D+ GPIO[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 7 of 83 6. CPU Architecture This family of microcontrolle rs is based on a high performan ce, 8-bit, Harvard architec ture microprocessor . Fi ve registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly acce ssible through[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 8 of 83 7. CPU Registers The CPU registers in enCoRe II devices are in two banks with 256 registers in each bank. Bit[4]/XIO bit in th e CPU Flags regist er must be set/cleared to select between the two register banks T able 7-1 on page 8 7.1 Flags Register The Flags Register is set or reset on l[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 9 of 83 7.2 Addressi ng Modes 7.2.1 Source Immediate The result of an instruction using this addressing mode is placed in the A register , the F register , the SP reg ister , or the X register , which is specified as part of the instruction opcode. Ope rand 1 is an immediate value that serves as [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 10 of 83 7.2.2 Source Direct The result of an instruction using this addressing mode is placed in either the A reg ister or the X register , which is specified as part of the instruction opcode. Operand 1 i s an address that points to a location in the RAM memory space or the register space that [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 1 1 of 83 7.2.6 Destination Direct Source Immediate The result of an instruction using this addressing mode is placed within the RAM memory space or the reg ister space. Operand 1 is the address of the result. T he source of the instruction is Operand 2, which is an immediate value. Arithmetic in[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 12 of 83 8. Instruction Set Summary The instruction set is summarized in Ta b l e 8 - 1 numerically and serves as a quick refer ence. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User G uide (available on the Cypr[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 13 of 83 9. Memory Organization 9.1 Flash Program Memory Organization Figure 9-1. Program Memory Sp ace with Interrupt V ector T able after reset Address 16-bit PC 0x00 00 Program execution begins here after a reset 0x0004 POR/L VD 0x0008 INT0 0x000C SPI Transm itter Empty 0x0010 SPI Receiver Ful[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 14 of 83 9.2 Dat a Memory Organizat ion The CY7C63310/638xx microcontrollers provide up to 25 6 bytes of data RAM. 9.3 Flash This section describes the Flash block of the enCoRe II. Much of the user visible Flash function ality includin g programming and security are implemented i n the M8C Super[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 15 of 83 T wo important variables that ar e used for all functions are KEY1 and KEY2. These variables ar e used to help discriminate between valid SSCs an d inadvertent SSCs . KEY1 must always have a value of 3Ah, while KEY2 must have the same value as the stack pointer when the SR OM function be[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 16 of 83 9.5.3 WriteBlock Function The WriteBlock function is used to store data in the Flash. Data is moved 64 bytes at a time from SRAM to Flash using this function. The WriteBlock function fi rst checks the protection bits and determines if the desired BL OCKID is writable. If write protecti o[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 17 of 83 9.5.6 EraseAll Function The EraseAll function p erforms a series of steps that destroy the user data in the Flash macros and resets the protection block in each Flash macro to all zeros (the unprote cted state). The EraseAll function do es not affect the th ree hidden blocks above the pr[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 18 of 83 Figure 9-3. SROM T able The Silicon IDs for enCoRe II devices are stored in SROM tables in the part, as shown in Figure 9-3. The Silicon ID can be read out from the part using SROM T able reads (T abl e 0). This is demonstrated in the foll owing pseudo cod e. As mentioned in the section [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 19 of 83 9.5.8 Checksum Function The Checksum function calculates a 16-bit checksum over a user specifiable number of blocks, within a single Flash macro (Bank) starting from block zero. The BLOCKID parameter is used to p ass in the numbe r of blocks to cal culate the ch ecksum over . A BLOCKID v[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 20 of 83 Figure 10-1. Clock Block Diagram CPU_CL K EXT 24 MHz MUX CLK_USB SEL SCALE CLK_24MHz CLK_EXT CPUCLK SEL MUX SCALE (divide by 2 n , n = 0-5,7) CLK_32 KHz LP OSC 32 KHz SEL SCALE OUT 0X 12 MHz 0X 12 MHz 1 1 EXT/2 11 EXT [+] Feedback [+] Feedback[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 21 of 83 10.1 Clock Architec ture Description The enCoRe II clock selection circuitry allows the selection of independent clocks for the CPU, USB, Interval Timers and Capture T imers. The CPU clock CPUCLK is sourced from an external cl ock or the Internal 24 MHz Oscillator . The selected clock so[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 22 of 83 T able 10 -2. LPO SC T rim (LPOSCTR) [0x36] [R/W] Bit # 76543210 Field 32 kHz Low Power Reserved 32 kHz Bias T rim [1:0] 32 kHz Freq T rim [3:0] Read/Write R/W – R/W R/W R/W R/W R/W R/W Default 0 DDD DD D D This register is used to calibrate the 32 kHz Low speed Oscillator . The reset [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 23 of 83 T ab le 10-4. OSC Control 0 (OSC_CR0 ) [0x1 E0] [R/W] Bit # 76543210 Field Reserved No Buzz Sleep T imer [1:0] CPU Speed [2:0] Read/Write – – R/W R/W R/W R/W R/W R/W Default 00000000 Bit [7:6]: Reserved Bit 5: No Buzz During sleep (the Sleep bit is set in the CPU_SCR Register— T ab[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 24 of 83 T ab le 10 -5. USB Osc lock Clock Configuration (OSCLCK CR) [0x39] [R/W] Bit # 76543210 Field Reserved Fine T une Only USB Osclock Disable Read/Write –––––– R/W R/W Default 00000000 This register is used to trim the Inter nal 24 MHz Oscillator using received low sp eed USB pa[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 25 of 83 10.1.1 Interval Timer Clock (ITMRCLK) The Interval T imer Clock (TITMRCLK), is sourced from an external clock, the Internal 24 MHz Oscillator , the Internal 32 kH z Low power Oscillator , or the T imer Capture clock. A programmable prescaler of 1, 2, 3 or 4 then divides the selected sour[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 26 of 83 10.2 CPU Clock During Sleep Mode When the CPU enters sleep mode the CPUCLK Select (Bit [0], T a ble 10-3 on page 22) is forced to the Internal Oscillator , and the oscillator is stopped. Whe n the CPU comes out of sleep mode it r uns on the internal oscillator. The internal oscillator re[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 27 of 83 1 1. Reset The microcontroller su pports two types of resets: Power on Reset (POR) and W atchdog R eset (WDR). When reset is initiated, all registers are restored to their default states and al l interrupts are disabled. The occurrence of a reset is recorded in the System S tatus and Con[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 28 of 83 1 1.1 Power on Reset POR occurs every time the powe r to the device is switched on. POR is released when the supply is typically 2.6V for the upward supply transition, with typicall y 50 mV of hyster esis during the power on transient. Bit 4 of the System St atus and Control Register (CP[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 29 of 83 12.1 Sleep Sequence The SLEEP bit is an input into th e sleep logic circuit. This circuit is designed to seque nce the device into a nd out of the hardware sleep state. The hardware sequence to put th e device to sleep is shown i n Figur e 12-1. and is defined as follows. 1. Firmware set[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 30 of 83 12.3 Low Power in Sleep Mode T o ach ieve the lowest possible power consumption during suspend or sleep, the follow ing conditions must be observed in addition to considerations for the sleep timer: 1. All GPIOs must be set to outputs and driven low . 2. Clear P1 1CR[0], P10CR[0 ] - duri[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 31 of 83 13. Low V olt age Detect Control T able 13 -1. Low V oltage Control Register (L VDCR) [0x1E3] [R/W] Bit # 7 6 5 4 3 2 1 0 Field Reserved PORLEV[1:0] Reserved VM[2:0] Read/Write – – R/W R/W –R / W R/W R/W Default 0 0 0 0 00 0 0 This register con trols the configuration o f the Power[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 32 of 83 13.0.1 ECO T rim Register T ab le 13-2. V oltage Monitor Comp arator s Reg ister (VL TCMP) [0x1E4] [R] Bit # 76543210 Field Reserved L VD PPOR Read/Write –––– –– R R Default 0000 00 0 0 This read only register allows reading the current state of the Low-Volt age -Detection an[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 33 of 83 14. General Purpose IO (GPIO ) Port s 14.1 Port Da t a Registers T able 14 -1. P0 Data Register (P0DA T A)[0x00] [R/W] Bit # 76543210 Field P0.7 P0.6/TIO 1 P0. 5/TIO0 P0.4/INT2 P0.3/INT 1 P0.2/INT 0 P 0.1/CLKOUT P0.0/CLKIN Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0000 00 0 0 Th[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 34 of 83 T ab le 14 -2. P1 Data Regist er (P1DA T A) [0x01] [R/W] Bit # 76543210 Field P1. 7 P1.6/SMISO P1.5/SMOSI P1.4/ SCLK P1.3/SSEL P1.2/VREG P1.1/D– P1.0/D+ Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 00000000 This register contains the data for Port 1. Writing to this re gister set[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 35 of 83 14.2 GPIO Port Configurat ion All the GPIO configuration r egi sters have common configuration controls. The fol lowing are the bit de finitions of the GPIO configuration registers. 14.2.1 Int Enable When set, the Int Enab le bit allows the G PIO to generate interrupts. Interrupt generat[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 36 of 83 Figure 14-1. Block D iagram of a GPIO V CC VREG V CC VREG GPI O PIN R UP Da ta O ut V CC GND VREG GND 3.3V Dri ve P u ll-U p E na ble O utpu t Ena ble Open Dr ai n Po rt Da ta High Sink D ata In TTL Thres hol d T able 14-5. P0.0/CLKIN Configuration (P00CR) [0x05] [R/W] Bit # 76543210 Fie[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 37 of 83 T ab le 14 -7. P0.2/INT 0–P0.4/INT2 Configur atio n (P02CR–P04CR) [0x07–0x09 ] [R/W] Bit # 76543210 Field Reserved Int Act Low TTL Thresh Reserved Open Drain Pull up Enable Output Enable Read/Write – – R/W R/W –R / W R/W R/W Default 0000 00 0 0 These registers control th e op[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 38 of 83 T ab le 14 -9. P0.7 Con figuration (P07C R) [0x0C] [R/W ] Bit # 76543210 Field Reserved I nt Enable Int Act Low TTL Thresh Reserved Open Drain Pull up Enable Output Enable Read/Write – R/W R/W R/W – R/W R/W R/W Default 00000000 This regist er controls the op eration of pin P0.7 . The[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 39 of 83 T able 14 -13. P1.3 Configu ration (P13CR) [0x10] [R/W] Bit # 76543210 Field Reserved In t Enable Int Act Lo w 3 .3V Drive High Sink Open Drain Pull up Ena ble Output Enable Read/Write – R/W R/W R/W R/W R/W R/W R/W Default 0000 00 0 0 This register co ntrols the operation of the P1.3 p[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 40 of 83 15. Serial Periphe ral Interface (SPI) The SPI Master/Slave Interface core lo gic runs on the SPI clock domain, so that its functiona lity is independent o f system cloc k speed. SPI is a four pin serial interface comprise d of a clock, an enable and two data pins. 15.1 SPI Data Register[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 41 of 83 15.2 SPI Configure Regis ter T ab le 15 -2. SPI Co nfigure Register (SPICR) [0x 3D] [R/W] Bit # 76543210 Field S wap LSB First Comm Mode CPOL CPHA SCLK Select Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0000 00 0 0 Bit 7: Swap 0 = Swap function disabled. 1 = The SPI block swaps it[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 42 of 83 15.3 SPI Interface Pins The SPI interfa ce uses the P1.3–P1.6 pins . These pins ar e configured using the P1.3 and P1.4–P1.6 Config uration. T ab le 15-4. SPI Mod e Timing vs. LSB First, CPOL and CPHA LSB First CPHA CPOL Diagra m 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 SCL K SSEL DA [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 43 of 83 16. Timer Registers All timer functions of the enCoRe II are provided by a single ti mer block. Th e timer block is asynchronous from the CPU clock. 16.1 Regist ers 16.1.1 Free Running Co unter The 16 bit free-running counte r is clocked by the T imer Capture Cl o ck (TCAPCLK). It is rea[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 44 of 83 T ab le 16 -3. Timer Capture 0 Rising (TIO0R) [0x22] [R/W] Bit # 76543210 Field Capt ure 0 Rising [7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0000 00 0 0 Bit [7:0]: Capture 0 Rising [7:0] This register holds the value of the Free-running T imer wh en th e last rising edge o [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 45 of 83 T able 16 -8. Prog rammable Interval Timer High (PITMRH) [0x27] [R] Bit # 76543210 Field Reserved Prog Interval T imer [1 1:8] Read/Write –––– RR R R Default 0000 00 0 0 Bit [7:4]: Reserved Bit [3:0]: Prog Intern al T im er [1 1:8] This register holds the high order nibble of th [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 46 of 83 16.1.2 T imer Capture Cypress enCoRe II has tw o 8-bit captures. Each capture has separate registers for the rising and fa lling time. The two eight bi t captures can be configured as a single 16 -bit captur e. When config ured, the capture 1 registers ho ld the high order byte of the 16[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 47 of 83 T ab le 16 -12. Captur e Interrupt Enable (TCA PINTE) [0x2B] [R/W] Bit # 76543210 Field Reserved Cap1 Fall Enable Cap1 Rise Enable Cap0 Fall Enable Cap0 Rise Enable Read/Write –––– R/W R/W R/W R/W Default 0000 00 0 0 Bit [7:4]: Reserved Bit 3: Cap1 Fall En able 0 = Disable the ca[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 48 of 83 Figure 16-3. Timer Functional Sequence Diagra m [+] Feedback [+] Feedback[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 49 of 83 Figure 16-4. 1 6-Bit Free Running Co unter Loading Timing Diagram clk_sy s writ e valid addr write data FRT reload ready Clk Timer 12b Prog Tim er 12b reload interrupt Capture tim er clk 16b free running counter load 16b free running counter 00A0 00A1 00A2 00A3 00A4 00A 5 00A6 00A7 00A8 [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 50 of 83 17. Interrupt Controller The interrupt controller and its associated registers allow the user ’s code to respond to an interrupt from almost every functional block in the enCoRe II de vices. The registers associated with the interrup t controller allow disab ling interrupts globally or[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 51 of 83 17.2 Interru pt Processi ng The sequence of events that occur during interrupt processing follows: 1. An interrupt becomes active, because: a. Th e interrupt cond ition oc curs (for example, a timer exp ires). b. A previou sly posted interrupt is enable d through an update of an interrup[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 52 of 83 17.5 Interrupt Regist ers The Interrupt Clear Registers (INT_CLRx) are used to enable the individual in terrupt sources’ ability to clear posted in terrupt s. When an INT_CLRx register is read, any bit s that are set indi cates an in terrupt has been posted for that hardware resource. [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 53 of 83 T ab le 17 -5. In terr upt Mask 3 (INT_MSK3) [0xDE] [R/W] Bit # 76543210 Field ENSWINT Reserved Read/Write R/W ––––––– Default 0000 00 0 0 Bit 7: Enable Software Interrupt (ENSWINT) 0= Disable. Writing 0s to an INT_CLRx register , when ENSW INT is cleared, causes the corres[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 54 of 83 T ab le 17 -7. In terrupt Mask 1 (INT_MSK1) [0xE1] [R/W] Bit # 76543210 Field TCAP0 Int Enable Prog In terval Ti m e r Int Enable 1 ms T imer Int Enable USB Active Int Enable USB Reset Int Enable USB EP2 Int Enable USB EP1 Int Enable USB EP0 Int Enable Read/Write R/W R/W R/W R/W R/W R/W [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 55 of 83 T ab le 17 -8. Inte rru pt Mask 0 (INT_MSK0) [0xE0] [R/W] Bit # 76543210 Field GP IO Port 1 Int Enable Sleep T imer Int Enable INT1 Int Enable GPIO Port 0 Int Enable SPI Receive Int Enable SPI Transmit Int Enable INT0 Int Enable POR/L VD Int Enable Read/Write R/W R/W R/W R/W R/W R/W R/W [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 56 of 83 18. Regulator Output 18.1 VREG Control T ab le 18-1. VREG Co ntrol Register (VREGCR) [0x73] [R/W] Bit # 76543210 Field Reserved Keep Alive VREG Enable Read/Write –––––– R/W R/W Default 0000 00 0 0 Bit [7:2]: Reserved Bit 1: Keep Alive Keep Alive, when set, allows the voltage [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 57 of 83 19. USB/PS2 T ransceiver Although the USB transceiver h as features to assist in inte rfacing to PS/2, these f eatures are not contro lled using these regis te rs. The registers only control the USB interfacing features. PS/2 interfacing optio ns are controlled by the D+ and D– GPIO Co[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 58 of 83 21. USB Device 21.1 USB Device Addres s 21.2 End point 0, 1, and 2 Count T ab le 21 -1. USB Device Address (USBCR) [0x40] [R/W] Bit # 76543210 Field USB En able Device Address[6:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0000 00 0 0 Bit 7: USB Enable This bit must be enabled b[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 59 of 83 21.3 End point 0 Mode Because both firmware and the SIE are allowe d to write to the En dpoint 0 Mode and Co unt Registers, the SIE provides an inte rloc king mechanism to prevent a ccidental overwriting of data. When the SIE writes to these registers th ey are locked and the pro cessor [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 60 of 83 21.4 End point 1 and 2 Mode T able 21 -4. Endpoint 1 and 2 Mode (EP1MODE – EP2MODE) [0x45, 0x46] [R/W] Bit # 76543210 Field S tall Reserved NAK Int Enable ACK’d T ransaction Mode[3:0] Read/Write R/W R/W R/W R/C (Note 4) R/W R/W R/W R/W Default 0000 00 0 0 Bit 7: St a l l When this bi[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 61 of 83 The three data buffers are used to hold dat a for both IN and OUT transactions. Each data buff er is 8 bytes long. The reset values of the Endpoint Data Registers are unknown. Unlike past enCoRe parts the USB data buffers are only accessible in the IO sp ace of th e processor . 22. USB M[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 62 of 83 22.3 SETUP , IN, and OUT Columns Depending on the mo de specified in the 'Enc oding' column, the 'SET UP', 'IN', and 'OUT ' columns contain the SIE's responses when the endpoint receives SETUP , IN, and OUT tokens, respe ctively . A 'Chec[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 63 of 83 0010 OUT <=10, <>2 valid x ST ALL 001 1 Y es Bad S tatus 0010 OUT 2 valid 0 ST ALL 001 1 Y es Bad S tatus 0010 OUT 2 valid 1 ACK 1 1 1 1 2 Y es G ood S tatus ACK_OUT_ST A T US_IN 101 1 SETUP >10 x x junk Ignore 101 1 SETUP <=10 invalid x junk Ignore 101 1 SETUP <=10 val[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 64 of 83 1 101 IN x x x ST ALL St all IN NAK IN 1 100 OUT x x x Ignore 1 100 IN x x x NAK If Enabled NAK IN 23. Det ails of Mode fo r Differing T raffic Conditions (continued) Control Endpoint SIE Bus Event SIE EP0 Mode Register EP0 Count Register EP 0 Interrupt Comment s Mode T o ken Count Dval [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 65 of 83 2A TMRCR First Edge Hold 8-bit capture Prescale Cap0 16bit Enable Reserved bbbbb--- 00000000 2B TCAPINTE Reserved Cap1 Fall Active Cap1 Rise Active Cap0 Fall Active Cap0 Rise Active ----bbbb 00000000 2C TCA PINTS Reserved Cap1 F all Active Cap1 Rise Active Cap0 Fall Active Cap0 Rise Acti[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 66 of 83 Legend In the R/W c olumn, b = Both Read and Write r = Read Only w = Write Only c = Read/Clear ? = Unknown d = calibration value. Must not change during normal use. E2 INT_VC Pending In terrupt [7:0] bbbbbbbb 0 0000000 E3 RESWDT Reset W atchdog Timer [7:0] wwwwwwww 00000000 -- CPU_A T em[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 67 of 83 25. V olt age Vs CPU Fr equency Characteristics Figure 25-1. V oltage vs CPU Frequency Characte ristics Running the CPU at 24 MHz re quires a minimum voltage of 4.75V . This ap plies to any CPU spe ed above 12 MHz, so using an external clock between 12 - 24 MHz must also adhere to this r[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 68 of 83 26. Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User gui delines are not tested. S torage T emperature ........................... ........ –40°C to +90°C Ambient T e mperature with Power Applied ..... –0°C to +70°C Supply V oltag[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 69 of 83 V DI Differential Input Sensitivity 0.2 V V CM Differential Input Common Mode Range 0.8 2.5 V V SE Single Ended Receiver Threshold 0.8 2 V C IN T ransceiver Capacitance 20 pF I IO Hi-Z S tate Data Line Leakage 0V < V IN < 3.3V –10 10 μ A PS/2 Interface V OLP S tatic Output Low S[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 70 of 83 USB Driver T R1 T ransition Rise Time C LOAD = 200 pF 75 ns T R2 T ransition Rise Time C LOAD = 600 pF 300 ns T F1 Tr a n s i ti on F a l l Ti me C LOAD = 200 pF 75 ns T F2 Tr a n s i ti on F a l l Ti me C LOAD = 600 pF 300 ns T R Rise/Fall T ime Matching 80 1 25 % V CRS Output Signal Cr[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 71 of 83 1 Figure 28-2. GPIO Timing Diagram Figure 28-1. Clock Timing Figure 28-3. USB Data Signal Timing CLOCK T CYC T CL T CH 10% T R_GPI O T F_GPIO G PI O P i n Output Vol ta ge 90% 90% 10% 90% 10% D − D + T R T F V crs V oh V ol Figure 28-4. Receiver Jitter T olerance Differe nti al Data Li[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 72 of 83 Figure 28-5. Differential to EO P T ransition Skew and EOP Wid th T PERI OD Di f f e r e n t i a l Da t a L i n e s Cr os s o v er Poi nt C rosso ver P oi nt Ext ended Sour c e EO P W i dt h : T EOPT Re c e i v er EOP W i d t h : T EOPR 1 , T EOPR2 D iff. D a ta to SE0 S k ew N * T PERI [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 73 of 83 Figure 28-7. SPI Master Timing, CPHA = 1 MSB T MSU LSB T MHD T SCKH T MDO SS SCK (CPOL=0) SCK (CPOL=1) MOSI MISO (SS is under firmware control in SPI Master mode) T SCKL MSB LSB Figure 28-8. SPI Slave Timing, CPHA = 1 MSB T SSU LSB T SHD T SCKH T SDO SS SCK (CPOL=0) SCK (CPOL=1) MOSI MIS[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 74 of 83 Figure 28-9. SPI Master Timing, CPHA = 0 Figure 28-10. SPI Slave Timing, CPHA = 0 MSB T MSU LSB T MHD T SCKH T MDO1 SS SCK (CPOL=0) SCK (CPOL=1) MOSI MISO (SS is under firmware control in SPI Master mode) T SCKL T MDO LSB MSB MSB T SSU LSB T SHD T SCKH T SDO1 SS SCK (CPOL=0) SCK (CPOL=1)[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 75 of 83 29. Ordering Information Ordering Code FLASH Size RAM Size Package T ype CY7C63310-PXC 3K 128 16-PDIP CY7C63310-SXC 3K 128 16-SOIC CY7C63801-PXC 4K 256 16-PDIP CY7C63801-SXC 4K 256 16-SOIC CY7C63803-SXC 8K 256 16-SOIC CY7C63803-SXCT 8K 256 16-SOIC, T ape and Reel CY7C63813-PXC 8K 256 18-[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 76 of 83 31. Package Diagrams Figure 31-1. 16-Pin (300-Mil) Molded DIP P1 Figure 31-2. 16-Pin (150-Mil) SOIC S16.15 DIMENSIONS IN INCHES MIN. MAX. SEATING PLANE 0.240 0.260 0.015 0.035 0.740 0.770 0.120 0.140 0.015 0.060 0.015 0.020 0.055 0.065 0.140 0.190 0.090 0.110 0.28 0 0.32 5 0.009 0.012 0.[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 77 of 83 Figure 31-3. 18-Pin (300-Mil) Molded DIP P3 Figure 31-4. 18-Pin (300-Mil) Molded SOIC S3 DIMENSIONS IN INCHES MIN. MAX. SEATING PLANE 0.240 0.270 0.030 0.060 0.870 0.920 0.140 0.190 0.090 0.110 0.055 0.065 0.015 0.020 0.120 0.140 0.015 0.060 0.009 0.012 0.310 0.385 0.300 0.325 0.115 0.16[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 78 of 83 Figure 31-5. 24-Pin (300-Mil) SOIC S13 Figure 31-6. 24-Pin QSOP O241 S DIM EN SION S IN INCH ES JEDEC STD REF MO- 119 51-85025-*C 0.033 0.228 0.150 0.337 0.053 0.004 0.025 0.008 0.016 0.007 0° -8° REF. 0.344 0.157 0.244 BSC. 0.012 0.010 0.069 0.034 0.010 SEATING PLANE MAX. DIMENSIONS I[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 79 of 83 Figure 31-7. 32-Pin QFN Package Figure 31-8. 32-Pin Sawn QFN Pa ckage 51-85188-* B 001-30999 *A [+] Feedback [+] Feedback[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 80 of 83 32. Document History Page Document Title: CY7C63310, CY7C638xx enCoRe ™ II Lo w Speed USB Peripheral Controller Document Number: 38 -0803 5 Rev . ECN No. Orig. o f Change Submission Date Description of Change ** 131 323 XGR 12/1 1/03 New data sheet *A 221881 KKU See ECN Added Regi ster[...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 81 of 83 *G 424790 TYJ See ECN Mino r text changes to make document more readable Removed CY7C639xx Removed CY7C639xx from Ordering Information on page 75 Added text concerning current draw for P0.0 and P0.1 in T able 5-2 on page 6 Correcte d Figure 9-2 on page 15 to represent single stack Added [...]

CY7C63310, CY7C638xx Document 38-08035 Rev . *K Page 82 of 83 *J 2147747 VG T/AESA 05/20/2008 TID number entere d on page 1. Also changed the sentence “High current drive on GPIO pins” to “2mA source current on all GPIO pins”. Point 26.0, DC Character istics on page 68, changed the min. an d max. voltages of Vcc3 (line 3) to 4.0 and 5.5 res[...]

Document 38-08035 Rev . *K Revised December 08 2008 Page 83 of 83 PSoC® is a register ed tradem ark of Cyp ress MicroS ystems. enCoRe is a trademar k of Cypre ss Semic onductor Corporatio n. All produ c t and company name s mentioned in thi s document are the trademar ks of th eir resp ective holders. CY7C63310, CY7C638xx © Cypress Semicondu ctor[...]