Cypress SL811HS manual

SL81 1HS Embedded USB Host/Slave Controller SL81 1HS Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document 38-08008 Rev . *D Revised February 2, 2007 Features • First USB Host/Slave controller for embedded systems in the market with a standard microprocessor bus interface • Supports bot[...]

SL81 1HS Document 38-08008 Rev . *D Page 2 of 32 Data Port, Microprocessor Interface The SL81 1HS microprocessor in terface provides an 8-bit bidirectional data path along with appropriate con t rol lines to interface to external processors or con trollers. Programmed I/O or memory mapped I/O designs are supported through the 8-bit interface, chip [...]

SL81 1HS Document 38-08008 Rev . *D Page 3 of 32 PLL Clock Generator Either a 12 MHz or a 48 MHz external crystal is used with the SL81 1HS [1] . T wo pins, X1 and X2, are provided to connect a low cost crystal circuit to the device as shown in Figure 2 and Figure 3 . Use an externa l clock source if available i n the appli- cation instead of the c[...]

SL81 1HS Document 38-08008 Rev . *D Page 4 of 32 “SL81 1HS Slave Mode Registers” on page 12 describes Slave register definitions). Access to the registers are through the microprocessor interface similar to normal RAM accesses (see “Bus Interface T iming Requirements” on page 26 ) and provide control and status information for USB transacti[...]

SL81 1HS Document 38-08008 Rev . *D Page 5 of 32 USB-A/USB-B Host Control Registers [Address = 00h, 08h] . Once the other SL81 1HS Control re gisters are configured (registers 01h-04h or 09h-0Ch) the Host Control regi ster is programmed to initiate the USB transfer . This register initiates the tr ansfer when the Enable and Arm bit are set as descr[...]

SL81 1HS Document 38-08008 Rev . *D Page 6 of 32 USB-A/USB-B Host Base Length [Address = 02h, 0Ah]. The USB A/B Host Base Length register con tains the maximu m packet size transferred between the SL81 1HS and a slave USB peripheral. Essentially , this designates the l argest packet size t hat is transferred by the SL81 1HS. Base Length designates [...]

SL81 1HS Document 38-08008 Rev . *D Page 7 of 32 USB-A/USB-B Host T ransfer Count Register (Read), USB Address (Write) [Address = 04h, 0Ch]. This register ha s two different functions depending on whether it is read or written. Wh en read, this register contains the number of bytes remaining (from Host Base Length va lue) after a packe t is transfe[...]

SL81 1HS Document 38-08008 Rev . *D Page 8 of 32 Control Register 1 [Add re ss = 05h]. The Control Register 1 en ables /dis ables USB tran sfe r operation with con trol bits defined as follows. At powe -up this register is cleared to all zeros. Low-power Modes [Bit 6 Control Register , Address 05h] When bit 6 (Suspend) is set to ’1’, the power [...]

SL81 1HS Document 38-08008 Rev . *D Page 9 of 32 Interrupt Enable Register [A dd ress = 06h]. The SL81 1HS provides an Interrupt Reque st Output, which is activate d for a number of conditions. The Interr u pt Enable register allows the user to select conditions that resu lt in an interrupt that is issued to an external CPU through the INTRQ pin. A[...]

SL81 1HS Document 38-08008 Rev . *D Page 10 of 32 Interrupt St atus Register , Address [Address = 0Dh]. The Interrupt St atus register is a READ/WRITE register provi ding interrupt status. Interrupts are cleared by writing to this regi ster . T o clear a sp ecific interru pt, the register is written wi th corre - sponding bit set to ’1’. Curren[...]

SL81 1HS Document 38-08008 Rev . *D Page 1 1 of 32 Example: T o set up SOF for 1 ms interval, SOF counter register 0Eh should be set to E0h. SOF Counter High/Control Regi ster 2 [Address = 0Fh]. When read, this register returns the valu e of the SOF counter divided by 64. The software must use thi s register to determine the av a ilable bandwidth i[...]

SL81 1HS Document 38-08008 Rev . *D Page 12 of 32 SL81 1HS Slave Mode Registers When in slave mode, the registers in the SL81 1HS are divided into two major groups. The first group contains Endpoint reg- isters that manage USB control transacti ons and data flow . The second group con tains the USB Registers that provide the control and status info[...]

SL81 1HS Document 38-08008 Rev . *D Page 13 of 32 Endpoint Control Registers Endpoint n Control Register [Address a = (EP# * 10h), b = (EP# * 10h)+8]. Each endpoint set has a Control register defined as follows: Endpoint Base Address [Address a = (EP# * 10h)+1, b = (EP# * 10h)+9]]. Pointer to memory buffe r location for USB reads and writes. End po[...]

SL81 1HS Document 38-08008 Rev . *D Page 14 of 32 Endpoint Packet S t atus [Address a = (EP# * 10h)+3, b = (EP# * 10h)+Bh]. The packet status contains information relative to the packet that is received or transmitted. The register is defined as follows: End point T ransfer Co unt [Addre ss a = (EP# * 10h)+4 , b = (EP# * 10h)+Ch]. As a peripheral d[...]

SL81 1HS Document 38-08008 Rev . *D Page 15 of 32 Control Register 1, Ad dress [05h]. The Control reg ister enables or disables U SB transfers and DMA operatio ns with control bits . T able 28 . Co ntrol Register 1 [Address 05h] 7 6 5 4 3 2 1 0 Reserved STBYD SPSEL J-K1 J-K0 DMA Dir DMA Enable USB Enable Bit Position Bit Name Function 7 Reserved Re[...]

SL81 1HS Document 38-08008 Rev . *D Page 16 of 32 Interrupt Enable Register , Address [06h] . The SL81 1HS provides an Interrupt Request Output that is activated resulting from a number of c onditions. The Interrupt Enable register allows the user to se lect events that generate the Interrupt Request Output assertion. A separate Interrupt S tatus r[...]

SL81 1HS Document 38-08008 Rev . *D Page 17 of 32 Current Data Set Register , Address [0Eh]. This re gister indicates current selected data set for each endpoint. Control Registe r 2, Address [0Fh]. Control Register 2 is used to co ntrol if the d evice is configur ed as a master or a slave . It can change the polarity of the Data+ and Data- pins to[...]

SL81 1HS Document 38-08008 Rev . *D Page 18 of 32 Physical Connections These parts are of fered in both a 28-pin PLCC package and a 48-pin TQFP package. The 28-pin PLCC packages are the SL81 1HS and SL81 1HS-JCT . The 48-pin TQFP packages is the SL81 1 HST -AXC. 28-Pin PLCC Physical C onnections 28-Pin PLCC Pin Layout *See T able 35 on page 21 for [...]

SL81 1HS Document 38-08008 Rev . *D Page 19 of 32 The diagram below illustrates a simple +3.3V voltage source. Package Markings ( 28-pin PLCC ) YYWW = Date code XXXX = Product code X.X = Silicon re vision number +5 V ( U S B ) GND R1 + 3 . 3 V ( V DD) Sample V DD Gene ra tor 45 Oh m s 3.9v , 1N52288CT- Zener 2N 2222 Figure 5. Samp le VDD Generator [...]

SL81 1HS Document 38-08008 Rev . *D Page 20 of 32 48-Pin TQFP Physical Co nnections 48-Pin TQFP AXC Pin Layout *See T able 35 on page 21 for Pin and Signal Description for Pins 43 and 44 in Host Mode. 48-Pin TQFP Mechanical Dimensions Note 4. NC. Indicates No Connection. NC Pins must be left unconnected. 48-Pi n TQ FP 1 12 13 24 25 48 37 36 NC NC N[...]

SL81 1HS Document 38-08008 Rev . *D Page 21 of 32 48/28-Pin USB Host Controlle r Pins Description The SL81 1HST -AXC is packaged in a 48-pin TQF P . The SL81 1 HS and SL81 1HS-JCT packages are 28-pin PLCC’s. These devices require a 3.3 VDC power source. The 48-Pin TQFP requires an external 12 or 48 MHz crystal or clock. T able 35. 4 8/28-Pin TQFP[...]

SL81 1HS Document 38-08008 Rev . *D Page 22 of 32 33 25 BIDIR D6 Data 6 . Microprocessor Data/Address Bus. 34 – NC NC No connectio n. 35 – NC NC No connectio n. 36 – NC NC No connectio n. 37 – NC NC No connectio n. 38 – NC NC No connectio n. 39 26 BIDIR D7 Data 7 . Microprocessor Data/Address Bus. 40 27 IN M/S Ma ster/Slave Mode Select . [...]

SL81 1HS Document 38-08008 Rev . *D Page 23 of 32 Package Markings (48-Pin TQFP) YYWW = Date code XXXX = Product code X.X = Silicon re vision number Par t Num ber YYW W - X. X X X X X[...]

SL81 1HS Document 38-08008 Rev . *D Page 24 of 32 Electrical Specifications Absolute Maximum Ratings This section lists the absolute maximum ratings of the SL81 1HS. S tresses above those l isted can cause pe rmanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device o peration and reliability . Recomm[...]

SL81 1HS Document 38-08008 Rev . *D Page 25 of 32 DC Characteristics USB Host T ransceiver Characteristics Every V DD pin, including USB V DD , must have a decoupling capacitor to ensure clean V DD (free of high frequency noise) at the chip input point (pin) itself. The best way to do this is to connect a ceramic capacitor (0.1 μ F , 6V) between t[...]

SL81 1HS Document 38-08008 Rev . *D Page 26 of 32 Bus Interface Timing Requirements I/O Write Cycle Note nCS an be held LOW for mult iple Write cycles provided nWR is cycled. Write Cycle T ime for Auto Inc Mode W rites is 170 ns minimum. nW R A0 D0- D7 DATA tw r twahl d twdhl d twasu twdsu twdsu twdhl d I/O W rite C y c le to R egis te r o r M em o[...]

SL81 1HS Document 38-08008 Rev . *D Page 27 of 32 I/O Read Cycle Note nCS can be kept LOW during mu ltiple Read cycles provided nRD is cycled. Rd Cycle T ime for Auto Inc Mode Reads is 170 ns minimum. nRD A0 D0-D7 DATA twr twa h ld twdhld twasu twdsu trdhl d I/O Re ad C y c le fro m Re gis te r o r M em or y B uffe r Regist er or Memory A ddress tr[...]

SL81 1HS Document 38-08008 Rev . *D Page 28 of 32 DMA Write Cycle Note nWR must go low after nDACK goes low in ord er for nDRQ to clear . If this sequence is not implemented as requested, the next nDRQ is not inserted. Parameter Description Min. T yp. Max. tdack nDACK low 80 ns tdwrlo nDACK to nWR low delay 5 ns tdakrq nDACK low to nDRQ high delay [...]

SL81 1HS Document 38-08008 Rev . *D Page 29 of 32 DMA Read Cycle Note Data is held until nDACK goes high regard less of state of nREAD. Reset Timing Note Clock is 48 MHz nominal. Parameter Description Min. T yp. Max. tdack nDACK low 100 ns tddrdlo nDACK to nRD low delay 0 ns tdckdr nDACK low to nDRQ high del ay 5 ns tdrdp nRD pulse width 90 ns tdhl[...]

SL81 1HS Document 38-08008 Rev . *D Page 30 of 32 Clock Timing Specificati ons Ordering Information CLK CLOCK TIMING trise tfall thigh tclk tlow Clock Timing Parameter Descriptio n Min. T yp. Max. t CLK Clock Period (48 MHz) 20.0 ns 20.8 ns t HIGH Clock HIGH T ime 9 ns 11 n s t LOW Clock LOW T ime 9 ns 11 n s t RISE Clock Rise T ime 5.0 ns t FA L L[...]

SL81 1HS Document 38-08008 Rev . *D Page 31 of 32 © Cypress Semico nductor Corpor ation, 2007. Th e information cont ained herei n is subject to ch ange without not ice. Cypress Semi co nductor Corpor atio n assumes no responsibility for the use of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor does it convey or imply an[...]

SL81 1HS Document 38-08008 Rev . *D Page 32 of 32 Document History Page Document Title: SL81 1HS Embedded USB Host/Slav e Controller Document Number: 38-08008 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 1 10850 12/14/01 BHA Converted to Cypress format from ScanLogic *A 1 12687 03/22/0 2 MUL 1) Chan ged power supply voltage to [...]