Freescale Semiconductor MCF52213 manual

MCF5221 1 ColdFire ® Integrated Microcontroller Reference Manual Devices Supported: MCF52210 MCF52211 MCF52212 MCF52213 Document Number : MCF52211RM Re v . 2 09/2007[...]

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MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor i Chapter 1 Overview 1.1 MCF5221 1 Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor ii 2.14 Pulse-W idth Modulator Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 1 2.15 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor iii 5.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor iv Chapter 8 Power Management 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor v 10.6.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Chapter 11 Real-Time Clock 1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor vi 13.4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.5 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor vii 15.5 OTG and Host Mode Oper ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-33 15.6 Host Mode Operation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor viii 18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor ix 21.4 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.5 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor x 22.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2.1 DMA T i mer Mode Registers (DTMR n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor xi 24.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor xii 25.3.7 Clock Synchronization and Ar bitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.3.8 Handshaking and Clock S tretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13 2[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor xiii Chapter 27 Pulse-Width Modula tion (PWM) Module 27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.1.1 Overview . . . . . . . . . . . . . . . [...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor xiv 28.6.2 Concurrent BDM and Processor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-41 28.7 Processor Status, Debug Data De finition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 [...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-1 Chapter 1 Overview This chapter provides an overview of the major features and functional components of the MCF5221 1 family of microcontrollers. The MC F5221 1 family is a highly integrat ed implementation of the ColdFire ® family of reduced in[...]

Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-2 F re escale Semiconductor 1.1 MCF52211 F amily Configurations T able 1-1. MCF52211 F amily Configura tions Module 52210 52211 52212 5221 3 V ersion 2 ColdFire Core with MA C (Multiply-Accumulate Unit) •••• System Clock 66, 80 MHz 50 MHz P erformance (Dhr [...]

Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-3 1.2 Bloc k Diagram The superset device in the MCF 5221 1 family comes in a 100-lead l eaded quad flat package (LQFP). Figure 1-1 shows a top-level block diagram of the MCF5221 1. Figure 1-1. MCF52211 Bloc k Diagr am 1.3 P ar t Numbers an[...]

Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-4 F re escale Semiconductor 1.2 Features The MCF5221 1 family includes the following features: • V ersion 2 ColdFire variable -length RISC processor core — S tatic operation — 32-bit address and data paths on-chip — Up to 80 MHz processor core frequency —[...]

Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-5 — Up to 16-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply support — Up to 128 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses • Power management — Fully static [...]

Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-6 F re escale Semiconductor — 12-bit resolution — Minimum 1.125 μ s conversion time — Simultaneous sampling of two channe ls for motor control applications — Single-scan or continuous operation — Optional interrupts on conversion complete, zero crossing [...]

Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-7 — Maintains system time-of-day clock — Provides stopwatch and alarm interrupt functions • Software watchdog timer — 32-bit counter — Low-power mode support • Backup watchdog timer (BWT) — Independent timer that can be used [...]

Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-8 F re escale Semiconductor – Power -on reset (POR) – External – Software – W atchdog – Loss of clock / loss of lock – Low-voltage detection (L VD) –J T A G — S tatus flag indication of source of last reset • Chip integration module (CIM) — Syst[...]

Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-9 real-time tracing capability is provided on 100-lead packages. This allo ws the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The on-chip breakpoint resources incl ude a total of nine[...]

Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-10 F re escale Semiconductor 1.2.4 On-Chip Memories 1.2.4.1 SRAM The dual-ported SRAM module provides a general-pur pose 8- or 16-Kbyte me mory block that the ColdFire core can access in a single cycle. The locat ion of the memory block can be set to any 8- or 16-K[...]

Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-11 1.2.7 U ARTs The MCF5221 1 has three full-duplex UAR T s that function independently . Th e three UAR T s can be clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third UAR T is[...]

Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-12 F re escale Semiconductor register (TCR n ). Each of these timers can be configured for input capture or reference (output) compare mode. T i mer events may optionally cause interrupt requests or DMA transfers. 1.2.12 General Purpose Timer (GPT) The general purp[...]

Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-13 1.2.17 Bac kup W atchdog Timer The backup watchdog timer is an independent 16-b it timer that, like the so ftware watchdog timer , facilitates recovery from runaway code. This timer is a free-running dow n-counter that generates a reset[...]

Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-14 F re escale Semiconductor 1.2.22 GPIO Nearly all pins on the MCF5221 1 have general purpo se I/O capability and are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that confi gure, monitor , and control the port pins.[...]

Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 2-1 Chapter 2 Signal Descriptions 2.1 Intr oduction This chapter describes signals implemented on this de vice and includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state[...]

Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-2 F re escale Semiconductor Figure 2-1. Bloc k Diagram wit h Signal Interfaces 2.3 Pin Functions Arbiter Interrupt Controller UART 0 QSPI UART 1 UART 2 I 2 C V2 ColdFire CPU 4 CH JT AG TA P 16 Kbytes SRAM (2K × 32) × 2 128 Kbytes Flash (16K × 16) × 4[...]

Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semiconductor 2-3 T able 2-1. Pin Functions b y Primary and Alternate Purpose Pin Group Primary Function Secondary Function Te r t i a r y Function Quaternary Functio n Drive Strength / Contr ol 1 Slew Rate / Control 1 Pull-up / Pull-down 2 Pin [...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-4 F re escale Semiconductor Signal Descriptions Interrupts IRQ7 — — G P I O L o w F A S T — 9 5C 45 8 IRQ6 — — GPIO Low F AST — 94 B4 — IRQ5 — — GPIO Low F AST — 91 A4 — IRQ4 — — G P I O L o w F A S T — 9 0C 55 7 IRQ3 — — GPIO Low F AST — 8[...]

Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semiconductor 2-5 QSPI QSPI_DIN/ EZPD — URXD1 GPIO PDSR[2] PSRR[2] — 16 F 3 12 QSPI_DOUT /EZPQ — UTXD1 GPIO PDSR[1] PSRR[1] — 17 G1 13 QSPI_CLK/ EZPCK SCL URTS1 GPIO PDSR[3] PSRR[3] pull-up 8 18 G2 14 QSPI_CS3 SYNCA — GPIO PDSR[7] PSRR[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-6 F re escale Semiconductor Signal Descriptions U ART 1 UCTS1 SYNCA URXD2 GPIO PDSR[15] PSRR[15] — 9 8 C3 61 URTS1 SYNCB UTXD2 GPIO PDSR[14] PSRR[14] — 4 B1 2 URXD1 — — GPIO PDSR[13] PSRR[13] — 100 B2 63 UTXD1 — — GPIO PDSR[12] PSRR[12] — 99 A2 62 U ART 2 UC[...]

Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semiconductor 2-7[...]

Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-8 F re escale Semiconductor 2.4 Reset Signals Ta b l e 2 - 2 describes signals that are used to re set the chip or as a reset indication. 2.5 PLL and Cloc k Signals Ta b l e 2 - 3 describes signals that are used to s upport the on-chip clock generation c[...]

Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 2-9 2.7 External Interrupt Signals Ta b l e 2 - 6 describes the external interrupt signals. 2.8 Queued Serial P eripheral Interface (QSPI) Ta b l e 2 - 7 describes the QSPI signals. T able 2-5. Cloc king Modes CLKMOD[1:0] XT AL Co[...]

Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-10 F re escale Semiconductor 2.9 I 2 C I/O Signals Ta b l e 2 - 8 describes the I 2 C serial interface module signals. 2.10 U AR T Module Signals Ta b l e 2 - 9 describes the UAR T module signals. 2.11 DMA Timer Signals T able 2-10 describes the signals [...]

Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 2-11 2.12 ADC Signals T able 2-11 describes the signals of the analog-to-digital converter . 2.13 General Purpose Timer Signals T able 2-12 describes the genera l purpose timer signals. 2.14 Pulse-Width Modulator Signals T able 2-[...]

Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-12 F re escale Semiconductor T est Data Inp ut TDI Serial input for test inst ructions and data. TDI i s sampled on the r ising edge of TC LK. I T est Data Output TDO Ser ial output for test inst ructions and data. TDO is three-sta teable and is actively[...]

Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 2-13 2.16 EzP or t Signal Descriptions Table 2-15 contains a list of EzPort external signals 2.17 P ower and Gr ound Pins The pins described in T able 2-16 provide system power a nd ground to the chip. Mult iple pins are provided [...]

Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-14 F re escale Semiconductor[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-1 Chapter 3 ColdFire Core 3.1 Intr oduction This section describes the organiza tion of the V ersion 2 (V2) ColdFire ® processor core and an overview of the program-visible registers. Fo r detailed information on instructions , see the ISA_A+ defi[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-2 F re escale Semiconductor instruction, fetches the required operands and then executes the required function. Because the IFP and OEP pipelines are decoupled by an inst ruction buf fer serving as a FIFO que ue, the IFP is able to prefetch instructions in adv[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-3 The supervisor-programming model is intended to be used only by syst em control software to implement restricted operating system functi ons, I/O control, and memory management. All accesses that af fect the control features of Cold[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-4 F re escale Semiconductor 3.2.1 Data Registers (D0–D7) D0–D7 data registers ar e for bit (1-bit), byte (8-bit ), word (16-bit) and longwor d (32-bit) operations; they can also be used as index registers. NO TE Registers D0 and D1 contai n hardware config[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-5 hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus, the register contents are a function of the processor operat ion mode, as shown in the following: if SR[S] = 1 then A7 = Supervisor Stack Pointer OT[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-6 F re escale Semiconductor 3.2.5 Pr ogram Counter (PC) The PC contains the currently exec uting instruction address. During in struction execution and exception processing, the processor automatically increments contents of the PC or places a new value in the[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-7 not implemented by ColdFire processo rs. They are assumed to be zero, forcing the table to be aligned on a 1 MByte boundary . Figure 3-7. V ector Base Register ( VBR) 3.2.7 Status Register (SR) The SR stores the processor status and[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-8 F re escale Semiconductor 3.3 Functional Description 3.3.1 V ersion 2 ColdFire Micr oarchitecture From the block diagram in Figure 3-1 , the non-Harvard architecture of th e processor is readily apparent. The processor interfaces to the local memory subsys t[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-9 Figure 3-10. V ersio n 2 ColdFire Proc essor Operand Execut ion Pipeline Diagram The instruction fetch pipeline prefet ches instructions from local memory using a two-stage structure. For sequential prefetches, the next instruction [...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-10 F re escale Semiconductor For simple register-to-register inst ructions , the first stage of the OEP performs the instruction decode and fetching of the required register operands (OC) fro m the dual-ported register file, while the actual instruction execut[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-11 Figure 3-12. V2 OEP Embed ded-Load P ar t 1 Figure 3-13. V2 OEP Embed ded-Load P ar t 2 For register -to-memory (store) opera tions, the stage functions (DS/OC, AG/EX) are effectively performed simultaneously allowing single-cycle [...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-12 F re escale Semiconductor For read-modify-write instructions, the pipeline ef fectively combines an em bedded-load with a store operation for a three-cycle execution time. Figure 3-14. V2 OEP Register-to-Memo ry The pipeline timing diagrams of Figure 3-15 d[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-13 Figure 3-15. V2 OEP Pipe line Execution T emplates 3.3.2 Instruction Set Ar chitecture (ISA_A+) The original ColdFire Instructi on Set Architecture (ISA _A) was derived from the M68000 family opcodes based on extensive analysis of [...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-14 F re escale Semiconductor Ta b l e 3 - 4 summarizes the instructions a dded to revision ISA_A to form revision ISA_A+. For more details see the ColdFir e Family Programmer ’ s Refer ence Manual . 3.3.3 Exception Pr ocessing Overview Exception processing f[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-15 fixed-length stack frame for all exceptions. The exception type determines whether the program counter placed in the exception stack frame define s the loca tion of the faulting instruction (fault) or the address of the next inst r[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-16 F re escale Semiconductor All ColdFire processors inhibit interrupt sampling dur ing the first instruction of all exception handlers. This allows any handler to disable interrupts ef fectiv ely , if necessary , by raising the interrupt mask level contained [...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-17 • The 8-bit vector number , vector[7 :0], defines the exception type a nd is calculated by the processor for all internal faults and represents the value supplied by the interrupt controller in case of an interrupt. See Ta b l e [...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-18 F re escale Semiconductor execution until all previous operations, including all pending write operations, are complete. If any previous write terminates with an access error , it is guaranteed to be reported on the NOP instruction. 3.3.4.2 Address Error Ex[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-19 In the original M68000 ISA definition, lines A and F were effe ctively reserved for user -defined operations (line A) and co-processor instructions (line F). Accordingly , there are two unique exception vectors associated with ille[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-20 F re escale Semiconductor 3. The processor then generates a trace exception. The PC in the exce ptio n stack frame points to the instruction after the stop, and the SR reflects the value loaded in the previous step. If the processor is not in trace mode and[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-21 3.3.4.11 TRAP Instruction Exception The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing system calls. The TRAP instruction may be used to change from user to supervisor mode. 3[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-22 F re escale Semiconductor ColdFire processors load hardware configurati on information into the D0 and D1 general-purpose registers after system reset. The hardware configuration information is loaded immediately after the reset-in signal is negated. This a[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-23 Information loaded into D1 defines the local memory hardware configuration as shown in the figure below . 11 MMU MMU present. This bit signals if the optional vir tual memo r y management uni t (MMU) is present in processor core. 0[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-24 F re escale Semiconductor T able 3-10. D1 Hard ware Configuration Informat ion Field Description Field Description 31–30 CLSZ Cache line size. This field is fix e d to a he x value of 0x0 indicating a 16-byte cache line size . 29–28 CCAS Configurable ca[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-25 3.3.5 Instruction Execution Timing This section presents p roce ssor in struction execution times in terms of processor -core clock cycles. The number of operand references for eac h instruction is enclosed in parentheses following[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-26 F re escale Semiconductor 3.3.5.2 MO VE Instruction Execution Times T able 3-12 lists execution times for MOVE.{B,W} instructions; T able 3-13 lists timings for MOVE.L. NO TE For all tables in this section, the execution time of a ny instruction using the P[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-27 3.3.5.3 Standard One Operand Instruction Execution Times (d8,A y ,Xi*SF) 3(1/0) 3 (1/1) 3(1/1) 3(1/1) — — — xxx.w 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — — xxx.l 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — — (d16,PC) 2(1/0) 2(1/1) 2 [...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-28 F re escale Semiconductor 3.3.5.4 Standard T wo Operand Instruction Execution Times T able 3-15. T wo Opera nd Instruction Execution Times Opcode <EA> Effective Address Rn (An) (An)+ -(An) (d16,An) (d16,PC) (d8,An,Xn*SF) (d8,PC,Xn*SF) xxx.wl #xxx ADD [...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-29 3.3.5.5 Miscellaneous Instruction Execution Times REMS.L <ea>,Dx ≤ 35(0/0) ≤ 38(1/0) ≤ 38(1/0) ≤ 38(1/0) ≤ 3 8(1/0) — — — REMU .L <ea>,Dx ≤ 35(0/0) ≤ 38(1/0) ≤ 38(1/0) ≤ 38(1/0) ≤ 38(1/0) — ?[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-30 F re escale Semiconductor 3.3.5.6 MA C Instruction Execution Times W D E B U G < e a > —5 ( 2 / 0 )— —5 ( 2 / 0 ) — — — 1 The n is the number of registers mov ed b y the MO VEM opcode. 2 If a MO VE.W #imm,SR instr uction is ex ecuted and i[...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-31 3.3.5.7 Branch Instruction Execution Times Table 3-18. General Branch Instruction Execu tion Times Opcode <EA> Effecti ve Address Rn (An) (An)+ -(An) (d16,An ) (d16,PC) (d8,An,Xi*SF) (d8,PC,Xi*SF) xxx.wl #xxx BRA — — — [...]

ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-32 F re escale Semiconductor[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-1 Chapter 4 Multipl y-Accumu late Unit (MA C) 4.1 Intr oduction This chapter describes the functiona lity , microarchitecture, and performance of th e multiply-a ccumulate (MAC) unit in the ColdFire family of processors. 4.1.1 Overview The MAC desi[...]

Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-2 F re escale Semiconductor cycles than comparable non-MAC architectures. For example, small di gital filters can tolerate some variance in an algorithm’ s execution time, but larg er , more complicated algorithms such as orthogonal transfo[...]

Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-3 BDM: 0x804 (MA CSR) Access: Supervisor read/wr ite BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 000000000000000000000 000 OMC S/U F/I R/T N Z VC W R e s e t[...]

Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-4 F re escale Semiconductor Ta b l e 4 - 3 summarizes the interaction of th e MACSR[S/U,F/I,R/T] control bits. 4.2.2 Mask Register (MASK) The 32-bit MASK implements the low-order 16 bits to minimize the alignmen t complications involved with [...]

Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-5 if extension word, bit [5] = 1, the MASK bit, then if <ea> = (An) oa = An & {0xFFFF, MASK} if <ea> = (An)+ oa = An An = (An + 4) & {0xFFFF, MASK} if <ea> =-(An) oa = (An - 4) & {0xFFFF[...]

Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-6 F re escale Semiconductor 4.3 Functional Description The MAC speeds execution of ColdFire integer -mu ltiply instructions (MULS and MULU) and provides additional functionality for multiply-a ccumulate ope rations. By executing MULS and MULU[...]

Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-7 4.3.1 Fractional Operation Mode This section describes behavior when the fr actional mode is used (MACSR[F/I] is set). 4.3.1.1 Rounding When the processor is in fractional mode, ther e are two operations during whi[...]

Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-8 F re escale Semiconductor int macsr; } macState; The following assembly language r outine shows the proper sequence for a correct MAC state save. This code assumes all Dn and An register s are available for use, and the memory location of t[...]

Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-9 4.3.3 MA C Instruction Execution Times The instruction execution time s for the MAC can be found in Section 3.3.5.6, “MAC Instruction Execution Ti m e s ” . 4.3.4 Data Representation MACSR[S/U,F/I] selects one [...]

Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-10 F re escale Semiconductor treated as a sticky flag, mea ning after set, it remains set until the accumu lator or the MACSR is directly loaded. See Section 4.2.1, “MAC Stat us Register (MACSR)” . • The optional 1-bit shift of the prod[...]

Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-11 else result[31:0] = 0x7fff_ffff } /* scale product before combining wit h accumulator */ switch (SF) /* 2-bit scale factor */ { case 0: /* no scaling specified */ break; case 1: /* SF = “<< 1” */ if (pro[...]

Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-12 F re escale Semiconductor break; case 1: case 3: /* signed fractionals */ if (MACSR.OMC == 0 || MACSR.V == 0) then { MACSR.V = 0 if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {Ry[31:16], 0x0000} else operandY[31:0] = {Ry[15:0][...]

Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-13 if (MACSR.OMC == 0 || MACSR.V == 0) then { MACSR.V = 0 /* select the input operands */ if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {0x0000, Ry[31:16]} else operandY[31:0] = {0x0000, Ry[15:0]} if (U/[...]

Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-14 F re escale Semiconductor then {if (inst == MSAC) then result[31:0] = acc[31:0] - product[3 1:0] else result[31:0] = acc[31:0] + product[3 1:0] } /* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.V = 1 if (in[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 5-1 Chapter 5 Static RAM (SRAM) 5.1 Intr oduction This chapter describes the on-chip static RAM (SRAM) implementation, including general operations, configuration, and initializ ation. It also provides information a nd examples showing how to minimiz[...]

Static RAM (SRAM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 5-2 F re escale Semiconductor 5.2.1 SRAM Base Address Regi ster (RAMB AR) The configuration information in the SRAM base-addr ess register (RAMBAR) c ontrols the operation of the SRAM module. • The RAMBAR holds the SRAM base address. The MOVEC instruction [...]

Static RAM (SRAM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 5-3 5.3 Initialization/Application Inf ormation After a hardware reset, the SRAM module contents are undefined. The valid bit of the RAMBAR is cleared, disabling the proces sor port into the memory . I f the SRAM re quires initializ[...]

Static RAM (SRAM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 5-4 F re escale Semiconductor 2. Read the source data and write it to the SR AM. V arious instructions support this function, including memory-to-memory move instru ctions, or the MOVEM opcode. The MOVEM instruction is optimized to generate line-sized burst [...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-1 Chapter 6 Cloc k Module 6.1 Intr oduction The clock module allows the device to be configured for one of several clocking methods. Clocking modes include internal phase-locke d loop (PLL) clocking with an external clock reference or an external c[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-2 F re escale Semiconductor next POR. If the relaxation oscillator was already selected as the system clock’ s source and is subsequently selected as the timer ’ s input source, the system and the timer can use the oscillator as the source. 6.3.2 RTC Mode A[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-3 In stop mode, all system cl ocks are disabled. There are several opt ions for enabling or disabling the PLL or crystal oscillator in stop mode, compromising be tween stop mode current and wakeup recovery time. The PLL can be disabled[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-4 F re escale Semiconductor Figure 6-1. Cloc k Module Bloc k Diagram EXTAL CLKMOD1 CLKSRC PLL Low Power Divider LPD[3:0] Reference Clo ck 0 1 ADC auto-standby clock PPRMH[11] CFM PPRMH[9] PWM PPRMH[8] GPT PPRMH[7] ADC PPRMH[ 4:3] PPRMH[1] Edge Port PPRMH[0] GPI[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-5 6.6 Signal Descriptions The clock module signals are summarized in Ta b l e 6 - 2 and a brief description follows. For more detailed information, refer to Chapter 2, “Signal Descriptions.” 6.6.1 EXT AL This input is driven by an [...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-6 F re escale Semiconductor 6.6.5 RST O The RSTO pin is asserted by one of the following: • Internal system reset signal • FRCRSTOUT bit in the reset cont rol statu s register (RCR); see Section 10.5.1, “Reset Control Register (RCR).” 6.7 Memory Map and[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-7 6.7.1.1 Synthesiz er Contr ol Register (SYNCR) IPSBAR Offset: 0x12_0000 (SYNC R) Access: Supervisor read/wr ite 15 14 13 12 11 10 9 8 R LOLRE MFD2 MFD1 MFD0 LOCRE RFD2 R FD1 RFD0 W Reset 0 0 0 1 0 0 0 0 76 5 4 3 2 10 R LOCEN DISCLK F[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-8 F re escale Semiconductor 14–12 MFD Multiplication F actor Divider . Contain the bina ry value of the divider in the PLL feedback loop . The MFD[2:0] value is the multiplication f actor appl ied to the re ference frequency . When MFD[2:0] are changed or the[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-9 6.7.1.2 Synthesiz er Status Register (SYNSR) The SYNSR is a read-only register th at can be read at any time. W rit ing to the SYNSR has no ef fect and terminates the cycle normally . 5 FWKUP F ast wakeup . Deter mines when the syste[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-10 F re escale Semiconductor T able 6-6. SYNSR Field Descriptions Field Description 7 EXT OSC Indicates if an e xter nal oscillator is providing the reference cloc k source 0) Ref erence clock is not e xter nal oscillator 1 Ref e rence clock is e xter nal osci [...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-11 6.7.1.3 Relaxation Oscillator Control Register (ROCR) The ROCR is used to trim the frequency of the on-chip oscillator . Setting one of the TRIM bits engages its associated bypass capacitance, wh ich increases or decreases the pe ri[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-12 F re escale Semiconductor 6.7.1.5 Clock Contr ol High Register (CCHR) The CCHR sets the pre-division fact or , which divides down the PLL input clock by 1 (CCH R[2:0] = 000) to 8 (CCHR[2:0] =1 1 1 ). This allows an external oscillat or or crystal of more tha[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-13 6.7.1.7 Oscillator C ontr ol High Register (OCHR) The OCHR is used to enable and configure the relaxation oscillator . IPSBAR Offset: 0x12_0009 (CCLR) Access: Super vis or read/write 76543210 R ———— — — OSCSEL1 OSCSEL0 W[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-14 F re escale Semiconductor 6.7.1.8 Oscillator C ontr ol Low Register (OCLR) The OCLR is used to enable and configure the external oscillator . IPSBAR Offset: 0x12_000A (OCHR) Access: Super vis or read/write 76543210 R OCOEN STBY —————— W Reset: Se[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-15 6.7.1.9 Real-Time C loc k Control Register (R TCCR) The R TCCR is used to conf igure the R TC oscillator . T able 6-13. OCLR Field Descriptions Field Description 7 OSCEN Externa l Oscillator Enable bit. This bit enables the cr ystal[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-16 F re escale Semiconductor 6.7.1.10 Bac kup W atchdog Time r Contr ol Register (BWCR) The BWCR is used to configure the interaction between the clock module and the Backup W atchdog T i mer module (see Chapter 7, “Backup W atchdog Timer (BWT) Module ”). N[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-17 6.8 Functional Description This section provides a functional description of the clock module. 6.8.1 System Cloc k Modes The system clock source and P LL mode (enabled/disabled) are determined during reset (see T able 10-5 ). The va[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-18 F re escale Semiconductor In PLL mode, the PLL operates in self-clocked mode (SCM) during reset until the input reference clock to the PLL begins operating within the limits given in the elec trical specifications. If a PLL failure causes a reset, the system[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-19 Figure 6-12. Crystal Oscillator Example 6.8.4.1 Phase and Freq uency Detector (PFD) The PFD is a dual-latch ph ase-frequency detector . It compares th e phase and frequency of the reference and feedback clocks. The reference clock c[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-20 F re escale Semiconductor 6.8.4.3 V oltage Control Output (VCO) The voltage across the loop filter co ntrols the frequency of the VCO output. The frequency-to-voltage relationship (VCO gain) is positive, and the output frequency is four times the tar get sys[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-21 Figure 6-13. Loc k Detect Sequence 6.8.4.6 PLL Loss of Lock Conditions After the PLL acquires lock after rese t, the LOCK and LOCKS flags are se t. If the MFD is changed, or if an unexpected loss of lock condition occu rs, the LOCK [...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-22 F re escale Semiconductor 6.8.4.8 Loss of Clock Detection The LOCEN bit in the SYNCR enables the loss of clock detection circuit to moni tor the input clocks to the phase and frequency detector ( PFD). When the reference or feedba ck clock frequenc y falls b[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-23 6.8.4.11 Loss of Cloc k in Stop Mode T able 6-19 shows the resulting actions for a loss of clock in stop mode wh en the device is being clocked by the various clocking methods. T able 6-19. Stop Mode Operation MODE In LOCEN LOCRE LO[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-24 F re escale Semiconductor NRM 0 0 0 Off On 1 Lose lock No loc k regain Unstable NRM 0–>‘LK 0–>1 ‘LC Block LOCKS until lock regained Lose reference clock or no f .b. clock regain Stuck — — — Lose reference clock, regain Unstable NRM 0–&g[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-25 NRM 1 0 0 Off On 0 Lose lock, f .b . clock Regain NRM ‘LK 1 ‘LC REF mode not entered durin g stop No f .b. clock or lock regain Stuck — — — Lose reference clock SCM 0 0 1 W akeup without lock NRM 1 0 0 Off On 1 Lose lock, [...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-26 F re escale Semiconductor NRM 1 1 0 On On 0 — — NRM ‘LK 1 ‘LC Lose clock RESET — — — Reset immediat ely Lose loc k Stuck — — — Lose lock, regain NRM 0 1 ‘L C NRM 1 1 0 On On 1 — — NRM ‘LK 1 ‘LC Lose clock RESET — — — Reset[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-27 SCM 1 0 0 On On 1 — — SCM 0 0 1 Lose reference clock SCM Note: PLL = PLL enabled dur ing ST OP mode. PLL = On when STPMD[1:0] = 00 or 01 OSC = oscillator enabled during STOP mode. Oscillator is on when STPMD[1:0] = 00, 01, or 10[...]

Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-28 F re escale Semiconductor[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 7-1 Chapter 7 Bac kup W atchdog Timer (BWT) Module 7.1 Intr oduction The Backup W atchdog T imer (BWT) module is used to he lp software recover from runaway code. This section presents the modes of opera tion, register information, and func tional de[...]

Backup W atchdog Timer (BWT ) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 7-2 F re escale Semiconductor 7.1.2.1 W ait Mode The functionality of the BWT in W ait mode depends on the value of WCR[W AIT]. When WCR[W AIT]=1, the BWT stops wh en the device enters W ait mode . When the device leaves W ait mode, the BW[...]

Backup W atchdog Timer (BWT) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 7-3 7.2.2 Register Descriptions 7.2.2.1 Backup W atchdog Time r Control Register (WCR) The WCR, shown in Figure 7-2 , configures the operation of the BWT . It is a read-always/write-once register; after the registe[...]

Backup W atchdog Timer (BWT ) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 7-4 F re escale Semiconductor 7.2.2.2 Backup W atchdog Timer Modulus Register (WMR) The WMR, shown in Figure 7-3 , contains the value (modulus) that is loaded into the BWT count register (WCNTR) when the BWT is serviced. This value ef fect[...]

Backup W atchdog Timer (BWT) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 7-5 7.2.2.4 Backup W atchdog Time r Service Register (WSR) The WSR is shown in Figure 7-5 , and is used to instruct the BWT to reset its internal counter to the value in WMR[WM]. This is known as servicing the BWT [...]

Backup W atchdog Timer (BWT ) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 7-6 F re escale Semiconductor 7.3 Functional Description When the BWT is properly enabled, it loads the value in WMR[WM] into WCNTR[WC] and begins to decrement WCNTR[WC]. If WCNTR[WC ] reaches zero, the BWT asserts a system reset. T o prev[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-1 Chapter 8 P o wer Management 8.1 Intr oduction This chapter explains the low- power operation of the MCF5221 1. 8.1.1 Features The following features support low-power operation. • Four modes of operation: run, wait, doze, and stop • Ability [...]

P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-2 F re escale Semiconductor 8.2.1 P eripheral P ower Mana g ement Register s (PPMRH, PPMRL) The PPMRH and PPMRL registers provide a bit map for controlling the generation of the module clocks for each decoded address space associat ed with the IPS controll[...]

Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-3 T able 8-2. PPMRH Field Descriptions Field Description 31–12 Reser v ed, should be cleared. 11 CDCFM Disable clock to the CFM (Common Flash Mo dule) 0 CFM modu le clock is enabled 1 CFM modu le clock is disabled 10 [...]

P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-4 F re escale Semiconductor 8.2.1.1 Peripheral P ower Management Register Low (PPMRL) IPSBAR Offset: 0x0018 (PPMRL) Access: read/write 31 30 29 28 27 26 25 24 R 0 0 0 0 0 00 0 W Reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 R0 0 0 0 0 0 CDINTC0 CDTMR 3 W R[...]

Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-5 8.2.2 Low-P ower Interrupt Contr ol R egister (LPICR) Implementation of low-power stop m ode and exit from a low-power mode via an interrupt require communication between th e CPU and logic associated with the inte rr[...]

P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-6 F re escale Semiconductor The following is the sequence of operations needed to enable this functionality: 1. The LPICR is programmed, setting the ENBSTOP bit (if stop mode is the desired low-power mode) and loading the appropria te interrupt priority le[...]

Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-7 8.2.3 P eripheral P ower Mana gement Set Register (PPMRS) The PPMRS register provides a simple memory-ma pped mechanis m to set a given bit in the PPMR x registers to disable the clock for a given IPS module without t[...]

P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-8 F re escale Semiconductor 8.2.4 P eripheral P ower Mana ge ment Clear Register (PPMRC) The PPMRC register provides a simple memory-mappe d mechanism to clear a given bit in the PPMR x registers to enable the clock for a given IPS module without the ne ed[...]

Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-9 8.3 IPS Bus Timeout Monitor The IPS controller implements a bus timeout monito r to ensure that every IPS bus cycle is properly terminated within a programmed period of time. The monitor continually checks for termina[...]

P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-10 F re escale Semiconductor the cycle with an error termination. At reset, the I PSBMT is enabled with a maximum timeout value. See Figure 8-7 and Ta b l e 8 - 9 for the IPSBMT definition. 8.4 Functional Description The functions and characteristics of th[...]

Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-11 A wakeup event is required to exit a low-power mode and return to run mode. W akeup events consist of any of these conditions: • Any type of reset • Any valid, enabled interrupt request Exiting from low-power mod[...]

P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-12 F re escale Semiconductor further details). A peripheral may be disabled at any time and rema ins disabled during any low-power mode of operation. 8.4.2 P eripheral Behavior in Lo w-P ower Modes 8.4.2.1 ColdFire Core The ColdFire core is disabled duri n[...]

Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-13 8.4.2.6 I 2 C Module When the I 2 C Module is enabled by the setting of the I2CR[IE N] bit and when the device is not in stop mode, the I 2 C module is operable and may generate an interrupt to bring the device out o[...]

P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-14 F re escale Semiconductor 8.4.2.10 I/O P or ts The I/O ports are unaf f ected by entr y into a low-power mode. These pi ns may impact low-power current draw if they are configured as out puts and are sourcing current to an ex ternal load. If low-power m[...]

Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-15 8.4.2.15 Pr ogrammable Interrupt Timers (PIT0–PIT1) In stop mode (or in doze mode, if so programmed), the programmabl e interrupt timer (PIT) ce ases operation, and freezes at the current value. When exiting these [...]

P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-16 F re escale Semiconductor I 2 C Module Enabled Y es 2 Enabled Y es 2 Stopped No QSPI Enabled Y es 2 Enabled Y es 2 Stopped N o DMA Timers Enabled Y es 2 Enabled Y es 2 Stopped No Interrupt Controll er Enab led Y es 2 Enabled Y es 2 Enabled Y es 2 I/O P [...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 9-1 Chapter 9 Chip Configuration Module (CCM) 9.1 Intr oduction This chapter describes the various ope rating configurations of the device. It also pr ovides a description of signals used by the CCM and a programming model. 9.1.1 Features The chip co[...]

Chip Configuration Module (CCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 9-2 F re escale Semiconductor 9.2.1 RCON The serial flash programming mode is entered by asserting the RCON pin (with the TEST pin negated) as the chip comes out of reset. While the device is in this mode, the EzPort has access to the flash mem[...]

Chip Configuration Modu le (CCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 9-3 9.3.2 Memory Map 9.3.3 Register Descriptions The following section describes the CCM registers. 9.3.3.1 Chip Configuration Register (CCR) T able 9-3. Chip Configuration Module Memory Map IPSBAR Offset 1 1 Addresse[...]

Chip Configuration Module (CCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 9-4 F re escale Semiconductor 9.3.3.2 Reset C onfiguration Register (RCON) At reset, RCON determines the defa ult operation of certain chip functi ons. All default functions defined by the RCON values can only be overridden duri ng reset config[...]

Chip Configuration Modu le (CCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 9-5 T able 9-6. CIR Field Description Field Description 15–6 PIN P ar t identification number . Contain s a uni que identification number f or the device . 5–0 PRN P ar t revision number . This number is increased[...]

Chip Configuration Module (CCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 9-6 F re escale Semiconductor[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 10-1 Chapter 10 Reset Contr oller Module 10.1 Intr oduction The reset controller is provided to de termine the cause of reset, ass ert the appropriate reset signals to the system, and keep a history of what caused the reset. The low voltage detecti o[...]

Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 10-2 F re escale Semiconductor Figure 10-1. Reset Contr oller Bloc k Diagram 10.4 Signals T able 10-1 provides a summary of the reset controller signal properties. Th e signals are described in the following sections. 10.4.1 RSTI Asserting the external[...]

Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 10-3 See T able 10-2 for the memory map and the following para graphs for a description of the registers. 10.5.1 Reset Contr ol Register (RCR) The RCR allows software control for requesting a reset, independen tly asserting th[...]

Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 10-4 F re escale Semiconductor 10.5.2 Reset Status Register (RSR) The RSR contains a status bit for ev ery reset source. When reset is ente red, the cause of the reset condition is latched, along with a value of 0 for the other reset sources that were [...]

Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 10-5 10.6 Functional Description 10.6.1 Reset Sour ces T able 10-5 defines the sources of reset and the signals driven by the reset controller . T o protect data integrity , a sync hronous reset source is not acted upon by the[...]

Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 10-6 F re escale Semiconductor Internal byte, word, or longword writes are guarant eed to complete without data corruption when a synchronous reset occurs. Ex ternal writes, incl uding longword writes to 16-bi t ports, are also guaranteed to complete. [...]

Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 10-7 10.6.2 Reset Contr ol Flow The reset logic contro l flow is shown in Figure 10-4 . In this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the fl ow descriptio[...]

Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 10-8 F re escale Semiconductor Figure 10-4. Re set Control Flow RSTI PIN OR WD TIMEOUT OR SW RESE T? LOSS OF CLOCK? LOSS OF LOCK? RSTI NEGA TED? PLL MODE? BUS CYCLE COMPLETE ? RCON ASSERTED? PLL LOCKED? ENABLE BUS MONIT OR ASSER T RST O AND LA TCH RESE[...]

Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 10-9 10.6.2.1 Synchr onous R eset Requests In this discussion, the refe rences in parentheses refer to the state numbers in Figure 10-4 . All cycle counts given are approximate. If the external RSTI signal is asserted by an ex[...]

Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 10-10 F reescale Semiconductor If a loss-of-clock or loss-of-loc k condition is detected during the 512 cycle wait, the reset sequence continues after a PLL lock (9, 9A). 10.6.3.2 Reset Status Flags For a POR reset, the POR and L VD bits in the RSR are[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-1 Chapter 11 Real-Time Cloc k 11.1 Intr oduction This section discusses how to operate and program the real-time clock (RTC) module that maintains the system clock, provides stopwatch, alarm, and interrupt functions, a nd supports the following fe[...]

Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-2 F re escale Semiconductor 11.1.3 Modes of Operation The incoming 1 Hz signal is used to increment the seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate R TC interrupt s when the T OD settings reach programmed valu[...]

Memory Map/Register Definition MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-3 11.2.1.1 R TC Hours and Minutes Counter Register (HOURMIN) The real-time clock hours a nd minutes counter regist er (HOURMIN) is used to program the hours and minutes for the TO D clock. It can be read or writ ten [...]

Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-4 F re escale Semiconductor 11.2.1.2 R TC Seconds Counter Register (SECONDS) The real-time clock seconds regist er (SECONDS) is used to program the seconds for the T OD clock. It can be read or written at any time. After a write, the time changes to th e ne[...]

Memory Map/Register Definition MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-5 11.2.1.3 R TC Hours and Minutes Alarm Register (ALRM_HM) The real-time clock hours a nd minutes alarm (ALRM_HM) register is used to configure the hours and minutes setting for the alarm. The alarm set tings can be [...]

Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-6 F re escale Semiconductor 11.2.1.4 R TC Seconds A larm Register (ALRM_SEC) The real-time clock seconds alarm (ALRM_SEC) register is used to configure th e seconds setting for the alarm. The alarm settings can be read or written at any time. Figure 11-5. R[...]

Memory Map/Register Definition MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-7 11.2.1.5 RTC Contr ol Register (RTCCTL) The real-time clock control (R TCCTL) register is used to enable the real-time clock module and specify the reference frequency info rmation for the prescaler . Figure 11-6. [...]

Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-8 F re escale Semiconductor 11.2.1.6 R TC Interrup t Status Register (R TCISR) The real-time clock interrupt status register (R TCISR) indicates the status of the various real-time clock interrupts. When an event of the types included in this register occur[...]

Memory Map/Register Definition MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-9 11.2.1.7 RTC Interrupt En able Register (R TCIENR) The real-time clock interrupt enable register (R TCIENR) is used to en able/disable the various real-time clock interrupts. Masking an interrupt bit has no ef fect[...]

Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-10 F reescale Semiconductor 11.2.1.8 R TC Stopwatch Minutes Register (STPWCH) The stopwatch minutes (STPWCH) re gister contains the current stopwatch countdown value. When the minute counter of the TOD clock increments, the value in this register decrements[...]

Memory Map/Register Definition MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-11 11.2.1.9 R TC Days Counter Register (D A YS) The real-time clock days c ounter register (DA Y S) is used to progr am the day for the TO D clock. When the HOUR field of the HOURMIN register rolls over from 23 to 00[...]

Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-12 F reescale Semiconductor 11.2.1.10 RTC Da y Alarm Register (A LRM_D A Y) The real-time clock day alar m (ALRM_DA Y) register is used to conf igure the day for the alarm. The alarm settings can be read or written at any time. Figure 11-11 . RTC Da y Alarm[...]

Functional Description MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-13 Figure 11-13. R TC General Oscillator Count Lo wer Register (RTCGOCL) 11.3 Functional Description The R TC uses a supplied 1 Hz signal to increment the seconds, minutes , hours, and days TOD counters. The alarm functions,[...]

Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-14 F reescale Semiconductor Interrupts signal when each of the four counters incr ements, and can be used to indicate when a counter rolls over . For example, each tick of the seconds counter caus es the 1HZ interrupt flag to be set. When the seconds counte[...]

Initialization/Applicatio n Information MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-15 Figure 11-14. Flow Cha r t of RT C Operation 11.4.2 Code Example for Initializing the Real-Time Cloc k Figure 1 1-15 shows sample code for initializing the R TC. MCF_CLOCK_RTCCR=0b01010110; //RTCCC MCF_RT[...]

Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-16 F reescale Semiconductor[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-1 Chapter 12 System Contr ol Module (SCM) 12.1 Intr oduction This section details the functionality of the syst em control module (SCM) th at provides the programming model for the system access contro l unit (SACU), system bus arbiter , 32-bit co[...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-2 F re escale Semiconductor • System access control unit (SACU) programming model — Master privilege registe r (MPR) — Peripheral access control registers (P ACRs) — Grouped peripheral access contro l registers (GP ACR0, GP ACR1) 12.4 Me[...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-3 12.5 Register Descriptions 12.5.1 Internal P eripheral System Base Address Register (IPSB AR) The IPSBAR specifies the base address for the 1-Gbyte memory space associated with the on-chip peripherals. At reset, the b[...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-4 F re escale Semiconductor NO TE Accessing reserved IPSBAR memory sp ace could result in an unterminated bus cycle that causes the core to hang. Only a hard reset allows the core to recover from this state. Therefore, all bus accesses to IPSBAR[...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-5 known as a ping-pong scheme) may load data into one portion of the dual-ported SRAM while the processor is manipulating data in another portion of the SRAM. After the processo r completes the data calculations, it beg[...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-6 F re escale Semiconductor • The back door enable bit, RAMBAR [BDE], is cleared at reset, di sabling the module access to the SRAM. NO TE The RAMBAR default value of 0x0000_0000 is invalid. The RAMBAR located in the processor ’ s CPU space [...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-7 12.5.4 Core W atc hdog Control Register (CWCR) The core watchdog timer prevents system lockup if the software becomes trapped in a loop with no controlled exit. The core watchdog timer can be enabled or disabled throu[...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-8 F re escale Semiconductor 12.5.5 Core W atchdog Service Register (CWSR) The software watchdog service sequence must be performed using the CWSR as a data register to prevent a CWT time-out. The service sequen ce requires two writes to this dat[...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-9 12.6 Internal Bus Arbitration The internal bus arbitration is perf ormed by the on-chip bus arbiter , wh ich containing the arbitration logic that controls which of up to four MBus masters (M0–M3 in Figure 12-6 ) ha[...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-10 F reescale Semiconductor • There are two arbitration algorith ms: fixed and round-robin. Fixed ar bitration sets the next-state arbitration pointer to the highest priority requester . Round-robin ar bitration sets the next-state arbitration[...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-11 • Master 2 (M2): 4-channel DMA • Master 0 (M0): V2 ColdFire Core IPSBAR Offset: 0x001C (MP ARK) Access: read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 M2_P _EN BCR2 4BIT 00 M2_PRTY M0_PR[...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-12 F reescale Semiconductor The initial state of the master priorities is M2 > M0. System software should guarantee that the programmed M n _PR TY fields are unique, otherwise the hardware defaults to the initial-state priorities. 12.7 System[...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-13 • User operand write Instruction fetch accesses are associ ated with the execute attribute. It should be noted that while the bus does not implement the concept of reference type (c ode versus data) and only suppor[...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-14 F reescale Semiconductor 12.7.3.1 Master Privile ge Reg is ter (M PR) The MPR specifies the access privilege level associated with each bus master in the platform. The regis ter provides one bit per bus master . Bit 3 is reserved a nd should [...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-15 IPSBAR Offset: 0x0024 + Offset (P ACR n ) Access: read/write 76543210 R LOCK1 A CCESS_CTRL1 LOCK0 ACCESS_CTRL0 W R e s e t : 00000000 Figure 12-9. P eripheral Access Control Register ( P A CR n ) T able 12-10. P A CR[...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-16 F reescale Semiconductor At reset, these on-chip modules are configured to have only supervisor read/write access capabilities. If an instruction fetch access to any of these peripheral modu les is attempted, the IPS bus cycle is immediately [...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-17 At reset, these on-chip modules are configured to have only supervisor read/write access capabilities. Bit encodings for the ACCESS_CTRL fi eld in the GP ACR are shown in T able 12-14 . T able 12-15 shows the memory [...]

System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-18 F reescale Semiconductor T able 12-15. GP A CR Address Space Regist er Space Protected (IPSB AR Offset) Modules Protected GP A CR0 0x0000 _0000– 0x03FF_FFFF P or ts, CCM, PMM, Reset controller , Clock, EPOR T , WDOG, PIT0–PIT3, QADC, G PT[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-1 Chapter 13 General Purpose I/O Module 13.1 Intr oduction Many of the pins associated with the external interface may be us ed for several diff erent functions. When not used for their primary function, many of the pins may be used as general-pur[...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-2 F re escale Semiconductor 13.2 Overview The MCF5221 1 ports module controls the confi guration for the following external pins: • External bus accesses • Chip selects • Debug data • Processor status •U S B •I 2 C serial control • [...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-3 T able 13-1. Register s in the MCF52211 P orts Address Space Address 1 1 The register address is the sum of the IPSBAR address and the value in this column. 31–24 23–16 15–8 7–0 Access 2 2 S/U = supervisor or u[...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-4 F re escale Semiconductor 13.6 Register Descriptions 13.6.1 P or t Output Data Registers (POR T n ) The PORT n registers store the data to be driven on the corresponding port n pins when the pins are configured for digital output. The PORT n re[...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-5 13.6.2 P or t Data Direction Reg ister s (DDR n) The DDR n registers control the direction of the port n pin drivers when the pins are configured for digital I/O. The DDR n registers with a full 8-bit implementation ar[...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-6 F re escale Semiconductor Setting any bit in a DDR n register configures the corresponding port n pin as an output. Clearing any bit in a DDR n register configures the corresponding pin as an input. IPSBAR Offsets: 0x10_002C (DDRDD) 0x10_0022 ([...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-7 13.6.3 P or t Pin Data/Set Data Register s (PORT n P/SET n ) The PORT n P/SET n registers reflect the current pin states and control the sett ing of output pins when the pin is configured for digital I/O. The PORT n P/[...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-8 F re escale Semiconductor IPSBAR Offsets: 0x10_003E (PORTT AP/SETT A) 0x10_003F (PORTTCP/SETTC) 0x10_0040 (PORTTDP/SETTD) 0x10_0041 (PORTU AP/SETUA) 0x10_0042 (PORTUBP/SETUB) 0x10_0043 (PORTUCP/SETUC) Access: User read/write 76543210 R 0 0 0 0 [...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-9 13.6.4 P or t Clear Output Data Registers (CLR n ) Writing 0s to a CLR n register clears the corr esponding bits in the PORT n register. Writing 1s has no effect. Reading the CLR n register returns 0s. The CLR n regist[...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-10 F reescale Semiconductor 13.6.5 Pin Assignment Regi sters All pin assignment registers are read/write. Refer to Table 2-1 for the different functi ons assignable to each pin. Some signals can be assigne d to different pins (see Table 2-1 ). Ho[...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-11 13.6.5.1 Dual-Function Pi n Assignment Registers The dual function pin assignment regist ers allow each pin controlled by each register bit to be configured for the primary function or the GPIO fu nction. The fields a[...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-12 F reescale Semiconductor IPSBAR Offset: 0x10_006C (PQSP AR) Access: User read/write 15 14 13 12 11 1 0 9 8 R 0 0 P n PAR 6 P n PAR5 P n PAR4 W R e s e t 00000000 76543210 R P n PAR3 P n PAR2 P n PAR1 P n PAR0 W R e s e t 00000000 Figure 13-2 4[...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-13 13.6.5.3 P or t NQ Pin Assign ment Register (PNQP AR) The port NQ pin assignment register (PNQPAR) contains quad-function (for IRQ1 ) and dual-function pin assignment controls. Refer to Table 13-6 and Table 13-7 for t[...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-14 F reescale Semiconductor IPSBAR Offset: 0x10_0078 (PSRR ) Access: User read/write 31 30 29 28 27 2 6 25 24 R PSRR31 PSRR30 PSRR29 PSRR28 PSRR27 PSRR26 PSRR25 PSRR24 W R e s e t 00000000 23 22 21 20 19 1 8 17 16 R PSRR23 PSRR22 PSRR21 PSRR20 PS[...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-15 13.6.6.2 Pin Drive Strength Register (PDSR) The pin drive strength register is read/write. Each bit resets to logic 0 in single chip mode (MCF52211 default) and logic 1 in EzPort and FA ST mode. The fields are describ[...]

General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-16 F reescale Semiconductor[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-1 Chapter 14 Interrupt Contr oller Module This section details the functionality for the MCF5221 1 interrupt controller . The general features of the interrupt controller include: • 57 interrupt sources — 50 fully-programmabl e interrupt sourc[...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-2 F re escale Semiconductor fetched data provides an index into the exception vector table, which contains 256 addresses, each pointing to the beginning of a specific exception service r outine. In particular , vectors 64–255 of the exception [...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-3 The level and priority is fully pr ogrammable for all sources except inte rrupt sources 1–7. Interrupt source 1–7 (from the Edge Port module) are fixed at th e corresponding level’ s midpoi nt priority . Thus, a[...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-4 F re escale Semiconductor if interrupt source 8 is active and acknowledged, then Vector number = 72 if interrupt source 9 is active and acknowledged, then Vector number = 73 ... if interrupt source 62 is active and acknowledged, then Vector nu[...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-5 14.3 Register Descriptions The interrupt controller registers are described in the following sections. IPSBAR + 0x0C54 ICR n 20 IC R n 21 ICR n 22 ICR n 23 IPSBAR + 0x0C58 ICR n 24 IC R n 25 ICR n 26 ICR n 27 IPSBAR +[...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-6 F re escale Semiconductor 14.3.1 Interrupt P e nding Regist ers (IPRH n , IPRL n ) The IPRH n and IPRL n registers, Figure 14-1 and Figure 14-2 , each 32 bits, provide a bit map for each interrupt request to indicate if there is an active re q[...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-7 14.3.2 Interrupt Mask Register (IMRH n , IMRL n ) The IMRH n and IMRL n registers are each 32 bits and provide a bit map for each interrupt to allow the request to be disabled (1 = disable the request, 0 = enable the [...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-8 F re escale Semiconductor NO TE A spurious interrupt may oc cur if an interrupt source is being masked in the interrupt controller mask register (IMR) or a module’ s interrupt mask register while the interr upt mask in the st atus register ([...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-9 request, 0 = negate request) in the appropriate INTFRC n register . The assertion of an interrupt request via the INTFRC n register is not affected by the interrupt mask register . The INTFRC n register is cleared by [...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-10 F reescale Semiconductor 14.3.4 Interrupt Request Level Register (IRLR n ) This 7-bit register is updated each machine cycle and rep resents the current interrupt requests for each interrupt level, where bit 7 corresponds to level 7, bit 6 to[...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-11 14.3.6 Interrupt Contr ol Registers (ICR nx ) Each ICR nx , where x = 1, 2,..., 63, specifies the interrupt level (1–7) and the priority within the level (0–7). As shown in T able 14-1 1 , all ICR nx registers ca[...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-12 F reescale Semiconductor IPSBAR Offsets: See T able 14-2 f or register offsets (ICR nx ) Access: R/W (Read only for ICR n 1-ICR n 7) 76543210 R 0 0 IL IP W R e s e t : 00 000000 Note: It is the responsibility of the software to program the IC[...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-13 14.3.6.1 Interrupt Sour ces T able 14-13 lists the interrupt sources fo r each interrupt request line. T able 14-13. Interrup t Source Assignment s Source Module Flag Source Description Flag Clearing Mechanism 0 Not [...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-14 F reescale Semiconductor 29 Not used (Reser v ed) 30 Not used (Reser v ed) 31 Not used (Reser v ed) 32 Not used (Reser v ed) 33 Not used (Reser v ed) 34 Not used (Reser v ed) 35 Not used (Reser v ed) 36 Not used (Reser v ed) 37 Not used (Rese[...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-15 14.3.7 Software and Level m IA CK Registers (SWIA CK n , L m IA CK n ) The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed via a processor- generated interrupt acknowle dge cycle[...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-16 F reescale Semiconductor 14.3.8 Global Le vel m IA CK Registers (GL m IA CK) In addition to the soft ware IACK registers ( Section 14.3.7, “Software and Level m IACK Registers (SWIACKn, LmIACKn)” ), there are global IACK registers, GL m I[...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-17 2. The processor executes a ST OP instruction which places it in stop mode. After the processor is stopped, each interrupt controller enables a special logic path that evaluates the incoming interrupt sources in a pu[...]

Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-18 F reescale Semiconductor[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-1 Chapter 15 Univer sal Serial Bus, O TG Capable Contr oller NO TE Portions of Chapter 15, “Universal Serial Bus, OTG Capable Controller,” relating to the EHCI specification are Copyright © Intel Corporation 1999-2001. The EHCI specificat ion[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-2 F re escale Semiconductor USB software provides a uniform vi ew of the system for all applica tion software, hiding implementation details making application software more portable. It manages the dynamic attach and detach of[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-3 15.1.2 USB On-The-Go USB (Universal Serial Bus) is a popular standard for connecting peripherals and portable consumer electronic devices such as digital cameras and hand-held comput ers to host PCs.[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-4 F re escale Semiconductor 15.1.3 USB-FS Features • USB 1.1 and 2.0 compliant fu ll-speed device controller • 16-Bidirectional end points • DMA or FIFO data stream interfaces • Low-power consumption • On-The-Go proto[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-5 Figure 15-3. Buffer Descr iptor T able 15.3.2 Rx vs. Tx as a USB T a r g et De vice or USB Host The USB-FS core can function as a USB target devi ce (function), or as a USB hosts, and may switch mode[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-6 F re escale Semiconductor BDT . The BDT must be located on a 512-byte boundary in system memory . Al l enabled TX and RX endpoint BD entries are indexed into the BDT to al low easy access via the US B-FS or ColdFire Core. Whe[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-7 Figure 15-5. Buf fer Descriptor Byte Format 31:26 25:16 15:8 7 6 5 4 3 2 1 0 RSVD BC (10-Bits) RSVD OWN DA T A0/1 KEEP/ T OK_PID[3] NINC/ T OK_PID[2] DTS/ 5 T OK_PID[1] BDT_ST ALL/ T OK_PID[0] 0 0 Bu[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-8 F re escale Semiconductor 15.3.5 USB T ransaction When the USB-FS transmits or receives data, it co mputes the BDT address using the address generation shown in T able 2. After the BDT has been read and if the OWN bit equals [...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-9 because it is assumed that a second attempt will be que ued and succeed in the future. For host mode, the TOK_DNE interrupt fires and the T OK_ PID field of the BDT is 1 11 1 to indicate the DMA late[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-10 F reescale Semiconductor The following sections provide details about the registers in the USB OTG memory map. 15.4.1 Capability Registers The capability registers sp ecify the software limits , restrictions, and capabil iti[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-11 15.4.1.2 P erip heral ID Comple ment Register (ID_COMP) The Peripheral ID Complement Register reads back th e complement of the Peripheral ID Register . For the USB Peripheral, this is the value 0xF[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-12 F reescale Semiconductor 15.4.1.3 P erip heral Re vision Register (REV) This register contains the re vision number of the USB Module. Figure 15-9 shows the REV register . 15.4.1.4 P erip heral Additional Inf o Register (ADD[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-13 15.4.1.5 O TG Interrupt Status Register (O TG_INT_ST A T) The OTG Interrupt S tatus Register records changes of the ID sense a nd VBUS signals. So ftware can read this register to determine which ev[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-14 F reescale Semiconductor 15.4.1.6 O TG Interrupt Cont rol Register (O TG_INT_EN) The OTG Interrupt Control Register enables the corr esponding interrupt status bits defined in the OTG Interrupt Status Register . Figure 15-12[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-15 15.4.1.7 Interrupt Status Register (O TG_ST A T) The Interrupt Status Register displa ys the actual value from the external comparator outputs of the ID pin and VBUS. Figure 15-13 shows the OTG_ST A[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-16 F reescale Semiconductor 15.4.1.8 O TG Control Register (O TG_CTRL) The OTG Control Register controls the operation of VBUS and Data Line termination resistors. Figure 15-14 shows the OTG_CTRL register . IPSBAR Offset: 0x1C_[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-17 15.4.1.9 Interrupt Status Register (INT_ST A T) The Interrupt S tatus Register contai ns bits for each of the interrupt sources within the USB Module. Each of these bits are qualified with their res[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-18 F reescale Semiconductor 15.4.1.10 Interrupt Enable Register (INT_ENB) The Interrupt Enable Register cont ains enable bits for each of the interrupt sources within the USB Module. Setting any of these bits enables the respec[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-19 15.4.1.11 Error Interrupt Status Register (ERR_ST A T) The Error Interrupt S tatus Register contains enable bits for each of the error sources within the USB Module. Each of these bits are qualified[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-20 F reescale Semiconductor 15.4.1.12 Error Interrupt Enable Register (ERR_ENB) The Error Interrupt Enable Register c ontains enable bits for each of th e error interrupt sources within the USB Module. Setting any of these bi t[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-21 15.4.1.13 Status Register (ST A T ) The S tatus Register reports the transaction status within the USB Module. When the ColdFire core has received a TOK_DNE interrupt the S tatus Register should be [...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-22 F reescale Semiconductor 15.4.1.14 Control Register (CTL) The Control Register provides va rious control and configuration information for the USB Module. Figure 15-20 shows the CTL register . IPSBAR Offset: 0x1C_0094 (CTL) [...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-23 15.4.1.15 Address Register (ADDR) The Address Register holds the unique USB address that the USB Module decodes when in Peripheral mode (HOST_MODE_EN=0). When operating in Host mode (HOST_MODE_EN=1)[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-24 F reescale Semiconductor 15.4.1.16 BDT Pa ge Register 1 (BDT_P A GE_01) The Buff er Descriptor T able Page Register 1 contains an 8-bit value that is used to compute the address where the current Buffer Des criptor T a ble ([...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-25 15.4.1.17 Frame Number Register L ow/High (FRM_NUML, FRM_NUMH) The Frame Number Register Low cont ains an 8-bit value that is used to compute the address where the current Buffer Descriptor T able ([...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-26 F reescale Semiconductor 15.4.1.18 T oken Register (T OKEN) The T oken Register is used to perform USB tran sactions when in host mode (HOST_MODE_EN=1). When the ColdFire core processor wishes to execute a USB transaction to[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-27 15.4.1.19 SOF Threshold Register ( SOF_THLD) The SOF Threshold Register is used only in Hosts mode (HOST_MODE_EN=1). When in Host mode, the 14-bit SOF counter counts the interval between SOF frames.[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-28 F reescale Semiconductor 15.4.1.20 BDT Pa ge Register 2 (BDT_P A GE_02) The Buff er Descriptor T able Page Register 2 contains an 8-bit value that is used to compute the address where the current Buff er Descriptor T abl e ([...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-29 15.4.1.22 Endpoint Con tr ol Registers 0 – 15 (ENDPT0–15) The Endpoint Control Registers cont ain the endpoint control bits for each of the 16 endpoints available within the USB Module for a dec[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-30 F reescale Semiconductor 5 Reser ved 4 EP_CTL_DIS This bit, when set, d isab les contro l (SETUP) transf er s. When cleared, control tr ansfers are enab led. This applies if and only if the EP_ RX_EN and EP_TX_EN bits are al[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-31 15.4.1.23 USB Control Register (USB_CTRL) IPSBAR Offset: 0x1C_0100 (USB_CTRL) Access: User read/wr ite 76543210 R SUSP PDE ———— CLK_SRC W R e s e t : 01000011 Figure 15-30. USB Contr ol Regi[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-32 F reescale Semiconductor 15.4.1.24 USB O TG Observe Register (USB_O TG_OBSER VE) IPSBAR Offset: 0x1C_0104 (USB_O TG_OBSERVE) Access: User read/write 76543210 R DP_PU DP_PD 0 D M_PD VBUSE VBUSCHG VBUSDIS 1 W R e s e t : 11000[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-33 15.4.1.25 USB O TG Control Register (USB_O TG_CONTROL) 15.5 O TG and Host Mode Operation The Host Mode logic allows devices such as digital cameras and palmt op computers to function as a USB Host C[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-34 F reescale Semiconductor Host mode is intended for use in handheld-portable de vices to allow easy connect ion to simple HID class devices such as printers and keyboards. It is NOT in tended to perform the functio ns of a fu[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-35 T o complete a control transaction to a connected device: 1. Complete all steps discover a connected device 2. Set up the endpoint control register for bidi rectional control transfers EP_CTL0[4:0] [...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-36 F reescale Semiconductor T o send a Full speed bulk data transfer to a target device: 1. Complete all steps discover a connected device and to configure a conn ected device. W rite the ADDR register with the address of the t[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-37 Figure 15-33. Dual Role A Device Flo w Diagram T able 15-38. Stat e Descriptions f or Figure 15-33 State Action Respons e A_IDLE If ID Interrupt. The cable has been un-plugge d or a T ype B cable ha[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-38 F reescale Semiconductor 15.7.2 O TG Dual Role B Devi ce Operation A device is considered a B device if it connected to the bus with a USB T ype B cable or a USB T ype Mini B cable. A dual role B device operates as the follo[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-39 15.7.3 P ower The USB-FS core is a fully synchronous static design. The power used by the de sign is dependant on the application usage of the core . Applications that trans fer more data or cause a[...]

Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-40 F reescale Semiconductor 15.7.4 USB Suspend State USB bus powered devices are required to respond to a 3ms lack of activity on th e USB bus by going into a suspend state. Software is notified of the suspend c ondition via th[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 16-1 Chapter 16 Edge P or t Module (EPORT) 16.1 Intr oduction The edge port module (EPOR T) has se ven external interrupt pins, IRQ7 –IRQ1 . Each pin can be configured individually as a level-sens itive interrupt pin, an edge-de tecting inte rrupt [...]

Edge Port Module (EPORT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 16-2 F re escale Semiconductor 16.2 Low-P o wer Mode Operation This section describes the operati on of the EPOR T module in low-power modes. For more information on low-power modes, see Chapter 8, “Power Management”. T able 16-1 shows EPOR T -mod[...]

Edge Port Module (EPORT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 16-3 16.4.1 EPOR T Pin Assign ment Register (EPP AR) The EPOR T pin assignment register (EPP AR) controls the function of each pin individually . T able 16-2. Edge Port Module Memory Ma p IPSB AR Offset Register Width (bits) [...]

Edge Port Module (EPORT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 16-4 F re escale Semiconductor 16.4.2 EPOR T Data Direction Register (EPDDR) The EPOR T data direction register (EPDDR) controls the direction of each one of the pins individually . 16.4.3 Edge P or t Interrupt Enable Register (EPIER) The EPOR T inter[...]

Edge Port Module (EPORT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 16-5 16.4.4 Edge P or t Data Register (EPDR) The EPOR T data register (EPDR) holds the data to be driven to the pins. 16.4.5 Edge P or t Pin Da ta Register (EPPDR) The EPOR T pin data register (EPPDR) re flects the current st[...]

Edge Port Module (EPORT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 16-6 F re escale Semiconductor 16.4.6 Edge P or t Flag Register (EPFR) The EPOR T flag register (EPFR) indi vidually latches EPOR T edge events. IPSBAR Offset: 0x13_0006 (EPFR) Access: User read/write 7 6 5 432 1 0 R EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-1 Chapter 17 DMA Contr oller Module 17.1 Intr oduction This chapter describes the direct memory access (DMA) controller modul e. It provides an overview of the module and describes in detail its si gnals and registers. The latter se ctions of this[...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-2 F re escale Semiconductor Figure 17-1. DMA Signal Dia gram NOTE Throughout this chapter , the terms exte rnal request and DREQ are used to refer to a DMA request from one of the on-chip UAR TS, DMA timers. For details on the connections associat ed [...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-3 17.2 DMA T ransf er Over vie w The DMA module can data within system memory (including memory and pe ripheral devices) with minimal processor intervention, greatly improvi ng overall system perfo rmance. The DMA module cons[...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-4 F re escale Semiconductor 17.3.1 DMA Request Contr ol (DMAREQC) The DMAREQC register provides a so ftware-controlled connection matrix for DMA requests. It logically routes DMA requests from the DMA timers and UAR T s to the four ch annels of the DM[...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-5 17.3.2 Sour ce Address Register s (SAR n ) SAR n , shown in Figure 17-4 , contains the address from which the DMA controller requests data. NOTE The backdoor enable bit must be set in the SCM RAMBAR as well as the secondary[...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-6 F re escale Semiconductor 17.3.4 Byte Count Register s (BCR n ) and DMA Status Register s (DSR n ) The Byte Count Registers (BCR n ) and DMA S tatus Registers (DSR n ) are two logical re gisters that occupy one 32-bit register , as shown in Figure 1[...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-7 IPSBAR Offsets: See Figure 17-6 (DSR n ) Access: read/write 76543210 R 0 CE BES BED 0 REQ BSY DONE W R e s e t : 00000000 Figure 17-7. DMA Status Re gisters (DSR n ) T a ble 17-3. DSR n Field Descriptions Field Description [...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-8 F re escale Semiconductor 17.3.5 DMA Contr ol Registers (DCR n ) The DMA control registers (DCR n ) are described in Figure 17-8 and T able 17-4 . IPSBAR Offsets: 0x00_010C (DCR0) 0x00_011C (DCR1) 0x00_012C (DCR2) 0x00_013C (DCR3) 31 30 29 28 27 26 [...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-9 27–25 BWC Bandwidth control. Indicates the n umber of b ytes in a bloc k transf er . When the byte count reaches a multiple of the BWC value , the DMA releases the bus. 24-23 Reserved, should be cleared. 22 SINC Source in[...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-10 F reescale Semiconductor 15–12 SMOD Source address modulo. Defines the size of the source data circular buf fer used by the DMA Controlle r . If enabled (SMOD is non-zero), the b uffer base address is locate d on a boundary of the buffer size. Th[...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-11 17.4 Functional Description In the following discussion, the te rm DMA request implies that DCR n [ST AR T] or DCR n [EEXT] is set, followed by assertion of an internal or external DMA request. The ST AR T bit is cleared w[...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-12 F reescale Semiconductor Source and destination address registers (SAR n and DAR n ) can be programmed in the DCR n to increment at the completion of a successful transfer . 17.4.1 T ransfer Requests (Cyc le -Steal and Cont inuous Modes) The DMA ch[...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-13 17.4.3 Channel Initialization and Startup Before a block transfer starts, channel registers must be initia lized with information describing configuration, request-generation method, and the data block. 17.4.3.1 Channel Pr[...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-14 F reescale Semiconductor As soon as the channel has been initialize d, it is started by wr iting a one to DCR n [ST AR T] or a peripheral DMA request, depending on the status of DCR n [EEXT]. Programming the cha nnel for internal requests causes th[...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-15 If BWC equals 000, the request si gnal remains asserted until BCR n reaches zero. DMA has priority over the core. In this scheme, the arbiter can al ways force the DMA to relinquish the bus. See Section 13.6.3, “Bus Mast[...]

DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-16 F reescale Semiconductor[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-1 Chapter 18 ColdFire Flash Module (CFM) 18.1 Intr oduction 18.1.1 Overview The ColdFire Flash Module (CFM) is a non-volatile memory (NVM) modul e for integration with a CPU. The CFM provides 128 Kbytes of 32-bi t Flash memory serving as electri c[...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-2 F re escale Semiconductor Figure 18-1. CFM Bloc k Diagram 18.1.2 Features • 128 Kbytes of 32-bit Flash memory • Automated program, erase, and verify operations • Single power supply for pr ogram and erase operations • Software programm[...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-3 • Protection scheme to preven t acciden tal program or erase of flash memory • Access restriction control for supervis or/user and data/instruction operations • Security feature to prevent unauthorized acces s [...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-4 F re escale Semiconductor 18.3.2 Flash Base Address Register (FLASHB AR) The configuration information in the flash base addr ess register (FLASHBAR) controls the operation of the flash module. • The FLASHBAR holds the base address of the fl[...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-5 NO TE Flash accesses (reads/writes) by a bus master other than the core, DMA controller , or writes to flash by the core during programming must use the backdoor flash address of IPSBAR plus an of fset of 0x0400_0000[...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-6 F re escale Semiconductor The CFM contains a set of control and status registers locat ed at the regi ster base address as defined by the system level configuration. A summary of the CFM registers is given in T able 18-3 . T able 18-2. FLASHB [...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-7 18.3.3 Register Descriptions 18.3.3.1 CFMMCR — CFM Module Configuration Reg ister The CFMMCR register is used to configure and c ontrol the operation of the internal bus interface. CFMMCR register bits [10:5] are r[...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-8 F re escale Semiconductor 18.3.3.2 CFMCLKD — CFM Clock Divider Register The CFMCLKD register is used to control the period of the clock used for time d events in program and erase algorithms. 8 AEIE Access Error Interrupt Enable The AEIE bit[...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-9 All CFMCLKD register bits are readable, while bi ts [6:0] write once and bit 7 is not writable. 18.3.3.3 CFMSEC — CFM Security Register The CFMSEC register is used to store the flash security word and CFM security [...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-10 F reescale Semiconductor The CFMSEC register is loaded from the flash c onfiguration field in the flash block at offset 0x0414 during the reset sequence, indicated by F in Figure 18-6 . The CFM flash security ope ration is described in Sectio[...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-11 T o change the flash memory protect ion on a temporary basi s, the CFMPROT register should be written after the LOCK bit in the CFMMCR register has been cleared. T o ch ange the flash memory protection loaded during[...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-12 F reescale Semiconductor 18.3.3.5 CFMSA CC — CFM Super visor Access Register The CFMSACC register is used to control supervisor/user access to the flash memory. Figure 18-9. CFM Supervisor Access Register (CFMSA CC) All CFMSACC register bit[...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-13 18.3.3.6 CFMD A CC — CFM Data Access Register The CFMDACC register is used to control data/instruction access to the flash memory. Figure 18-10. CFM Data Access Register (CFMD A CC) All CFMDACC register bits are r[...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-14 F reescale Semiconductor CFMUST A T register bits CBEIF , PVIOL, ACCERR, an d BLANK are readable a nd writable while CCIF is readable but not writable, and remain ing bits read 0 and are not writable. The CFMUST A T register bits CBEIF , CCIF[...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-15 18.3.3.8 CFMCMD — CFM Command Register The CFMCMD register is th e flash command register. Figure 18-12. CFM Command Buff er and Register (CFMCMD) All CFMCMD register bits are readable and writable except bit 7, w[...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-16 F reescale Semiconductor 18.3.3.9 CFMCLKSEL — CFM Clock Select Register The CFMCLKSEL register reflects th e factory setting for read access la tency from the system bus to the flash block. Figure 18-13. CFM Cloc k Select Register (CFMCLKSE[...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-17 18.4.2 Flash Normal Mode In flash normal mode, the user can access the CFM registers and the CFM flash memory (see Section 18.3.1, “Memory Map” ). 18.4.2.1 Read Operation A valid read operation occurs when a tra[...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-18 F reescale Semiconductor Therefore, the clock to the flas h block timing control, FCLK, is: FCLK = (input clock) / (DIV + 1) 150KHz < FCLK <= 200KHz For example, if the input clock fr equency is 33 MHz, the CFMCLKD DI V field should be [...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-19 buffered command waits for the active command to be completed before being launched. The CCIF flag in the CFMUST A T register set upon completio n of all active and buffered commands. A command write sequence can be[...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-20 F reescale Semiconductor check operation (CCIF=1), the BLANK flag sets in the CFMUST A T register if the entire flash memory is erased. If any flash memory locati on is not erased, the blank check operation terminates and the BLANK flag remai[...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-21 P age Erase V erify The page erase verify operation ve rifies all memory addresses in a flash logical page are erased. An example flow to execute the page erase verify operation is shown in Figure 18-15 . The page e[...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-22 F reescale Semiconductor Figure 18-15. Example Pa ge Erase V erify Command Flow Program The operation programs a previously erased address in the flash memory using an embedded algorithm. Write: Register CFMCLKD Read: Register CFMCLKD Write: [...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-23 An example flow to execute the program operati on is shown in Figure 18-16 . The program command write sequence is as follows: 1. W rite to a word address in a flash physical block to start the command write sequenc[...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-24 F reescale Semiconductor Figure 18-16. Example Pr ogram Command Flow P age Erase The page erase operation eras es all memor y addresses in a flash logi cal page using an embedded algorithm. Write: Register CFMCLKD Read: Register CFMCLKD Write[...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-25 An example flow to execute the page erase operati on is shown in Figure 18-17 . The page erase command write sequence is as follows: 1. W rite to any word address in a flash logical page to star t the command wr ite[...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-26 F reescale Semiconductor Figure 18-17. Example Pa ge Erase Command Flow Mass Erase The mass erase operation erases all flash me mory addresses using an embedded algorithm. Write: Register CFMCLKD Read: Register CFMCLKD Write: Logical Page Add[...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-27 An example flow to execute the mass erase command is shown in Figure 18-18 . The mass erase command write sequence is as follows: 1. W rite to any flash memory address to start the command write sequence for the mas[...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-28 F reescale Semiconductor Figure 18-18. Example Mas s Erase Command Flow Write: Register CFMCLKD Read: Register CFMCLKD Write: Array Address and Write: Register CFMCMD Mass Erase Command 0x41 Write: Register CFMUST A T yes no Clear bit CBEIF 0[...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-29 18.4.2.3.5 Flash Normal Mo de Illegal Operations The ACCERR flag is set during the command write sequence if any of th e following illegal operations are performed, causing the command write sequence to immediately [...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-30 F reescale Semiconductor If a command is not active (CCIF=1) when the MC U enters stop mode, the ACCERR flag does not set. 18.4.3 Flash Security Operation The CFM provides security informati on to the integration module and the rest of the MC[...]

ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-31 18.4.3.2 Blank Chec k A secured CFM can be unsecur ed by verifying that the entire flash me mory is erased. If required, the mass erase command can be executed on the flash memory. The blank check command must then [...]

ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-32 F reescale Semiconductor[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 19-1 Chapter 19 EzP or t EzPort is a serial flash programming interface that allows the flas h memory contents on a 32-bit general purpose microcontroller to be read, erased, and programmed from of f-chip in a compatible format to many standalone fla[...]

EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 19-2 F re escale Semiconductor Figure 19-1 is a block diagram of the EzPort. Figure 19-1. EzP or t Bloc k Diagram 19.3 External Signal Description 19.3.1 Overview Table 19-1 contains a list of Ez Port external signals. 19.3.2 Detailed Signal Descriptions 19.3.2.1 EZPC[...]

EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 19-3 EZPCK.The maximum frequency of the EzPort clock is half the system clock frequency for all commands except when executing the read da ta command. When executing the Read Data command, the EzPort clock has a maximum frequency of one eight[...]

EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 19-4 F re escale Semiconductor 19.4.1 Command Descriptions 19.4.1.1 Write Enable The W rite Enable command sets the write enable regist er bit in the status regi ster. The write enable bit must be set for a W rite Configurat ion Register (WRCR), Page Program (PP), Sec[...]

EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 19-5 19.4.1.4 Write Configuration Register The W rite Configuration Command updates the flash cont roller ’ s clock configurat ion register. The clock configuration register divides down the flash contro ller ’ s internal system clock to [...]

EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 19-6 F re escale Semiconductor 19.4.1.5 Read Data The Read Data command returns data from the flash memory , starting at the address specified in the command word. Data continues being returned for as long as the EzPort chip select (E Z PCS ) is asserted, with the add[...]

EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 19-7 19.4.1.8 Sector Erase The Sector Erase command erases the contents of a 2-Kb yte space of flash memory. The 3-byte address sent after the command byte can be a ny address within the space to erase. This command should not be used if the [...]

EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 19-8 F re escale Semiconductor 19.6 Initialization/Application Information Prior to issuing any program or eras e commands, the clock configuration register must be written to set the flash state machine clock (FCL K). The flash controller module r uns at the system c[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 20-1 Chapter 20 Pr ogrammable Interrupt Timer s (PIT0–PIT1) 20.1 Intr oduction This chapter describes the opera tion of the two programmable in terrupt timer modules: PIT0–PIT1. 20.1.1 Overview Each PIT is a 16-bit timer that pr ovides precise in[...]

Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 20-2 F re escale Semiconductor NO TE The low-power interrupt control regist er (LPICR) in the system control module specifies the interrupt level at or above which the device can be brought out of a low-power mode. In wait mode, the[...]

Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 20-3 20.2.1 PIT Contr ol and St atus Register (PCSR n ) The PCSR n registers configure the corresponding timer ’ s operation. 2 User mode accesses to super visor only addresses hav e no ef fect and result[...]

Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 20-4 F re escale Semiconductor 20.2.2 PIT Modulus Re gister (PMR n ) The 16-bit read/write PMR n contains the timer modulus value loaded into the PIT counter when the count reaches 0x0000 and the PCSR n [RLD] bit is set . When the P[...]

Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 20-5 20.2.3 PIT Count Register (PCNTR n ) The 16-bit, read-only PCNTR n contains the counter value. Reading the 16-bit counter wi th two 8-bit reads is not guaranteed coherent. W riting to PCNTR n has no ef[...]

Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 20-6 F re escale Semiconductor Figure 20-5. Counter Reloading from the Modulus Latc h 20.3.2 Free-Running Timer Operation This mode of operation is selected when the PCSR n [RLD] bit is clear . In this mode, the counter rolls over f[...]

Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 20-7 The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR.[...]

Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 20-8 F re escale Semiconductor[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-1 Chapter 21 General Purpose Timer Module (GPT) 21.1 Intr oduction This device has one 4-channel gene ral purpose timer module (GP T). It c onsists of a 16-bit counter driven by a 7-stage programmable prescaler . A timer overflow function allows s[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-2 F re escale Semiconductor 21.3 Block Dia gram Figure 21-1. GPT Block Dia gram Prescal er Channel 0 PT0 16-Bit Counter System LOGIC PR[2:0] Divide-by-64 GPTC0H:GPTC0L EDGE DETECT GPTP ACNTH:GPTP A CNTL PA O V F PEDGE PA O V I PA M O D PA[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-3 21.4 Low-P o wer Mode Operation This subsection describes the operation of the ge neral purpose time module in low-power modes and halted mode of operation. Low-pow er modes are described in Chapter 8, “Power[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-4 F re escale Semiconductor 21.5.3 SYNC n The SYNC n pin is for synchronization of th e timer counter . It can be used to synchronize the counter with externally-timed or clocked events. A hi gh signal on this pin clears the counter . 21.[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-5 21.6.1 GPT Input Capture/Out put Compare Select Register (GPTIOS) 0x1A_0017 GPT Channel 3 Register Low (GPTC3L) 2 8 21.6.14/21-13 0x1A_0018 Pulse Accumulator Control Register (GPTP A CTL) 8 R/W 0 x00 21.6.15/21[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-6 F re escale Semiconductor 21.6.2 GPT Compare For ce Register (GPCFORC) NO TE A successful channel 3 output compar e overrides any compare on channels 2:0. For each OC3M bit that is set, the output compare action reflects the correspondi[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-7 21.6.4 GPT Output Compare 3 Data Register (GPT OC3D) NO TE A successful channel 3 output compare overrides any channel 2:0 compares. For each OC3M bit that is set, the output compare action reflects the corresp[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-8 F re escale Semiconductor 21.6.6 GPT System Contr ol Register 1 (GPTSCR1) T able 21-8. GPTCNT Field Descriptions Field Description 15–0 CNTR Read-only field that provides the current count of the timer coun ter . T o ensure coherent r[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-9 Figure 21-8. Fas t Clear Flag Logic 21.6.7 GPT T ogg le-On-Overflow Register (GPTT O V) 21.6.8 GPT Contr ol Register 1 (GPTCTL1) IPSBAR Offset: 0x1A_0008 (GPTT O V) Access: Super vis or read/write 76543210 R 0 [...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-10 F reescale Semiconductor 21.6.9 GPT Contr ol Register 2 (GPTCTL2) 21.6.10 GPT Interrupt Enable Register (GPTIE) T able 21-11. GPTCL1 Field Descriptions Field Description 7–0 OMx/OLx Output mode/o utput le vel. Selects the ou tput act[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-11 21.6.11 GPT System Control Register 2 (GPTSCR2) T able 21-13. GPTIE Field Descriptions Field Description 7–4 Reser v ed, should be cl eared. 3–0 C n l Channel interrup t enable . Enables the C[3:0]F flags [...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-12 F reescale Semiconductor 21.6.12 GPT Flag Register 1 (GPTFLG1) 21.6.13 GPT Flag Register 2 (GPTFLG2) 2–0 PR Prescaler bits. Select the prescaler divisor f or the GPT counter . 000 Prescaler divisor 1 001 Prescaler divisor 2 010 Presc[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-13 Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is se t, an y access to the GPT coun ter registers clears GPT flag register 2. 21.6.14 GPT Channel Registers (GPTC n ) 21.6.15 Pulse Accumulator Co ntrol[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-14 F reescale Semiconductor 21.6.16 Pulse Accum ulator Flag Register (GPTP AFLG) T able 21-18. GPTP A CTL Field Descriptions Field Description 7 Reser ved, should be cleared. 6 PA E Enables the pulse accumulator . 1 Pulse accumulator enab[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-15 NO TE When the fast flag clear all enable bit (GP TSCR1[TFFCA]) is set, any access to the pulse accumulator counter registers clears all the flags in GP TP AFLG . 21.6.17 Pulse Accum ulator Counter Register (G[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-16 F reescale Semiconductor 21.6.18 GPT P or t Data Register (GPTPORT) 21.6.19 GPT P or t Data Di rection Register (GPTDDR) 21.7 Functional Description The general purpose timer (GP T) m odule is a 16-bit, 4-channel time r with input capt[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-17 21.7.1 Prescaler The prescaler divides the module cl ock by 1 or 16. The PR[2:0] bits in GP TSCR2 select the prescaler divisor . 21.7.2 Input Capture Clearing an I/O select bit (IOS n ) configures channel n as[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-18 F reescale Semiconductor 21.7.4 Pulse Accum ulator The pulse accumulator (P A) is a 16-bit counter that can operate in two modes: 1. Event counter mode: counts edge s of selected polarity on the pulse accumulator input pin, P AI 2. Gat[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-19 The P A counter register (GP TP ACNT) reflects the number of pulses from the divide-by-64 clock since the last reset. NO TE The GP T prescaler generates the divi de-by-64 clock. If the timer is not active, the[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-20 F reescale Semiconductor T able 21-23. GPT Settings and Pin Functions GPTEN DDR 1 1 When DDR sets the pin as input (0), reading the data regi ster re turns the state of the pin. When DDR se t the pin as output (1), reading the data reg[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-21 21.8 Reset Reset initializes the GP T registers to a known startup state as described in Section 21.6, “Memory Map and Registers .” 21.9 Interrupts T able 21-24 lists the interrupt reque sts generated by t[...]

General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-22 F reescale Semiconductor 21.9.3 Pulse Accum ulator Input (P AIF) P AIF is set when the selected edge is detected at the P AI pin. In event counter mode, the event edge sets P AIF . In gated time accumulation mode , the trailing edge of[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 22-1 Chapter 22 DMA Timer s (DTIM0–DTIM3) 22.1 Intr oduction This chapter describes the configuration and operation of the four direct memory access (DMA) timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture and[...]

DMA Timers (DTIM0–DTIM3) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 22-2 F re escale Semiconductor Figure 22-1 is a block diagram of one of the four identical timer modules. Figure 22-1. DMA Timer Block Diagr am 22.1.2 Features Each DMA timer module has: • Maximum timeout period of 266,521 seconds at 66 MHz (~74 h[...]

DMA Timer s (DTIM0–DTIM3 ) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 22-3 22.2.1 DMA Timer Mode Regis ters (DTMR n ) DTMRs, shown in Figure 22-2 , program the prescaler and various timer modes. T able 22-1. DMA Timer Module Memory Map IPSB AR Offset Register Width (bits) Access Reset V alu[...]

DMA Timers (DTIM0–DTIM3) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 22-4 F re escale Semiconductor 22.2.2 DMA Timer Extended Mode Registers (DTXMR n ) The DTXMR n register programs DMA request a nd increment modes for the timers. T able 22-2. DTMR n Field Descriptions Field Description 15–8 PS Prescaler value . Th[...]

DMA Timer s (DTIM0–DTIM3 ) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 22-5 22.2.3 DMA Timer Event Registers (DTER n ) DTER n , shown in Figure 22-4 , reports capture or refere nce events by setting DTER n [CAP] or DTER n [REF]. This reporting happens regardless of th e corresponding DMA req[...]

DMA Timers (DTIM0–DTIM3) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 22-6 F re escale Semiconductor 22.2.4 DMA Timer Reference Register s (DTRR n ) Each DTRR n , shown in Figure 22-5 , contains the reference value compared with the respective free-running timer coun ter (DTCN n ) as part of the output-compare functio[...]

DMA Timer s (DTIM0–DTIM3 ) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 22-7 22.2.5 DMA Timer Capture Registers (DTCR n ) Each DTCR n latches the corresponding DTCN n value during a capture operation when an edge occurs on DTIN n , as programmed in DTMR n . The internal bus clock is assu med [...]

DMA Timers (DTIM0–DTIM3) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 22-8 F re escale Semiconductor 22.3 Functional Description 22.3.1 Prescaler The prescaler clock input is selected from the internal bus clock (f sys divided by 1 or 16) or from the corresponding timer input, DTIN n . DTIN n is synchronized to the in[...]

DMA Timer s (DTIM0–DTIM3 ) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 22-9 22.4 Initialization/Application Information The general-purpose timer modules typically , but not necessarily , follow this program order: • The DTMR n and DTXMR n registers are configured for th e desired function[...]

DMA Timers (DTIM0–DTIM3) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 22-10 F reescale Semiconductor move.l #0x0000,D0;writing to the timer counter with any move.l DO,TCN0 ;value resets it to zero move.l #0xAFAF,DO ;set the timer0 refer ence to be move.l #D0,TRR0 ;defined as 0xAFAF The simple example below uses T imer[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-1 Chapter 23 Queued Serial P eripheral Interface (QSPI) 23.1 Intr oduction This chapter describes the queued serial peripheral inte rface (QSPI) module. Afte r the feature set overview is a description of operation including details of the QSPI’[...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-2 F re escale Semiconductor 23.1.2 Overview The queued serial peripheral interface module provides a serial periphe ral interface with queued transfer capability . It allows users to queue up to 16 tran sfers at once, eliminating C[...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-3 23.3 Memory Map/Register Definition T able 23-2 is the QSPI register memory map. Reading reserved locations returns zeros. 23.3.1 QSPI Mode Register (QMR) The QMR, shown in Figure 23-2 , determines the b[...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-4 F re escale Semiconductor T able 23-3. QMR Field Descriptions Field Description 15 MSTR Master mode enable. 0 Reser ved, do not use. 1 The QSPI is in master mode. Must be se t f or the QSPI module to operate correctly . 14 DOHIE [...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-5 Figure 23-3 shows an example of a QSPI clocking and data transfer . Figure 23-3. QSPI Cloc king and Data T ransfer Example 23.3.2 QSPI Dela y Register (QDL YR) The QDL YR is used to initiate master mode [...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-6 F re escale Semiconductor 23.3.3 QSPI Wrap Register (QWR) The QSPI wrap register provides halt transfer control, wraparound settings, and queue pointer locations. 23.3.4 QSPI Interrupt Register (QIR) The QIR contains QSPI interr [...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-7 23.3.5 QSPI Address Register (QAR) The QAR is used to specify the locatio n in the QSPI RAM that read and write ope rations affect. As shown in Section 23.4.1, “QSPI RAM” , the transmit RAM is locate[...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-8 F re escale Semiconductor 23.3.6 QSPI Data Register (QDR) The QDR is used to access QSPI RAM indirectly . The CPU read s and writes all data from and to the QSPI RAM through this register . A write to QDR causes data to be writte[...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-9 NO TE The command RAM is accessed only us ing the most significant byte of QDR and indirect addre ssing based on QAR[ADDR]. 23.4 Functional Description The QSPI uses a dedicated 80-byte block of static R[...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-10 F reescale Semiconductor The RAM is organized so that 1 byte of command cont rol data, 1 word of transmit data, and 1 word of receive data comprise 1 of the 16 queue entries (0x0–0xF). NO TE Throughout ColdFire documentation, [...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-11 23.4.1 QSPI RAM The QSPI contains an 80-byte block of static RAM that can be accesse d by the user and the QSPI. This RAM does not appear in the device memory map, becau se it can only be access ed by t[...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-12 F reescale Semiconductor stored in the least significant bits of the RAM. Unus ed bits in a receive queue entry are set to zero upon completion of the i ndividual queue entry . QWR[CP TQP] shows which queue entrie s have been ex[...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-13 The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following expression: Eqn. 23-1 23.4.3 T ransfer Dela ys The QSPI supports programmable delays for the QSPI_C S s[...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-14 F reescale Semiconductor where QDL YR[DTL] has a range of 1–255. A zero value for DTL causes a delay-af ter-transfer value of 8192/f sys . Standard delay period (DT = 0) is calculated by the following: Eqn. 23-4 Adequate delay[...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-15 QIR[SPIFE] is set. QIR[SPIF ] is not automatically rese t. If interrupt driven QSPI service is used, the service routine must clear QIR[SPIF] to abort the current reques t. Additional interr upt request[...]

Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-16 F reescale Semiconductor[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-1 Chapter 24 U AR T Modules 24.1 Intr oduction This chapter describes the use of the three univers al asynchronous receiver/t ransmitters (UAR T s) and includes programming examples. NOTE The designation n appears throughout this section to refer [...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-2 F re escale Semiconductor NOTE The DTIN n pin can clock UAR T n . However , if the timers are used, input capture mode is not av ailable for that timer . The serial communication channel provides a full-duplex asynchronous/synchronous receiver and transmit[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-3 24.2 External Signal Description T able 24-1 briefly describes th e UAR T module signals. Figure 24-2 shows a signal configuration for a UAR T/RS-232 interface. Figure 24-2. U AR T/RS-232 Interface 24.3 Memory Map/Register Definit[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-4 F re escale Semiconductor T able 2 4-2. U A RT Module Memory Map IPSBAR Offset Register Width (bit) Access Reset V alue Section/Pa ge UA R T 0 UA R T 1 UA R T 2 0x00_0200 0x00_0240 0x00_0280 U ART Mode Registers 1 (UMR1 n ), (UMR2 n ) 1 UMR1 n , UMR2 n , a[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-5 24.3.1 U ART Mode Register s 1 (UMR1 n ) The UMR1 n registers control configuration. UMR1 n can be read or written when the mode register pointer points to it, at RESET or after a RESET MODE REGISTER POINTER command using UCR n [M[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-6 F re escale Semiconductor 24.3.2 U AR T Mode Register 2 (UMR2 n ) The UMR2 n registers control UAR T module configuration. UMR2 n can be read or written when the mode register pointer points to it, wh ich occurs after any access to UMR1 n . UMR2 n accesses[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-7 24.3.3 U ART Status Register s (USR n ) The USR n registers, shown in Figure 24-5 , show the status of the transmit ter , the receiver , and the FIFO. T able 24- 4. UMR2 n Field Descriptions Field Description 7–6 CM Channel mode[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-8 F re escale Semiconductor IPSBAR Offset: 0x00_0204 (USR0) 0x00_0244 (USR1) 0x00_0284 (USR2) Access: User read-only 76543210 R RB FE PE OE TXEMP TXRD Y FFULL RXRD Y W R e s e t : 00000000 Figure 24-5. U ART St atus Register s (USR n ) T able 24-5. USR n Fie[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-9 24.3.4 U AR T Clock Select Register s (UCSR n ) The UCSRs select an external clock on the DTIN input (divided by 1 or 16) or a prescaled internal bus clock as the clocking source for th e transmitter and receiver . See Section 24.[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-10 F reescale Semiconductor T able 24-7 describes UCR n fields and commands. Examples in Section 24.4.2, “T ransmitter and Receiver Operating Modes ,” show how these commands are used. IPSBAR Offset: 0x00_0208 (UCR 0) 0x00_0248 (UCR 1) 0x00_0288 (UCR 2) [...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-11 24.3.6 U ART Receive Buff ers (URB n ) The receive buffers (shown in Figure 24-8 ) contain one serial shift regi ster and three receiver holding registers, which act as a FIFO. URXD n is connected to the serial shif t register . [...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-12 F reescale Semiconductor 24.3.7 U AR T T ransmit Buffers (UTB n ) The transmit buffers consist of th e transmitter holding register and th e transmitter shift register . The holding register accepts characters fr om the bus master if UAR T’ s USR n [TXR[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-13 24.3.9 U AR T A uxiliary Control Register (U A CR n ) The UACRs control the input enable. 24.3.10 U ART Interrupt Status/Mask Register s (UISR n /UIMR n ) The UISRs, shown in Figure 24-12 , provide status for all pote ntial inter[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-14 F reescale Semiconductor NOTE T rue status is pr ov ided in the UISR n regardless of UIMR n settings. UISR n is cleared when the UAR T module is reset. IPSBAR Offset: 0x00_0214 (UISR0) 0x00_0254 (UISR1) 0x00_0294 (UISR2) Access: User read/write 76543210 R[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-15 24.3.11 U ART Baud Rate Ge nerator Register s (UBG1 n /UBG2 n ) The UBG1 n registers hold the MSB, and the UBG2 n registers hold the LSB of the preload value. UBG1 n and UBG2 n concatenate to provide a divider to the inte rnal bu[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-16 F reescale Semiconductor 24.3.13 U ART Output P or t Command Registers (UOP1 n /UOP0 n ) The UR TS n output can be asserted by writing a 1 to UOP1 n [R TS] and negated by writing a 1 to UOP0 n [R TS]. See Figure 24-16 . 24.4 Functional Description This se[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-17 24.4.1.1 Pr ogrammable Divider As Figure 24-17 shows, the UAR T n transmitter and receiver can us e the following clock sources: • An external clock signal on the DTIN n pin. When not divided, DTIN n provides a synchronous cloc[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-18 F reescale Semiconductor Using a 66-MHz internal bus clock and letting baud rate equal 9600, then Eqn. 24-2 Therefore, UBG1 n equals 0x00 and UBG2 n equals 0xD6. 24.4.1.2.2 External Cloc k An external source clock (DTIN n ) passes through a divide-by- 1 o[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-19 optional parity bit, and the programmed number of st op bits. The lsb is sent first. Data is shifted from the transmitter output on the falling edge of the clock source. After the stop bits are sent, if no new character is in the[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-20 F reescale Semiconductor Figure 24-19. T ransmitter Timin g Diagram 24.4.2.2 Receiver The receiver is enabled through its UCR n , as described in Section 24.3.5, “UAR T Command Registers (UCRn) .” When the receiver detects a hi gh-to-low (mark-to-spac[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-21 framing error , overrun error, and received break conditions set the respective PE, FE, OE, and RB error and break flags in the USR n at the received character bounda ry . They are valid only if USR n [RXRDY] is set. If a break c[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-22 F reescale Semiconductor programming the ERR bit in the UAR T’ s mode re gister (U MR1 n ), status is provided in character or block modes. USR n [RXRDY] is set when at least one character is availa ble to be read by the CPU. A read of the recei ve buff[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-23 24.4.3.1 A utomatic Echo Mode In automatic echo mode, shown in Figure 24-21 , the UAR T automatically rese nds received data bit by bit. The local CPU-to-receiver communi cation continues normally , but th e CPU-to-transmitter li[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-24 F reescale Semiconductor Figure 24-2 3. Remote Loopbac k 24.4.4 Multidrop Mode Setting UMR1 n [PM] programs the UAR T to ope rate in a wake-up mode for multidrop or multiprocessor applications. In this mode, a mast er can transmit an address charac ter fo[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-25 Figure 24-24. Mult idrop Mode Timing Diagr am A character sent from the master st ation consists of a start bit, a programmed number of data bits, an address/data (A/D) bit flag, and a programmed number of stop bits. A/D equals 1[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-26 F reescale Semiconductor 24.4.5 Bus Operation This section describes bus operati on during read, write, and interrupt acknowledge cycles to the UAR T module. 24.4.5.1 Read Cyc les The UAR T module responds to reads with byte data. Reserved registers retur[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-27 3. Unmask appropriate bits in the core’ s st atus register (SR) to enable interrupts. 4. If TXRDY or RXRDY generates interrupt requests, verify that DMAREQC (in th e SCM) does not also assign the UAR T’ s TXRDY and RXRDY into[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-28 F reescale Semiconductor T o configure the UAR T for DMA requests: 1. Initialize the DMAREQC in the SCM to map th e desired UAR T DMA requests to the desired DMA channels. For example, setting DMAREQC[7:4] to 1000 maps UAR T0 re ceive DMA requests to DMA [...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-29 b) If preferred, program operation of transmitter ready-to-send (TXR TS). c) If preferred, program operation of clear-to-send (TXCTS bit). d) Select stop-bit length (SB bits). 7. UCR n : Enable transmitter and/or receiver . Figur[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-30 F reescale Semiconductor Figure 24-25. U ART Mode Pr ogramming Flowc har t (Sheet 2 of 5) CHCHK CHCHK Place Channel In Local Loopback Mode Enable T ransmitter Clear Status Word TxCHK Is T ransmitter Ready? Y N SNDCHR RxCHK Send Character T o T ransmitter [...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-31 Figure 24-25. U ART Mode Pr ogramming Flowc har t (Sheet 3 of 5) A B B FRCHK Hav e F raming Error? Set F raming Error Flag PRCHK Hav e P arity Error? Set P arity Error Flag Get Character F rom Receiver Same As T ransmitted Charac[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-32 F reescale Semiconductor Figure 24-25. U ART Mode Pr ogramming Flowc har t (Sheet 4 of 5) Wa s IRQ Caused By Beginning Of A Break? SIRQ ABRKI N Clear Change-in- Break Status Bit ABRKI1 N Has End-of-break IRQ Arrived Ye t ? Y Y Clear Change-in- Break Statu[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-33 Figure 24-25. U ART Mode Pr ogramming Flowc har t (Sheet 5 of 5) OUTCH Is T ransmitter Ready? N Y Send Character T o T ransmitter Return[...]

U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-34 F reescale Semiconductor[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-1 Chapter 25 I 2 C Interface 25.1 Intr oduction This chapter describes the I 2 C module, clock synchronization, and I 2 C programming model registers. It also provides extensiv e programming examples. NO TE The MCF5221 1 contains two I 2 C modules[...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-2 F re escale Semiconductor 25.1.1 Block Diagram Figure 25-1 is a block diagram of the I 2 C module. Figure 25-1. I 2 C Module Bloc k Diagram Figure 25-1 shows the I 2 C registers, described in Section 25.2, “Memory Map/ Register Definition” : •I 2 C [...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-3 The interface operates up to 100 Kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of the internal bus cloc k divided by 20, with reduced bus loading. The maximum c[...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-4 F re escale Semiconductor 25.2.1 I 2 C Address Register s (I2ADR n ) The I2ADR n hold the address the I 2 C responds to when addressed as a sl ave. It is not the address sent on the bus during the address transfer when th e module is performing a master t[...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-5 25.2.3 I 2 C Contr ol Registers (I2CR n ) The I2CR n enable the I 2 C modules and the I 2 C interrupts. They also contai n bits that govern operation as a slave or a master . IPSBAR Offset: 0x0304 (I2FDR0) 0x0384 (I2FDR1) Access:[...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-6 F re escale Semiconductor IPSBAR Offset: 0x0308 (I2CR0) 0x0388 (I2CR1) Access: User read/write 76543210 R IEN IIEN MST A MTX TXAK RST A 0 0 W R e s e t : 00000000 Figure 25-4. I2CR n Regi sters T able 25-4. I2 CR n Field Descriptions Field Description 7 I[...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-7 25.2.4 I 2 C Status Registers (I2SR n ) The I2SR n contain bits that indicate tr ansaction direction and status. IPSBAR Offset: 0x030C (I2SR0) 0x038C (I2SR1) Access: User read/write 76543210 R ICF IAAS IBB IAL 0 SR W IIF RXAK W R[...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-8 F re escale Semiconductor 25.2.5 I 2 C Data I/O Register s (I2DR n ) In master -receive mode, reading the I2DR n s allows a read to occur and for the next data byte to be received. In slave mode, the same function is available after the I 2 C has received[...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-9 Figure 25-7. I 2 C St andard Comm unication Pr otocol 25.3.2 Sla ve Address T ransmission The master sends the slave address in the first byte after the ST AR T signa l ( B). After the seven-bit calling address, it sends the R/W [...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-10 F reescale Semiconductor 25.3.4 Ac knowledge The transmitter releases the SDA line high during the acknowle dge clock pulse as shown in Figure 25-9 . The receiver pulls down the SDA line during the acknowledge clock pulse so that it remains stable low du[...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-11 Figure 25 -10. Repeat ed ST ART V arious combinations of read/w rite formats are then possible: • The first example in Figure 25-1 1 is the case of master -transmitter transmitting to slave-receiver . The transfer directi on i[...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-12 F reescale Semiconductor 25.3.7 Cloc k Synchr onization and Arbitration I 2 C is a true multi-master bus that allows more than one ma ster connected to it. If two or more master devices simultaneously request control of the bus, a clock synchronization p[...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-13 25.3.8 Handshaking and Cloc k Stretching The clock synchronization m echanism can acts as a handshake in da ta transfers. Slave devices can hold SCL low after completing one byte transfer. In such a case, the clock mechanism hal[...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-14 F reescale Semiconductor may need to wait until the I2C is busy after writing the calli ng address to the I2DR before proceeding with the following instructions. The following example signals ST AR T and transm its the first byte of da ta (slave address)[...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-15 For a master receiver to terminate a data transf er , it must inform the sl ave transmitter by not acknowledging the last data byte. This is done by set ting I2CR[TXAK] before re ading the next-to-last byte. Before the last byte[...]

I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-16 F reescale Semiconductor Figure 25-14. Flow-Chart of T ypical I 2 C Interrupt Routine Clear Master Mode? TX/Rx ? Last Byte T ransmitted ? RXAK= 0 ? End of ADDR Cycle (Master RX) ? Write Next Byte to I2DR Switch t o Rx Mode Dummy Read from I2DR Generate S[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-1 Chapter 26 Analog-to-Digital Con verter (ADC) 26.1 Intr oduction The analog-to-digital converter (ADC) consists of tw o separate and complete ADCs, each with their own sample and hold circuits. The converters share a co mmon voltage reference a [...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-2 F re escale Semiconductor 26.3 Block Dia gram The ADC function, shown in Figure 26-1 , consists of two four-channel i nput select functio ns, interfacing with two independent Samp le and Hold (S/H) circui ts, which feed two 12-bit ADC[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-3 26.4.1 Contr ol 1 Register (CTRL1) The CTRL1 register , shown in Figure 26-2 , is used to configure and control the ADC module. The associated field descri ptions are given in T able 26-2 . Please see Section 26[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-4 F re escale Semiconductor 12 SYNC0 Synchronization 0 Enable bit. When this bit is set, a co nv ersion may be initiated by asser ting a positive edge on the SYNC0 input. Any subsequent SYNC0 input pulses that occur dur ing the scan are[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-5 26.4.2 Contr ol 2 Register (CTRL2) The structure of the CTRL2 register depends on whether the ADC is operating in sequential or parallel mode (see Section 26.4.1, “Control 1 Register (CTRL1) ”). 26.4.2.1 CTR[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-6 F re escale Semiconductor 26.4.2.2 CTRL2 Under P arallel Scan Modes When the ADC operates in a parallel scan mode, the CTRL2 register is used to control the operation of converter B. The interaction betw een converters A and B (and he[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-7 12 SYNC1 Synchronization 1 Enable bit. In parallel-scan modes when SIMUL T equaling 0, setti ng SYNC1 allows a conv ersion to b e initiated by asser ting a positive edge on the SYNC1 input. Any subsequen t SYNC1[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-8 F re escale Semiconductor 26.4.3 Zer o Crossing Co ntr ol Register (ADZCC) The ADC zero crossing control (ADZCC ) register provides the ability to monitor the sele cted channels and determine the direction of zero crossing triggering [...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-9 SAMPLE4-7 should only contain binary values between 100 and 1 1 1. No dama ge occurs if this constraint is violated, but results are undefined. When inputs are configured as differ ential pairs, a reference to e[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-10 F reescale Semiconductor 26.4.5 Sample Disable Re gister (ADSDIS) This register is an exte nsion to the ADLST1and ADLST2, providing the ability to enab le only the desired samples programmed in the SAMPLE0–S AMPLE7. At reset, all s[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-11 26.4.6 Status Re gister (ADST A T) This register provides the curren t status of the ADC module. RDY n bits are cleared by reading their corresponding result (ADRSL T n ) registers. The HLMTI and LLMTI bi ts ar[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-12 F reescale Semiconductor T able 26-11. ADST A T Field Descriptions Field Description 15 CIP0 Conv ersion in Progress 0 bit. This bit indicates whe n a scan is in progress. This bit suppor ts any sequential scan or parallel scan with [...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-13 26.4.7 Limit Status Regis ter (ADLST A T) The ADC limit status (ADLST A T) register latches in th e result of the comparison between the result of the sample in the ADRSL T n register and the respective limit r[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-14 F reescale Semiconductor 26.4.8 Zer o Crossing Stat us Register (ADZCST A T) The ADC zero crossing status (ADZCST A T) register latches in the result of a sign comparison between the current and previous sample. The type of comp aris[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-15 Negative results (SEXT = 1) are alwa ys presented in twos-complement fo rmat. If an application requires that the result be always positive, the corresponding of fset register (ADOFS n) must be set to 0x0. The [...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-16 F reescale Semiconductor IPSBAR Offsets: 0x19_0022 (ADLLMT0) o x19_0024 (ADLLMT1) 0x19_0026 (ADLLMT2) 0x19_0028 (ADLLMT3) 0x19_002A (ADLLMT4) 0x19_002C (ADLLMT5) 0x19_002E (ADLLMT6) 0x19_0030 (ADLLMT7) Access: read/wr ite 1 5 1 4 1 3[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-17 26.4.11 Offset Registers (ADOFS n ) The values in the of fs et regis ters (ADOFS n ) are subtracted from the raw ADC values, and the results are stored in the ADRSL T n registers. T o obtain unsigned results, t[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-18 F reescale Semiconductor 5. Current mode • Normal current mode is used to power the converters at cloc k rates above 100 kHz. • S tandby current mode uses less power and is engaged only when the ADC clock is at 100 kHz. The curre[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-19 10 PSTS0 Conv er ter A P ower Status bit. This bit is asser ted i mmediately after PD0 is set. It is deasser ted PUDELA Y ADC clock cycles after PD0 is c leared if APD is 0. This bit can be read as a status bit[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-20 F reescale Semiconductor 26.4.13 V oltage Reference Re gister (CAL) In earlier series, this register supported ADC calibration and had a di fferent name. Improvements in ADC performance have eliminated the need for on-ch ip calibrati[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-21 26.5 Functional Description The ADC’ s conversion process is in itiated by a sync signal from one of two input pins (SYNCx) or by writing 1 to a ST AR T n bit. S tarting a single conversion actually begins a [...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-22 F reescale Semiconductor Parallel scan can be simultaneous or non-simultaneous. Duri ng simultaneous scan, the scans in the two converters are done simultaneously and always result in simultane ous pairs of conversions, one by conver[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-23 Optional interrupts can be generated at the end of a scan sequence. Interrupts are available simp ly to indicate the scan ended, that a sa mple was out of range, or at seve ral dif ferent zero crossing conditio[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-24 F reescale Semiconductor Figure 26-20. Input Select Mux P arallel, Single Ended The two 1-of-4 select muxes can be set f or the appropr iate input line. The low er switch selects V REFL for t h e V - input of the A/D . The upp er s w[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-25 26.5.2 ADC Sample Con version The ADC consists of a cyclic, algor ithmic architecture using two recu rsive sub-ranging sections (RSD#1 and RSD#2), shown in Figure 26-21 . Each sub-ranging section resolves a sin[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-26 F reescale Semiconductor 26.5.2.1 Single- Ended Samples The ADC module performs a ratio metric conversion. For single ended measurements, the digital result is proportional to the ratio of the analog input to the reference voltage in[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-27 Figure 26-22. T ypical Connections f or Differen tial Measurements 26.5.3 ADC Data Pr ocessing As shown in Figure 26-23 , the raw result of the ADC conversion proc ess is sent to an adder for offset correction.[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-28 F reescale Semiconductor Figure 26-2 3. Result Register Dat a Manipulation 26.5.4 Sequential vs. P arallel Sampling All scan modes make use of the 8 SAMPLE slots in the ADLST1 and AD LST2 registers. These slots are used to define whi[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-29 bit is 1, when the SYNC0 i nput goes high. A scan ends when the first disabled sample slot is encountered in the SDIS register . Completion of the scan triggers the EOSI0 interrupt if the interrupt is enabled b[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-30 F reescale Semiconductor completion of the previous scan. In loop parallel scan modes, both converter s restart together if SIMUL T equals 1 and restart independe ntly if SIMUL T equals 0. All subse quent start and sync pulses are ig[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-31 T able 26-21. ADC Scan Modes Scan Mode Description Once sequential Upon ST ART or an enab led sync signal, sample s are taken one at a time star ting with SAMPLE0 until a first disa bled sample is encountered. [...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-32 F reescale Semiconductor 26.5.7 Interrupt Sour ces Figure 26-24 illustrates how five interrupt sources are combined into three entries in the interrupt vector table. Figure 26-24. ADC Interrupt Sour ces 26.5.8 P ower Management The f[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-33 PUDELA Y ADC clock cycles execute at the start of all scans while th e ADC engages the conversion clock and the ADC powers up, stabil izing in the standby current mode. This provides the lowest possible power c[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-34 F reescale Semiconductor When starting up in normal mode, fi rst set PUDELA Y to the lar ge power-up value. Next, clear the PD0 and or PD1 bits to power - up the required converters. Po ll the status bits (PSTS n in the POWER registe[...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-35 26.5.9.2 Description of Clock Operation As shown in Figure 26-25 , the conversion clock is the primary s ource for the ADC clock and is always selected as the ADC clock when conversions are in process. The DIV [...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-36 F reescale Semiconductor standby power mode requires an 8 MHz oscillator clock from th e relaxation oscillator , crystal oscillator , or external oscillator . 26.5.9.3 ADC Cloc k Resynchronization at Start of Scan At the fastest ADC [...]

Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-37 Figure 26-27. ADC Cloc k Resynchr onization f or Non-Sim ultaneous Pa rallel Modes 26.5.10 V oltage Reference Pins V REFH and V REFL The voltage difference between V REFH and V REFL provides the reference volta[...]

Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-38 F reescale Semiconductor V REFH is as noise-free as possibl e. Any noise residing on the V REFH voltage is directly transferred to the digital result. Figure 26-28 illustrates the internal workings of the ADC voltage ref erence circu[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-1 Chapter 27 Pulse-Width Modulation (PWM) Module 27.1 Intr oduction This chapter describes the configuration and operati on of the pulse-width modul ation (PWM) module. It includes a block diagram, programming model, and functional description. 27[...]

Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-2 F re escale Semiconductor Main features include the following: • Double-buffered period and duty cycle • Left- or center -aligned outputs • Eight independent PWM modules • Byte-wide registers provide program mable duty cycle an[...]

Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-3 27.2.1 PWM Enable Register (PWME) Each PWM channel has an enable bit (PWME n ) to start its waveform output. While in run mode, if all eight PWM output channels are disa bled (PWME[7:0] = 0), the prescal er c[...]

Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-4 F re escale Semiconductor 27.2.2 PWM P olarity Register (PWMPOL) The starting polarity of each PWM channel waveform is determined by the associated PWMPOL[PPOL n ] bit. If the polarity is changed wh ile a PWM signal is being generated,[...]

Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-5 27.2.4 PWM Prescale Cloc k Select Register (PWMPRCLK) The PWMPRCLK register selects the prescale clock source fo r clocks A and B indepe ndently . If the clock prescale is changed while a PWM si gnal is being[...]

Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-6 F re escale Semiconductor 27.2.5 PWM Center Align En able Register (PWMCAE) The PWMCAE register contains eight control bits for the selection of center -aligned outputs or left-aligned outputs for each PWM channel. W rite these bits on[...]

Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-7 27.2.6 PWM Contr ol Register (PWMCTL) The PWMCTL register provides various control of the PWM module. Change the CON n(n+1) bits only when both corresponding channels are disabled. See Section 27.3.2.7, “PW[...]

Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-8 F re escale Semiconductor 27.2.7 PWM Scale A Register (PWMSCLA) PWMSCLA is the programmable scale value used in sc aling clock A to generate clock SA. Clock SA is generated with the following equation: Eqn. 27-1 Any value written to th[...]

Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-9 27.2.8 PWM Scale B Register (PWMSCLB) PWMSCLB is the programmable scale value used in sc aling clock B to generate clock SB. Clock SB is generated according to the following equation: Eqn. 27-2 Any value writ[...]

Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-10 F reescale Semiconductor (PWME n =0), the PWMCNT n register does not count. When a channel is enabled (PWME n =1), the associated PWM counter starts at the count in the PWMCNT n register . For more detailed information on the operatio[...]

Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-11 27.2.11 PWM Channel Duty Registers (PWMDTY n ) The PWM duty registers determine the duty cycle of the associated PWM channel. T o calculate the output duty cycle (high time as a percentage of period) for a p[...]

Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-12 F reescale Semiconductor 27.2.12 PWM Shutdown Register (PWMSDN) The PWM shutdown register provi des emergency shutdown functiona lity of the PW M module. The PWMSDN[7:1] bits are ignored if PWMSDN[SDNEN] is cleared. T able 27-12. PWMD[...]

Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-13 27.3 Functional Description 27.3.1 PWM Clock Select There are four available clocks—clock A, B, SA (s caled A), and SB (s caled B) —all based on the internal bus clock. Clock A and B can be programmed to[...]

Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-14 F reescale Semiconductor Figure 27-1 4. PWM Clock Select Bloc k Diagram 27.3.1.1 Prescaled Cloc k (A or B) The internal bus clock is the input cl ock to the PWM prescaler that can be disabled when the device is in debug mode by settin[...]

Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-15 27.3.1.2 Scaled Cloc k (SA or SB) The scaled A (SA) and scaled B (SB) clocks use clock A and B respectively as inputs, divide it further with a user programmable value, then di vide this by 2. The rates avai[...]

Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-16 F reescale Semiconductor Figure 27-15. PWM Timer Channel Bloc k Diagram 27.3.2.1 PWM Enable Each PWM channel has an enable bit (PWME n ) to start its waveform output. When any of the PWME n bits are set (PWME n =1), the associated PWM[...]

Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-17 and/or period values to be latched. In addition, because the co unter is readable, it is possible to know where the count is with respect to th e duty value, and software can be used to make adjustments . Wh[...]

Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-18 F reescale Semiconductor 27.3.2.5 Left-Aligned Outputs The PWM timer provides the choice of two types of outputs: le ft- or center -aligned. Th ey are select ed with the PWMCAE[CAE n ] bits. If the CAE n bit is cleared, the correspond[...]

Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-19 Figure 27-17. PWM Left-Aligned Out put Example W avef orm 27.3.2.6 Center -Aligned Outputs For center-aligned output mode selection, set the PWMCAE[CAE n ] bit and the corresponding PWM output is center -ali[...]

Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-20 F reescale Semiconductor Eqn. 27-10 27.3.2.6.1 Center-Aligned Output Example As an example of a center -aligned output, consider the following case: Clock source = internal bus clock, wher e internal bus clock = 40 MHz (25 ns period) [...]

Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-21 Figure 27-20. PWM 1 6-Bit Mode Left- or center -aligned out put mode can be used in concatenated mode and is controlled by the low order CAE n bit. The high order CAE n bit has no effect. The table shown bel[...]

Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-22 F reescale Semiconductor T able 27-16. PWM Boundary Cases PWMDTY n PWMPER n PPOL n PWM n Output 0x00 (indicates no duty) >0x00 1 Alwa ys Low 0x00 (indicates no duty) >0x00 0 Alwa ys High XX 0x00 1 (indicates no per iod) 1 Counte[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-1 Chapter 28 Deb ug Module 28.1 Intr oduction This chapter describes the revision B+ enhanced hardware debug module. 28.1.1 Block Diagram The debug module is shown in Figure 28-1 . Figure 28-1. Pr ocessor/Debug Modu le Interface 28.1.2 Overview De[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-2 F re escale Semiconductor The first version 2 ColdFire core devices implemented the original de bug architecture, now called revision A. Based on feedback from custom ers and third-party developers, e nhancements have been added to succeeding generations of[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-3 28.3 Real-Time T race Support Real-time trace, which defines the dynamic execution pa th and is also known as instruction trace, is a fundamental debug function. The ColdFi re solution is to include a para llel output port providing[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-4 F re escale Semiconductor Execution speed is affected only when both storage elements contain valid data to be dumped to the DDA T A port. The core stalls until one FIFO entry is available. T able 28-3 shows the encoding of these signals. T able 28-3. Pro c[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-5 28.3.1 Begin Execution of T aken Branch (PST = 0x5) PST is 0x5 when a taken branch is executed. For some opcodes, a branch tar get address may be displayed on DDA T A depending on the CSR settings. CSR also c ontrols the number of a[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-6 F re escale Semiconductor 28.4 Memory Map/Register Definition In addition to the existing BDM comm ands that provide access to the pr ocessor ’ s registers and the memory subsystem, the debug module contain a number of registers to support the required fu[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-7 NO TE Debug control registers can be written by the external development system or the CPU through the WDEBUG instru ction. These control registers are write-only from the programming model and they can be written through the BDM po[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-8 F re escale Semiconductor DRc[4:0]: 0x00 (CSR) Access: Super visor write-only BDM read/write 31 30 29 28 27 2 6 25 24 23 22 21 20 19 18 17 16 R BST A T FOF TRG HAL T BKPT HRL 0 0 PCD IPW W R e s e t 00000 00010 01 0 0 0 0 15 14 13 12 11 1 0 9 8 7 6 5 4 3 2 [...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-9 15 MAP F orce processor references in emulator mode. 0 Al l emulator-mode ref erences are mapped into super visor code and data spaces. 1 The processor maps all references while in emul ator mode to a special address space, TT equal[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-10 F reescale Semiconductor 28.4.3 BDM Address Attrib ute Register (B AAR) The BAAR register defines the address space fo r memory-referencing BDM commands. BAAR[R, SZ] are loaded directly from the BDM command, while th e low-order 5 bits can be programmed fr[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-11 setting of the trigger definition re gister (TDR). AA TR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and through the BDM port using the WDMREG command. DRc[4:0]: 0x06 (AA TR) Access:[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-12 F reescale Semiconductor 28.4.5 T rig ge r Definition Register (TDR) The TDR configures the operation of the hard ware breakpoint logic corresponding with the ABHR/ABLR/AA TR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the debug module. TDR con[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-13 DRc[4:0]: 0x07 (TD R) Access: Super visor write-only BDM write -only Second Lev el T rigge r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W TRC L2EBL L2ED L2DI L2EA L2EPC L2PCI R e s e t 0 00 00 0 0 00 0 0 00 0 0 0 First Lev e[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-14 F reescale Semiconductor 20–18 L2EA Enable Le vel 2 Address Breakpoint. Setting an L2EA bit enables the corresponding address breakpoint. Clear ing all three bits disables the breakpoint. 17 L2EPC Enable Le vel 2 Pc Breakpoint. 0 Disable PC breakpoint 1 [...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-15 28.4.6 Pr ogram Counter Breakpoint /Mask Registers (PBR0–3, PBMR) The PBR n registers define an instruction address for use as part of the trigger . These registers’ contents are compared with the processor ’ s program counte[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-16 F reescale Semiconductor contents of the breakpoint registers are compared with the processo r ’ s program counter register when TDR is configured appropriately . The PC breakpoint registers are accessible in supe rvisor mode using the WDEBUG instruction[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-17 28.4.7 Ad dress Breakpoint Regis ters (ABLR, ABHR) The ABLR and ABHR define regions in the processor ’ s data address space that can act as part of the trigger . These register values are compared with the address for each tr ans[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-18 F reescale Semiconductor 28.4.8 Data Breakpoint and Mask Register s (DBR, DBMR) The data breakpoint register (DBR), specify data patterns used as part of the trigger in to debug mode. DBR bits are masked by setting correspond ing DBMR bits, as defined in T[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-19 28.5 Backgr ound Debug Mode (BDM) The ColdFire family implements a low-level system debugger in th e microprocessor in a dedicated hardware module. Communication with the development system is managed through a dedicated, high-spee[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-20 F reescale Semiconductor 3. The execution of a HAL T instruction immediately suspends execution. Attempting to execute HAL T in user mode while CSR[UHE] is cleared generates a privilege violation exception. If CSR[UHE] is set, HAL T can be executed in user[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-21 Figure 28-13 . Maximum BDM Serial Interf ace Timing DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled, along with DSI, on the rising edge of PSTCLK. DSO is de layed from the DSCLK-enab led PS[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-22 F reescale Semiconductor 28.5.2.2 Transmit P acket Format The basic transmit packet consists of 16 data bits and 1 reserved bit. 28.5.3 BDM Command Set T able 28-20 summarizes the BDM command set. Subsequent paragraphs contain detailed descriptions of each[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-23 Freescale reserves unassigned comm and opcodes. All unused command fo rmats within any revision level perform a NOP and return the illegal command respo nse . T able 28-20. BDM Command Summary Command Mnemonic Description CPU State[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-24 F reescale Semiconductor 28.5.3.1 ColdFire BDM Command Format All ColdFire family BDM commands include a 16-bit operation word followed by an optional set of one or more extension words. 28.5.3.1.1 Extension W ords as Required Some commands require extensi[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-25 28.5.3.2 Command Sequence Diagrams The command sequence diagram in Figure 28-17 shows serial bus traf fic for commands. Each bubble represents a 17-bit bus transfer . The top half of each bubble indicates the data the development s[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-26 F reescale Semiconductor • Results are returned in the two serial transfer cycles after the memory access completes. For any command performing a byte-sized memory read opera tion, the upper 8 bits of the response data are undefined and the referenced da[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-27 28.5.3.3.2 Write A/D Register ( WAREG / WDREG ) The operand longword data is written to the specified addr ess or data register . A wr ite alters all 32 register bits. A bus error response is returned if the CPU core is not halted.[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-28 F reescale Semiconductor Command/Result Formats: Command Sequence: Figure 28-23. READ Command Sequence Operand Data: The only operand is the longw ord address of the requested location. Result Data: W ord results return 16 bits of data; l ongword results r[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-29 28.5.3.3.4 Write Me mory Location ( WRITE ) W rite data to the memory location specified by the longword address. BAAR [TT ,TM] defines address space. Hardware forces low-order address bits to 0s for word and longword accesses to e[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-30 F reescale Semiconductor Command Sequence: Figure 28-25. WRITE Command Sequen ce Operand Data: This two-operand inst ruction requires a longword abso lute address that specifies a location the data operand is written. Byte data is sent as a 16-bit word, ju[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-31 NO TE DUMP does not check for a valid address; it is a valid command only when preceded by NOP , READ , or another DUMP command. Otherwise, an illegal command response is returned. NOP can be used for intercommand padding without c[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-32 F reescale Semiconductor Result Data: Requested data is returned as a wo rd or longword. Byte data is returned in the least-significant byte of a wo rd result. W ord results return 16 bits of significant data; longword results return 32 bits. A valu e of 0[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-33 Command Sequence: Figure 28-29. FIL L Command Sequence Operand Data: A single opera nd is data to be writte n to the memory location. Byte data is sent as a 16-bit word, justified in the least-si gnificant byte; 16- and 32-bit oper[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-34 F reescale Semiconductor Operand Data: None Result Data: The command-complete response ( 0xFFFF) is returned during the next shift operation. 28.5.3.3.8 No Operation ( NOP ) NOP performs no operation and may be us ed as a null command where required. Comma[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-35 Command Sequence: Figure 28-35. SYNC _ PC Command Sequence Operand Data: None Result Data: Command complete status (0xFFFF) is returned when the register write is complete. 28.5.3.3.10 Read Co ntrol Register ( RCRE G ) Read the sel[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-36 F reescale Semiconductor Command Sequence: Figure 28-37. RCREG Command Sequence Operand Data: The only operand is the 32-bi t Rc control register select field. Result Data: Control regist er contents are returned as a l ongword, most-significant word first[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-37 else A7 = User Stack Pointer OTHER_A7 = Supervisor Stack Point er The BDM programming model supports reads and writes to A7 and OTHER_A7 directly . It is the responsibility of the external deve lopment system to determine the ma pp[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-38 F reescale Semiconductor 28.5.3.3.13 Read Deb ug Module Register ( RD MR E G ) Read the selected de bug module register and return the 32-bit result. The only va lid register selection for the RDMREG command is CSR (DRc = 0x00). This read of the CSR clears[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-39 Command Format: T able 28-4 shows the definition of the DRc write encoding. Command Sequence: Figure 28-43. WDMREG Command Sequence Operand Data: Longword data is written into the specified debug register . The data is supplied mos[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-40 F reescale Semiconductor The breakpoint status is also posted in the CSR. CS R[BST A T] is cleared by a CSR read when a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoi nt is not enabled. Status is also cleared by[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-41 When debug interrupt operati ons complete, the R TE instruction execut es and the processor exits emulator mode. After the debug interrupt handler completes ex ecution, the external development system can use BDM commands to read t[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-42 F reescale Semiconductor NO TE Breakpoint registers must be carefully configured in a de velopment system if the processor is executing. The debug module contains no hardware interlocks, so TDR should be disabled while breakpoi nt registers are loaded, aft[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-43 T able 28-25. PST/DD A T A Specificat ion for User -Mode Instructions Instruction Opera nd Syntax PST/DD A T A add.l <ea>y ,Dx PST = 0x1, {PST = 0xB, DD = source operand} add.l Dy ,<ea> x PST = 0x1, {PST = 0xB, DD = sou[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-44 F reescale Semiconductor divu.w <ea>y ,Dx PST = 0x1, {PST = 0x9, DD = source operand} eor .l Dy ,< ea>x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} eori.l #<data>,Dx PST = 0x1 e xt.l Dx PST = 0x1 e xt.w Dx PST = 0x1[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-45 or .l Dy ,<ea>x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB , DD = destination} ori.l #<data>,Dx PST = 0x1 pea.l <ea>y PST = 0x1, {PST = 0xB, DD = destination operand} pulse PST = 0x4 rems.l <ea>y ,Dw:Dx[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-46 F reescale Semiconductor T able 28-26 shows the PST/DDA T A specification fo r multiply-accumulat e instructions. 1 During nor mal exception processing, the PST output is driven to a 0xC indicating the e xception pr ocessing state. The exception stack writ[...]

Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-47 28.7.2 Supervisor Instruction Set The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown below . The PST/DDA T A specificati on for these opcodes is shown in T able 28-27 . The move-[...]

Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-48 F reescale Semiconductor Figure 28-44. Recommended BDM Connector 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 Dev eloper reser ved 1 GND GND RESET EVDD 2 GND F reescale reserved GND IVDD BKPT DSCLK Dev eloper reser ved 1 DSI DSO GND[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 29-1 Chapter 29 IEEE 1149.1 T est Access P or t (JT A G) 29.1 Intr oduction The Joint T est Action Group (JT AG) is a dedicated user -accessible test logic compliant with the IEEE 1 149.1 standard for boundary-scan testability , which helps with syst[...]

IEEE 1149.1 T est Acc ess P ort (JT AG) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 29-2 F re escale Semiconductor 29.1.2 Features The basic features of the JT AG module are the following: • Performs boundary-scan operations to te st circuit board electrical continuity • Bypasses instruction to reduce the sh ift re[...]

IEEE 1149.1 T est Access Port (JT A G) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 29-3 When one module is selected, the inputs into the ot her module are disabled or forced to a known logic level, as shown in T able 29-3 , to disable the corresponding module. NO TE The JT AG_EN does not suppo[...]

IEEE 1149.1 T est Acc ess P ort (JT AG) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 29-4 F re escale Semiconductor 29.2.5 T est Reset/Development Serial Cloc k (TRST /D SCLK) The TRST pin is an active low asynchronous reset input with an internal pull-up resistor that forces the T AP controller to the test-logic-reset [...]

IEEE 1149.1 T est Access Port (JT A G) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 29-5 29.3.3 Bypass Register The bypass register is a single-bit shift register path from TDI to TDO when the BYP ASS instruction is selected. 29.3.4 JT A G_CFM_CLKDIV Register The JT AG_CFM_CLKDIV register is a [...]

IEEE 1149.1 T est Acc ess P ort (JT AG) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 29-6 F re escale Semiconductor The boundary scan register cont ains bits for bonded-out and non bonded-out signals, excluding JT AG signals, analog signals, power supplies, comp liance enable pins, and clock signals. 29.4 Functional Des[...]

IEEE 1149.1 T est Access Port (JT A G) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 29-7 Figure 29-4. T AP Contr oller State Machine Fl ow 29.4.3 JT A G Instructions T able 29-5 describes public and private instructions. T able 29-5. JT A G Instructions Instruction IR[3:0] Instruction Summary E[...]

IEEE 1149.1 T est Acc ess P ort (JT AG) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 29-8 F re escale Semiconductor 29.4.3.1 IDCODE Instruction The IDCODE instruction selects the 32-bit IDCODE register for connection as a shift path between the TDI and TDO pin. This instruction allows interrogation of the MCU to determi[...]

IEEE 1149.1 T est Access Port (JT A G) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 29-9 and held in the boundary scan update registers. EXTEST can also confi gure the direction of bidirectional pins and establish high-impedance st ates on some pins. EXTEST asserts internal reset for the MCU sy[...]

IEEE 1149.1 T est Acc ess P ort (JT AG) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 29-10 F reescale Semiconductor to a single bit (the bypass register ) while conducting an EXTEST type of instruction through the boundary scan register . 29.4.3.9 BYP ASS Instruction The BYP ASS instruction selects the bypass register ,[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-1 Appendix A Register Memory Map Quic k Reference Ta b l e A - 1 summarizes the address, name, and byte assi gnment for registers within the MCF5221 1 CPU space. Ta b l e A - 2 lists an overview of the memory map for the on-chip modules, and Ta b l[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-2 F re escale Semiconductor T able A-2. Modul e Memory Map Overview Address Module Size 0x0000_0000 On-chip Flash/RAM Array 1G IPSBAR + 0x00_0000 System Contro l Module 64 bytes IPSBAR + 0x00_0040 Reser ved 64 bytes IPSBAR + 0x00_0080 Res[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-3 IPSBAR + 0x18_0000 Reser ved 64K IPSBAR + 0x19_0000 ADC 64K IPSBAR + 0x1A_0000 General Purpo se Timer 64K IPSBAR + 0x1B_0000 PWM 64K IPSBAR + 0x1C_0000 USB-O TG 6 4K IPSBAR + 0x1D_0000 CFM (Fla sh) Control Regi[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-4 F re escale Semiconductor IPSBAR + 0x0031 Grouped P eripheral Access Control Reg ister 1 G P A CR1 8 DMA Registers IPSBAR + 0x0100 Source Address Register 0 SAR0 32 IPSBAR + 0x0104 Destination Address Register 0 DAR0 32 IPSBAR + 0x0108 [...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-5 IPSBAR + 0x021C (Read) Reserved 8 U ART Baud Rate Generator Register 2 0 UBG20 8 IPSBAR + 0x0234 (Read) U ART Input P or t Register 0 UIP0 8 (Write) Reser ved 8 IPSBAR + 0x0238 (Read) Reser ved 8 (Write) U ART [...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-6 F re escale Semiconductor IPSBAR + 0x0288 (Read) Reser ved 8 (Write ) U ART Command Register 2 UCR2 8 IPSBAR + 0x028C (Read) UAR T Receive Buff er 2 URB2 8 (Write) UA RT T ransmit Buff er 2 UTB2 8 IPSBAR + 0x0290 (Read) U ART Input P or[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-7 I 2 C1 Reg isters IPSBAR + 0x0300 I 2 C Address Registe r 1 I2 ADR1 8 IPSBAR + 0x0304 I 2 C F requency Divider R egister 1 I2FDR1 8 IPSBAR + 0x0308 I 2 C Control Register 1 I2CR1 8 IPSBAR + 0x030C I 2 C Status [...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-8 F re escale Semiconductor IPSBAR + 0x0480 DMA Timer Mode Register 2 DTMR2 16 IPSBAR + 0x0482 DMA Timer Ext ended Mode Register 2 DTXMR2 8 IPSBAR + 0x0483 DMA Timer Event Register 2 DTER2 8 IPSBAR + 0x0484 DMA Timer Ref erence Register 2[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-9 IPSBAR + 0x0C4C Interrupt Control Register 0-12 ICR012 8 IPSBAR + 0x0C4D Interrupt Control Register 0-13 ICR013 8 IPSBAR + 0x0C4E Interrupt Control Register 0-14 ICR014 8 IPSBAR + 0x0C4F Interr upt Control Regi[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-10 F re escale Semiconductor IPSBAR + 0x0C6D Interrupt Control Register 0-45 ICR045 8 IPSBAR + 0x0C6E Interrupt Control Register 0-46 ICR046 8 IPSBAR + 0x0C6F Interr upt Control Register 0-47 ICR047 8 IPSBAR + 0x0C70 Interr upt Cont rol R[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-11 IPSBAR + 0x0FFC Global Le vel 6 Interr upt Ac knowledge Register GL7IACK 8 GPIO Registers IPSBAR + 0x10_0000 Reser ved — 8 IPSBAR + 0x10_0001 Reser ved — 8 IPSBAR + 0x10_0002 Reser ved — 8 IPSBAR + 0x10_[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-12 F re escale Semiconductor IPSBAR + 0x10_001E Reser ved — 8 IPSBAR + 0x10_001F Reserved — 8 IPSBAR + 0x10_0020 P or t NQ Data Direction Register DDRNQ 8 IPSBAR + 0x10_0021 Reser ved — 8 IPSBAR + 0x10_0022 Port AN Data Direction Re[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-13 IPSBAR + 0x10_003C P or t QS Pin Da ta/Set Data Register POR TQSP/ SETQS 8 IPSBAR + 0x10_003D Reser ved — 8 IPSBAR + 0x10_003E P or t T A Pin Data/Set Data Register PORTT AP/ SETT A 8 IPSBAR + 0x10_003F P or[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-14 F re escale Semiconductor IPSBAR + 0x10_0058 P or t TD Clear Output Data R egister CLR TD 8 IPSBAR + 0x10_0059 P or t U A Clear Output Data Register CLR UA 8 IPSBAR + 0x10_005A P or t UB Clear Output Data Register CLRUB 8 IPSBAR + 0x10[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-15 Reset Control, Chip Configur ation, and Po wer Manag ement Registers IPSBAR + 0x11_0000 Reset Co ntrol Register RCR 8 IPSBAR + 0x11_0001 Reset Status Register RSR 8 IPSBAR + 0x11_0004 Chip Configuration Regist[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-16 F re escale Semiconductor Programmable Interrupt Timer 0 Registers IPSBAR + 0x15_0000 PIT Control and Status Registe r 0 PCSR0 16 IPSBAR + 0x15_0002 PIT Modulus Register 0 PMR0 16 IPSBAR + 0x15_0004 PIT Count Register 0 PCNTR0 1 6 Prog[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-17 IPSBAR + 0x1A_0009 GPT Control Register 1 GPTCTL1 8 IPSBAR + 0x1A_000B GPT Cont rol Register 2 GPTCTL2 8 IPSBAR + 0x1A_000C GPT Interrupt Enable Register GPTIE 8 IPSBAR + 0x1A_000D GPT System Control Register [...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-18 F re escale Semiconductor IPSBAR + 0x1B_0014 PWM Channel P eriod Register 0 PWMPER0 8 IPSBAR + 0x1B_0015 PWM Channel P eriod Register 1 PWMPER1 8 IPSBAR + 0x1B_0016 PWM Channel P eriod Register 2 PWMPER2 8 IPSBAR + 0x1B_0017 PWM Channe[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-19 IPSBAR + 0x1C_0098 Address Register ADDR 8 IPSBAR + 0x1C_0 09C BDT Pa ge Register 1 BDT _P A GE_01 8 IPSBAR + 0x1C_00A0 Fr ame Number Register Low FRM_NUML 8 IPSBAR + 0x1C_00A4 F rame Number Register High FRM_[...]

Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-20 F re escale Semiconductor IPSBAR + 0x1D_0008 CFM Security Register CFMSEC 32 IPSBAR + 0x1D_0010 CFM Protection Register CFMPRO T 32 IPSBAR + 0x1D_0014 CFM Super visor Access Register CFMSACC 32 IPSBAR + 0x1D_0018 CFM Data Access Regist[...]

MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor B-1 Appendix B Re vision Histor y This appendix describes corrections to the MCF5221 1 Refer ence Manual . For convenience, the corrections are grouped by revision. B.1 Changes between Rev . 1 and Rev . 2 T able 1. MCF52211RM Re v . 1 to Re v . 2 Cha[...]

Revision History MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 B-2 F re escale Semiconductor B.2 Changes between Rev . 0 and Rev . 1 T able 2. MCF52211RM Re v . 0 to Re v . 1 Changes Location Description Throughout • F or matting, lay out, spell ing, and grammar corrections . • Remov ed the “Preliminar y” label. [...]