Intel 460GX manual

Intel® 460GX Chipset System Software Developer ’ s Manual June 2001 Docume nt Nu mb er: 248 704 -001[...]

ii Intel® 4 60GX Chipset Sy stem Soft ware Deve loper’ s Manual THIS DOCUMENT IS PRO V IDED “AS IS” WITH NO W ARRANTIES WHA TSOEVER, INCLUDING ANY W ARRANT Y OF MERCHANT ABILITY , FITNESS FOR ANY P AR TICULAR PURPOSE, OR ANY W ARRANT Y O THERWI SE ARISING OUT OF ANY PRO POSAL, SPECIFICA TION OR SAMPLE. Infor mation i n this docum ent is prov[...]

Intel ® 460G X Chipset Sy stem Software De velop er ’ s Manu al iii Contents 1 Introducti on............ ................... .................... ............ .................... ................... ............ .... 1-1 1.1 System O verview ............... ............. ................... ................... .................... ......... 1-1[...]

iv Intel ® 460G X Chipset Sy stem Soft ware Develop e r ’ s Manual 3 Sy stem Archite cture ....... ............. .................... ................... ................... .................... ...... 3-1 3.1 C oherency ......... .................... ................... ............. ................... .................... ...... 3- 1 3.1.1 Pr[...]

Intel ® 460G X Chipset Sy stem Software De velop er ’ s Manu al v 6.1.6 Private Bus between S AC and SDC .................. ............. ................... ... 6-2 6.2 Memory E CC Routing . .................... ............ .................... ................... ................ 6- 3 6.3 Data Poi soning ...... ................... ...........[...]

vi Intel ® 460G X Chipset Sy stem Soft ware Develop e r ’ s Manual 7.2 AGP Traffic .. ...... ....... ...... ....... ...... ....... ...... ............. ...... ....... ...... ....... ...... ....... ...... 7-6 7.2.1 Address es Used by the Graphics Ca rd .... ................... .................... ...... 7- 6 7.2.2 Traffic Priority ........... ..[...]

Intel ® 460G X Chipset Sy stem Software De velop er ’ s Manu al vii 8.2.14 Extende d Hot-Plug M iscellane ous ........ ................... .................... ....... 8 -18 9 IFB Register Mapping.. ............. .................... ................... ................... .................... ......... 9-1 9.1 PCI / LPC / FWH Configu ration ...[...]

viii Intel ® 460GX Chi pset System Software Developer ’ s Man ual 11.1.16 Determ inistic La tency Cont rol Register (Function 0) ... .................... .... 11- 7 11.1.17 M GPIOC – Muxed GPIO Control (Function 0) .............. .................... .... 11-8 11.1.18 P DMACFG – PCI DM A Configu ration Resi ster (Function O) ............ ...[...]

Intel ® 460G X Chipset Sy stem Software De velop er ’ s Manu al ix 13.2.4 PCIS TS – PCI Devic e Status Regi ster (Funct ion 2) .......... ............. ....... 13-3 13.2.5 RID – Revision Ident ificatio n Register ( Function 2) ........... ................... . 13-3 13.2.6 CLAS SC – Class Co de Register (Function 2) ................... ....[...]

x Intel ® 460G X Chipset Sy stem Soft ware Develop e r ’ s Manual 15 PCI/L PC Br id ge Des crip tio n ............... ............. ...... ...... ....... ...... ....... ...... ....... ...... ........... 15-1 15.1 PCI Interfa ce .................. .................... ................... ............. ................... ........... 15-1 15.1.1 T[...]

Intel ® 460G X Chipset Sy stem Software De velop er ’ s Manu al xi 7-4 GART En try Format for 4 MB Pages ..... ................... .................... ................... ... 7-3 7-5 GART SRAM Ti mings . .................... ................... ................... .................... ......... 7-5 Tabl es 1-1 Intel ® 460GX Chip set Compo nent[...]

xii Intel ® 460GX Chi pset System Software Developer ’ s Man ual 10-10 Ultra D MA Timing Value Ba sed on Driv e Mode .......... .................... ............... 10- 11 10-11 Ultra D MA/Multi Word DMA/S ingle Wo rd Transfer/Mo de Values ......... ......... 1 0-12 10-12 PIO Trans fer/Mode Va lues .......... ................... ................[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 1-1 Introduction 1 This document provides in f ormation about the Intel® 460GX chipset com pon ents. The 460GX chipset is a high per formance me mory and I/O chipse t for the Intel Itan ium™ processor , tar geted for multiprocess or server and high-end works tatio n designs. This documen[...]

Introduc tion 1-2 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 1.1.1 Component Overvi ew Ta b l e 1 -1 lists th e 460 GX chipset components. T ab le 1- 1. Intel ® 460 GX Chipset Compone nt s Component Na me Functio n SAC 82461GX System A ddress Controller Interfaces the address and control portion of the It anium ™ processor syste[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 1-3 Introdu ction 1.2 Product Features 1.3 It anium ™ Processor System Bus Su pport • Full support for the Itanium pro cessor system bus. — 64-bit data bus. — 266 MHz data bus fr equency . — Cache line size of 64 b ytes. — Supports SAPIC i nterrupt protoco l. • Full su pport f[...]

Introduc tion 1-4 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 1.4 D RAM Interface Support • SDRAM 3.3 volt, 168- pin DIMM ’ s are the on ly me mo ry ty pe sup por ted . • Support for 64 MB to 64 GB o f DRAM. • Minimum memory size is 64 MB us ing 16 MB DIMM ’ s. • Minimum incremental size is 64 MB using 16 MB DIMM ’ s. [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 1-5 Introdu ction • Parity protection on all PC I signals. • Data collection & write assembl y . — Combines back-to- back sequential proces sor -to-PCI memory writes to PCI burst writes. — Processor to PCI write ass embly of full/partial line writes . • T wo outbound read requ[...]

Introduc tion 1-6 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual • I2C Slave Interface will allow viewing and modifying of specific error and configuration registers. 1.7 Other Platform Components These 460GX devices p rovide access to flash s pace, interrupt collection and legac y features. 1.7.1 I/O & Firmwar e Bridge (IFB) The[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 1-7 Introdu ction • JT AG IEEE 1 149.1 Specification (http://www .ieee.com) • Universal Serial Bus Specification (http://www .usb.org) • System Management Bus Specificatio n , Rev . 1.0 • Low Pin Count (LPC) Interface Specifica tion , Rev 1 .0 Note: Contact yo ur Intel rep resentat [...]

Introduc tion 1-8 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-1 Register Descriptions 2 The 460GX c hipset has both memo ry mapped and PCI configuration space mapped regis ters. The 460GX chipset supp orts access mechanis m #1 as defined in the PCI specification. T wo 32-bit register locations (CONFIG_ADDRESS and CONFIG_ DA T A) are defined in the I[...]

Regi ster D escrip tions 2-2 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual to a PCI bus. Reads r esu lt in data being returned by the xXB th rough the SAC to the system bus. • Otherwise, the access is forwarded to the xXB to be placed on the PCI bus (or AGP bus) as a Configurati on Read or Co n figuration W r ite cy cle. Reads will [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-3 Regi st er Desc riptions translates CF8/CFC accesses to the MAC registers into r ead/write commands o ver the I2C port. The SAC also contains an IIADR pointer regi ster that can be used in conjunction with a CF8/C FC access to generate I2C commands to gener ic I2C devices on the memory [...]

Regi ster D escrip tions 2-4 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 2.2.6 Consistency There are a number of registers that are r epeated in both the SAC and xXB/PCI spaces. I t is so ftwa re ’ s respon sib ility to insure that these registers are programmed in a consisten t fashion. Failure to insu re consistency can produce [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-5 Regi st er Desc riptions subordinate bus numb er is in that rang e. For a type 1 cycle, th e Bus Number is mapped to AD [23:16] during the address phase. 15:1 1 Device Number . This field selects one agent on the PCI bus selected by the Bus Number . Device 16 (10h) on Bus #0 is always r[...]

Regi ster D escrip tions 2-6 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual Bits Description 7 Disable This bit can be written by software. When set, the ITID is retir ed imm edi ately and not captured. Therefo re there can be no checking of the address . See Section 6 for the usage of this bit. 6 V alid If set then the ITID in b its 5[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-7 Regi st er Desc riptions Bits Description 7 Dis abl e This bit can be written by software. When set , the IT ID is reti red imm ediately and not captured. Therefore there can be no checking of the address. See Section 6 for the usage of this bit. 6 V alid If set then the ITID in bits 5:[...]

Regi ster D escrip tions 2-8 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 18 ‘ Completion ’ Command Underflow; MAC B, S tack R (CCBR) One of these 4 bits is set when the SAC receives a completion f rom the MAC and the SAC ha s no out s t andi n g tran sactio n. 17 BERR# Observed (BER) BERR# seen on the system bus. Set whenev er B[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-9 Regi st er Desc riptions 2.4.1.6 SA_FERR: System Address on First Error Bus CBN, D evice N umber: 00h Functi on: 1 Address O ffset: 60h Size: 128 bit s Default Value: und efined after Attribute: Read Only Sticky: Yes Locked: No This register r ecords and latches the address for the f ir[...]

Regi ster D escrip tions 2-10 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 2.4. 1.8 BIUDA T A: BIU Dat a Register Bus CB N, De v ice Num ber: 0 0h Funct ion: 1 Address Offset: 90h Size: 128 bits Default Value: undef in e d Attribute: Read On ly Sticky : No Locked: No This is the contents o f the CAM concatenated with the conten ts of[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-11 Regi st er Desc riptions 2.4.2 SDC 2.4.2.1 SEC0_ D_ FERR: Data on First Memory Card B SEC Bus CBN, Device Numb er: 04h Address Offset: 40-47h Size: 64 bits Default Value: 0 Attribute: Read Only, New Value Latched anytime appropriate FERR reg ister bit is set This register r ecords and [...]

Regi ster D escrip tions 2-12 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 2.4.2.4 DED0_ D_FERR: Dat a on First Memory Card B DED Bus CBN, Device Number: 04h Address Offs et: 50-57h Size: 64 bi ts Default Value: 0 Attribute: Read Only, New Value Latched anytime appropriate FE RR register bit is set This register records and latches t[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-13 Regi st er Desc riptions This register r ecords and latches the d ata correspond ing to the first SEC de tected by memory interface 1 in the SDC. Bits Description 63:0 DE - System Data of Error . 2.4.2.8 SEC1_EC C_FERR: ECC on First Memory Card A SEC Bus CBN, Device Numb er: 04h Addres[...]

Regi ster D escrip tions 2-14 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 2.4.2.1 1 D ED1_ECC_FERR: ECC on First Memory Card A DED Bus CBN, Device Number: 04h Address Offs et: 78h Size: 8 bi ts Default Value: 00h Attribute: Read Only, New Value Latched anytime appropriate FE RR register bit is set This register records and latches t[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-15 Regi st er Desc riptions 26 ’ Forward ’ Overlapping ’ Forward ’ ; Card A (FWMDI1) Indicates FWMDI sampled asserted while a s tore transaction is in pr ogress 25 ’ Load ’ Ov erlapping ’ Load ’ ; Card A (LRMDI1) Indicates LRMDI sampled ass erted while a stor e transaction[...]

Regi ster D escrip tions 2-16 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 5 System B us Double Bit Er ror (DEDF) ECC Double Bit Error Detected on syst em bus. 4 System Bus Si ngle Bit Error (SECF) ECC Single Bit Error Detected on system bus. 3 SDC Card A Double Bit Error (DED1) ECC Double Bit Error Detected from Memory Card A. 2 SDC[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-17 Regi st er Desc riptions This register records and latches the data associated with the first parity error detected on the PITID bu s. Bits Description 7 If set then the error was detected on the 1 st hal f of the double- pumped tran sfer . Otherwise, these fields contain the informati[...]

Regi ster D escrip tions 2-18 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual while masked will return an invalid ECC code. To disable testing, the mask value is left at 0h (the default). The mask is a bit-wise XOR wit h the comp ut ed ECC. Bits Description 7:0 ECC Generation Mask - For 64 bi ts of d a ta . 2.4.2. 20 ECCM SK1: E CC Mask[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-19 Regi st er Desc riptions 5 Memory Bus A ECC corr ection/detection enable. 4 Memory Bus B ECC correction /detection enable. 3:0 Double byte p arity mask for 128 bits of d ata. 2.4.2.23 PVD_D_FERR: Dat a on First PVD Parity Error Bus CBN, Device Numb er: 04h Address Offset: D0-D7h Size: [...]

Regi ster D escrip tions 2-20 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 2.4.2.26 SECF_D_FERR: Data on First System Bus SEC Bus CBN, Device Number: 04h Address Offset: E0-E7h Size: 64 bits Default Value: 0 Attribute: Read On ly, New Value Latched anytime appropriate FE RR register bit is set This register records and latches the da[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-21 Regi st er Desc riptions This register records and latches the data correspond ing to the first DED detected by sy stem bus interface in the SDC. Bits Description 63:0 DE - System Data of Error . 2.4.2.30 DEDF_EC C_FERR: ECC on First System Bus DED Bus CBN, Device Numb er: 04h Address [...]

Regi ster D escrip tions 2-22 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 0 Parity Err or - CMND Parity Er ror Detected on SAC-MAC CMND Bu s. Look i n CMND_F ERR Reg ister to isolate. When the error i s detected, the MAC will complete those operations which have a RAS pending, and stop. No new RAS cycles will b e issued after the pa[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-23 Regi st er Desc riptions 3 Inbo und D elay ed Read T ime-o ut Fl ag Each inbound r ead request that is accepted and serviced as a delayed read (i.e. the PXB retries the r equest) will initiate a watchdog t imer (2 15 cycles, p er the PCI spec) . If the data has been return ed and the t[...]

Regi ster D escrip tions 2-24 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 2.4.5 GXB 2.4. 5.1 FERR_ GXB Function Nu mber : BFN+1 Address Offs et: 80h Size: 8 bits Default Val ue: 00h Attribute: R ead/Write Cl ear Sticky: Yes Locked: No These registers recor d the first erro r detected by the GXB. For the order to clear th is register[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-25 Regi st er Desc riptions Default Value: 00h Attribute: Read/W rite Clear Sticky: Yes Locked: No These registers reco rd and latch the fir st error detected in the AGP interface. Bits Description 7:6 r eserved (0) 5 Lo-prior ity Read Dat a Que Parity E rro r This is data returned to the[...]

Regi ster D escrip tions 2-26 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 2.4. 5.6 NERR_ GART Function Nu mber : BFN+1 Address Offset: 8Eh Size: 8 bits Default Value: 00h each Attribute: Read/Write Clear Sticky: Yes Locked: No This register records all error cond itio ns detect ed in the GAR T lo gic after the first error . Er rors [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-27 Regi st er Desc riptions 2.4.6 WXB 2.4.6.1 ERRSTS: E rror St atus Register Address Offset: 44h Size: 8 bits Default Value: 00h Attribute: Read /W rite Clear, Sticky This register records certain error conditio ns detect ed from the PCI bus. This register is sticky through reset; that i[...]

Regi ster D escrip tions 2-28 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 2.4.6.2 ERRCMD: Error Command Regist er Addr ess Offset: 45h – 46h Size: 16 bits Default Value: 8040 h Attribute: Read /W rite This regis ter provid es exte nded contr ol over the signallin g of err ors through SERR_OU T#, XBINIT#, and INTRQ#. Thes e co ntro[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-29 Regi st er Desc riptions each of these errors varies and is (g enerally) contr olled throug h a combination of th e PCICMD and ERRCMD r egist ers. R efer t o Section 6.12 for information on the condition al repo rting of these errors via t he SERR# , XBINIT#, or INTRQ# o utputs. Note, [...]

Regi ster D escrip tions 2-30 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 2.4.6.5 F EPCIAL: PCI First Er ror Address/Command Log Address Offs et: A5h – ADh Size: 72 bits Default V alue: 00 000000000 00000 00h Attribut e: Read/Writ e Clear, Sticky These registers recor d and latch the add ress/command information, sent or received,[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-31 Regi st er Desc riptions The IT_MON_PMD_[0 to 5 ] registers ho ld the performan ce monitoring cou nt values. 39-b its of the counter are used for event co unting, the 40th-bit is used as a overflow d etection bit. The 39-bit count value allows up to 70 minutes of event collection at 13[...]

Regi ster D escrip tions 2-32 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 23:15 UMASK Encodings 0 0000 0 000 - Pro cessor 0 - Monitor transactions originat ing fro m Processor 0 0 0000 0 010 - Pro cessor 1 - Monitor transactions originat ing fro m Processor 1 0 0000 0 100 - Pro cessor 2 - Monitor transactions originat ing fro m Proc[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-33 Regi st er Desc riptions 001 01 1 1b Memory Read that was to be retried and received a HITM 001 1000b Memory Read with active OWN# and received a HITM 001 1001b Memory Read fr om a CPU that received a HITW 001 1010b Memory Read fr om a CPU that received a HITM 001 101 1b Memory Read fr[...]

Regi ster D escrip tions 2-34 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 2.5.2 SDC 2.5.2.1 FSB_D_PMC_ [1,0]: Sy stem B us Performanc e Monitor Conf iguration Regi ste r Bus CBN, Device Number: 04h Address Offset: 98-9Ah, 9C-9Eh Size: 24 bits each Default Value: 0000 00h each Attribute: Read/W rite The FSB_D_PMC_[1,0] Regis ters spe[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-35 Regi st er Desc riptions 01b Disable wh en counter overflows . 10b Disable o n fallin g edge (Deas sertion) o f SDC E vent 0. 1 1b Disab l e on f alling ed ge (Deassert ion) of SDC Event 1. 4:3 Enab le So ur ce . Selects event that will enable the perfo rmance monitor . 00b Never E nab[...]

Regi ster D escrip tions 2-36 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 2.5.3 PXB 2.5.3.1 P MD[1:0]: Performance Monitoring Data Register Address Offset: D8-DBh, E0 -E3h Size: 32 bits each Default Value: 0000_ 0000h each Attribute: Read/Write T wo perform ance monitoring counters , with associated event se lection and control reg [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-37 Regi st er Desc riptions Once configured to count, all counters in the SAC and each PXB can be (nearly) simultaneously s tarted and st opped using a s eparate enable. 1:0 Rel oad Mode Reload has priority o ver increment. That is , if a Reload event an d a count event h appen simultaneo[...]

Regi ster D escrip tions 2-38 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 5:0 Event Selection T h i s f i e l d s p e c i f i e s t h e b a s i c P C I b u s t r a n s a c t i o n o r P C I b u s s i g n a l t o b e m o n i t o r e d . All other encoding s are reserved. NOTE: 1. Counting data cycles is undefined for this selection. [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-39 Regi st er Desc riptions 38:0 Coun t V alue This register contains the Perf ormance Monitor Data Register . Y ou may preset the value of the per formance counter by writing to this register . Y ou may read b ack the value of t he performance counter b y reading this register . 2.5.4.2 [...]

Regi ster D escrip tions 2-40 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 0 Event 0 Input This bit is fed an input into Event 0 logic. This bit is OR ’ ed wit h any ot her l o gic generating Event 0, guaranteeing that if this bit is set, then Event 0 will b e asserted . 2.5.4.4 A GP_PMC_[0,1]: AGP Performance Monito r Configuratio[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-41 Regi st er Desc riptions 7 EVENT1 C ount E nable If set, then this bit over-rides bits 13:8. If set, then AGP_PMD_0 will count the number of occurrences of EVENT1 and AGP_PMD_1 will count the number of clocks that EVENT1 is active. When th is bit is no t set, then the 2 counters are co[...]

Regi ster D escrip tions 2-42 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 00 0010b All PCI Clocks 00 0100b Idle Bus Cycles 00 01 1 1b All Disconnect Ev ents 00 1000b Lock As serted Clock s 00 1001b Lock Assert ed Events 00 101 1b I/O Reads - Events 00 1 101b I/O W rites - Ev ents 00 1 1 1 1b Memory R ead Events 01 0001b Memory W rit[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-43 Regi st er Desc riptions 2.5.5 WXB 2.5.5.1 PCI_WXB _PMC0: PC I Perf ormance Monito r Configuration Register Address Offset: DCh – DFh Size: 32bits Default Value: 000 00000h Attribute: Read/W rite This register controls the PCI per formance m onitors. There are two perform ance monito[...]

Regi ster D escrip tions 2-44 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 2.5.5.2 P CI_WXB_PMC1: PCI Performance Monitor Configurat ion Register Address Offs et: E8h – EBh Size: 32bits Default V alue: 00 000000h Attribut e: Read/Write This register co ntrols the PCI perfo rmance monitors . There are two p erformance mo nitors for [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-45 Regi st er Desc riptions 15:8 XTP R 1 These bits represen t the external task priority fo r symmetric agent I D 01h. 7:0 XTP R 0 These bits represen t the external task priority fo r symmetric agent I D 00h. 2.6.2 PID PCI Memory-mapped Registers The PID uses two 32-bit memory-mapped re[...]

Regi ster D escrip tions 2-46 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 2.6.2.2 I/O Window Register (FEC000 10h) This register is mapped onto th e PID ’ s internal register that is selected by the I/O r egister select register . Readability/writeability by soft ware is determined by the ch aracteristics of the internal register [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-47 Regi st er Desc riptions 2.6.3.1 I/O (x )APIC ID Regist er (00h) T ab le 2-6. Memor y-mapped Reg ister Summar y Offset Nam e Access Default V alue 00h I/O (x)API C ID Register R/W 00000000h 01h I/O (x)A PIC V ers ion Register R/O 003F00vvh a 02h I/O (x)API C Arbitration ID Register R/O[...]

Regi ster D escrip tions 2-48 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual The I/O (x )AP IC ID re giste r is re ad/w rite by softw are. On re set, th is reg ist er ’ s contents are reset to zero. This regist er is provided for APIC compatibility only and it does not serve any other purpos e. The PID ’ s (x) APIC ID regi ster has[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-49 Regi st er Desc riptions 2.6.3.2 I/O (x )APIC V ersion Register ( 01h) The PID contains an I/O (x)APIC ve rsion r egister that iden tifies the type of I/O (x)APIC it implements. Software can use this to provide compatibi lity between di fferent I/O (x)APIC implementations and their ver[...]

Regi ster D escrip tions 2-50 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 2.6.3.4 I/O (x)APIC RTE (10h-8 Fh) The interrupt R T has a dedicated entry for each interrupt input pin. Software can individually choose the interrupt vector n umber for input pins. For each individual pin, the operating system can also specify the sign al po[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 2-51 Regi st er Desc riptions 16 MASK MAS K This bit mas ks the (x)API C delivery of this interrupt. A 0 indicate s that delivery of this int errupt is not ma sked. An edge or level on an interrupt pin that is not masked results in the delivery of the interrupt to the destination. A 1 indic[...]

Regi ster D escrip tions 2-52 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 1 1 DE STINA TION MODE DESTINA TION MODE This bit determines the interpretation of the destination field. A 0 indicates physical mode. In physical APIC mode, a destination APIC is identified by it s ID. Bit s 56 through 59 of the destinati on field specify the[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 3-1 System Architecture 3 This chapter pr ovides an explanation o f the 460GX chipset ’ s han dlin g of var ious aspects of th e system architecture. It co vers coherency , ordering, interrupts and r elated issues. 3.1 Coherency For any comp uter system, data coherency between proces sor [...]

System Archi tecture 3-2 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual For WC memory , one processor may write to an address that is mar ked WC in its page table and hold the write in its own data buffer , while waiting to write to the bus. If a dif fer ent processor were to read this addr ess, the first proc es sor does not snoop the[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 3-3 System Arch itect ure New EM code may be weakly or dered. T o allow the processor to take advantage of this , the 460GX chipset defers all reads and retur ns the data out- of-order to the processor . By returning data in an out-of- order fas hi on, the DRAM ’ s may be accessed in an o[...]

System Archi tecture 3-4 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual Arbitrat ion for Outboun d T rans actio ns The WXB relies heavily on the PCIset core and the PCI Specification regarding tr ansaction ordering for deali ng with starvatio n on outbou nd trans actions. O nce the WXB has won PC I arbitration for an outb oun d tran sa[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 3-5 System Arch itect ure AGP LOCKS There is no LOCK signal on the AGP bus. However , legacy code that issues read -modify-write (RMW) transactions could still be converted for use w ith an AGP device. The GXB will attemp t to establish a “ pse udo- lock ” to cover such an event. Howeve[...]

System Archi tecture 3-6 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual location, there is no guarantee th at AGP has not written the location while the lock wa s activ e on the sys tem bus. A GP may read or wr i te thos e l ocati ons o r any ot h er memo ry l ocati on, i ndep enden t of the processor lock. 3.7 I nterrupt Delivery Inte[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 3-7 System Arch itect ure 3.8.1 Slot Power-up a nd Enable T o power-up a PCI slot, so ftware sets a com mand bit in a register . Then the hot-plug lo gic performs the following step s: 1. Set PWREN active to the slot and clock the parallel latch. 2. Set CLKEN# active to the slot but do not [...]

System Archi tecture 3-8 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 4-1 System Address Map 4 4.1 Memory Map The Itanium ™ processor s upp orts a 44 bit address space. The 460GX ch ips et s upp orts o nly 36 bits of the add ress bus fo r a 64 GB of physical memory and m ust addr ess up t o several GB of memory mapped I/O space . The 460GX c hipset attaches[...]

Syste m Ad dres s Map 4-2 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 4.1.1.4 System Firm ware The 64 KB region fro m F_0000 h to F_FFFFh is treated as a si ngle block. Read/W rite attribute enables defined in the MAR registers may be used to direct accesses to the compatibilit y PCI bus or main memory . At power-on, this area is ma[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 4-3 System Addres s Map 4.1.2 Lo w Extended Memory Region The 15 MB Low E xtended Memory r egion is always mapped to main memory . Since the 460GX chipset do es not s upport ISA cards, ther e is no g ap prov ided in thi s region. 4.1.3 Medium Extended Memory Region The Medi um Ex tende d Me[...]

Syste m Ad dres s Map 4-4 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual — FEB0_0CC0: This addres s is used for BSP selection. It is a write on ce register in the SAC. Figur e 4-1 shows how the SAPIC and G AR T spaces are allocated. There may be up to 2 55 I/O SAPICs in the system. Ther e is one region defined for the GAR T space. 4.[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 4-5 System Addres s Map 4.2 I/O Address Map The 460GX c hipset al lows I/O addresses t o be ma pped to r esources s upported on the I/O buses underneath the 460GX chipset controller . This I/O space is partitione d into sixteen 4K byte segments. Each of the segmen ts can be in dividually co[...]

Syste m Ad dres s Map 4-6 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual • I/O addresses used for VGA controllers: 03B0h-03BBh and 03C0h-03DFh. These addresses are specifically decoded so they can be mapped to the PCI bus specified by the VGA Space Register . An I/O access must be contained fully within the VGA I/O r ange to be r ema[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 4-7 System Addres s Map 4.3 Devices View of the System Memory Map Figur e 4-1 shows an Expand er Bridge device ’ s view of system memory . The goal is to prevent invalid accesses at the ex pander bridge lev el, since dif ferent expander bridge devices a re allowed to access dif ferent reg[...]

Syste m Ad dres s Map 4-8 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 4.4 Lega l and Illegal A ddress Disposition Below is the disp osition of addresses done by the Bus Interface Unit (BIU). T able 4-1. Address Disposition Address Range Outbound Inbound Dest. Decision 0-07FFFFh DRAM DRAM 080000h-09FFFFh DRAM DRAM MAR=1 1 or (Read an[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 4-9 System Addres s Map Note: Accesses listed as “ unclaimed ” in the table for inbound transactions assume th e PXB is programmed correctly . If an access were received up the Ex pander bus that hits in th e listed address range, then its behav ior is the same as ou tbound trans action[...]

Syste m Ad dres s Map 4-10 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 5-1 Memory Subsystem 5 The Intel 460GX chipset ’ s memory subsystem consists of the SAC ’ s DR AM controller , the SDC ’ s buff ering and datapath access, the MAC and MDC components, and the DR AMs themselves. Ta b l e 5 - 1 summarizes the 460GX chip set ’ s general memory character[...]

Memory Subsystem 5-2 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual Each card is or ganized as 2 stacks of up to 4 rows each. A stack cons ists of 1 to 4 rows of DRAM which share a comm on data bus. A row consists of th e 4 DIMM sockets which ha ve a common address/control bu s. A row is the minim um atomic unit that can b e accessed. [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 5-3 Memory Su bsy s tem Figur e 5-2 for an illustration. In theory all 4 of th ese lin es could be transferring data at the same time. It would then be muxed by the MDC to the SDC and then by the SDC to the bus. This allo ws data to be moved with no dead cycles on consecutiv e reads. An ot [...]

Memory Subsystem 5-4 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 5.2 Interleav ing/Configur ations Maximum system bandwidth is obtainabl e in several way s. If the address patterns are well -behaved then one can us e the page mode of the DRAM i tsel f to obtai n hi gh band widths. G enerally page hi ts can sustain abo ut 5 times the[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 5-5 Memory Su bsy s tem 5.2.1 S ummary of C onfiguration Ru les The memory s ystem may pop ulate any row in any order . There are preferred way s of popula ting the memory subsystem for performance, but all co nfig uratio n s will wo r k. The following rules sum m a rize the way the mem ory[...]

Memory Subsystem 5-6 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 5.4 Me mory Subsystem Clocking The DIMMs are clocked at half the system bus frequen cy . For the Itaniu m processor , this means the DRAMs are clo cked at 15 ns. Data is clocke d out at the rate of 32B per 15 ns . The following table lists the DRAM parameters used for [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 5-7 Memory Su bsy s tem 5.5.3 Hardware Initi alization In order to d ecrease boot time of systems with lar ge amounts of DR AM installed, hardware initialization of mem o ry will be supported. Since multi ple rows will be initialized sim u ltaneously , the memory system will be able to init[...]

Memory Subsystem 5-8 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-1 Data Integrity and Error Handling 6 6.1 Int egr ity This chapter expl ains the various erro rs in the chips et. Error hand ling requires catching the er ror , containing it, notifyin g the system, and r ecovery or sys tem restart. Dif ferent platforms h ave differen t requirements fo r [...]

Data Integrity and Erro r Handling 6-2 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 6.1.2 DRAM • The 460GX ch ipset provides ECC generation on all wr ites into the DRAM, an d ECC checking on all reads from the DR AM. Single-bit errors are cor r ected. Multi-bit errors will return poisoned dat a. Both types of erro rs are log ged, w[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-3 Data Integri ty and Er ror Handli ng 6.2 Memory ECC R outing The ECC code used in DRAM is the same code as used in the Itanium processor , requiring 8 check bits to cover 64 bits of data. On the sys tem bus, this code d etects and corrects all sing le-bit errors, and detects double-b it[...]

Data Integrity and Erro r Handling 6-4 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual Note: In the SAC if there is a sing le-bit error and a double-bit error reported f rom the SDC on the same cycle, then only the double-bit error is reported and only the double-bit erro r has its ITID captured in the SAC. The SDC will have its SEC bit[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-5 Data Integri ty and Er ror Handli ng 6.4.4 XBINIT# XBINIT# is an input t o the SAC an d an outp ut from one o f the xXB ’ s or can also be generated by platform logic. XBINIT# is G TL+ level, and therefore all the outpu ts f r om th e xXB ’ s can be tied together and fed into the SA[...]

Data Integrity and Erro r Handling 6-6 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 6.5.2 System Bus Errors There are several er rors that are detected by the SAC. • System Bus Address Parity E rror . Parity is checked on both addr ess phases. — On A[43:24] #, detected by AP[1]#. — On A[23:3]# , detected by A P[0]#. • System [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-7 Data Integri ty and Er ror Handli ng The SDC will capture the following errors on its side o f the interface. • PDB Data Parity Error . On data received fro m the SAC, parity is checked. If p arity is bad, th e data is sent to memory or the syst em bus with poisoned ECC. • PDB Byte [...]

Data Integrity and Erro r Handling 6-8 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual • ‘ Load ’ Overlapp i ng ‘ Forw ard ’ . Set w hen the SDC is d o ing a ‘ Forward ’ by s endi ng da ta t o the MDC and the MDC s tarts to send the SDC data before the ‘ Forward ’ is com plete. • ‘ Forw ard ’ ov erl appin g ‘ L[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-9 Data Integri ty and Er ror Handli ng Other errors capture th e address associated with the failure. This is also for d ebug and diagn ostic purposes, bu t also has the potential for us e in system recover y . For instance, if there is an uncorrectable erro r on a data read, and the acce[...]

Data Integrity and Erro r Handling 6-10 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual After this the error repo rting is in the clean st ate. After the ITID is found, the actual address is needed. Again this is somewhat in direct. There are 2 locations in the SAC in which the address may b e found. One is the B us Interface Unit ’ s[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-11 Data Integri ty and Er ror Handli ng • DEDF - first do uble-bit ECC error o n the sy stem bus. • PCMD - first parity er ror on the command bus. • PITID - firs t parity error on t he ITID bus. • SDCRSP - f irst f ailing t ransmissi on on t he resp onse bus. The resp onse b us do[...]

Data Integrity and Erro r Handling 6-12 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual capable of any recover y . The first error , especially if it is fatal, may its elf have caused do wnstream errors to be fl agged. The erro r that is flagged as fir st should be consider ed as correct and an indication of some real problem . The prob[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-13 Data Integri ty and Er ror Handli ng 6.8.2 SAC Multip le Err ors There are sever al important case s of multiple error s in the SAC. Some o f these are caused by the SAC and SDC not being i n one chip and theref ore having dela ys in the handshaki ng paths that will allow events that o[...]

Data Integrity and Erro r Handling 6-14 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual T ake the case where processor 1 read s a line from memor y and there are no er rors , and then does a write into its cache. Later pr ocessor 2 does a read, getting an IWB. The SAC starts a sp eculative read for the line bef ore seeing the HITM#. I f[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-15 Data Integri ty and Er ror Handli ng 6.10 Error Conditions 6.10.1 T able of Errors Ta b l e 6 - 1 is a list of possible error s found in the system. The table shows the error and the system action. It also shows the in format ion th at is captured on any failure. The captured info is s[...]

Data Integrity and Erro r Handling 6-16 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual T able 6-1. Err o r Case s Error Chip Detecting System Act io n St atus Register Log Register Qua lifie r System Bus 1x ECC S DC Correct the data and pass to bus . Conditional Interrupt. SDC_FERR[SECF], FERR_SAC[SNE] SECF_D_FER R, SECF_ECC_FERR, SECF[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-17 Data Integri ty and Er ror Handli ng Request Parity Error SAC Conditional BINIT# FER R_SA C [RQE ] SA_FERR Flag System Bus Parity Errors Unsupported ASZ SAC Conditional BINIT# FERR_SAC[A SE ] SA_F ERR Flag System Bus Parity Errors Illegal HITM (HITM on any Expander bus access) SAC Unco[...]

Data Integrity and Erro r Handling 6-18 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual ‘ Accept ’ Underflow SDC Unc onditional BINIT# SDC_F E RR[AEx], FERR_SAC[SFE] Nothing Internal SDC Error Data Buffer Ram Parity Error S DC Unconditional Interrupt SDC_F ERR[RPE], FERR_SAC[SNE] Nothing GXB ERRORS AGP Request Queue Overflow GXB Unc[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-19 Data Integri ty and Er ror Handli ng GART Parity Error GXB Continue, u se address as read from GART , Unconditional XINTR#, Conditional XBINIT#. (NOTE: if XBINIT# is driven, then it is not required to drive XINTR#) FERR_GAR T Nothing GAR TER R_BINITE Illegal SMM Access GXB Unconditiona[...]

Data Integrity and Erro r Handling 6-20 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 6.1 1 PCI Integrity The PCI bus prov ides a single even-par ity bit (PAR) that covers the AD[ 31:0 ] and C /BE #[3: 0] lines. The agent that drives the AD[31:0] lines is r e sp onsible for driving PAR . Any un define d signals must still be driven to[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-21 Data Integri ty and Er ror Handli ng The default op tion is to return a “ normal ” respons e. If the abor ted transaction was a read , the PXB will re tu rn al l 1 ’ s f or the data. If the aborted transaction was a write, the PXB will discard the w rite data. SERR# is not asse r[...]

Data Integrity and Erro r Handling 6-22 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual • After the first data transfer if the transaction is us ing an unrecog nized addressing mode ( t he PXB will only support linear incr ementing as a targ et), • On reads, when no mo re data is available in the read buffers, and • On writes, whe[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-23 Data Integri ty and Er ror Handli ng 6.1 1.4.1 GXB Error Signals The GXB has 2 error signals : XBINIT# and XINTR#. 6.1 1. 4.1.1 G XB_X BINI T# XBINIT# is used to signal a fatal error . All header errors are fatal, since the GXB and SAC are out of sync with each other at that point. Dat[...]

Data Integrity and Erro r Handling 6-24 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 6.1 1.4.2.2 G ART Interface Error s • GAR T Parity Error - Th ere is one parity b it covering each GAR T entry . When the GAR T is accessed, parity is check ed. If an erro r occurs, then this bit is set. Parity errors ar e only reported when the ac[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-25 Data Integri ty and Er ror Handli ng • PCI Outbound Write Qu e Data Parity Error - This error signifies th at eith er a) data was received from the Exp ander b us with bad parity o r b) the OB write Que was corrupted. As data is read from the queue and p assed to the PCI bus , the pa[...]

Data Integrity and Erro r Handling 6-26 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 6.12 WXB Dat a Integrity and Error Handlin g 6.12.1 Integrity Error handling in the context of a ch ipset componen t requires obs erving the error , containing it, notifying the system, and recovery or system res tart. Dif ferent platforms have d iff[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-27 Data Integri ty and Er ror Handli ng Note: Additionall y , error respo nses such as SERR #, XBINIT# and INTRQ# are predicated on both First Error and Next E rror contents since a s econd error may occur while the first error is in the proces s of being ser viced by the WXB hard ware. T[...]

Data Integrity and Erro r Handling 6-28 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 6.12.5. 1 SERR# Generation Most errors can be caused to steer th e observation o f the error to the signaling of an SE RR# . The system then has a chance to respond to the ev ent while it continues to run. Often, S ERR# re sult s in an NMI which itse[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-29 Data Integri ty and Er ror Handli ng 6.12.5.2 XBINIT# Generation A certain subset of error s within the WXB will always resu lt in the WXB attempting to sign a l an XBINIT# . Whenever an error o ccurs that forces an XBI NIT# , an internal “ over ride ” bit is set as XBINIT# is driv[...]

Data Integrity and Erro r Handling 6-30 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 6.12.8 Error Conditions 6.12. 8.1 WXB as B us Ma ster 6.12.8.1.1 Master Abort If the WXB initiates a PC I transaction and no target responds, the WXB will ter mi nate the transaction w ith a master-abort. The WXB will wait five PCI clocks after asser[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 6-31 Data Integri ty and Er ror Handli ng ( DPE ) bit is asserted. R egardless, if the transaction is a read, the PCI STS regi ster ’ s Pari t y Er ro r ( PE ) bit will be set. Additionally , address , command, and d ata related inf ormation is l ogged in the FEPCIAL and FEPCIL registers [...]

Data Integrity and Erro r Handling 6-32 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual • MWI to a misaligned ( non-cache-line -boundary) add ress • MWI to an aligned ad dress, but with one o r more byte enables n ot asserted Refer to the PCI sp ecif ication for a complete description of the required PCI protocol. 6.12.8. 3 PCI Inte[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 7-1 AGP Subsystem 7 AGP is a new port defined for graphics adapters. In the initial implementation it is a 500 MB /s port. There is also an ext ens ion cal le d AGP 4X mo de, w hich has a ba ndwi dth of 1 GB/ s. A GP 2X mo de cards will work in an AGP 4X mode slot. The 460GX chipset is desi[...]

AGP Su bsystem 7-2 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual Figure 7-1. GART T able Usage for 4k Pages Figure 7-2. GART T able Usage for 4 MB Pages Off set 39 11 0 GART Tabl e + 36b Mai n Memory Ad dres s 24 Bit GART Ent ry 12b 24b 18b AG P address (39:12) - APB AS E(3 9:12) AGP add ress (If less than APB AS E+Aperture) (16b if25[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 7-3 AGP Subsy s tem 7.1.1 GART Implement a tion The GX impl ementati on will suppor t 256 MB, 1 GB, or 32 GB (32 G B requires 4 MB p ages by the O.S.) of translation space. This limit is im plementation-based not architectural. Each entry in the GAR T requ ires 24 bits fo r the addres s, 1 [...]

AGP Su bsystem 7-4 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 7.1.1.1 Page Sizes The Itanium proces sor supports both a 4kB and a 4 MB page size. The AGP programming mo del is designed us ing 4kB pages for GAR T entries. Usin g the lar ger page size would greatly reduce the number of misses and reduce the num ber of entr ies needed[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 7-5 AGP Subsy s tem 7.1.3 GART Implement a tion Figur e 7-5 shows the timings for the SRAM interfa ce. Sync hronou s SRAM will be clocked at 7.5 ns. The SRAM w ill be used i n the p ipelined mode. This allows address es to be presented to the SRAM every cycle. The d ata is valid to be latch[...]

AGP Su bsystem 7-6 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual For all AGP-type accesses which hit in the AGP rang e, there is a bit per GAR T entry which determines whether the address is coheren t. For AGP-type accesses outside the AGP range, there is a bit in a conf i guration register o f the GXB which d etermines t he coherency[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 7-7 AGP Subsy s tem The range may lie ab ove the top of physical memor y . Or th e range may be placed in one o f the gaps used to map a ddresses to PCI, and have th at gap marked as reserved and not usable for addressi ng PCI devices. In the first case, the v irtual range used by the graph[...]

AGP Su bsystem 7-8 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual Note: Accesses from an AGP card that are di rected to a PCI bus are a sy stem fault and cause a B INIT# (system reboot). T he 460GX chipset does NOT suppo rt any access originatin g from the AGP port to another PCI bus. This is true for PCI cycles (FRAME# active) as well[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 7-9 AGP Subsy s tem this point the inbound Expander lo gic establ ish es a pseudo-lock and will no-longer send coherent requests from the AGP streams. Non-coherent request s can still be issued, but anything that can b lock the PCI stream i n the SAC ’ s queues must be hel d in the GXB. 5[...]

AGP Su bsystem 7-10 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual Delayed transactions are issued and serviced as f ollows: 1. Upon receiving a read req uest, the address is compared against the GXB ’ s in tern al b uffers. Unless the data corresponding to this request is already available in the buffers (i.e. from a previously retr[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 7-11 AGP Subsy s tem When a DRC is valid in the GXB , a 2 15 PCI clock timer is started as des cribed in the PCI 2 .2 Specification. When the timer expir es the DRC is discarded and the associated delayed read matching registers are cleared. This cond ition is optionally treated as an error[...]

AGP Su bsystem 7-12 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 7.2.7.8 R etry/Disconnect Conditions The GXB as a PCI tar get retries the initial data phase o f inbound acces s when: • The read request is to an address that has already been accepted as a delayed transaction (i.e. the request is already b eing serviced, b ut data h[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 7-13 AGP Subsy s tem 7.2.7.1 1 Fast Back -t o- Back T ransactions The GXB as a PCI tar get will accept fast back -to-back cycles from a PCI master accessing dif ferent agents during back -to-back sequ ence. As an initiator the GXB does not generate a f ast back-to- back cycle. 7.3 B and wid[...]

AGP Su bsystem 7-14 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 7.3.1 Inbound Read Prefetching The PCI protocol has no trans fer size ex pl icitly spelled out. Reads begin and continue until th e device has the data it needs. For performance, a PCI bridge coul d prefetch data ahead of when the PCI device requests it. AGP , as oppose[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 7-15 AGP Subsy s tem All regions, including the two des cribed above, must be checked after GAR T translation. The GXB must only allow access es that are directed to p hysical memory to reach the SAC . Therefore, the GXB must force a BINIT#, by asser ting its “ XBINIT# ” o utput , when [...]

AGP Su bsystem 7-16 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 8-1 WXB Hot-Plug 8 8.1 IHPC Con figuration Reg isters Each WXB support s two indepen den t Integr at ed Hot-Pl ug 1 Con trollers (IHPCs). The A-side controller (IHP A) and the B-side controller (IHPB) are configured indepen dently . Each IHPC therefore has its own configuration s pace. Both[...]

WXB Ho t-Pl u g 8-2 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual T able 8-1. IHPC Configuration Register Space DID VID 00h 80h PCIST S PCICMD 04h 84h CLASS RID 08h 88h HDR MLT CLS 0Ch 8Ch Base Address 10 h 90 h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 38h B8h Interrupt Pin Interrupt Line 3Ch BC[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 8-3 WXB Hot-Pl ug 8.1.1 Page Number List for the IHPC PCI Register Descriptions Register Page Arbiter SERR Status........ ............. .... ...... .... ....... ... ................. ................. ....... 8-10 Base Address ........ ....... ....... .......... ....... ....... .......... .[...]

WXB Ho t-Pl u g 8-4 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 8.1.4 PCICMD: PCI C ommand Register Address Offs et: 04h-05h Size: 16 bits Default Value: 0000h Attribute: Partial R ead/ Write The PCI command reg ister provides cont rol over the I HPC ’ s ability to gen erate and respond to PCI cycles. When a zero (0) is written to[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 8-5 WXB Hot-Pl ug 8.1.5 PCISTS: P CI S t atus Register Address O ffset: 06h – 07h Size: 16 bits Default Value: 0200h Attrib ute: Partial Read/Wr ite, Stick y The PCI status register is used to r ecord status inform ation for PCI bu s-related events. The definition of each of the bits is g[...]

WXB Ho t-Pl u g 8-6 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual Bits Description 7:0 Revisi on Identifica tion Number This is an 8-bit value that indicates the rev isio n identification number for the IHPC WXB A Steppings: Hardwired V al ue = 00h WXB B0 Step: Hardwired V alue = 01h 8.1.7 C LASS: Class Register Address Offs et: 09 ?[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 8-7 WXB Hot-Pl ug Bits Description 7 Multi-fu nction Device Selects whether this is a multi-function device, that may have altern ativ e configuration layouts. The IHPC is not a mu ltif unction device. Hardwired V alue = 0. 6:0 Conf igur ation L ayout This field identifies the format of the[...]

WXB Ho t-Pl u g 8-8 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual This is a standard PCI co nfiguration register which defines which interrupt request line on the interrupt controller th is function ’ s interrupt pin (s ee register 3DH) is connected to. T he power -up de fa ul t val ue is F Fh . 8.1.15 Interrupt Pin Address Offset: [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 8-9 WXB Hot-Pl ug 11: 8 reserved(0) 7 Enable PCI Configuration Space Access to Hot-Plug Registers. Enables IHPC memory- mapped register access through the ind ex register ( configuration of fs et 50h ) and data port (configur ation of fset 5 4h). 6:2 r eserved (0) 1 r eserved (1) 0 On / Off[...]

WXB Ho t-Pl u g 8-10 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 8.1.21 A rbite r SERR S tat u s Address Offset: 4A Size: 8 bits Default Value: 00h Attribute: Partial R ead/Write Bits Description 7:0 r eserve d (0) 8.1.22 M emory Acces s Index Address Offs et: 50h-53h Size: 32 bits Default Value: 00000000h Attrib ute: Partial Read/W[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 8-11 WXB Hot-Pl ug T ab le 8-2. IHPC Memor Mappe d Register S p ac e Hot-Plug Miscellaneous (RW) Slot Enable (RW) 00h 80h LED Control ( RW) 04 h 84h Hot-Plug Interrupt Input and Clear (RW) 08 h 88h Present 1 bits Present 2 bits Power Faults Switches Hot-Plug Interrupt Mask(RW) 0Ch 8Ch Prese[...]

WXB Ho t-Pl u g 8-12 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 8.2.1 Page Number List for IHPC Memory Mapped Register Descripti ons Reg iste r Page Extended Hot-Plug Miscellaneo us .......... ................. ................. ................. ... 8-18 LED Control.......... ....... .......... ................. ................. [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 8-13 WXB Hot-Pl ug 8.2.3 Hot-Plug Miscell aneous Address Offset: 02h - 0 3h S ize: 16 bits Default Value: 0040h Attribute: Par tial Read/Write Bits Description 15 r eserved (0) 14 Enable SERR on Power Fault. When set, the as sertion of a slot po wer fault caus es a SERR# to be asserted if S[...]

WXB Ho t-Pl u g 8-14 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual for unpopu lated s lots and s lots with open sw itches. The s et of us able LED Cont rol bit s is determined by the strapp ing val ues on the P (A,B)HSIL, P (A,B)HSOL, and P( A,B)HSOC in puts. Unsupported slots in a s ystem do not hav e writeable LED Control bits. LEDs[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 8-15 WXB Hot-Pl ug into this register . Writing a logic 1 will clear the pending interrupt . If there are no other pendi ng interrupts on the bit, the bit will clear . This register takes on a value b a sed on the monitored status of the sl ots and th erefore has no particul ar default val [...]

WXB Ho t-Pl u g 8-16 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual Bits Description 31:30 reserved ( 0) 29 Slot F PR SNT ( 0)#, PCI Present Si gnal 1 28 Slot E PRS NT(0)#, P CI Pr esent Signal 1 27 Slot D PR SNT ( 0)#, PCI Presen t Sig nal 1 26 Slot C PRSNT (0)#, P CI Pr esent Sig nal 1 25 Slot B PRSNT (0)#, P CI Pr esent Sig nal 1 24[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 8-17 WXB Hot-Pl ug 8.2.8 S erial Input Byte Pointer Address O ffset: 11h Size: 16 bits Default Value: 00h Attr ib ute: Read/Write, Read-O nly Used to input a byte into the IHPC input registers. The byte number is written to the pointer. After the Serial Input Busy Statu s is read as a logic[...]

WXB Ho t-Pl u g 8-18 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 8.2.12 H ot-Plug Switch I nterrupt Redirec t Enable Address Offset: 2Ch Size: 8 bits Default Value: 00h Attribute: Read /W rite This register allows th e slo t sw itch change interrupts to be redirected to the S ERR # instead of the INT A#. Bits Description 7:6 r eserv[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 9-1 IFB Register Mapping 9 The IFB internal regis ters are or ganized in to four Functions – LPC/FWH interface bridge, IDE Controll er , USB Host C ontrol ler , and Enhanced Power Man agement. Each Function has its registers divided i nto 1 se t of PC I Confi guration R egister s and one [...]

IFB Regist er Mappi ng 9-2 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 06 – 07h PCISTS PCI Device S tatus R/W 08h RID Revi sion Identifi cation RO 09-0Bh CLASSC Class Code RO 0C – 0Dh – Reserved – 0Eh HEDT Header T ype RO 0F – 3Fh – Reserved – 40 – 43h ACPIBR ACPI Base Addres s Register R/W 44h ACPIEN ACPI E nable R/[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 9-3 IFB Reg ister Mapping 9.2 IDE Conf iguration The IFB PCI fun ction 1 contains an IDE C ontroller capable of standard Progr ammed I/O (PIO) transfers as well as Bus Master transfer capability . It also supports the “ Ultra DMA/33 ” synchron ous DMA mod e of data transf er . 9.2.1 PCI[...]

IFB Regist er Mappi ng 9-4 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual 9.3 U niversal Serial Bus (USB) Configu r ation The IFB integrates an USB Contro llers. The USB Con troller is UHCI 1.1 compliant. It imp lements the root hu b of the US B, which co ntains two ports . The IFB PCI f unction 2 reflects both the Universal S erial Bu[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 9-5 IFB Reg ister Mapping 9.4 SMBus Contro ller Configuration The IFB PCI func tion 3 contains the SMBus Contro ller configur ation space. 9.4.1 SMBus Confi gur ation Registers (Function 3) T able 9-4. PCI Configuration Registers – Function 3 (SMBus Controller Interface ) Configuration Of[...]

IFB Regist er Mappi ng 9-6 Intel ® 460GX Chip se t Software De ve lop er ’ s Manual[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 10-1 IFB Usage Considerations 10 This section talks abo ut the normal usage f or some of th e features in the IFB comp onent. 10.1 Usa ge of 1MIN Timer in Power Managemen t IFB does not support the glob al stan dby timer concept. The determination of a system in activ ity can be done b y us[...]

IFB Usage Cons id er ations 10-2 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual into the sys tem firmwa re by the vend or . This re porting w ill make th ese register locations safe and the OS will not use these locations random ly if a PNP conflicting device is relocatable in those I/O or memory location s. These locations also got to[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 10-3 IFB Usag e Considera tions NOTES: • The Ultra DMA Enable bit s pecifies the current Ultra DMA enabled status: — Disabled by default: This field ne eds to be enabled i n order to t ake advantag e of the IFB Ultra DMA timings. When this field is disabled, the IFB Ultra DMA T imi ng R[...]

IFB Usage Cons id er ations 10-4 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual For IFB IDE T iming Configuration, each o f the following thing s must be deter mined: • Drive T ype: A T API or A T A (non-A T API) • Best D MA Cap ability • Best U ltra DMA Capability O R • Best Multi W ord DMA Capability (if Ultra DMA not su ppor[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 10-5 IFB Usag e Considera tions 10.5.4 Determining a Drive ’ s Best Ultra DMA Cap ability The drive ’ s ultra DMA mode capability and cu rrent conf igur atio n are sp ecif ied in the IDENTIFY_DRIVE buf fer , W ord 88. Software must first check to see that the W ord 88 is valid before de[...]

IFB Usage Cons id er ations 10-6 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual The drive ’ s multi word DMA mode capability and current configu rat ion are specified in the IDENTIFY_DRIVE buffer , W ord s 63 and 65 Software must first check to see that the W ords 64-70 are valid before determin in g the drive ’ s multi word DMA dr[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 10-7 IFB Usag e Considera tions NOTE: T im in g cycle times are defined by the A T A specification. A device that reports a given DMA mode capability must be capable of supporting the minimum DMA cycle time. A drive ’ s Multi W ord DMA or Single W ord DMA speed is the f astest Multi W ord[...]

IFB Usage Cons id er ations 10-8 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual Software at this stage needs to determ ine if at least one of th e above modes is sup ported by the drive. Software should ini tially determine a drive ’ s best PIO w/IORDY capability (PIO4 w/IORDY or PIO3 w/IORDY) in itially . If these PIO w/IORDY modes [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 10-9 IFB Usag e Considera tions 10.5.6 IFB Timing Settings 10.5.6.1 DMA/PIO T iming Settings In Ta b l e 1 0 - 7 , ‘ x ’ =depends on the type of drive ins talled , ‘ 1 ’ =enabled, and ‘ 0 ’ =disabled. Ultra DMA mode settings are completel y independent of the following timings. [...]

IFB Usage Cons id er ations 10-1 0 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual Configurations where a driv e reports a PIO speed much slower than its reported DMA speed require the DMA T iming Enable Only Select bit to be Enabled. NOTES: 1. DMA T iming E nable Only field is in general Disabled. It is only Enabled in cer tain cases [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 10-11 IFB Usag e Considera tions 10.5.6.2 Ultra DMA Timing Settings The following settings apply to Ultra DMA Mod e Settin gs only . 10.5.7 Drive Configurati o n for Selected T imings Once the IFB T iming Modes for DMA, PIO and Ultra DMA have been selected, the Set Features Command (0 x EF)[...]

IFB Usage Cons id er ations 10-1 2 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual Refer to the Set Featur es Command descripti on in the A T A Specif icatio n fo r more information. A drive may only be enabled for a Single DMA capability . In general, if a drive supports a supported Ultra DMA speed, then Ultra DMA is configured for th[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 10-13 IFB Usag e Considera tions 10.5 .7.1 BMIS 1 - Bus Mast er IDE S tatus Regist er 1 (Primary: Bus Ma ster IDE Base I/O Address + Offset 02h) 10.5 .7.2 BMIS 2 - Bus Mast er IDE S tatus Regist er 2 (Secondary: Bus Master IDE Base I/O Address + Offset 0Ah) • The Drive 0 DMA Capab le bit [...]

IFB Usage Cons id er ations 10-1 4 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 10.5.9 Example Configurations This section provides examples of drive configurations on a IFB-based system. 10.5.9 .1 Ex ample #1: Ul tra DMA/33 Configurat ion In the above configuration, since both dr ives support U ltra DMA, Ul tra DMA will be enabled [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 10-15 IFB Usag e Considera tions 10.5. 9.2 Exampl e #2: Mixed Ul tra DMA/33 and Non-ultra D MA/33 Confi guration In the above configuration, Ultra DMA Mode 2 will only be enabled on Drive 0. Non-ultra DMA and Fast PIO support will b e enabled on each drive as well. . 10.5.9.3 Example #3: No[...]

IFB Usage Cons id er ations 10-1 6 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual In the abov e configurat io n, none o f the drives suppo rts Ul tra DMA. On ly Non- ultra D MA and Fas t PIO support will be enabled on each drive. 10.5.10 U ltra DMA System Sof tware Considerations This section outlines some of the key system co nsidera[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 10-17 IFB Usag e Considera tions II. Provide recovery for data transf ers that fail as the result of Ultra DMA/33 Interface CRC Errors: A. Determine that the data transfer command ’ s error sour ce is Ultra DMA/33 Interface CRC error . B. Retry data transfer command when Ultra DMA/33 Inte[...]

IFB Usage Cons id er ations 10-1 8 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual This register enables/disab les bus master capability for the IDE function and pro vides d ir ectio n control for the IDE DMA transfers. This regi ster also provides bits that software uses to indicate DMA capability of the IDE device. 10.5.1 1.3 BMISX ?[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 10-19 IFB Usag e Considera tions 10.6 USB Resume Enable Bit T wo bi ts have been added to the USB Host contro ller fun c tio nality in function 2 of IFB (PCI Register configuration space at Offs et C4h). This register is in the r esume well of this function. USB Resume Enable: (IFB Function[...]

IFB Usage Cons id er ations 10-2 0 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-1 LPC/FWH Interface Configuration 11 The IFB PCI Function 0 contains a LPC/FWH interface, interr upt controller and counter / timers, including the real time clock. The reg ister set as sociated with this Function ality and associated logic is s hown below w ith actu al register d escrip[...]

LPC/FWH Interface Con figuration 11-2 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 1 1.1.3 PCICMD – PCI Command Register (Function 0) Addre ss Of fset: 04 – 05 h Default Value: 0007h Attribute: Read/W rite This 16- bit regist er provides basic control over t he IFB's ability t o respond to PCI cycles. 1 1.1.4 PCISTS – PCI [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-3 LPC/FWH Int erface Confi guration 1 1.1.5 RID – Revision Identification Register (Function 0) Address O ffset: 08h Default Val ue: Stepping Depe ndent Attribute: Read Only This 8 bit register con tains device stepp ing information. W rites to this register h ave no ef fect. 1 1.1.6 C[...]

LPC/FWH Interface Con figuration 11-4 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 1 1.1.8 ACPI Base Address (Function 0) Add ress: 40- 43h Default V alue: 00000001h Attribute: Read/W rite 1 1.1 .9 A CPI En able ( Functi on 0) Add ress: 44h Default Value 00 Attribute: Read/W rite 1 1.1.10 SCI IRQ Routin g Control Add ress: 45h Defaul[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-5 LPC/FWH Int erface Confi guration 1 1.1.1 1 BI OSEN – BI OS En able R egist er (FU NCTION 0 ) Address Offset: 4E-4Fh Default Value: 07C1h Attribute: Read/Wr ite This register is used to imp lem ent pr otect ions to wr ites to firmware (BIOS) ranges. 1 1.1.12 P IRQRC [A:D] – PIRQx R[...]

LPC/FWH Interface Con figuration 11-6 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 1 1.1.13 SerIRQC – Se rial IRQ Control Register (Function 0) Address Of fset: 64h Default V alue: 1 0h Attribute: R/W This register cont rols the Star t Frame Pulse W idth generated on the Serial Interrupt signal (SERIRQ). 1 1.1 .14 TOM – T op of M[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-7 LPC/FWH Int erface Confi guration 1 1.1.15 M ST A T – Miscellaneous S t atus Register (Function 0) Address Offset: 6A – 6B h Default Value: 0000h Attribute: Read/Write This regist er provi des miscella neous statu s and control Functi ons. 1 1.1.16 Deterministi c Latency Control Re[...]

LPC/FWH Interface Con figuration 11-8 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 1 1.1 .17 M GPI OC – Muxed GP IO Contro l (F unctio n 0) Offset: 84-85h Default Value: 0500h Attribute: Read/W rite 1 1.1.18 PDM ACFG – PCI DMA C onfiguration Resister (Function O) Address Offs et: 90-91 h Default Value: 0000h Attribute: Read/W rit[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-9 LPC/FWH Int erface Confi guration These registers provid e the base addr ess for dist ributed DMA slave channel registers, one for each DMA controller . Bits 5:0 are reserved to provide access to a 64 byte I/O space (1 6 bytes per channel). The chann els are accessed using of fset from[...]

LPC/FWH Interface Con figuration 11-1 0 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.1.21 GPIO Base Address (FUNCTION 0) Address: D0- D3h Default V alue: 00000001h Attributes: Read /Write 1 1.1.22 GPIO E nable (FUNCTION 0) Addre ss: D4h Default Value 00h Attributes: Read /Write 1 1.1.23 LPC COM Deco de Ranges (Function 0) Addr e[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-11 LPC/FWH Int erface Confi guration 1 1 .1.24 LPC FDD/LPT Decode Rang es (Function 0) Address : E1h Default Value: 00h Attributes: Read/Write 3 Reserved. 2:0 Decode Range: The following table describes which range to decode for the COMA Port Bit s Decode Range 000 3F8 - 3FF (C OM 1) 001[...]

LPC/FWH Interface Con figuration 11-1 2 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.1.25 LPC Sound Decode Ranges (Function 0) Addr ess: E2h Default Value: 00h Attributes: Read /Write 1 1.1.26 LPC Generic Decode Range (Function 0) Address: E4 -E5h Default Value: 0000h Attributes: Read /Write Bit Description 7:6 Reserved. 5:4 Mic[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-13 LPC/FWH Int erface Confi guration 1 1.1.27 LPC Enables (Function 0) Address : E6-E7h Default V alue: 0000h Attributes: Read/Write 1 1.1.27 .1 Firmware H ub (FWH) D ecode Enable Regist er Address : E3H Default V alue: 0 0H 1 Attributes: Read/Write Bit Description 15 Reserved. This bit [...]

LPC/FWH Interface Con figuration 11-1 4 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.1.27.2 F irmware H ub (FWH) S elect Regi ster Addr ess: E8H Default V alue: 0011223 3H Attributes : Read/Write 5 FWH_E8_EN: This enables decoding 512KB of the FWH memory range starting at 4 GB – 1. 5 MB (FFE80000H) to 4 GB – 1 MB (FFEFFFFFH)[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-15 LPC/FWH Int erface Confi guration 1 1.1.27.3 T est Mode Register Address: FC -FFh Default V alue: 00000000h Attributes: Read/Write 1 1.2 PCI to L PC I/O Sp ace Registers 1 1 .2.1 DMA Re gisters The IFB contains DMA circuitry that incorporates the functionality of two 82C37 DMA control[...]

LPC/FWH Interface Con figuration 11-1 6 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.2.1.2 Dcm – Dma Channel Mode Register (I/ O) I/O Addr ess: Channels 0-3=0Bh ; Channels 4-7=0D6 h Default V alue: B its [7:2]=0; Bits[1:0]=undefined (CPURST or Master Clear) Attribute: Write Only Each channel has a 6-b it DMA Channel Mode Reg i[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-17 LPC/FWH Int erface Confi guration 1 1.2.1.4 WSMB – Write Sin gle Mask Bit (I /O) I/O Address : Channels 0-3 – 0A h; Channels 4-7 – 0D4h Default V alue: B its[ 1:0]=undefined; Bit 2=1; Bits[7:3 ] =0 (CPURST or a Master Clear) Attribute: Write Only A channel's mask bit is aut[...]

LPC/FWH Interface Con figuration 11-1 8 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.2.1.6 Ds – Dma St atus Regis ter (I/O ) I/O Addr ess: Channels 0-3 – 08h; Channels 4 -7 – 0D0h Default V alue: 0 0h Attribute: R ead Only Each DMA controller has a read-only DMA S tatus Register that indicates which channels hav e reached [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-19 LPC/FWH Int erface Confi guration 1 1.2.1.8 DBCNT – Dma Base and Current Count Registers (I/O) I/O Address: DMA Channel 0 – 001h DMA Channel 4 – 0C 2h DMA Channel 1 – 003h DMA Channel 5 – 0C 6h DMA Channel 2 – 005h DMA Channel 6 – 0C Ah DMA Channel 3 – 007h DMA Channel[...]

LPC/FWH Interface Con figuration 11-2 0 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.2.1.1 1 D mc – Dma Master Cl ea r Regist e r (I/O) I/O Addr ess: Channel 0-3 – 00Dh; Channel 4-7 – 0D Ah Default V alue: All bits undefined Attribute: Write Only This software instru ctio n has the same effect as the hardware Reset. 1 1.2.[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-21 LPC/FWH Int erface Confi guration 1 1.2.2.2 Ic w2 – Initialization Command W ord 2 Register (I/O) I/O Address: INT CNTRL-1 – 021h; INT CNTRL-2 – 0A1 h Default V alue: All bits undefined Attribute: Write Only ICW2 is used to initialize the interrupt contro ller with the five most[...]

LPC/FWH Interface Con figuration 11-2 2 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.2.2.4 Icw3 – Initializat ion Command W ord 3 Register (I/O) I/O Address: INT CNTRL-2 – 0A1h Default V alue: All bits undefined Attribute: Write Only On CNTRL-2 (the slave co ntroller), ICW3 is the slave identification cod e broadcast by CNTR[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-23 LPC/FWH Int erface Confi guration 1 1.2.2.7 Oc w2 – Operational Control W ord 2 Register (I/O) I/O Address: INT CNTRL-1 – 020h; INT CNTRL-2 – 0A0 h Default V alue: B it[ 4: 0]=undefined; Bit[7:5]=001 Attribute: Write Only OCW2 controls bot h the Rotate Mode and the End of Interr[...]

LPC/FWH Interface Con figuration 11-2 4 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.2.2.9 Elcr1 – Edge/Level Control Register (I/O) I/O Address: INT CNTRL-1 – 4D0h Default V alue: 0 0h Attribute: Read /W rite ELCR1 regi ster allows IRQ3 - IRQ 7 to be edge or le v el pro gram mabl e o n an i nte rr upt b y in ter rup t basis[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-25 LPC/FWH Int erface Confi guration 1 1.2.2.1 0 Elcr2 – Edge/Level Control Regi ster (I/O) I/O Address: INT CNTRL-2 – 4D 1h Default V alue: 0 0h Attribute: Read/Write ELCR2 regi ster allows IRQ[15,14,1 2:9] to be e dge or level programmab le on an in terrupt by interrupt basis. Note[...]

LPC/FWH Interface Con figuration 11-2 6 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual The T imer Control W ord Register specifies the co unter selection, the operating mode, the coun ter byte programmi ng order an d size of the count v alue, and wheth er the coun ter counts down in a 1 6- bit or binary-cod ed decimal (BCD) format. A [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-27 LPC/FWH Int erface Confi guration Register bit definitions are different during the Counter Latch Command than for a normal T imer Counter Register writ e. Note t hat, If a cou nter is pr ogrammed to read/write two -byte coun ts, a program must no t trans fer contro l between r eading[...]

LPC/FWH Interface Con figuration 11-2 8 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.2 . 4 NMI Re gis te rs The NMI logic incorporates two differen t 8-bit registers. The CPU reads the NMISC Reg ister to determine the NMI source ( bit s set to a 1). After the NMI interrupt routine process es th e interrupt, software clears the N[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-29 LPC/FWH Int erface Confi guration 1 1.2.4.2 NmiEN – Nmi Enable Register (Shared with Real-time Clock Index Register) (I/O) I/O Address: 070h Default V alue: B it[ 6:0]=undefined; Bit 7=1 Attribute: Write Only This port is shared with th e real-time clock. Do not m odify the contents[...]

LPC/FWH Interface Con figuration 11-3 0 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.2.5.3 RTCEI – Real-time Clock Extended Index Register (I/O ) I/O Addr ess: 072h Default V alue: U nknown Attribute: Write Only The index port f or accesses to the R TC extended RAM bank. 1 1.2.5.4 RTCED – Real-time Clock Extended Dat a Regis[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-31 LPC/FWH Int erface Confi guration 1 1.2.6.2 APMS – Advanced Power Management S tatus Port (I/O) I/O Address: 0B3h Default V alue: 0 0h Attribute: Read/Write This register passes status information between the OS and the SMI handler . The IFB operation is not effected by the data in [...]

LPC/FWH Interface Con figuration 11-3 2 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.2.7.2 Power Management 1 Enable Address Of fset: 02-03h Attributes: R ead/W r ite Default V alue: Bit 10: Undefined, All other b its ‘ 0 ’ Size: 16 bits 1 1.2.7.3 Power Management 1 Control Address Of fset: 04-05h T ype: Read/Write Default V[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-33 LPC/FWH Int erface Confi guration 1 1.2.7.4 Power Management 1 T imer Address O f fset: 08-0Bh Attributes: Read Only Default V alue: 00000000h Size: 32 bits 1 1.2.7.5 General Purpos e 0 S t atus Address O f fset: 0C-0Dh Attributes: Read/Write Default V alue: 0800h Size: 16 bits When a[...]

LPC/FWH Interface Con figuration 11-3 4 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.2.7.6 General Purpose 0 Enable Address Of fset: OE-0Fh Attributes: R ead/W r ite Default V alue: 0000h Size: 16 bits Bit Description 15:12 Reserved. 11 PWR_FAIL: This bit will be set t o 1 when a power failure occurs. This is defi ned as either [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-35 LPC/FWH Int erface Confi guration 1 1.2.7.7 General Purpos e 1 S t atus Address O f fset: 16-17h Attributes: Read/Write Default V alue: 0000h Size: 16 bits When any bit is set in this reg ister, and the corresponding bit is enabled in the General Purpose 1 Enable register , an SCI and[...]

LPC/FWH Interface Con figuration 11-3 6 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.2.8.1 Global Co ntrol and Enable Address Of fset: 1A-1Bh Attributes: R ead/W r ite Default V alue: B its 8 Undefined, Bit 3 ‘ 1 ’ , All other bits ‘ 0 ’ Size: 16 bits Bit Description 15:13 Reserved. 12 ACPI_TMR_EN: If not using A CPI (SC[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-37 LPC/FWH Int erface Confi guration 1 1.2.8.2 Global St atus Register Address Of fset : 1 Ch-1Dh Attributes: Read/Write Default V alue: 0000h Size: 16 bits 1 1.2.9 G ene ra l P urpo se I/O Re gis t e rs For the fol lowing GPIO Registers , bits 28:1 6 refer t o the Muxed GPIO si gnal s, [...]

LPC/FWH Interface Con figuration 11-3 8 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.2.9.1 GP Output Offset : 00-03h Attribute: Read /W rite Default V alue: 00000000h Size: 32 bits 1 1.2.9.2 GP Data Offset : 04-07h Attribute: Read /W rite Default V alue: 00000000h Size: 32 bits 25 GPIO[19] 5 GPIO[5] 24 GPIO[18] 4 GPIO[4] 23 Rese[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-39 LPC/FWH Int erface Confi guration 1 1.2.9.3 GP TTL Offse t: 08- 0Bh Attribute: Read/Write Default V alue: 00000000h Size: 32 bits 19:16 Muxed Data: If a data bit is programmed to be an output, then this bit can be updated by software to drive a value on the output pin. If the data bit[...]

LPC/FWH Interface Con figuration 11-4 0 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 1 1.2.9.4 GP Blink Of fs et : 0C- 0F h Attribute: Read /W rite Default V alue: 00000000h Size: 32 bits 1 1.2.9.5 GP Lock Offset : 10-13h Attribute: Read /W rite Default V alue: 00000000h Size: 32 bits 1 1.2.9.6 GP Invert Offset : 14-17h Attribute: R[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 11-41 LPC/FWH Int erface Confi guration 1 1.2.9.7 GP SMI Offse t: 1C-1 Fh Attribute: Read/Write Default V alue: 00000000h Size: 32 bits 1 1.2.9.8 GP Pulse Offse t: 20- 23h Attribute: Read/Write Default V alue: 00000000h Size: 32 bits 1 1.2.9.9 GP Core Offse t: 24- 27h Attribute: Read/Write [...]

LPC/FWH Interface Con figuration 11-4 2 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 12-1 IDE Configuration 12 The IFB PCI Function 1 co ntains an I DE C ontroller capable o f Pro grammed I/O ( PI O) transfers as well as Bus Master tran sf er capability . I t also supports the “ Ultra D MA/33 ” synchron ous DMA mode of data tran sfer . The register set ass ociated with [...]

IDE C onfi gurati on 12-2 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 12.2.1 VID – V endo r Identification Reg ister (Function 1) Add r ess Offse t : 00 – 01h Default V alue: 8086h Attribute: Read only The VID Register cont ains the vendor identification number . This register , along with the Device Identification Register, uni[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 12-3 IDE Co nfiguration 12.2.4 PCISTS – PCI Device S tatus Register (Function 1) Address Of fset: 0 6 – 07h Default V alue: 0280h Attribute: Read/Write PCISTS is a 16-bit status register for the IDE interface Fu nction. The register also indicates the IFB's DEVSEL# signal timing. 1[...]

IDE C onfi gurati on 12-4 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 12.2.6 ML T – Master Latency Timer Re gister (Function 1) Addr ess Offset: 0Dh Default V alue: 0 0h Attribute: Read /W rite ML T controls the amou nt of time IFB, as a bus master , can burst data on the PCI Bus. The coun t value is an 8 bit quantity . However, M[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 12-5 IDE Co nfiguration 12.2.8 SVID – Subsystem V endo r ID (Function 1) Address : 2C-2Dh Default V alue: 0000h Attribute: Read only 12.2.9 SID – Subsystem ID (Function 1) Address : 2E-2Fh Default V alue: 0000h Attribute: Read only 12.2.10 IDETIM – IDE T i ming Register (F unction 1) [...]

IDE C onfi gurati on 12-6 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 12.2.1 1 SIDETIM – Slave IDE T iming Register (Function 1) Address Of fset: 44h Default V alue: 0 0h Attribute: R ead /W rite only This register controls th e I FB ’ s IDE interface and selects the timing characteristics for the slav e drives on each IDE chann[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 12-7 IDE Co nfiguration 12.2.12 DMACTL – Synchronous DMA Control Register (Function 1) Address Of fset: 4 8h Default V alue: 0 0h Attribute: Read/Write This register en ables each individual channel and driv e for Synchron ous DMA transfers. For no n- synchron ous DMA op eration, this reg[...]

IDE C onfi gurati on 12-8 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 12.2.13 SDMA TIM – Synchronous DMA Timing Register (Function 1) Address Of fset: 4A-4Bh Default V alue: 0000h Attribute: R ead /W rite only This register con trols the timings used by each Synchrono us DMA enabled device. For non- sy nc hron ous DM A op e rati o[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 12-9 IDE Co nfiguration NOTES: 1. T able 12-3 assumes that if the attached slave drive i s Mode 0 or not present, the SITRE bit is ‘ 0 ’ . 2. T able 12-3 assumes that 25 MHz is not supported as a t arget PCI system speed. If the DMA Timing Enable Only (DTE) bit has been enabled for that[...]

IDE C onfi gurati on 12-1 0 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 12.3 .2 BMIS x – Bus Master ID E S tat us Register (I /O) Address Off s et: P rimary Chann el – Base + 02h; Secondar y Chann el – Ba se + 0 Ah Default V alue: 0 0h Attribute: Read /Write Clear This regist er provid es status information about the IDE devi[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 12-11 IDE Co nfiguration 12.3.3 BMIDTPx – Bus Master IDE Descr iptor T able Poi nter Register (I/O) Address Of fset : Primary Channel – Base + 04 h; Second ary Channel – Base + 0 Ch Default V alue: 00000000h Attribute: Read/Write This register provides the base m emory address of the [...]

IDE C onfi gurati on 12-1 2 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 13-1 Universal Serial Bus (USB) Configuration 13 The IFB integrates one USB Controller . The USB Controller is UHCI 1.1 com pliant and implement s the root hub of the USB, which con tains t wo ports. The IFB PCI Function 2 reflects the USB Host and Root Hubs, with 2 con nected USB ports. Th[...]

Univ ersa l Seria l Bus ( USB) Co nfig ur ation 13-2 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 13.2 USB Host Contro ller Register Descriptions (PCI Funct ion 2) This section describes in d etail the registers associated with the I FB USB Host Controller Functions. This includes UHCI compatible registers and Legacy Keyboard registe[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 13-3 Univer sal Se rial Bus ( USB) Co nfiguration 13.2.4 PCISTS – PCI Device S tatus Register (Function 2) Address O f fset: 06-07h Default V alue: 0280h Attribute: Read/Write DSR is a 16-bit status re gister that reports the occurr ence of a PCI maste r-abor t by the USB HC module or a P[...]

Univ ersa l Seria l Bus ( USB) Co nfig ur ation 13-4 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 13.2.6 CLASSC – Cl ass Code Register (Function 2) Address Of fset: 0A-0Bh Default V alue: 0 C03h Attribute: Read only This register identif ies the Base Class Code, Sub- Class Code, and Device Prog ramming interface for IFB P CI Functi[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 13-5 Univer sal Se rial Bus ( USB) Co nfiguration 13.2.9 USBBA – USB I/O Sp ace Base Address (Function 2) Address O f fset: 20-23h Default V alue: 00000001h Attribute: Read/Write This register contains the base address of the USB I/O Registers. 13.2.10 SVID – Subsystem V endo r ID (Func[...]

Univ ersa l Seria l Bus ( USB) Co nfig ur ation 13-6 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 13.2.13 INTPN – Interrupt Pin (Function 2) Addr ess Offset: 3Dh Default V alue: 0 4h Attribute: Read only This register indi cates wh ich P CI interrupt pin is used for the USB module int erru pt. The USB interrupt is internally ORed t[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 13-7 Univer sal Se rial Bus ( USB) Co nfiguration Bit Description 15 End OF A20GA TE Pass Through St atus (A20PTS) – R/WC. This bit is set to 1 to indicate that the A20GA TE pass-through sequence has ended. This bit will only be set if bit 7 of this register is also set. Software must use[...]

Univ ersa l Seria l Bus ( USB) Co nfig ur ation 13-8 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 13.2.17 USBREN – USB Resume Enable Address Of fset: C4h Default V alue: 0 0h Attribute: Read /W rite 13.3 USB Host Contro ller I/O Sp ace Registers 13 .3.1 US BCMD – USB Command Register (I/O) I/O Addr ess: Base + (00-01h) Default V [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 13-9 Univer sal Se rial Bus ( USB) Co nfiguration 3 Enter Globa l Suspend Mode (E GSM). 1=Host Controller enters t he Global Suspe nd mode. No USB transactions occur during this time. The Host Controller is able to receive resume signals from USB and interrupt the sys tem. Software resets t[...]

Univ ersa l Seria l Bus ( USB) Co nfig ur ation 13-1 0 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 13 .3.2 US BSTS – USB S t atus R egister (I/ O) I/O Addr ess: Base + (02-03h) Default V alue: 0000h Attribute: Read /Write Clear This register indicates pen ding interrupts and vario us states of the Hos t Controller . The status re[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 13-11 Univer sal Se rial Bus ( USB) Co nfiguration 13.3.4 FRNUM – Fram e Nu mber Reg ist er (I/ O) I/O Address : Base + (06- 07h) Default V alue: 0000h Attribute: Read/Write (W rites must be W ord W rites ) Bits [10:0] of this register contain the curr ent frame number which is included i[...]

Univ ersa l Seria l Bus ( USB) Co nfig ur ation 13-1 2 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual required by the USB specification . It ’ s initial programmed valu e is sy stem dependent based on the accuracy of hard ware USB clock and is initialized by s ystem BIOS. It may be r eprogrammed by USB system software at any time. I[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 13-13 Univer sal Se rial Bus ( USB) Co nfiguration 12 Suspend – R/W . 1=Port in suspend state. 0=Port not in sus pend state. This bit should not be written to a 1 if global suspend is active (bit 3=1 in the US BCMD registe r). Bit 2 and b it 12 of this register define the hub states as fo[...]

Univ ersa l Seria l Bus ( USB) Co nfig ur ation 13-1 4 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 14-1 SM Bus Controller Configuration 14 The IFB PCI Function 3 contains the SMBus Con troller configuration space. 14.1 SM Bu s Configurat ion Registers (F unction 3) Configur ation Offset Mnemonic Reg ister Register Access 00 – 01h VID V endor Identification RO 02 – 03h DID Device Iden[...]

SM Bu s Controlle r Configu ration 14-2 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 14.2 System Management Register D escriptions This section describ es in detail the registers as sociated with the IFB System Manag ement Function. 14.2.1 VID – V endo r Identification Register (F unction 3) Add r ess Offse t : 00 – 01h Default V[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 14-3 SM Bus Co ntroller Confi guration 14.2.4 PCISTS – PCI Device S tatus Register (Function 3) Address O f fset: 06-07h Default V alue: 0280h Attribute: Read/Write DSR is a 16-bit status regis ter that reports the occurr ence of a PCI targ et-abort when the Sys tem Management Function is[...]

SM Bu s Controlle r Configu ration 14-4 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 14.2.6 CLASSC – Cl ass Code Register (Function 3) Address Of fset: 09-0Bh Default V alue: 0C0500h Attribute: Read only This register identif ies the Base Class Code, Sub- Class Code, and Device Prog ramming interface for IFB P CI Functi on 3. 14.2.[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 14-5 SM Bus Co ntroller Confi guration 14.2.9 SID – Subsystem ID (Function 3) Address : 2E-2Fh Default V alue: 0000h Attribute: Read only 14.2.10 INTLN – Interrupt Line Register (Fun ction 3) Address Of fset: 3 Ch Default V alue: 0 0h Attribute: Read/Write Software prog rams this regist[...]

SM Bu s Controlle r Configu ration 14-6 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 14.2.13 smbsl vc – SMBus Slave Command (Function 3) Address Of fset: 41h Default V alue: 0 0h Attribute: Read /W rite 14.2.14 smbshdw1 – SMBus S lave Shadow Port 1 (Func tion 3) Address Of fset: 42h Default V alue: 0 0h Attribute: Read /W rite 14[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 14-7 SM Bus Co ntroller Confi guration 1 4 . 3 . 1 s m b h s ts ts – SMBus Host St atus Register (I/O) I/O Address: B ase + (00 h) Default V alue: 0 0h Attribute: Read/Write This register prov ides status information concerning the SMBus contr oller host interface. 14.3.2 smbslvst s – S[...]

SM Bu s Controlle r Configu ration 14-8 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 14.3.3 smbhstcnt – SMBus Host Con trol Register (I/O) I/O Addr ess: Base + (02h) Default V alue: 0 0h Attribute: Read /W rite The control register is used to enable SMBus controller host interface Function s. Reads to this register clears the host [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 14-9 SM Bus Co ntroller Confi guration 14.3.4 smbhstcmd – SMBus Host Command Register (I/O ) I/O Address: B ase + (03 h) Default V alue: 0 0h Attribute: Read/Write This register is transmitted by the SMBu s co ntroller host interface in the command field of the SMBus pr otocol. 14.3.5 smb[...]

SM Bu s Controlle r Configu ration 14-1 0 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 14.3.7 smbhst dat1 – SMBus Host Dat a 1 Register (I/O) I/O Addr ess: Base + (06h) Default V alue: 0 0h Attribute: Read /W rite This register is transmitted by the SMBus controller host interface in the Data1 field of the SMBus prot oco l. 14.3.8[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 14-11 SM Bus Co ntroller Confi guration 14.3.9.1 10 .3.10. smbshdw cmd – SMBus Shadow Command Register (I/O) I/O Address: B ase + (09 h) Default V alue: 0 0h Attribute: Read only This register is us ed to store command va lues for external SMBus master acces ses to the ho st slave and sla[...]

SM Bu s Controlle r Configu ration 14-1 2 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 15-1 PCI/LPC Bridge Description 15 15.1 PCI In terface The IFB incorpo rates a fully PCI Bus compatible master and slav e interface. As a PCI mas ter , the IFB runs cycles o n behalf of DMA, Bus Master I DE, and USB. The IFB implements an internal arbiter to request the PCI bus IDE and USB [...]

PCI/LPC Br idge Desc ription 15-2 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual internal interrupts are used f or in ternal Functions o nly . IRQ2 is used to cascade the two controllers together and is not available to the user . IRQ0 is u sed as a system timer interrupt an d is tied to Interval T imer 1, Counter 0. IRQ13 is connected[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 15-3 PCI/L PC Br idge Des crip tion For CNTRL-2, ICW3 is the slave identification cod e used during an interrupt acknowledge cycle. CNTRL-1 bro adcasts a code to CNTR L-2 over three in ternal cascade lines if an IRQ[x] line fro m CNTRL-2 won the prio rity arbitration o n the master contr ol[...]

PCI/LPC Br idge Desc ription 15-4 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual perform a non -specific EOI oper ation at the trailin g edge of the last interrupt acknowledge puls e. Note that fr om a system s tandpoint, this mode s hould be us ed only when a nested mu lti-lev el interrupt st ru cture i s no t r equi r ed w it hi n a [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 15-5 PCI/L PC Br idge Des crip tion 15.2.3.4 Spec i fic Rot ation (Specif i c Priority) The programmer can change priorities by programming the bottom priori ty and thus fixing all other priorities. For example, if IRQ5 is programmed as the bottom priority device, then IRQ6 will be the high[...]

PCI/LPC Br idge Desc ription 15-6 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 15.2.5 Edge and Level T r iggered Mode This mode is p rogrammed using bit 3 in ICW1. With IFB this bit is disabled an d a new register for edge and lev el trigger ed mode select ion, per inte rrupt in put, is in cluded. This is the Edge /Level control Regi[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 15-7 PCI/L PC Br idge Des crip tion Thus, any interrupts may b e selectively enabled b y load ing the Mas k Register with the ap pro priate pattern. W i thout Special Mask Mode, if an interrupt service routine acknowledges an interrup t with out issuing an EOI to clear the IS bit, the inter[...]

PCI/LPC Br idge Desc ription 15-8 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual individual PIRQ x# li ne to any one of 1 1 IRQ inputs. The assi gn ment is pro g rammable throu gh t he PIRQx Rout e Cont rol regist ers. On e or more PI RQx# lines can be routed t o the sam e IRQx inpu t. If interrup t steeri ng is not require d, the Rou [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 15-9 PCI/L PC Br idge Des crip tion During the Sample phase, the devi ce driv es SERIR Q low if the corresponding interr upt sig n al is low . If th e co rres pon ding in terrupt is h igh, then the dev i ces will tri-s tate the SER IRQ sign al. I t will remain high due to pu ll-up res istor[...]

PCI/LPC Br idge Desc ription 15-1 0 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 15.4 T imer/Counters The IFB contains three cou nters that are equivalent to tho se found in the 82C54 prog rammable interval timer . The thr ee counters are contained in one IFB timer unit, referred to as T imer-1. Each counter out put provi des a key [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 15-11 PCI/L PC Br idge Des crip tion The Counter Latch Command latches the curren t count so that it can b e read by the sys tem. The countdown pr ocess continues. The Read Back Command reads the c ount value, programmed mo de, the current s tate of the OUT pins, and the state of the Null C[...]

PCI/LPC Br idge Desc ription 15-1 2 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual If a counter is prog rammed to read/write two-b yte counts, the following precaution applies: A program mus t not tr ansfer control between wri ting th e first and second by te to anot her routine which also writes in to that same counter . Otherwise, t[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 15-13 PCI/L PC Br idge Des crip tion If a counter is programmed to read/write two- byte counts, a p rogram must not transfer control between reading the f irst and second by te to another rou tine which also reads fro m that same counter . Otherwise, an incorr ect count will be read. 15.4.1[...]

PCI/LPC Br idge Desc ription 15-1 4 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual The time and calendar d at a sh ould matc h the dat a mode (BCD or bi nary) and hour mode (1 2 or 24 hour) as selected in r egister B. It is up to the programmer to make sure that da ta stored in these locations is within the reasonable v alues ranges a[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 15-15 PCI/L PC Br idge Des crip tion The extended RAM bank is also accessed using an indexed scheme . I/O address 72h is used as the address pointer and I /O address 73h is used as the data reg ister . Index address es above 1 27h ar e not valid. 15.5.1. 1 Register A Address Offset: 0Ah Def[...]

PCI/LPC Br idge Desc ription 15-1 6 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual 15.5.1. 2 Register B Add r ess Offse t : 0Bh Default V alue: X 0000XXXb Attribute: Read /W rite This regist er is used fo r general co nfigurati on of th e R TC Function s. 15.5.1. 3 Register C Add r ess Offse t : 0Ch Default V alue: 0 0h Attribute: Rea[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 15-17 PCI/L PC Br idge Des crip tion 15.5.1. 4 Register D Address Offset: 0Dh Default V alue: NA - This r egister is not af fected by any sys tem reset signal. Attribute: Read/Write This regis ter is used f or various flags . 15.5 .2 RTC Up date Cy c le An update cycle occu rs once a second[...]

PCI/LPC Br idge Desc ription 15-1 8 Intel ® 460 GX Chip se t Software De ve lop er ’ s Manual[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 16-1 IFB Power Management 16 16.1 Overview IFB is designed fo r desktop sys tems, and includ es the following power man agement features for the de skt op des ign: 1. Compliance with industry standard specifications : APM Rev 1.2 ACPI Rev 1.0 Energy St ar (30W i dle) PCI Power Management Re[...]

IFB Power Manage men t 16-2 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 16.2 IFB Power Planes 16.2.1 Power Plane Descripti ons The IFB contains three po wer planes: 16.2.2 SMI# Generation T able 1 6-2 shows which sources can cause the IFB to drive SMI# active. When oper ating with an ACPI-based Operating System, som e of the causes [...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 16-3 IFB Powe r Management 16.2.3 SCI Generation In an ACPI environment, an SC I (syst em control i nterrup t) must be generated for any even t that must be handl ed by ACPI s oftware. If the SCI_EN bit is set, the IF B will gene rate an SCI bas ed on the sources listed b elow in T able 16-[...]

IFB Power Manage men t 16-4 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual 16.2.5 ACPI Bits Not Implemen te d by IFB Many ACPI registers and bits are optional, an d do not have to b e implemented for a s tandard desktop design. T able 1 6-4 sh ows whi ch bits are not implemented by IFB. 16.2.6 Entry/Exit for the S4 and S5 St ates As pa[...]

Intel ® 460G X Chipset So ftware Dev eloper ’ s Manua l 16-5 IFB Powe r Management A W ake event will cause an exit from th e Soft-Off state. The wake events that can wake from the S5 state are: 16.3 Han dling of Power Failures in IFB A power failure is defined as any one of the followin g: • PWROK goes low and the IFB did not y et cause SUSB [...]

IFB Power Manage men t 16-6 Intel ® 460GX Chipse t Software De ve lop er ’ s M anual[...]