Intel 830 manual

Intel ® Pentium ® D Processor 800 Δ Sequence Datasheet – On 90 nm Process in the 775- land LGA Package and supporting Intel ® Extended Memory 64 T echnology Φ February 2006 Document Number: 307506-003[...]

2 Datasheet Contents INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WI TH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIE D, BY ESTOPPEL OR OT HER WISE, TO ANY INTELLECTUAL PROP ER TY RIGH TS IS GRANTED BY THIS DOCUMENT . EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHA TSOEVER[...]

Datasheet 3 Contents Contents 1 Introduction ................ ............. ................ ............. ................ ................ ............. ........... ............... ... 11 1.1 Terminology .............. ............. ................ ............. ................ ............. ................ ............ ....... 12 1.1.1 Proces[...]

4 Datasheet Contents 5.2 Processor Thermal Features ....... ... ... ... .... ... ... ... .... ... ... ... .... ... ............. ... ... ... .... ... ... ... ... .... ... 79 5.2.1 Thermal Monitor.... ... .... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ............. ... ... ... .... ... ... ... ... .... ... 79 5.2.2 On-Demand Mode ..[...]

Datasheet 5 Contents Figures 2-1 VCC Static and Transient Tolerance for 775 _VR_CONFIG_05A Pentium D Processor ............ 22 2-2 VCC Static and Transient Tolerance for 775 _VR_CONFIG_05B Pentium D Processor ............ 24 2-3 VCC Overshoot Example Waveform ............. ............. ................ ................ ................ ...........[...]

6 Datasheet Contents Tables 1-1 References ............. ............. ................ ............. ................ ............. ............. ................ . ............... 13 2-1 Voltage Identification Definit ion .............. ................ ............. ................ ................ ............. ... ....... 17 2-2 Processor DC [...]

Datasheet 7 Contents Revision History § Revision Number Description Date -001 • Initial release May 2005 -002 • Added Balanced T e chnology Extended (BTX) Type I Boxed Processor S pecifications chapter . October 2005 -003 • Added Intel ® Pentium ® D processor 805 spe cifications. • Updated THERMTRIP# signal description in T able 4-3. Feb[...]

8 Datasheet Contents[...]

Datasheet 9 Contents Intel ® Pentium ® D Processor 800 Sequence Features The Intel ® Pentium ® D processor delivers Intel's advanced, po werful processors for desktop PCs that are based on the Intel NetBurst ® microarchitecture. The Pentium D processo r is designed to del i ver performance across applications and usages where end-us ers c[...]

10 Datasheet Contents[...]

Datasheet 11 Introduction 1 Introduction The Intel ® Pentium ® D processor extends Intel's Desktop dual-core pro duct li ne. The Pentium D processor uses Flip-Chip Land Gri d Array (FC- LGA4) package techno logy , and plugs in to a 775- land LGA socket, referred to as the LGA775 socket. The Pentiu m D processor, like the Intel ® Pentium 4 p[...]

12 Datasheet Introduction 1.1 T erminology A ‘#’ symbol after a signal name ref e rs to an ac tive lo w signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low , a reset has been requested. Conversely , when NMI is high, a nonmaskable int e rrupt has occurred. In th e case of signals where [...]

Datasheet 13 Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document: § T able 1- 1. References Document Document Location Intel ® Pentium ® D Processor and Intel ® Pentium ® Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines http://developer .intel[...]

14 Datasheet Introduction[...]

Datasheet 15 Electrical Specifications 2 Electrical Specifications This chapter describes the elect rical characteristics of the pro cessor interfaces and signals. DC electrical characteris tics are provided. 2.1 Power and Ground Lands The Intel ® Pentium ® D processor has 226 VCC (power) and 273 VSS (grou nd) inputs for on-chip power distributio[...]

16 Datasheet Electrical Specifications 2.2.3 FSB Decoupling The Pentium D processor package in tegrates signal termination on the die as well as incorporates high frequency decoupling capacitan ce on the pro cessor package. Decoup ling must also be provided by the system baseboard for proper G TL+ bus operation. 2.3 V olt a ge Identification The V [...]

Datasheet 17 Electrical Specifications T able 2-1. V olt age Identification Definition VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VI D1 VID0 VID 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 [...]

18 Datasheet Electrical Specifications 2.4 Reserved, Unused, FC and TESTHI Signals All RESER VED lands must remain unco nnected. Connection of these lands to V CC , V SS , V TT , or to any other signal (including each other) can re sult in component malfunction or incomp atibility with future processors. See Chapter 4 for a land listing of the proc[...]

Datasheet 19 Electrical Specifications 2.5 V olt age and Current S pecifications 2.5.1 Absolute Maximum and Minimum Ratings Ta b l e 2 - 2 specifies absolute maximum and min imu m ratings. W ithi n functional operation limits, functionality and long-t erm reliability can be expected. At conditions outsi de functional operation co ndition limits, b [...]

20 Datasheet Electrical Specifications T able 2-3. V olt age and Current Specifications Symbol Parameter Min T yp Max Unit Notes VID range VID 1.200 — 1.400 V 1 NOTES: 1. Individual processor VID values may be calibrat ed during manufactu ring such that two devices at the same speed may have diffe rent VID settings. Processor number Core Frequenc[...]

Datasheet 21 Electrical Specifications 5. 775_VR_CONFIG_05A and 775_V R_CONFIG_05B refer to voltage regulator configurations that are defined in the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socke t . 6. Refer to Table 2-4 and Figure 2-1 for the minimum, typical, a nd maximum V CC allowed for a given current. The processor s[...]

22 Datasheet Electrical Specifications NOTES: 1. T he loadline specification includes bot h static and transi ent limits except for overshoot allowed as shown in Section 2.5.3 . 2. T his loadline specific ation shows the deviation from t he VID set point. 3. The loadlines specify voltage limits at the di e measured at the VCC_SENSE and VSS_SENSE la[...]

Datasheet 23 Electrical Specifications T able 2-5. V CC St atic and T ransient T olerance for 775_VR_CONFIG_05B Pentium D Processor Icc (A) V oltage Deviation from VID Setting (V) 1, 2, 3 NOTES: 1. The loadline specification inclu des both static and transient limits exce pt for over shoot allowed as shown in Section 2.5.3 . 2. This table is intend[...]

24 Datasheet Electrical Specifications Figure 2-2. V CC St atic and T ransient T olerance for 775_VR_CONFIG_05B Pentiu m D Processor VID - 0.000 VID - 0.025 VID - 0.050 VID - 0.075 VID - 0.100 VID - 0.125 VID - 0.150 VID - 0.175 VID - 0.200 VID - 0.225 0 1 02 03 04 05 06 07 08 09 0 1 0 0 1 1 0 1 2 0 Icc [A] Vcc [V] Vcc Maxim um Vcc Typical Vcc Mini[...]

Datasheet 25 Electrical Specifications 2.5.3 V CC Overshoot S pecification The Pentium D processo r can tolerate s hort transient overs hoot events where V CC exceeds the VID voltage when transitioning from a high-to-low curren t load condition. This overshoot cannot exceed VID + V OS_MAX (V OS_ MAX is the maximum allowable oversh oot vo ltag e). T[...]

26 Datasheet Electrical Specifications 2.5.4 Die V oltage V alidation Overshoot events on the processor must meet the specifications in Ta b l e 2 - 6 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events th at are < 10 ns in durat ion may be ignored. These measurements of processor die lev el oversh oot must be taken with a b[...]

Datasheet 27 Electrical Specifications Ta b l e 2 - 8 outlines the signals which include on-die terminat ion (R TT ). Open drain signals are also included. Ta b l e 2 - 9 provides signal reference voltages. T able 2-7. FSB Signal Group s Signal Group T ype Signals 1 NOTES: 1. Refer to Se ction 4.2 for signal descriptions. G TL+ Common Clock Input S[...]

28 Datasheet Electrical Specifications 2.6.2 G TL+ Asynchronous Signals The signals A20M#, IGNNE#, INIT#, SMI#, a nd STPCLK# utilize CMOS input buffers. G TL+ asynchronous si gnals follow t he same DC requirem ents as G TL+ signals; however , the outputs are not actively driven high (duri ng a logi cal 0 to 1 transition) by the processor . G TL+ as[...]

Datasheet 29 Electrical Specifications 2.6.3 FSB DC Specifications The processor front side bus DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated . T able 2-10. BSEL[2:0] and VID[5: 0] Signal Group DC Specifications [...]

30 Datasheet Electrical Specifications T able 2-12. PWRGOOD Input and T A P Signal Group DC Specifications Symbol Parameter Min Max Unit Notes 1, 2 NOTES: 1. Unless otherwise noted, all specifications in this t able apply to all processor frequencies. 2. All outputs are open dr ain. V HYS Input Hysteresis 200 350 mV 3 3. V HYS represents the amount[...]

Datasheet 31 Electrical Specifications 2.6.3.1 G TL+ Front Si de Bus Specifications In most cases, termination resist ors are no t requ ired as these are integr ated into the processor silicon. See Ta b l e 2 - 8 for details on which G TL+ signals do not include on-di e term ination. V alid high and low levels are determined by the input buffers by[...]

32 Datasheet Electrical Specifications 2.7 Clock S pecifications 2.7.1 FSB Clock (BCLK[1:0 ]) and Processor Clocking BCLK[1:0] directly controls the FS B interface speed as well as the core frequency of the processor . As in previous generation processors, the Pentium D processor core frequency is a multiple of the BCLK[1:0] frequency . The process[...]

Datasheet 33 Electrical Specifications 2.7.3 Phase Lock Loop (PLL) and Filter V CCA and V CCIOPLL are power sources required by the PL L clock generators for the Pentium D processor. Since these PL Ls are analog in nature, they require quiet power suppl ies for min imu m jitter . Jitter is detrimental to the system: it degrad es external I/O timing[...]

34 Datasheet Electrical Specifications NOTES: 1. Diagr am not to scale. 2. No specifications for frequenc ies beyond fcore (cor e fre quency). 3. fpeak, if existent, should be less than 0.05 MHz. 4. fcore r epresents the maximum core frequency supported by the platform. § Figure 2-4. Phase Lock Loop (PLL) Filter Requiremen ts 0 dB –28 dB –34 d[...]

Datasheet 35 Package Mechanical Specifications 3 Package Mechanical Specifications The Intel ® Pentium ® D processor is packaged in a Flip-C hip Land Grid Array (FC-LGA4) package that interfaces with the moth erboard via an LGA 775 socket. The package consists of a processor core mounted on a substrate land-carrier . An integr ated heat spreader [...]

36 Datasheet Package Mechanic al Specifications Figure 3-2. Processor Package Drawing 1[...]

Datasheet 37 Package Mechanical Specifications Figure 3-3. Processor Package Drawing 2[...]

38 Datasheet Package Mechanic al Specifications Figure 3-4. Processor Package Drawing 3[...]

Datasheet 39 Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contai n components on the substrate that defin e component keep-ou t zone requirements. A therm al and mechanical solution design must not intrud e into the required keep- out zones. Decoupling capacito rs are typically moun ted to either the to[...]

40 Datasheet Package Mechanic al Specifications 3.5 Package Insertion S pecifications The Pentium D processor can be inserted int o and rem oved from a LGA775 socket 15 times. The socket should m eet the LGA775 req uirements detailed in the LGA775 Socket Mechanical D esign Guide . 3.6 Processor Mass S pecification The typical mass of the Pentium D [...]

Datasheet 41 Package Mechanical Specifications Figure 3-6. Proces sor T op-Side Marking Example ( Intel ® Pentium ® D Processor 805) ATPO S/N Processor Num ber/ S-Spec/ Country of Assy INTEL XXXXXXXX 2.66GHZ/2M/533/05A 805 SLxxx [COO] [FPO] [e4] m © ‘0 4 Frequency/L2 Cache/Bus/ 775_VR_CO NFIG_05x FPO 2- D Mat r i x Ma rk Unique Unit Identifi e[...]

42 Datasheet Package Mechanic al Specifications 3.9 Processor Land Coordinates Figure 3-7 shows the top view of the processor land coordinates. The coordinates are referred to throughout the docum e nt to id enti fy processor lands. . § Figure 3-7. Processor Land Coor dinates, T op View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2[...]

43 Datasheet Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the p rocessor land assignment and si gnal descriptions. 4.1 Processor Land Assignment s This section contains the land listings for the Intel ® Pentium ® D processor. The landout fo otprint is shown in Figure 4-1 and Figure 4-2 . These [...]

44 Datasheet Land Listing and Signal Descriptions Figure 4-1. Landout Diagram (T op V i ew – Left Side) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AM VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AL VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS[...]

Datasheet 45 Land Listing and Signal Descriptions Figure 4-2. Landou t Diagram (T op View – Right Side) 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 VCC VSS VCC VCC VSS VCC VCC FC16 VSS_MB_ REGULA TION VCC_MB_ REGULA TION VSS_ SENSE VCC_ SENSE VSS VSS AN VCC VSS VCC VCC VSS VCC VCC FC12 VTTPWRGD FC1 1 VSS VID2 VID0 VSS AM VCC VSS VCC VCC VSS VCC VCC VSS VID[...]

Land Listing and Signal Descriptions 46 Datasheet T able 4-1. Alphabetical Land Assignment s Land Name Land # Signal Buffer Ty p e Direction A3# L5 Source Synch Input/Output A4# P6 Source Syn ch Input/Output A5# M5 Source Synch Input/Output A6# L4 Source Synch Input/Output A7# M4 Source Synch Input/Output A8# R4 Source Synch Input/Output A9# T5 Sou[...]

Land Listing and Signal Descr iptions Datasheet 47 D21# E10 Source Synch Input/Output D22# D10 S ource Synch Input/Output D23# F1 1 Source Synch Input/Output D24# F12 Source Synch Input/Output D25# D13 S ource Synch Input/Output D26# E13 Source Synch Input/Output D27# G13 Source Synch Input/Output D28# F14 Source Synch Input/Output D29# G14 Source [...]

Land Listing and Signal Descriptions 48 Datasheet G TLREF1 H2 Power/Other Input HIT# D4 Common Clock Input/Output HITM# E4 Common Clock Input/Output IERR# AB2 As ynch G TL+ Output IGNNE# N2 Asynch G TL+ Input IMPSEL F6 Power/O ther Input INIT# P3 Asynch G TL+ Input ITP_CLK0 AK3 T AP Input ITP_CLK1 AJ3 T AP Input LINT0 K1 Asynch G TL+ Input LINT1 L1[...]

Land Listing and Signal Descr iptions Datasheet 49 VCC A C27 P ower/ Other VCC A C28 P ower/ Other VCC A C29 P ower/ Other VCC A C30 P ower/ Other VCC AC8 Power/Other VCC A D23 P ower/ Other VCC A D24 P ower/ Other VCC A D25 P ower/ Other VCC A D26 P ower/ Other VCC A D27 P ower/ Other VCC A D28 P ower/ Other VCC A D29 P ower/ Other VCC A D30 P owe[...]

Land Listing and Signal Descriptions 50 Datasheet VCC AK14 Pow er/Othe r VCC AK15 Pow er/Othe r VCC AK18 Pow er/Othe r VCC AK19 Pow er/Othe r VCC AK21 Pow er/Othe r VCC AK22 Pow er/Othe r VCC AK25 Pow er/Othe r VCC AK26 Pow er/Othe r VCC AK8 Power/Other VCC AK9 Power/Other VCC AL1 1 Pow er/Othe r VCC AL12 Power/Other VCC AL14 Power/Other VCC AL15 P[...]

Land Listing and Signal Descr iptions Datasheet 51 VCC K30 Power/Other VCC K8 Pow er/Othe r VCC L8 Power/ Other VCC M23 Power/Other VCC M24 Power/Other VCC M25 Power/Other VCC M26 Power/Other VCC M27 Power/Other VCC M28 Power/Other VCC M29 Power/Other VCC M30 Power/Other VCC M 8 Pow er/Othe r VCC N23 Power/Other VCC N24 Power/Other VCC N25 Power/Ot[...]

Land Listing and Signal Descriptions 52 Datasheet VSS AA24 Power/Other VSS AA25 Power/Other VSS AA26 Power/Other VSS AA27 Power/Other VSS AA28 Power/Other VSS AA29 Power/Other VSS AA3 Power/Other VSS AA30 Power/Other VSS AA6 Power/Other VSS AA7 Power/Other VSS AB1 Power/Other VSS AB23 Power/Other VSS AB24 Power/Other VSS AB25 Power/Other VSS AB26 P[...]

Land Listing and Signal Descr iptions Datasheet 53 VSS AJ23 Power/Oth er VSS AJ24 Power/Oth er VSS AJ27 Power/Oth er VSS AJ28 Power/Oth er VSS AJ29 Power/Oth er VSS AJ30 Power/Oth er VSS AJ4 Power/Oth er VSS AJ7 Power/Oth er VSS AK10 Power/Other VSS AK13 Power/Other VSS AK16 Power/Other VSS AK17 Power/Other VSS AK2 Power/Other VSS AK20 Power/Other [...]

Land Listing and Signal Descriptions 54 Datasheet VSS E1 1 Power/Other VSS E14 Power/O ther VSS E17 Power/O ther VSS E2 Power/Oth er VSS E20 Power/O ther VSS E25 Power/O ther VSS E26 Power/O ther VSS E27 Power/O ther VSS E28 Power/O ther VSS E29 Power/O ther VSS E8 Power/Oth er VSS F10 Pow er/Othe r VSS F13 Pow er/Othe r VSS F16 Pow er/Othe r VSS F[...]

Land Listing and Signal Descr iptions Datasheet 55 VSS R30 Power/O ther VSS R5 Power/Other VSS R7 Power/Other VSS T3 Power/Other VSS T6 Power/Other VSS T7 Power/Other VSS U1 Power/Other VSS U7 Power/Other VSS V23 Power/O ther VSS V24 Power/O ther VSS V25 Power/O ther VSS V26 Power/O ther VSS V27 Power/O ther VSS V28 Power/O ther VSS V29 Power/O the[...]

Land Listing and Signal Descriptions 56 Datasheet T able 4-2. Numerical Land Assignment Land # Land Name Signal Buffer Ty p e Direction A2 VSS Power/Other A3 RS2# Common Clock Input A4 D2# Source Syn ch Input/Output A5 D4# Source Syn ch Input/Output A6 VSS Power/Other A7 D7# Source Syn ch Input/Output A8 DBI0# Source Synch I nput/Output A9 VSS Powe[...]

Land Listing and Signal Descr iptions Datasheet 57 C24 VSS Power/Other C25 VTT Power/Other C26 VTT Power/Other C27 VTT Power/Other C28 VTT Power/Other C29 VTT Power/Other C30 VTT Power/Other D1 RESERVED D2 ADS# Common Clock Input/Output D3 VSS Power /Other D4 HIT# Common Clock Input/Output D5 VSS Power /Other D6 VSS Power /Other D7 D20# Source Sync[...]

Land Listing and Signal Descriptions 58 Datasheet F19 VSS Pow er/Other F20 D41# Source Synch Input/Out put F21 D43# Source Synch Input/Out put F22 VSS Pow er/Other F23 RESERVED F24 TESTHI7 Power/Other Input F25 TESTHI2 Power/Other Input F26 TESTHI0 Power/Other Input F27 VTT_SEL Power/Other Outp ut F28 BCLK0 Clock Input F29 RESERVED G1 VSS P ower/Ot[...]

Land Listing and Signal Descr iptions Datasheet 59 J12 VCC Pow er/ Ot her J13 VCC Pow er/ Ot her J14 VCC Pow er/ Ot her J15 VCC Pow er/ Ot her J16 DP0# Common Clock Input/Output J17 DP3# Common Clock Input/Output J18 VCC Pow er/ Ot her J19 VCC Pow er/ Ot her J20 VCC Pow er/ Ot her J21 VCC Pow er/ Ot her J22 VCC Pow er/ Ot her J23 VCC Pow er/ Ot her[...]

Land Listing and Signal Descriptions 60 Datasheet N30 VCC Power/Other P1 TESTHI1 1 Power/Other Input P2 SMI# Asynch G TL+ Input P3 INIT# Asynch G TL+ Input P4 VSS Power/Other P5 RESERVED P6 A4# Source Synch Input/Out put P7 VSS Power/Other P8 VCC P ower/Ot her P23 VSS Power/Other P24 VSS Power/Other P25 VSS Power/Other P26 VSS Power/Other P27 VSS P[...]

Land Listing and Signal Descr iptions Datasheet 61 W2 TESTHI12 Power/Other Input W3 TESTHI1 Power/Other Input W4 VSS P ower/O ther W5 A16# Source Synch Input/Output W6 A18# Source Synch Input/Output W7 VSS P ower/O ther W8 VCC Power/ Other W23 VCC Power/Other W24 VCC Power/Other W25 VCC Power/Other W26 VCC Power/Other W27 VCC Power/Other W28 VCC Po[...]

Land Listing and Signal Descriptions 62 Datasheet AD4 VSS Power/Other AD5 ADSTB1# Source Synch Input/Output AD6 A22# Source Synch Input/Output AD7 VSS Power/Other AD8 VCC Power/Other AD23 VC C Power/ Other AD24 VC C Power/ Other AD25 VC C Power/ Other AD26 VC C Power/ Other AD27 VC C Power/ Other AD28 VC C Power/ Other AD29 VC C Power/ Other AD30 V[...]

Land Listing and Signal Descr iptions Datasheet 63 AG10 VSS Power/Other AG1 1 VCC Power/ Other AG12 VCC Power /Other AG13 VSS Power/Other AG14 VCC Power /Other AG15 VCC Power /Other AG16 VSS Power/Other AG17 VSS Power/Other AG18 VCC Power /Other AG19 VCC Power /Other AG20 VSS Power/Other AG21 VCC Power /Other AG22 VCC Power /Other AG23 VSS Power/Ot[...]

Land Listing and Signal Descriptions 64 Datasheet AK2 VSS Power/Other AK3 ITP_CLK0 T AP Input AK4 VID4 Power/Other Outp ut AK5 VSS Power/Other AK6 FORCEPR# Asynch G TL+ Input AK7 VSS Power/Other AK8 VCC Pow er/Othe r AK9 VCC Pow er/Othe r AK10 VSS Power/Other AK1 1 VCC Power/Other AK12 VCC P ower/Ot her AK13 VSS Power/Other AK14 VCC P ower/Ot her A[...]

Land Listing and Signal Descr iptions Datasheet 65 AM24 VSS Power/Oth er AM25 VCC P ower/Ot her AM26 VCC P ower/Ot her AM27 VSS Power/Oth er AM28 VSS Power/Oth er AM29 VCC P ower/Ot her AM30 VCC P ower/Ot her AN1 VSS Power/Other AN2 VSS Power/Other AN3 VCC_SENSE Power/Other Output AN4 VSS_SENSE Power/Other Output AN5 VCC_MB_ REGULA TION P ower/Ot h[...]

66 Datasheet Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference T able 4-3. Signal Descrip tion (Sheet 1 of 8) Name T ype Description A[35:3]# Input/ Output A[35:3]# (Address) define a 2 36 -byte physical memory a ddress space. In sub- phase 1 of the address phase, these signals transmit the a ddress of a transaction. In sub-ph[...]

Datasheet 67 Land Listing and Signal Descriptions BINIT# Input/ Output BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropr iate pins/lands of all such agents. If the BINIT# driver is enabled during power-on con figuration, BINIT# is asserted to signal any bus condition t hat preve[...]

68 Datasheet Land Listing and Signal Descriptions D[63:0]# Input/ Output D[63:0]# (Data) are the data signals. Th ese signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/ lands on all such agents. The dat a driver as serts DRDY# to indicate a valid dat a transfer . D[63:0]# are quad-pumped sign[...]

Datasheet 69 Land Listing and Signal Descriptions DRDY# Input/ Output DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer , DRDY# may be de-asserted to insert idle clocks. T his signal must connect the appropriate pins/lands of all processor FSB agents[...]

70 Datasheet Land Listing and Signal Descriptions IERR# Output IERR# (Internal Error) is asserted by a pr ocessor as the result of an internal error . Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This transacti on may optionally be converted to an external error signal (e.g., NMI) by syste m core log ic.[...]

Datasheet 71 Land Listing and Signal Descriptions MCERR# Input/ Output MCERR# (Machine Check Error) is asserted to indicate a n unrecoverable error without a bus protocol violation. It may be driven by all processor FSB agents. MCERR# assertion conditions are config urable at a system level. Assertion options are defined by the following options: ?[...]

72 Datasheet Land Listing and Signal Descriptions RSP# Input RSP# (Response Parity) is driven by t he response agent (the agent responsible for completion of the current transaction) during a ssertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins/lands of all processor FSB agents. A corr[...]

Datasheet 73 Land Listing and Signal Descriptions § TMS Input TMS (T est Mode Select) is a JT AG spec ification support signal used by debug tools. TRDY# Input TRDY# (T arget Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer . TRDY# must connect the appropriate pins/lands of all FS[...]

74 Datasheet Land Listing and Signal Descriptions[...]

Datasheet 75 Thermal Specifications a nd Design Considerat ions 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal S pecifications The Intel ® Pentium ® D processor requires a thermal solutio n to mai ntain temperatures within operatin g limits as set fort h in Section 5.1.1 . Any attempt to operate th e processor outside th[...]

76 Datasheet Thermal Specificat ions and Design Considerations Refer to the Intel ® Pentium ® D Processor and Intel ® Pent ium ® Pr ocessor Extr eme Edition 840 Thermal and Mechanical Design Guidelines and the Processor Power Characterization Methodology for the detai ls of th is me tho dology . The case temperature is defined at the geometric [...]

Datasheet 77 Thermal Specifications a nd Design Considerat ions T able 5-2. Thermal Profile for the Pentium D Process or with PRB=1 Power (W) Maximum T C (°C) Power (W) Maximum T C (°C) Power (W) Maximum T C (°C) Power (W) Maximum T C (°C) 0 43.8 34 50.6 68 57.4 102 64.2 2 44.2 36 51.0 70 57.8 104 64.6 4 44.6 38 51.4 72 58.2 106 65.0 6 45.0 40 [...]

78 Datasheet Thermal Specificat ions and Design Considerations T able 5-3. Thermal Profile for the Pentium D Processor wit h PRB=0 Power (W) Maximum T C (°C) Power (W) Maximum T C (°C) Power (W) Maximum T C (°C) Power (W) Maximum T C (°C) 0 43.2 26 48.9 52 54.6 78 60.4 2 43.6 28 49.4 54 55.1 80 60.8 4 44.1 30 49.8 56 55.5 82 61.2 6 44.5 32 50.2[...]

Datasheet 79 Thermal Specifications a nd Design Considerat ions 5.1.2 Thermal Metrology The maximum and minimum case temperatures (T C ) are specified in Ta b l e 5 - 1 . These temperature specifications are meant to help ensure proper operation of the processor . Figure 5-3 illustrates where Intel recommends T C thermal measurements sh ould be mad[...]

80 Datasheet Thermal Specificat ions and Design Considerations W ith a properly designed and char acteri zed thermal solu tion, it is anticipated that the TCC would only be activated for very short perio ds of tim e when ru nning the most power int ensive applications. The processo r performance impact due to thes e brief periods of TCC activat io [...]

Datasheet 81 Thermal Specifications a nd Design Considerat ions As a bi-directional signal, PROCHOT# allows for some protection of various com ponents from over-temperature situations. The PR OCHOT# signal is bi-directional in that it can either signal when the processor (either core) has reached its maximum operating temperatur e or be driven from[...]

82 Datasheet Thermal Specificat ions and Design Considerations 5.2.5 THERMTRIP# Signal Regardless of whether or not t he Thermal Monitor f eature is enabled, in th e event of a catastrophic cooling failure, the processor will automatically shut dow n when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Ta b l [...]

Datasheet 83 Thermal Specifications a nd Design Considerat ions § T able 5-5. Thermal Diode Interface Signal Name Land Number Signal Description THERMDA AL1 diode anode THERMDC AK1 diode cathode[...]

84 Datasheet Thermal Specificat ions and Design Considerations[...]

Datasheet 85 Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardw are. The Intel ® Pentium ® D processor samples the hardware configuration at reset, on the active-to-in activ e transition of RESET#. For specifications on these options, refer to Ta b l e 6 - 1 . The sampled informat ion c[...]

86 Datasheet Features 6.2.1 Normal St ate This is the normal operatin g state for the processor . 6.2.2 HAL T and Enhanced HAL T Powerdown St ates The Pentium D processor supports the HAL T or En hanced HAL T po werdown state. The Enha nced HAL T Powerdown state is config ured and enabled via the BIOS. The Enhanced HAL T state is a lower power stat[...]

Datasheet 87 Features The system can generate a STPCLK# while the processor is in the HAL T Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HAL T state. While in HAL T Power Down state, the processor will pro cess bus snoo ps. 6.2.2.2 Enhanced HAL T Powerdown St ate Enhanced HAL T is a l[...]

88 Datasheet Features 6.2.4 Enhanced HAL T Snoop or HA L T Snoop St ate, Grant Snoop State The Enhanced HAL T Snoop State is used in conj unction with the new En hanced HAL T state. If Enhanced HAL T state is not enabled in the BIOS , the default Snoop State entered will be the HAL T Snoop State. Refer to the sections below for details on HAL T Sno[...]

Datasheet 89 Boxed Processor Specifications 7 Boxed Processor Specifications The Intel ® Pentium ® D processor will also be offered as an Intel boxed processor . Inte l boxed processors are intended for system integrators wh o buil d systems from baseboard s and standard components. The boxed Pentium D processor will be suppli ed with a cooling s[...]

90 Datasheet Boxed Processor Specificat ions 7.1 Mechanical S pecifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mech anical specifications of the box ed Pentium D pro c essor. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed Pen ti[...]

Datasheet 91 Boxed Processor Specifications 7.1.2 Boxed Processor Fan Heat sink Weight The boxed processor fan heatsink will no t weigh more than 550 grams. See Chapter 5 and the Intel ® Pentium ® D Pr ocessor and Intel ® Pentium ® Processor Extr eme Edition 840 Thermal and Mechanical Design Guidelines for details on the processor weight and he[...]

92 Datasheet Boxed Processor Specificat ions The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connecto r labeled as CONTROL. The boxed processor's fan heatsi nk requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM cont rol . The power header on the baseboard m[...]

Datasheet 93 Boxed Processor Specifications 7.3 Thermal S pecifications This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor . 7.3.1 Boxed Processor Cooling Requirement s The boxed proc essor may be direct ly cool ed wit h a fan heatsink. However , meeting the processor's temperature spec[...]

94 Datasheet Boxed Processor Specificat ions Figure 7-7. Boxed Processor Fan He atsink Airsp ace Keepout Requirement s (side 1 view) Figure 7-8. Boxed Processor Fan He atsink Airsp ace Keepout Requirement s (side 2 view)[...]

Datasheet 95 Boxed Processor Specifications 7.3.2 V ariable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin m otherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a [...]

96 Datasheet Boxed Processor Specificat ions If the boxed processor fan heatsink 4-pin con nector is connected to a 4-pin motherboard header and the motherboard is desi gned with a fan speed controller with PWM output (For details on CONTROL, see Ta b l e 7 - 1 ) and remote thermal diode measurem ent capability the boxed processor will operate as f[...]

Datasheet 97 Balanced T echnology Extended (BTX) Type I Boxed Processor Specification s 8 Balanced T echnology Extended (BTX) T ype I Boxed Processor Specifications The Intel ® Pentium ® D processor will also be offered as an boxed Intel processor . Boxed Intel processors are intended for system integrat ors wh o buil d systems from largely stand[...]

98 Datasheet Balanced T echnology Extended (BTX) T ype I Boxed Processor Specifications 8.1 Mechanical S pecifications 8.1.1 Cooling Solution Dimensions This section documents the mech anical specifications of the box ed Pentium D pro cessor TMA. The boxed processor will be shi pped with an unattached TMA. Fi gure 8-2 shows a mechanical representat[...]

Datasheet 99 Balanced T echnology Extended (BTX) Type I Boxed Processor Specification s 8.1.3 Boxed Processor Support and Retention Module (SRM) The boxed processor TMA requires a SRM assembly to attach directly to th e chassis base pan and to secure the processor and TMA in the mainboa rd socket. The boxed processor TMA will ship with the heatsink[...]

100 Datasheet Balanced T echnology Extended (BTX) T ype I Boxed Processor Specifications The fan heatsink receives a PWM s igna l from the motherbo ard from the 4 th pin of the connector labeled as CONTROL. Note: The boxed processor ’ s fan heatsink requires a constant +12 V supplied to pin 2 and does no t support variable voltage control or 3-pi[...]

Datasheet 101 Balanced T echnology Extended (BTX) Type I Boxed Processor Specification s 8.3 Thermal S pecifications This section describes the cooling requirements o f the fan heatsink solution used by the boxed processor . 8.3.1 Boxed Processor Cooling Requirement s The boxed proc essor may be direct ly cool ed wit h a fan heatsink. However , mee[...]

102 Datasheet Balanced T echnology Extended (BTX) T ype I Boxed Processor Specifications 8.3.2 V ariable S peed Fan If the boxed processor fan heatsink 4-pin connecto r is connect ed to a 3-pin mo therboard header , it will operate as follows: The boxed processor fan will operate at differ ent speeds over a short range of temperatures based on a th[...]

Datasheet 103 Balanced T echnology Extended (BTX) Type I Boxed Processor Specification s If the boxed processor TMA 4-pin connector is co nnected to a 4-pin moth erboard header and the motherboard is designed with a fan speed controller with PWM outp ut (see Ta b l e 8 - 1 ) and remote thermal diode measurement capability , the boxed processor will[...]

104 Datasheet Balanced T echnology Extended (BTX) T ype I Boxed Processor Specifications[...]

Datasheet 105 Debug Tools Specificat ions 9 Debug T ools Specifications Refer to the eXtended Debug Port: Deb ug Port Design Guide for UP and DP Platforms and th e ITP700 Debug Port Design Gu ide for information reg a rdi ng debug tools specifications. Fo r mo re information, contact your Intel sales representative. The ITP700 Debug Port Design Gui[...]

106 Datasheet Debug T ools Specifications[...]