Intel cpci borard with a intel pentuim M manual

Diversified Technology, Inc. CPB4612 Configuration and Maintenance Guide Rev 1.2 CPB4612 CPCI Board with a Intel® Pentium® M © Copyright 2005 by Diversified Technology , Inc. All rights reserved . Printed in the United States of America. No part of this publication ma y be reproduced, stored in a retrieval system, or transmitted, in any form or [...]

CPB4612 Configuration and Maintena nce Guide ii Return Shipment Information If service or repair is required, contact DTI’s Service Department for a Return M aterial Authorization (RMA) number and shipping instructions. If the product is out of warranty, or was dama ged during shipment, a purchase order will be required fo r the repair. The produ[...]

CPB4612 Configuration and Maintena nce Guide iii For Your Safety CAUTION: The cPB-4612 contains a lithium battery. This battery is not field-replaceable. There is a danger of explosion if the battery is incorre ctly replaced or handled. Do not disassemble or recharg e the battery. Do not disp ose of the battery in fire. When the battery is replaced[...]

CPB4612 Configuration and Maintena nce Guide iv Revision History Date Revision Summary of Corrections 08/31/04 1.0 Initial Release 10/12/04 1.1 Added links throughout manual. 8/19/05 1.2 Removed references to ethernet sign al routing. Update BIOS Section[...]

CPB4612 Configuration and Maintena nce Guide v Table of Contents Return Shipment Info rmation .................................................................................................... ...............................ii For Your Safe ty ........................................................................................................[...]

CPB4612 Configuration and Maintena nce Guide vi 2.8 Operating S ystem Installation.................................................................................................. ......................... 17 3 CONFIGURAT ION .................................................................................................... 19 3.1 Switch De scrip[...]

CPB4612 Configuration and Maintena nce Guide vii 7.3.2 Preloa d Value 2 (BAR+04h) ...................................................................................................... ........................ 35 7.3.3 Gene ral Interrupt Status (BAR+08h) ............................................................................................. .[...]

CPB4612 Configuration and Maintena nce Guide viii B.2 J15 (Compact PCI Bus Con nector)................................................................................................. ................... 71 B.3 J11 (Compact PCI Bus Con nector)................................................................................................. .........[...]

CPB4612 Configuration and Maintena nce Guide ix Tables Jumper Cross-Re ference Table ................................................................................................... ..................... 20 Connector As signments .......................................................................................................... ..........[...]

CPB4612 Configuration and Maintena nce Guide x Document Organization This document describes t he operation and use of the CPB-4612 Computer Proce ssor Board with an Intel® Pentium® M. The following topics are co vered in this document. Chapter 1, "Introduction," introdu ces the key features of the CPB- 4612. This cha pter includes a pr[...]

1 Chapter 1 1 1 Introduction This chapter provides an introdu ction to the CPB-461 2 including a product defini tion, a list of product features, and a functional block diag ram with descriptions of each block. The "cPB-4612 Faceplate" illustration identifies the connectors, in dicato rs, and switches avai lable on the cPB-4612's fac[...]

2 1.1 Product Definition The cPB-4612 Computer Processor Bo ard is a single board computer de signed to work as a modular component in a CompactPCI system. It utilizes the Intel ® Pentium ® M processor in a micro FCBGA package along with dual Gigabit Ethernet controllers and the latest in memo ry and I/O technology to provide an inexpensive, yet [...]

3 CPB-4612 Faceplate Ejector Handle Ejector Handle PMC PMC 10/100 Ethernet COM RS-232 Serial Por t USB Hotswap LED Reset Switch[...]

4 1.2 Features There are two SKU's of the cPB-4612. The first is the cPB-4612, whi ch has a 64bit/66Mhz PMC site and a 32bit/33Mhz PMC site. . The second is the cPB-4612 w/ IDE, which has a 64bit/66Mhz PMC site an d an on-board 2.5” HDD IDE connector . Other features in clude: • CompactPCI Specification, PICMG 2.0, Version 2.1** compli ant[...]

5 Functional Block Diagram 1.3.1 CompactPCI/PSB Architecture The cPB-4612 is designed to operate in a PICMG 2.0 Co mpactPCI backplane. If the system is placed in a system slot, the bridge will automatically configure itse lf as a transparent bridge, and the board will perfo rm as the host. If the board is placed in a peripheral slot , the bridge wi[...]

6 system's fabric-switched Li nk Ports A and B, and can be inserted into system or peripheral slots. The cPB- 4612 is keyed for insertion into compati ble slots. The "CompactPCI" topic in Appendix D contains a link to the PCI Industrial Computer Manufact urers Group. 1.3.2 Processor The cPB-4612 uses the Mobile Pentium M in a micro F[...]

7 1.3.5 Memor y and I/O Addressing The cPB-4612 supports up to 2GB of DDR333/2 66/200 via two right-angled SODIMM so ckets. Memory can be purchased from DTI separately. See the "Memory Configuration" and "I/O Configurat ion" topics in Chapter 2 for more information. 1.3.6 Pow er Ramp Circuitry The cPB-4612 features a power contr[...]

8 Access Controller (MAC) and the physi cal layer (PHY) interfa ce combined into a single component solution. Both Ethernet Channels are dire cted to the re ar connector at J3 for PICMG 2.16 support. The "Ethernet " topic in Appendix D contains lin ks to the datasheet s for the Ethernet devices used on the cPB-4612. 1.3.11 10/100 Ethernet[...]

9 • Real-Time Clock • On-board PCI devices Enhanced capabilities incl ude the ability to configure each interrupt level for active high-g oing edge or active low-level inputs. The cPB-4612's interrupt c ontrollers reside in the 630 0ESB device. The "Intel 855GME Chipset" topic in Appendix D provides a link to the datasheet for th[...]

10 1.3.20 Universal Serial Bus (USB) The Universal Serial Bus (USB) provides a common i nte rface to slower-speed periph erals. Functions such as keyboard, serial ports, printer p ort, and mouse ports can be consolidated into USB, simplifying cabli ng requirements. The cPB-46 12 provides one USB port at it s faceplate (connecto r J20 is Port 0). US[...]

11 Chapter 2 2 2 Getting Started This chapter summari zes the information needed to make the cPB-4612 operational. This chapter should be read before using the board.[...]

12 2.1 Unpacking Check the shipping carto n for damage. If the shipping carton and contents are damaged, notify the carrier and DTI for an insurance settlement. Retain the ship ping carton and packin g material for inspection by the carrier. Obtain authorization before returning any product to DTI. Refer to the Return Shipment Information page for [...]

13 Configuration 5V (avg) 5V (peak) 3.3V (avg) 3.3V (peak) 12V (avg) 12V (peak) -12V (avg) -12V (peak) 1.7GHz / 512MB 6.9A TBD* 2.4A TBD* 20mA 50mA 0.0A 0.0A Hard disk (add) (typical) 540mA 1.00A N/A N/A N/A N/A N/A N/A PMC card typ ical 1 (add) 1.00A 1.70A 0.75A 1.30A 100mA 200mA 20mA 40mA PMC card max. 2 (add) 1.50A 3.00A 2.25A 4.50A 500mA 500mA [...]

14 Memory Address Map Example 4 GB FFF80000h - FFFFFFFFh SYSTEM BIOS/Flash 8000000h - FFF7FFFFh PCI PERIPHERALS 100000h - 1FFFFFFFh SYSTEM MEMORY 4 GB - 512 KB 512 MB 1 MB E0000h - FFFFFh SYSTEM BIOS C8000h - DFFFFh BIOS EXTENSION C0000h - C7FFFh VGA BIOS A0000h - BFFFFh VGA DISPLAY MEMORY 0h - 9FFFFh LOCAL DRAM 896 KB 800 KB 768 KB 640 KB 0[...]

15 2.4 I/O Configuration The cPB-4612 addresses up to 64 KB of I/O using a 16-bit I/O address. The cPB-4612 is populated with many commonly used I/O peripheral de vices. The I/O address location for each peripheral is shown in the "I/O Address Map" illustration. I/O Address Map D00 - FFFFh PCI* *Onboard ISA peripherals CF8 - CFFh PCI Conf[...]

16 80h Diagnostic Port 78 - 79h Reserved 70 - 77h On-board Real-Time Clo ck 60 - 6Fh Keyboard and System Ports 50 - 5Fh Reserved 40 - 4Fh On-board Timer/Counters 30 - 3Fh Reserved 2E - 2Fh Super I/O Configuration 22 - 2Dh Reserved 20 - 21h On-board master Interrupt Controlle r 0 - 1Fh On-board Master DMA Controller 2.5 Connectors The cPB-4612 inclu[...]

17 Setup Screen SYSTEM CONFIGURATION SUMMARY Diversified Technology, Inc – cPB4 612 CPU Type :Intel(R) Pentium(R) M processor 1700MHz CPU Speed : 1.70GHz Hard Disk 0: Not Dete cted L2Cache : 1024KB Hard Disk 1: Not Detected Base RAM : 639K Hard Disk 2: Not Detected Extended RAM: 480MB Hard Disk 3: Not De tected Video RAM : 32MB COM Ports : 3F8 2F[...]

18 5. Proceed with the OS installation as directed, being sure to select approp riate device types if prompted. Refer to the appropriate ha rdware ma nuals for specific device types and compatib ility modes of DTI products. 6. When installation is complete, reboot the syst em and set the boot device order in the SETUP boot menu appropriately.[...]

19 Chapter 3 3 3 Configuration The cPB-4612 has been designed for m aximum flexibility. Many features can be configured by the user for specific applications. Most configuration options are select ed through the BIOS Setup utility (discussed in the "BIOS Configuration Ov erview" topi c in Chapter 2). Some options cannot be software contro[...]

20 Jumper Options and Lo cations The cPB-4612 contains a push-button switch o n t he faceplate and eight jumpers on the component si de of the board. The jumpers are listed and briefly descr ibed in the "Ju mper Cross-Reference" table belo w. Factory default switch settings are shown in the "Defa ult Jumper Settings" figure. Jum[...]

21 Default Jumper Configuration 3.1 Switch Descriptions The following topics list the switches in n umerical or der and provide a detailed de scription of each switch. 3.1.1 PB1 (Reset) PB1 is a push-button on the front of the cPB-4612. Pr essing PB1 issues a hard reset. Reset is dis cussed in more detail in Chapter 4. 3.1.2 J16-1 (BKT-GND to GND) [...]

22 3.1.3 J16-2 (+12V to J5-pin D1). Installing this jumper will connect +12V to the Compac tPCI connector J5, pin D1. This is only to be used for specially designed RTM cards that may need it. The default is for no jum per. J16-2 Function Open Default CPCI J5-pin D1 is a no connect. Closed CPCI J5-pin D1 is shorted to +12V. 3.1.4 J16-3 (+5V PMC I/O[...]

23 3.1.8 J17-3 (Disable Onboard Video) Installing this jumper will disable the onb oard video. Place this jumper if using a PCI video card only. J17-3 Function Open Default Onboard video is enabled. Closed The onboard video is di sabled. 3.1.9 J17-4 (Manufacture Test Mode) Used by DTI for testing purposes. Do not install a jumper at this location. [...]

24 Chapter 4 4 4 Reset This chapter discusses the reset type s and reset sources on the cP B-4612. If necessary, the cPB-4612’ s board reset characteristics can be tailored to the requirements of a specific system.[...]

25 4.1 Reset Types and Sources The cPB-4612’s reset types are listed b elow. The source s for each reset type are detaile d in the following topics. • Hard Reset: All devices are held in reset. • Soft Reset: CPU initializa tion only. Other devices are not reset. • Backend Power Do wn: The backend logic is powered off. The board is powered o[...]

26 4.1.4 NMI Sources Watchdog Timer (Sy stem Register Address 79h) The watchdog timer may be prog rammed to generate a non- maskable interrupt if it is not strobed within a given time-out period. This function is di scussed in Chapter 7, "Watchd og Timer."[...]

27 Chapter 5 5 5 System Monitoring and Control The cPB4612 has an IPMI System Monitor that compli es with PICMG ® 2.9 specification, and complies with IPMI Specification 1.5. This allows a PICMG 2.9 compliant chassis that utilize s a chassis manager, or Baseboard Management Controller (BMC) to detect the presence of the cPB4612 and make Field Repl[...]

28 5.1 Monitoring and Control Functions The IPMI System Monitor has a dedicated serial interf ace to the host processor on the cPB4612. It is a 16550-compatible UART that is config urable in SETUP . If this interface is not required, it can be disabled. Otherwise, it will be given a unique serial port addre ss and interrupt. Note that the interrupt[...]

29 5.3 Field Replaceable Unit (FRU) Information Board information, such as se rial number, date of manufacture, OEM name, part number, etc., are retrievable from the FRU. It complies with the IPMI FRU 1.0 Specification. The information in the FRU can be customized to add other p roduct information, such a s asset tag, other part numbers, etc. 5.4 S[...]

30 Chapter 6 6 6 IDE Controller The cPB-4612 with IDE has an on-board IDE controll er that provides two IDE channels for interfacing with up to four IDE devices. The IDE c ontroller is incorporated into t he Intel 6300ESB , which supports ATA- 100. There is one 50-pin IDE connector on the cPB-4 612 with IDE, which supports up to two I DE devices (t[...]

31 6.1 Features of the IDE Controller • Primary and Secondary channel s for interfacing up to four devices • IBM-AT compatible • Supports PIO and Bus Master IDE • "Ultra ATA/33/66/100" Synchronous DMA Operatio n • Bus Master IDE transfers up to 100 MB /sec. • Individual software control for each IDE channel 6.2 Disk Drive Supp[...]

32 Chapter 7 7 7 Watchdog Timer This chapter explains the operation of the cPB-4612’s wat chdog timer. It provides an overview of watchdog operation and feature s, as well as samp le code to help you learn how the watchdo g timer works with applications.[...]

33 7.1 Watchdog Timer Overview The watchdog timer is implemented by using the 6300ESB ICH integrated watchdog timer. The prim ary function of the watchdog timer is to monitor the cPB-4612’ s operation and take corrective action if the software fails to function as programm ed. T he major features of the watchdog timer are: • Two-stage operation[...]

34 7.2.2 WDT Configuration Register (60h) Offset: 60-61h Default Value: 00h Size: 16 bits Attribute: R/W Bit Description 15-6 Reserved 5 WDT_OUTPUT: Outpu t Enable This bit indicates whether or not the WDT will toggle the WDT_TO UT# pin if the WDT times out. 4-3 Reserved 2 WDT_PRE_SEL: Prescaler Select The WDT provides two options for pre scaling t[...]

35 Bit Description 7:3 Reserved 2 WDT_TOUT_CNF: Timeo ut configuration 0 – Watchdog Timer Mode 1 – Free Running Mode 1 WDT_ENABLE: Watchdog Enable 0 – Disabled 1 - Enabled 0 WDT_LOCK Setting this bit will lock values of this register until a hard reset occurs or power is cycled. 0 – Unlocked 1 - Locked 7.3 Memory Mapped Registers The follow[...]

36 Bit Description 31:20 Reserved 19:0 Preload_Value_2 7.3.3 General Interrupt Status (BAR+08h) Offset: BAR+08h Default Value: 00h Size: 8 bits Attribute: R/WC Bit Description 7:1 Reserved 0 Watchdog Timer Interrupt Activ e This bit is set when the first stage of the 35 bit down counter reaches zero. Thi s is a sticky bit and is cleared by writing [...]

37 7.4 Using the Watchdog in an Application The following topics are provided to aid you in learning to use watchdog in an applicatio n. 7.4.1 WDT Unlocking and Programming Sequence Unlocking and programmi ng the WDT Memory Mapped registe rs involves the following sequence: 1. Write “80” to the Reload Register (offset BAR + 0Ch) 2. Write “86?[...]

38 Chapter 8 8 8 System BIOS The embedded BIOS on the cPB-4612 is implem ented as firmware that resid es in the on-board flash read-only memory (ROM). The BIOS contains stan dard PC-compatible basic input/output (I/O) se rvices and several DTI specific functions a nd features. Support for applicable SBC periphe ral devices (SCSI, NIC, video adapter[...]

39 8.1 BIOS Upgrade and Recovery To reprogram the BIOS or update it if it becomes corrupted, use the DTIFLASH .EXE utility available from DTI and discussed later in this chapter. 8.1.1 Flash Utility Program DTIFLASH.EXE is a utility program that can be obtained from DTI in the event a BIOS should be updated. Run DTIFLASH.EXE to modify the BIOS in t[...]

40 Once the memory is present, the compressed portions of the BIOS are de-compressed into the shado w memory occupying the standard BIOS memory ranges. The BIOS can now scan for and init ialize other interfaces such as I/O devices and items on the PCI or ISA busse s. If a video adapter is in the system it is located a nd initialized. The video adap[...]

41 devices within a category (such as to boot from IDE hard drive instead of SCSI), or to perm anently change the boot order, you will have to enter SETUP and chang e the boot options. If any errors are detected up to this point they will now be displayed on the scre en along with the following prompt to direct further actions. Pre ssing F1 will i [...]

42 ROM Utilities SYSTEM SUMMARY Displays various info rmation about the system installed SYSTEM SETUP Used to configure the time/date, floppy drive types, and other BIOS options HARD DISK SETUP Used to configure the hard drive types BOOT ORDER Used to specify boot device orderin g PERIPHERALS Used to enable/disable onboard I/O device s USB CONFIG U[...]

43 8.2.3 System Summary The System Configuration Summary utility provides valuable information abo ut the system. The information supplied can also be u seful in determining items that are present in the systems and how they are configured. The System Configuration Summary screen is sho wn below, followed by a brief description of information suppl[...]

44 Build Date: Displays the date on which the BIOS was generated. PCB Revision: Displays the PCB board revision level. Hard Disk 0 - 3: Displays the driv e type selected for the IDE drive. COM Ports: Displays the I/O addresses of all installed serial ports. Memory Mode: Displays the type and speed of the memory. PMC Slots: Displays the PCI type and[...]

45 System Time: A new time is set by typi ng in the HOUR, MINUTE, and SECONDS each followed by pressing < ENTER >. The time is displayed in 24-hour format; therefore, AM hours range from 0 through 11 and the PM hours range from 12 through 23. Invalid times cann ot be entered. System Date: A new date is set by tying in the MONTH, DAY, and YEAR[...]

46 8.2.5 IDE Config The IDE Configuration Utility is used to configure the hard drive contro ller and inte rface properties for the system. The following page descr ibes the configuration option s. IDE CONFIGURATION UTILITY IDE Configuration P-ATA Only P-ATA Channel Selection Both Hard Disk Write Protect Disabled IDE Detect Time Out (Sec) 35 ATA(PI[...]

47 8.2.6 Hard Disk Setup The Hard Drive Configuration Utility is used to configure the hard drives insta lled in the system. The following page describes the configuration option s. PRIMARY MASTER CONF IGURATION SUMMARY Device : Hard Disk Vendor : SMART ATA FLASH DISK Size : 513MB LBA Mode : Supported Block Mode: Not Supported PIO Mode : 4 Async DM[...]

48 Hard Drive Setup Descriptions The configuration options described below work identically for HARD DRIVES 0 - 3. Device: Displays the type of IDE device cu rrently installed. Type choices includ e Not Installed, Hard Disk, ATAPI CDROM, and ARM D. Vendor: Displays the manufacturer device identification information. Size: Displays the storage capac[...]

49 8.2.7 Boot Order The Boot Order Configuration Utility is used to determ ine the order in which the BIOS will attempt to boot from devices. The BIOS attempts to boot from the devices in descending orde r beginning from the top of the list. If the device is not bootable, then the next item down in the list is tried. Removable Devices and Hard Disk[...]

50 Boot Order Descriptions Boot Device Priority: Selects the boot order fo r installed boot able devices. The BIOS attempts to boot in descending order beginning from the top of the list. ATAPI CDROM Drives: Boot from an IDE CDROM. Hard Disk Devices: Boot from hard disk driv e. The desired hard d rive must be selected through Hard Disk Drives. Remo[...]

51 8.2.8 Peripherals The Peripheral Configurati on Utility allows onboard devices to be enabled, disabled, or confi gured. The onboard programmable I/O adapter includes a floppy disk interface, two serial ports, and a pa rallel printer port. PERIPHERAL CONFIGURATION SU MMARY ONBOARD PERIPHERAL CO NTROL Video Controller En abled Graphics Memory Sele[...]

52 Onboard Peripheral Control Descriptions Video Controller: This item displays the enable/disable status of the onboard video controller. Graphics Memory Select: Selects the amount of system memory used by the internal g raphics device. The choices are 1MB, 4MB, 8MB, 16MB, or 32MB. Ethernet Controller: This item con trols the enable/disable of the[...]

53 I/O Address Interrupt COM Port 3F8h IRQ4 COM1 2F8h IRQ3 COM2 3E8h IRQ4 COM3 2E8h IRQ3 COM4 8.2.9 USB Configuration The USB Configuration Utility allows co ntrol of the board’s USB features. USB CONFIGURATION UTILITY USB DEVICES DETECTED USB Devices : 1 Keyboard, 1 Mouse, 1 Hub, 1 Drive USB Configuration USB Function All USB Ports USB 2.0 Contr[...]

54 USB Control Descriptions USB Function: Enables USB host controllers. May be enabl ed for all ports, specific ports, or no ports. USB 2.0 Controller: Controls the USB 2.0 Cont roller. When enabled, the system will suppo rt high-speed (480 Mbps) USB devices, provided the OS loads a driver for the 2.0 Controller. USB 2.0 Controller Mode: Toggles th[...]

55 8.2.10 MISC Config The PCI and PNP Configuration Utility allows configuration of the PCI bus, PNP opt ions, as well as ACPI related items. MISC. CONFIGURATION UTILITY PCI OPTIONS PCI Latency Timer 64 Allocate IRQ to PCI VGA Yes Interrupt 19 Capture Disabled Reserved Memory Size 16k Reserved Memory Addr ess D0000 PNP OPTIONS Plug & Play O/S N[...]

56 Reserved Memory Address: This it em specifies the location of the Re served Memory if not disabled. PNP Options Descriptions Plug & Play O/S: If disabled (default), the BIOS will set up any plug & play devices. If enabled, the operating system is assumed to config ure plug & play devices. Reset Configuration Data: If set to “Yes”[...]

57 8.2.11 Event Logging The Event Logging Configuration Utility is used to configure and view sy stem events that have been logged. EVENT LOGGING CONFIGURATION UTILITY View Event Log Mark All Events As Read Clear Event Log Event Log Statistics SYSTEM SUMMARY SYSTEM SETUP HARD DISK SETUP BOOT ORDER PERIPHERALS USB CONFIG MISC. CONFIG EVENT LOGGING S[...]

58 8.2.12 Security/Virus The Security and Anti-Virus Configuration Utility is us ed to set system passwords and control system anti- virus items. SECURITY AND ANTI-VIRUS CONFIGURATION UTILITY Supervisor Password : Not Installed User Password : Not Installed Change Supervisor Password Change User Password Clear User Password Boot Sector Virus Protec[...]

59 8.2.13 Exit The Exit Menu provides a way to exit setup and save or discard changes. It also provides a way to load the default settings stored in the BIOS. EXIT MENU Save Changes and Exit Discard Changes and Exit Load Defaults Discard Changes Save Custom Defaul ts Load Custom Defaul ts Clear Custom Defaults SYSTEM SUMMARY SYSTEM SETUP HARD DISK [...]

60 8.3 Plug and Play (PnP) The system BIOS supports the followin g industry standards for making the sy ste m “Plug and Play ready” such as ACPI, PCI local bus spec ification rev 2.1 and SMBIOS 1. 8.3.1 Resource Allocation The system BIOS identifies, allocates, and initializes resources in a manner co nsistent with industry standards. The BIOS [...]

61 Drivers and/or the OS can detect the installed dev ices and determin e resource consumption using the defined PCI, legacy PnP BIOS, and/or ACPI BIOS interface functions. 8.3.4 Legacy ISA Configuration Legacy ISA add-in devices are not s upported by these platforms. 8.3.5 Automatic Detecti on of Video Adapters The BIOS detects video adapters in t[...]

62 LEDS Status MSB to LSB Visible colors: FFRF (Off Off Red Off) Bit in the lower nibble is high: POST CODE 02--- BIT values (MSB to LSB) 0000 0010 I I Upper Nibble Lower Nibble LEDS Status MSB to LSB Visible colors: FFGF (Off Off Green Off) Bits in the same location are both high: POST CODE 33 --- BIT values (MSB to LSB) 0011 0011 I I Upper Nibble[...]

63 If the board fails to boot or hangs-up at any of these POST codes, please follow these steps. Step1: Check all power connection s and cables to verify they are fully in serted and there are not any loose connections. Step2: Observe the indicating POST code and refer to the followin g section pertaining to the failure. POST CODES TROUBLE SHOOTING[...]

64 Appendix A A A Specifications This appendix describes the electrical, environmenta l, and mechanical specifications of the cPB-4612. It includes connector descript ions and pin outs, as well as illustrations of the board dimensions and connector locations. A.1 Electrical and Environmental The topics listed below provide tables a nd illustrations[...]

65 Supply Current, Icc: 4.5A average (typic al with 1.2 GHz processor and 512 MB SDRAM. Peak (short duration) power su pply current may be significantly higher (up to 50%) and will vary depending upon the application. Supply Current, Icc3: 2.5A average (typic al with 1.2 GHz processor and 512 MB SDRAM. Peak (short duration) power su pply current ma[...]

66 A.4.1 Board Dimensions and Weight The cPB-4612 meets the CompactP CI Specification, PICMG 2.0, Version 2.1** for all mechanical parameters. In a CompactPCI enclo sure with 0.8 inch spacing. Mechanical dimensi ons are shown in the "PCB Dimensions" illust ration and are outlined belo w. PCB Dimensions: 233.35 mm x 160 mm x 1.6 mm Board D[...]

67[...]

68 Appendix B B B Connectors As shown in the "Connecto r Locations" figure, the c PB-4612 includes several connecto rs to interface to application-specific devices. A brief description of each connector is given in the "Connecto r Assignments" table below. A detailed de scription and pin out for each connector is given in the fo[...]

69 B.1 Connector Locations CPB-4612 Connectors Locations (Topside) 5V Key 3.3V Key 1 1 128 3 9 38 6 4 65 102 103 1 [B] [A] 4 2 3 1 A 1 1 1 1 12 22 2 3 3 3 34 44 A1 1 1 1 1 1 A 1 1 1 1 3 . 3 V K e y 4 20 14 29 30 1 1 A1 ZRC_ISP BKT-GND PMC_+5V +12V_RTM VIDEO_DIS MANU_MODE CLR_CMOS M A D E I N U S A D I V E R S I F I E D T E C H N O L O G Y P / N : 6[...]

70 Backplane Connectors - Pin Locations 11 J1 1 15 25 J3 J5 1 19 1 22 1 22 J2 E D C B A E D C B A[...]

71 B.2 J15 (CompactPCI Bus Connector) J15 is a 110-pin, 2 mm x 2 mm, female 32-bit Com pactPCI connector (AMP 352068-1). Rows 12-14 are used for connector keying. See the "J1 CompactP CI Bus Connector Pin out" table below for pi n definitions. Refer to the "Backp lane Connectors – Pin Locations " illustration for pin placement[...]

72 B.3 J11 (CompactPCI Bus Connector) J11 is a 110-pin 2 mm x 2 mm female 64-bit Compac tPCI connector (AMP 352152-1). See the "J11 CompactPCI Bus Conne ctor Pin out" table for pin def initions and the "Backplan e Connectors - Pin Locations" illustration for pin placement. J11 CompactPCI Bus Connec tor Pin out J11 – CompactPCI[...]

73 B.4 J8 (CompactPCI Connector) J8 is a 95-pin 2 mm x 2 mm female con nector (A MP 352171-1). See the "J8 Connector Pin out" table below for pin definitions and the "Backplane Conn ec tors - Pin Locations" illustration for pin placem ent. J8 Connector Pin out J8 – CompactPCI P3 A1 PWR_VIO_PMC64_CPCI B1 PIM[52] C1 PIM[51] D1 P[...]

74 B.5 J2 (Rear Panel I/O C ompactPCI Connector) J2 is a 110-pin 2 mm x 2 mm female connecto r (AMP 352152-1) providing rear-panel u ser I/O. See the "J2 Rear Panel I/O Connector Pin out" table below fo r pin definitions and the "Backpla ne Connectors - Pin Locations" illustration for pin placement. J2 Rear Panel I/O Connector P[...]

75 B.6 J1 (10/100 Ethernet) J1 is an 8-pin RJ-45 connector providing 10 Mb (10BASE-T) and 10 0 Mb (100BASE-TX) protocols out the front of the board. Two LEDs are located insi de each RJ-45 conn ector: First LED : • Green indicates a lin k • Blinking Green indicates activity Second LED : • Off = 10 MB • Green = 100 MB Ethernet signals are di[...]

76 B.8 J3 (COM1 Serial Port) J3 is an DB9 connector pro viding a front-panel COM1 interface. See the "J3 COM1 Serial Port Pin out" table below for pin definitions. J3 COM1 Serial Port Pin out Pin# Function Pin# Function 1 DCD 6 DSR 2 RXD 7 RTS 3 TXD 8 CTS 4 DTR 9 RI 5 GND - SCD B.9 J6, J7, J9, J10 ( 64bit/66Mhz PCI Mezzanine Connectors) J[...]

77 24 GND 56 GND 25 GND 57 VCC3 (VIO) 26 CBE(3)# 58 PCI_AD(3) 27 PCI_AD(22) 59 PCI_AD(2) 28 PCI_AD(21) 60 PCI_AD(1) 29 PCI_AD(19) 61 PCI_AD(0) 30 VCC 62 VCC 31 VCC3 (VIO) 63 GND 32 PCI_AD(17) 64 REQ64# J7 – 66Mhz/64bit PMC site (JN2) 1 +12V 33 GND 2 PMC_TRST_64_66# 34 PMC_RSVD34 3 PMC_TMS_64_66 35 TRDY# 4 NC 36 VCC3 5 PMC_TDI_64_66 37 GND 6 GND 3[...]

78 J9 – 66Mhz/64bit PMC site (JN3) 1 NC 33 GND 2 NC 34 PCI_AD(48) 3 GND 35 PCI_AD(47) 4 CBE(7)# 36 PCI_AD(46) 5 CBE(6)# 37 PCI_AD(45) 6 CBE(5)# 38 GND 7 CBE(4)# 39 VCC3 (VIO) 8 GND 40 PCI_AD(44) 9 VCC3 (VIO) 41 PCI_AD(43) 10 PAR64 42 PCI_AD(42) 11 PCI_AD(63) 43 PCI_AD(41) 12 PCI_AD(62) 44 GND 13 PCI_AD(61) 45 GND 14 GND 46 PCI_AD(40) 15 GND 47 PC[...]

79 J10 – 66Mhz/64bit PMC site (JN4) 1 PIM[1] 33 PIM[33] 2 PIM[2] 34 PIM[34] 3 PIM[3] 35 PIM[35] 4 PIM[4] 36 PIM[36] 5 PIM[5] 37 PIM[37] 6 PIM[6] 38 PIM[38] 7 PIM[7] 39 PIM[39] 8 PIM[8] 40 PIM[40] 9 PIM[9] 41 PIM[41] 10 PIM[10] 42 PIM[42] 11 PIM[11] 43 PIM[43] 12 PIM[12] 44 PIM[44] 13 PIM[13] 45 PIM[45] 14 PIM[14] 46 PIM[46] 15 PIM[15] 47 PIM[47] [...]

80 B.10 J12 and J13 (32bit/33Mhz PCI Mezzanine Connectors) J12 and J13 are 64-pin, 1.00mm, dual row, vertical st acking receptacles providing a PCI local bus interface to optional PMC cards. These connectors provide a complete 32-bit PCI interface. See the following "J12 PCI Mezzanine Conne ctor Pin out" and "J13 PCI Mezzanine Connec[...]

81 J13 – 33Mhz/32bit PMC site (JN2 ) 1 +12V 33 GND 2 PMC_TRST_32_33# 34 NC 3 PMC_TMS_32_33 35 TRDY# 4 NC 36 VCC3 5 PMC_TDI_32_33 37 GND 6 GND 38 STOP# 7 GND 39 PERR# 8 NC 40 GND 9 NC 41 VCC3 10 NC 42 SERR# 11 BUSMODE2# 43 CBE(1)# 12 VCC3 44 GND 13 PCIRST# 45 PCI_AD(14) 14 BUSMODE3# 46 PCI_AD(13) 15 VCC3 47 GND 16 BUSMODE4# 48 PCI_AD(10) 17 PME# 4[...]

82 B.11 J14 (IDE Connector) J14 is a 50-pin, header providing a prim ary IDE chan nel interface. See the "J14 IDE Connect or Pin out" table below for pin definitions. J14 – 2.5” HDD IDE connector (if available) 1 IDE_CONFIG_A 26 NC 2 IDE_CONFIG_B 27 DREQ 3 IDE_CONFIG_C 28 GND 4 IDE_CONFIG_D 29 DIOW# 5 NC 30 GND 6 NC 31 DIOR# 7 RST# 32[...]

83[...]

84 Appendix C C C Thermal Considerations This appendix describes the therm al requirements for relia ble operation of a cPB-4612 using the Mobile Pentium 4 processor - M. It covers basi c thermal requirements an d provides specifics about monitoring the board and processor temperature.[...]

85 C.1 Thermal Requirements The cPB-4612 is equipped with an integ rated heatsink for cooling the processo r module. The maximum processor core temperature must not exceed 100°C . The heatsink allows a maximum ambient air temperature of 50°C with 200 linear feet per minute (L FM) of airflow. The maxi mum power dissipation of the CPU is 25 W at 1.[...]

86 When checking airflow co nditions, let the Processor Co re Temperature Test dwell for at lea st 30 minutes and verify that the core temperature does not ex ceed 65° C. The processor "core" temperatu re must never exceed 100°C unde r any condition of ambient temperature or usage. WARNING: Temperatures ov er 100°C may result in perman[...]

87[...]

88 Appendix D D D Datasheet Reference This appendix provides links to data sheets, standards, and specifications for the technology desi gned into the cPB-4612.[...]

89 D.1 CompactPCI CompactPCI specifications can be p urchased from the PCI Industrial Computer M anufacturers Group (PICMG) for a nominal fee. A short form CompactPCI specification is also available on PICMG's Website at: http://www.picmg.org** D.2 Ethernet Refer to the Intel 82559 Fast Ethernet P CI Cont roller datasheet for more information [...]

90 D.5 PMC Specification For more information about PMC module s and the PMC Specification, refer to the spon soring organization's Website at: http://www.vita.com/** D.6 Super I/O Refer to the SMSC LPC47M192 Super I/O with Hardware Monito ri ng Block datasheet for more information on the following cPB-4612 functions: • Hardware Monitoring T[...]

91[...]

92 Appendix E E E Agency Approvals E.1 CE Certification The cPB-4612 meets the intent of Directiv e 89/336/EEC for Electromagnetic Compatibility [EN55024:1998, EN55022:1998] an d Low-Voltage Dire ctive 73/23/EEC for Prod uct Safety [EN60950- 1:2001]. The final product configuration may need further testing. DTI is ready to work with you to get your[...]

93 approved chassis. These limits are d esigned to provide reasonable protection a gainst harmful interference when the equipment is op erated in a commercial environment. This product generate s, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may caus e harmful interferen ce t[...]

94 Appendix F F F cRT Specifications The cRT-4612 hosts a CompactFl ash site and a 40 pin IDE connector, and prov ides access t o the following features on the rear panel: • Two USB 2.0 Ports • Serial Communications on COM2 • Video via standard CRT connector • A PIM site that can be used in conjunction with a PMC card, on th e cPB-4612, to [...]