Intel GD82559ER manual

GD82559ER F ast Et hernet** PCI C ontr oller Networking Sili con Datasheet Product Features ■ Optimum Integration for Lowest Cost Solu tio n — Integrated I EEE 802.3 10 B ASE-T and 100B ASE-TX compatible PHY — Glueless 3 2-bit PCI master interface — 128 Kby te Flash interface — Thin BGA 15m m 2 package — A CPI and PCI Po wer Managemen t[...]

GD82559ER - Networking Silicon ii Datasheet Informatio n in this do cument is pr o vided in connect ion with Int el products. No li cense, express or implie d, by estoppel or o the rwise, to any intellectual proper ty r ights is grant ed by this do cument. Excep t as provided in Intel's T erm s and Cond itions of Sale for such produ cts, Inte [...]

Datashee t iii Networking Silicon — GD825 59ER Cont ents 1. INTRODUCTION ................ ................... .................... ................... ................... .................... ............ 1 1.1 GD82559E R Overview .................... ................... ................... .................... ................... ...... 1 1.2 Su[...]

GD82559E R — Networking Silicon iv Datasheet 6.1.2 100BASE-TX Tra nsmit Blocks ........ ...... ...... ....... ................... ....... ...... .............. 37 6.1.3 100BASE-TX Rec eive Bl ocks ............... ...... ....... ...... .................... ...... ....... ....... 40 6.1.4 100BASE-TX Col lisi on Detecti on .... ...... ...... .......[...]

Datashee t v Networking Silicon — GD825 59ER 8.1.10 Flow Contro l Register ................... ................... ................... .................... .......... 60 8.1.11 Power Ma nagement Drive r Register ..................... .................... ................... .... 6 0 8.1.12 General Co ntrol Register . ......................... ...[...]

GD82559E R — Networking Silicon vi Datasheet[...]

Datashee t 1 Netw orkin g Silicon — G D82559ER 1. In troduction 1.1 GD82559ER Overvie w The 82559ER is part of Intel 's second generation family of fully integrated 10BASE-T/100 BASE- TX LAN solutions. The 8255 9ER consists of both the Media Access Controller (MAC) and the physical layer (PHY) combined into a singl e component solut ion. 825[...]

GD82559E R — Networkin g Silicon 2 Datasheet[...]

Datashee t 3 Netw orkin g Silicon — G D82559ER 2. GD82559ER Architectu ral Overview Figur e 1 is a high level block di agram of the 82 559ER. It is divided i nto four mai n subsystems: a parallel subsystem, a FIFO subsystem, the 10/100 Mbps Carrier- Sense Multiple Access with Collision D etect (CSMA/ CD) unit, and the 10/10 0 Mbps physical layer [...]

GD82559E R — Networkin g Silicon 4 Datasheet operate independen tly . Control is switched between the two units according to th e microcode instruction flow . Th e independence of the R eceive and Command un its in the micromachine allows the 82559ER to interleave commands and receive in coming frames, with no real-time CPU int erve ntio n. The 8[...]

Datashee t 5 Netw orkin g Silicon — G D82559ER 2.3 10/100 Mb p s Serial CSMA/CD Unit Overview The CSMA/CD unit of the 82 55 9ER all ows it t o be conn ected to either a 10 or 10 0 Mbps Et hern et network. Th e CSMA/CD unit perf orms all o f the function s of the 802 .3 protoc ol such as f rame formatting, frame stripping, co llision handling, def[...]

GD82559E R — Networkin g Silicon 6 Datasheet[...]

Datashee t 7 Networkin g Silicon — GD82559ER 3. Si g nal Descri p tions 3.1 Si g nal T yp e Definitions 3.2 PCI Bus Interface Si g nal s 3.2.1 Address a nd Data S i g nals T ype Name Description IN Input The input pin is a standard input onl y si g nal. OUT Output The output pin is a T otem Pole Output pin and is a standard active driver . T/S T [...]

GD82559E R — Networkin g Silicon 8 Datasheet 3.2.2 Inter fa ce Control S i g nal s Symbol T ype Name and Function FRAME# S/T/ S Cycle Frame. The c y cle frame si g nal is driven b y the current master to indicate the be g innin g and duration of a transaction. FRAME# is asserted to indicate the start of a transaction and de-asserted durin g the f[...]

Datashee t 9 Networkin g Silicon — GD82559ER 3.2.3 S y stem and Power Mana g ement Si g nals 3.3 Local Memor y Interface Si g nal s Symbol T ype Name and Function CLK IN Clock. The Clock si g nal provides the timin g for all PCI tr ansactions and is an input si g nal to ever y PCI device. Th e 82559ER re q uires a PCI Clock si g nal ( fre q uenc [...]

GD82559E R — Networkin g Silicon 10 Datasheet 3.4 T estabilit y Port Si g nals FLA[13]/ EEDI OUT Flash Address[13]/EEPROM Data Input. Durin g Flash accesses, this multiplexed pin acts as t he Flash Address [13] output si g nal. Durin g EEPROM accesses , it acts as serial output data to t he EEPROM Data Input si g nal. FLA[12:8] OUT Flash Address[[...]

Datashee t 11 Networkin g Silicon — GD82559ER 3.5 PHY Si g nals NOTE: 619 Ω and 549 Ω f or the RBIAS100 and RBIAS10, respectivel y , are onl y a recommended values and should be fine tuned for various desi g ns. Symbol T ype Name and Function X1 A/I Crystal Input One. X1 and X2 can be driven b y an external 3.3 V 25 MHz cr y stal. Otherwise, [...]

GD82559E R — Networkin g Silicon 12 Datasheet[...]

Datashee t 13 Netw orkin g Silicon — G D82559ER 4. GD82559ER Media A ccess Control Function al Descri p tion 4.1 82559ER Initi alization The 82559ER has four sources for initialization. They are listed according to their precedence: 1. AL TRST# Signal 2. PCI RST# S ignal 3. Software Reset (Software C ommand) 4. Selective Reset (Sof tware Comman d[...]

GD82559E R — Networkin g Silicon 14 Datasheet 4.2 PCI Interface 4.2. 1 825 59ER B us O p erations After configuration, the 82559ER is ready f or normal oper ation. As a Fast Ethernet contro ller , the role of the 82559ER is to access transmitted data or deposit received data. In both cases the 82559ER, as a bus master dev ice, will initiate memor[...]

Datashee t 15 Netw orkin g Silicon — G D82559ER The figures below show CSR zero wait-state I/O read and write cycles. In the case of accessing the Control/Status R e gi sters, the CPU is the initiator an d th e 82559ER is the target of the transaction. Read Accesses: The CPU, as the initiator , drives address lines AD[31:0], the command and byte [...]

GD82559E R — Networkin g Silicon 16 Datasheet controls the TRDY# signal and asserts it from the data access. The 82559 ER allows the CPU to issue only one I/O write cycle to the Control/Status Registers, generating a disconnect by asserting the STOP# signal. This is true fo r both memory mapp ed and I/O mapped accesses. 4.2.1.1.2 Flash Buffer Acc[...]

Datashee t 17 Netw orkin g Silicon — G D82559ER Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE# [3:0] an d the control lines IRD Y# and FRAME# . It also prov ides the 82559ER with valid d ata immediately after asserting IRDY# . The 82559ER con trols the TRDY# signal and de-asse[...]

GD82559E R — Networkin g Silicon 18 Datasheet Note: The 82559ER is considered the target in the abo ve diagram; thus, TRDY# is not asserted. 4.2.1.1.4 Error Handlin g Data Parity Err ors: The 82559ER checks for data parity errors while it is the target of the transaction. If an erro r was detected, the 82559ER always sets the Detected Parity Er r[...]

Datashee t 19 Netw orkin g Silicon — G D82559ER 8 depict memory read and write burst cycles. For bus master cy cles, the 82559ER is the initiator and the host m ain memory (or the PCI host b ridge, depending o n the configuration o f the system) is the target. The CPU provides th e 82559ER with action commands and pointers to the data buffers tha[...]

GD82559E R — Networkin g Silicon 20 Datasheet Byte Count value indicates the maximum number of transmit DMA PCI cycles that will be completed after an 82559ER internal arbitration. (Details on the Configure command are described in t he S oftwar e Developer ’ s Man ual .) The 82559ER, as the initiator , d ri ves the address lines AD[31:0], the [...]

Datashee t 21 Netw orkin g Silicon — G D82559ER 1. Minimum transfer of o ne cache line 2. Active byte enable bits (or BE#[ 3:0] are all low) during MWI access 3. The 82559ER may cross the cache line bound ary only if it intend s to transfer the next cache line too. T o ensure the above conditions, the 82559ER may use the MWI com mand only if the [...]

GD82559E R — Networkin g Silicon 22 Datasheet • This feature is not recommended for use in non-cache line oriented systems since it may cause shorter burs ts and lo wer perfor mance. • This feature should be used only when the CLS register in PCI Configuration spac e is set to 8 or 16 Dwords. • The 82559ER reads all control data stru ctures[...]

Datashee t 23 Netw orkin g Silicon — G D82559ER 4.2. 4 Pow er Stat es The 82559ER ’ s power manageme nt register im plements al l four power st ates as defi ned in the Power Management Network Device Class Reference Specification, Revision 1.0. The four states, D0 throug h D3, vary fr om maximum power consum ption at D0 to th e minimum po wer c[...]

GD82559E R — Networkin g Silicon 24 Datasheet 4.2.4.4 D3 Power Stat e In the D3 power state, the 82 5 59ER has the same capabilit ies and consumes the same amount of power as it does in the D2 state. However , it enables the PCI system to be in the B3 state. If the PCI system is in the B3 state ( in other words , no PCI power i s present ), the 8[...]

Datashee t 25 Netw orkin g Silicon — G D82559ER . 4.2.4.6 Auxili ar y Power Si g nal The 82559ER senses whet her it is connected to the PC I power supply or to an auxiliary power supp ly (V AU X ) via the FLA1/AUXPWR pin . The auxiliary power detection pin (multiplexed with FLA1) is sampled when the PCI R ST# or AL TR ST# signals are active. An e[...]

GD82559E R — Networkin g Silicon 26 Datasheet In a LAN on Mot herboard sol ution, th e PCI power goo d signal is supplied by the system. In network adapter implemen ta tions, the PCI po wer go od sign al can b e either g enerated locally using an external analog device, or con nected directly to the PCI reset signal. In designs, that use both the[...]

Datashee t 27 Netw orkin g Silicon — G D82559ER • ISOL A TE# tra ilin g ed ge The internal initialization signal resets th e PCI C onfiguration Space, MAC configuration, and memory struc ture. The behavior of the PC I RST# signal and the internal 82559 ER initialization signal are shown in the figu re below . 4.2.5 W ake-u p Events There are tw[...]

GD82559E R — Networkin g Silicon 28 Datasheet 4.2.5.2 Link Status Chan g e Event The 82559ER link status indication circuit is capable of issuing a PME on a link status ch ange from a valid link to an inval id link cond ition or vice versa . The 82559ER rep orts a PME link stat us event in all power states. The PME# sig nal is gated by the PME En[...]

Datashee t 29 Netw orkin g Silicon — G D82559ER All accesses, either read or write, are preceded by a command instruction to the device. The address field is six bits for a 64 r egister EEPROM or eight bits f or a 256 register EEPROM. The end of the add ress field is indicated by a dummy zero bit fr om the EEPROM, which indicates the entire addre[...]

GD82559E R — Networkin g Silicon 30 Datasheet Note that wor d 0Ah contains se veral conf iguration bi ts. Bits fr om word 0Ah, F Bh through FEh, and certain bits from wor d 0Dh are described as fo llows: Note: The IA read from the EEPROM is used by the 82559 ER until an IA Setup com mand is issued by software. The IA def ined by the IA Setup comm[...]

Datashee t 31 Netw orkin g Silicon — G D82559ER 4.5.1 Full Du p lex When operating in full dup lex m ode the 8 25 59ER can tran smit and receive frames simultaneously . T ransmission starts regardless of the state of th e internal receive path. Reception starts when the internal PHY detects a valid frame on the receive dif ferential pair of the P[...]

GD82559E R — Networkin g Silicon 32 Datasheet 4.6 Med ia Inde p endent Interface ( MII ) Mana g ement Interface The MII management interface allows the CPU to control the PHY unit via a control register in the 82559ER. This allows the software driv er to place the PHY in specific modes such as full duplex, loopback, po wer down, etc., with out th[...]

Datashee t 33 Netw orkin g Silicon — G D82559ER 5. GD82559ER T est Port Fun ctionalit y 5.1 Introduction The 82559ER ’ s NAND-Tre e T est Access Port (T AP ) is the access point f or test data to and from the device. The port provid es th e ability to perform basic productio n level testing. The port pro- vides two f unction s: 1) The th e sync[...]

GD82559E R — Networkin g Silicon 34 Datasheet 5.5 T riState This comma nd set all 82559E R Input and Outp ut pins into a TRI-state (HIGH-Z) mode, all int ernal pull-ups an d pull-downs are disabl ed. This mode is entered b y setting the followin g T es t Pin Com- binations: TEST = ‘1, TCK = ‘0, TEXEC = ‘0, TI = ‘1, and resetting the devic[...]

Datashee t 35 Netw orkin g Silicon — G D82559ER 19 STOP# FLD2 20 GNT# FLD3 21 PERR# FLD4 22 P AR FLD5 23 AD16 FLD6 24 C/BE1# FLD7 25 AD15 FLA0 26 AD14 FLA1 27 AD13 FLA2 28 AD12 FLA3 29 AD1 1 FL A4 30 AD10 FLA5 31 AD9 FLA6 32 AD8 FLA7 33 C/BE0# FLA8 34 AD7 FLA9 35 AD6 FLA10 36 AD5 FLA1 1 37 AD4 FLA12 37 AD3 FLA13/EEDI 39 AD2 FLA14/EEDO 40 AD1 FLA1[...]

GD82559E R — Networkin g Silicon 36 Datasheet[...]

Datashee t 37 Netw orkin g Silicon — G D82559ER 6. GD82559ER Ph y sical La y er Functional Descri p tion 6.1 100BASE-TX PHY Unit 6.1.1 100BASE-TX T ransmit Clock Generation A 25 MHz crystal or a 25 MHz oscillator is used to drive the PHY unit’ s X1 and X2 pins. The PHY unit derives its internal trans mit digital clocks from thi s crys tal or os[...]

GD82559E R — Networkin g Silicon 38 Datasheet 6.1.2.2 100BASE-TX Scrambler and ML T-3 Encoder Data is scram bled in 1 00BASE- TX to redu ce electr omagnet ic emissi ons du ring long tran smis sions of high-freq uency data codes. T he scrambler logic accepts 5 bits fro m the 4B/5B encod er block and presents the scrambled data to the ML T-3 encode[...]

Datashee t 39 Netw orkin g Silicon — G D82559ER 6.1.2.3 100BASE-TX T rans mit Framin g The PHY unit does not dif ferentiate between the fields of the MAC frame containing pream ble, Start of Frame Delimiter , data and Cyclic Redundancy Check (CRC). The PHY unit encodes the first byte of the pream ble as the “JK” symbol, encodes all other piec[...]

GD82559E R — Networkin g Silicon 40 Datasheet 6.1. 3 100B ASE-TX Re ceive Blocks The receive subsection of the PHY unit accepts 100BASE-TX ML T-3 data on the receive diff erential p air . Due to t he advanced d igital signal pr ocessing des ign tech niques e mployed, th e PHY unit will accurately receive valid da ta from Category-5 (CA T5) UTP an[...]

Datashee t 41 Netw orkin g Silicon — G D82559ER 6.1.4 100BASE-TX Co llision Detection 100BASE-TX collisio ns in half duplex mode o nl y are detected sim ilarly to 10BASE -T collis ion detection, via simultaneous transmission and receptio n. 6.1.5 100BASE-TX Link Inte g rit y and Auto-Ne g otiation Solution The 82559 Au to-Negotiation function aut[...]

GD82559E R — Networkin g Silicon 42 Datasheet 6.2.2 10BASE-T T ransmit Blocks 6.2.2.1 10BASE-T Manchester Encode r After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock performs the Manchester encod ing. The Manchester code always has a mid-bit transitio n. If the value is 1b then th e transition is from low to[...]

Datashee t 43 Netw orkin g Silicon — G D82559ER All other activity is determ ined to be either data, link test pulses, Auto -Negotiation fast link p ulses, or the idle conditio n. W hen activity is detected, the carrier sense si gn al is asserted to the MAC. 6.2.3.3 10BASE-T Err or Detection and Re p ortin g In 10 Mbps mo de, the PHY unit can det[...]

GD82559E R — Networkin g Silicon 44 Datasheet 6.3.1 D escri p tion Auto-Negotia tion selects the fastest operating mode (in ot her words, the highest common denominator) available to hardware at bo th ends of the cable. A PHY’ s capability is encod e d by bursts of link pu lses calle d Fast Link Pulses (FLPs). Connection is establ ished by F LP[...]

Datashee t 45 Netw orkin g Silicon — G D82559ER will perform Aut o-Negot iation or Parallel Detection wi th no data packets being transm itt ed. Connection is then established either by FLP exch ang e or Parallel Detection. The PHY un it will look for both FLPs and lin k integrity pulses. The followin g diagram illustrates this p rocess . 6.4 LED[...]

GD82559E R — Networkin g Silicon 46 Datasheet Fi g ure 16. T wo and Three LED Schematic Dia g ram LILED ACTLED VCC SpeedLED LILED ACTLED SpeedLED 82559ER[...]

Datashee t 47 Netw orkin g Silicon — G D82559ER 7. PCI Confi g uration Re g isters The 82559E R acts as both a m aster and a slave on the PCI bus. As a master , the 8 2559ER interacts with the system main memory to access da ta for transmission or depo sit received data. As a slave, some 82559ER control structures are accessed by the host CPU to [...]

GD82559E R — Networkin g Silicon 48 Datasheet 7.1.2 PCI Command Re g iste r The 82559ER Co mmand register at word address 04h in the PCI co nfiguration space pro vides control over the 82 559ER’ s abi lity to generate and respond to P CI cycles . If a 0His written to this register , the 82559 ER is logically disconnected from the PCI bus for al[...]

Datashee t 49 Netw orkin g Silicon — G D82559ER 7.1.3 PCI S tatus Re gister The 82559ER Status register is used to record status inform ation for PCI bus related even ts. The format of this register is shown in th e figu re below . Note that bits 21, 2 2, 26, and 27 are set to 0b and bits 20, 2 3, and 25 are set to 1b. The PCI Status register bit[...]

GD82559E R — Networkin g Silicon 50 Datasheet 7.1.4 PCI Revis ion ID Re g ister The Revisio n ID is an 8-b it read only r egister with a default val ue of 08h for the 8255 9ER. The three least s ignifi cant b its of the Revis ion ID can be overri dden by the ID and R evisio n ID fields in the EEPROM ( Section 4.4, “Serial EEPROM Interface” on[...]

Datashee t 51 Netw orkin g Silicon — G D82559ER Note: Bit 3 is set to 1b only if the value 0000 10 0 0b (8H) is written to this regis ter , and b it 4 is set to 1b only if the value of 0001 0000b (16H) is wr itten to this regist er . All othe r bits are read only and wi ll return a value of 0b on read. This register is expected to be written by t[...]

GD82559E R — Networkin g Silicon 52 Datasheet Note: Bit 0 in all base registers is read o nly and u sed to determin e whether the regis ter maps into m emory or I/O space. Base registers that map to memory space m ust r eturn a 0b in b it 0. Base registers that map to I/O space must retu rn 1b in bit 0. Base registers that map into I/O space are [...]

Datashee t 53 Netw orkin g Silicon — G D82559ER 7.1.10 PCI Subs y stem V endor ID and Subs y stem ID Re g isters The Subs ystem V endor ID fiel d identifies t he vendor of an 82559 ER-based solut ion. The Subsyst em V endor ID values ar e based upon the vendo r ’ s PCI V endor ID and is cont rolled by the PCI Special Interest Group (SIG). The S[...]

GD82559E R — Networkin g Silicon 54 Datasheet 7.1. 13 Interru p t Pin Re g ister The Interru pt Pin reg ister is read only and defines wh ich of the f our PC I interrup t request pins, INT A# thro ugh INTD#, a PCI device is con nected to. The 825 59ER is connected the INT A# pin. 7.1.14 Minimum Grant Re g iste r The Minimum Grant (Min_Gnt) regist[...]

Datashee t 55 Netw orkin g Silicon — G D82559ER 7.1.19 Power Mana g emen t Cont rol/Sta tus R e g ister ( PMCSR ) The Power Management Contro l/Status is a word register . It is used to determine and chan ge the current power state of the 82 559ER and control the power man agement interrupts in a standard manner . 24:22 000b Read Onl y Auxiliary [...]

GD82559E R — Networkin g Silicon 56 Datasheet 7.1. 20 Dat a Re g ister The data register is an 8-bit read only r egister that p rovides a mechanism fo r the 82 559ER to r eport state depende nt maximum p ower consump tion and heat d issipation. The value rep orted in this register depends on th e valu e written to the Data Select field in the PMC[...]

Datashee t 57 Networking Silicon — GD825 59ER 8. Contro l/Status Registers 8.1 LAN (Ethernet) Control/St atus Registers The 82559ER’ s Cont rol/S tatus Register (CSR) is illust rated in the figure below . NO TE: In Figure 23 abo v e, SCB is defined as the System Control Block of the 82559ER, and PMDR is defined as the P ower Management Driver R[...]

GD82559E R — Networking Silicon 58 Datasheet MDI Cont rol Re gist er: The MDI Control r egister allo ws the CPU to read and wr ite information fro m the PHY unit (or an e xternal PHY comp onent) through the Man agement Data Interface. Receive DMA Byte Count: The Receiv e DMA Byte Count reg ister keeps track of ho w many bytes of receive dat a hav[...]

Datashee t 59 Networking Silicon — GD825 59ER 8.1.2 System Control Bloc k Command W ord Commands for the 82559E R’ s Command and Recei ve units are placed in this re gister by the CPU. 8.1.3 System Contro l Bloc k General P ointer The System Cont rol B lock (SCB) General Pointer is a 32-bit f ield that points to v arious data structures dependi[...]

GD82559E R — Networking Silicon 60 Datasheet 8.1.8 Receive Direct M emory Access Byte Count The Recei ve DMA Byte Coun t reg ister keeps track of ho w many b ytes of recei ve data hav e been passed into host memory via DMA. 8.1.9 Early Rece ive Inter rupt The Early Recei ve In terrupt reg ister allo ws the 825 59ER to generate an ear ly interrupt[...]

Datashee t 61 Networking Silicon — GD825 59ER Note: The PMDR is initialized at AL TRST# reset only . 8.1.1 2 G eneral Cont r ol Regi st er The G e neral Con trol registe r is a byte registe r an d is des cribed be low . 8.1.13 General Status Regist e r The General Status reg ister is a byte re gister which indicates the link status of the 82 559E[...]

GD82559E R — Networking Silicon 62 Datasheet 8.2 Statistical Counters The 82559ER provi des inform ation fo r networ k managemen t statis tics b y pro viding on-chip statistical counters that count a v ariety of e vents asso ciated with both transmit and recei ve. Th e counters are up dated b y the 82559ER when it comp lete s th e processing of a[...]

Datashee t 63 Networking Silicon — GD825 59ER The Statistical Count ers are initially set to zero by the 82559ER after res e t. They cannot be preset to anythin g other than zero. The 82559ER incr ements the counters b y internally reading them, incrementing them and writing them back. This process is in visible to the CPU and PCI b us. In additi[...]

GD82559E R — Networking Silicon 64 Datasheet[...]

Datashee t 65 Networking Silicon — GD825 59ER 9. PHY Unit Registers The 82559ER provid es status and accepts managemen t information via the Man agement Data Interface (MDI) within the CSR space. Acronyms m entioned in the re gisters are defined as fo llows: 9.1 MDI Register s 0 - 7 9.1.1 Register 0: Control Register Bit Definitions SC - self cle[...]

GD82559E R — Networking Silicon 66 Datasheet 9.1.2 Regis ter 1: Stat us Registe r Bit Definit ions 9 Res tar t Auto - Negotiation This bit restar ts the Auto-Negotiation process and is self- clearing. 1 = Restar t Auto-Negotiation process 0R W SC 8 Duple x Mode This bit con trols the duplex mode when A uto-Negotiation is disabled. If the PHY repo[...]

Datashee t 67 Networking Silicon — GD825 59ER 9.1.3 Registe r 2: PHY Ide ntifi er Register Bit D efinitions 9.1.4 Registe r 3: PHY Ide ntifi er Register Bit D efinitions 9.1.5 Regist er 4: Auto-Negotiation Ad ver tisement Register Bit Definitions 9.1.6 Register 5: Auto-Negotiation Link P ar tner Ability Register Bit Definitions Bit(s) Name Descri[...]

GD82559E R — Networking Silicon 68 Datasheet 9.1.7 Register 6: A uto-Negotiation Expansion Register Bit Definitions 9.2 MDI Register s 8 - 15 Registers eigh t through f i fteen are reserved for IEEE. 9.3 M DI Register 16 - 31 9.3.1 Register 16: PHY Unit Status and Control Register Bit Definitions Bit(s) Name Description Default R/W 15:5 Reser ved[...]

Datashee t 69 Networking Silicon — GD825 59ER 9.3.2 Register 17: PHY Unit Special Control Bit Definitions 8 P olarity T his bit indicates 10BASE-T polarity . 1 = Rev erse polarity 0 = Nor mal polarity -- RO 7:2 Reser ved These bits are reser v ed and should be set to 0B . 000000 RO 1 Speed This bit indicates the A u to-Neg otiation result. 1 = 10[...]

GD82559E R — Networking Silicon 70 Datasheet 9.3.3 Regis ter 18: PHY Addres s Register 9.3.4 Register 19: 100B ASE-TX Receive F alse Carrier Counter Bit Definitions 9.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions 9.3.6 Register 21: 100B ASE-TX Receive Error Frame Counter Bit Definitions 9.3.7 Register 22: Receive Symbol E[...]

Datashee t 71 Networking Silicon — GD825 59ER 9.3.8 Register 2 3: 100B ASE-TX Receiv e Premature End of Frame Err or Counter Bit Definitions 9.3.9 Regist er 24: 10BASE-T Receive E nd of Frame Err or Counter Bit Definitions 9.3.10 Regist er 25: 10B ASE-T T ransmit Jabber Detect Counter Bit Definitions 9.3.11 Regist er 26: Equalizer Control and Sta[...]

GD82559E R — Networking Silicon 72 Datasheet[...]

Datashee t 73 Networking Silicon — GD825 59ER 10. Electrical and Timing Specificatio ns 10.1 Absolute Maxim um Ratings Maximum ratings are listed below: Case T emperature under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 85 C Storage T emperature . . . . . . . . . . . . . . . . . . . . . . . . .[...]

GD82559E R — Networking Silicon 74 Datasheet NO TES: 1. These values are only applicable in 3.3 V signaling environments. Outside of this limit the input buff er must consume its m inim um current. 2. Input leakage currents include high-Z output leakage f or all bidirectional buff ers with tri-state outputs. 3. Signals without pull-up resistors h[...]

Datashee t 75 Networking Silicon — GD825 59ER NO TES: Current is measured on all V CC pi ns (V CC = 3.3 V). 1. T ransmitter peak current is att ained by dividi ng the measured maximum diff erential output peak volt age by the load resistance v alue. NO TES: Current is measured on all V CC pin s ( V CC = 3.3 V) . 1. T ransmitter peak current is at[...]

GD82559E R — Networking Silicon 76 Datasheet 10.3 A C Specifications NO TES: 1. Switching Current High specifications are not relev an t to PME#, SERR#, or INT A #, which are open drain outputs. 2. Maximum current requirem ents will be met as dr iv ers pull bey ond the first step volt age (A C driv e point). Equations defining these maximums (A a[...]

Datashee t 77 Networking Silicon — GD825 59ER 10.4 Timing Specificati ons 10.4.1 Cloc ks Speci fications 10.4.1.1 PCI Clock Specifi cations The 82559ER uses the PC I Clock signal directly . Fi gure 2 6 sho ws the clock wa vefo rm and requi red measurement points for the PCI Clock signal. Ta b l e 2 2 summarizes the PCI Clock specification s. NO T[...]

GD82559E R — Networking Silicon 78 Datasheet 10.4.2 Timing P arameters 10.4.2.1 M easurement and T est Cond it ions Figur e 27 , Figure 28 , and Ta b l e 2 4 define the co nditions under which timing measurements are done. The comp onent test guarantees that all timings are met with m inimum clock sle w rate (slowest ed ge) and vo ltage swing. Th[...]

Datashee t 79 Networking Silicon — GD825 59ER NO TE: Input test is done with 0.1V CC ov erdr ive. V max spec ifies the maximum peak-to-peak wav eform allowed for testing input timing. 10.4.2.2 PCI Timings NO TES: 1. Timing measurement conditions are illustrat ed in Figure 27 . 2. PCI minimum times are specified wit h loads as detailed in the PCI [...]

GD82559E R — Networking Silicon 80 Datasheet NO TES: 1. These timing specifications apply to Flash read cycles. The Flash timings ref ere nced are 28F020-150 timings. 2. These timing specifications apply to Flash write cycles . The Flash timings ref erenced are 28F020-150 timings. T able 26. F las h Tim ing P ar amet ers Symbol Parameter Min Max [...]

Datashee t 81 Networking Silicon — GD825 59ER 10.4.2.4 EEPROM Interface Ti mings The 82559ER is desig ned to supp ort a stand ard 64x 16, or 256 x16 seri al EEPR OM. Ta b l e 2 7 provides the timing p arameters for the EEPR OM interface signals. The timing parameters are illustrated in Figu re 30 . Figure 29. Flas h Timings f or a Read Cy c le FL[...]

GD82559E R — Networking Silicon 82 Datasheet 10.4.2.5 PHY Timings Figure 30. EEPROM Timings EECS FLA15EESK FLA13EEDI T51 T52 T54 T53 T ab le 28. 10BASE-T NLP Timing P arameters Symbol Par ameter Condition Min T yp Max U nits T56 T nlp_wi d NLP Width 10 Mbps 100 ns T57 T nlp_p er NLP P eriod 10 Mbps 8 24 ms Figure 31. 10BASE-T NLP Timings Normal L[...]

Datashee t 83 Networking Silicon — GD825 59ER Figure 32. A uto-Negotiation FLP Timings Fast Link Pulse T60 T58 T59 Clock Pulse Data Pulse Clock Pulse FLP Bursts T62 T63 T able 30. 100Base-TX T r ansmitter A C Specification Symbol Parameter Condition Min T yp Max Units T64 T jit TDP/TDN Diff erential Output P eak J i tt er HLS Data 1400 ps[...]

GD82559E R — Networking Silicon 84 Datasheet[...]

Datashee t 85 Networking Silicon — GD825 59ER 12. P acka g e and Pinou t Inf ormation 12.1 P acka ge Inf ormation The GD82559ER is a 196-pin Ball Grid Ar ray (BGA) package. Package dimension s are sho wn in Figur e 24 . More information on In tel device packaging is a v ailable in the Intel Pac kaging Handbook, which is av ailable from the Intel [...]

GD82559E R — Networking Silicon 86 Datasheet 12.2 Pinout Information 12.2.1 GD82559 ER Pin Assignments T ab le 15. G D82559ER Pin Ass ignments Pin Name Pin Name Pin Name A1 NC A2 SER R# A3 VCC A4 IDSE L A5 AD25 A6 P ME# A7 VCC A8 AD30 A9 AL TRST # A10 NC A11 VCC A1 2 LILED A13 TEST A14 NC B1 AD22 B 2 AD23 B3 VS SPP B4 AD24 B5 AD26 B6 AD27 B7 VSS [...]

Datashee t 87 Networking Silicon — GD825 59ER H1 ST OP# H2 INT A# H3 DEVSEL # H4 NC H5 VCC H6 VCC H7 VCC H8 VCC H 9 VSS H10 V SS H11 VSS H12 FLD6 H13 FLD5 H14 FLD4 J1 P AR J2 PERR# J3 GNT# J4 NC J5 VCC J6 VCC J7 VCC J8 VC C J9 VCC J10 VCC J11 VCC J12 FLA1 J13 F LA0 J14 FLD7 K1 AD16 K2 VSSPP K3 VCC K4 VCC K5 VCC K6 VCC K7 VCC K8 VCC K9 VCC K10 VCC[...]

GD82559E R — Networking Silicon 88 Datasheet 12.2.2 GD825 59ER Ball Gri d Array Diagram Figure 25. GD82 559ER Ball Gri d Array Dia gram NC FLA9 VCCPL X2 FLA13/ EEDI FLA16 VSSPL EECS AD2 AD3 AD6 AD8 VCCPP NC FLA8 FLA10 VSSPL X1 FLA14/ EEDO FLCS# VCCPL AD0 VCCPP AD4 AD7 AD9 AD10 VSSPP FLA6 FLA7 FLA11 FLA12 FLA15/ EESK FLWE# FLOE# AD1 VSSPP AD5 CBE0[...]