Intel IXP43X manual

Document Nu mber: 316844; Revision: 001US Intel ® IXP43X Product Line of Network Processors Hardware De sign Guidelines April 2007[...]

Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 2 Document Number: 316844; Revision: 001US INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH IN TEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHE RWISE, T O ANY INTELL ECTUA L PRO PER TY RIGHT S IS GR ANTED BY TH IS DOCUMENT . EXCEPT AS PROVIDED IN INTEL[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 3 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors Contents 1.0 Introduction ......... ......... .......... ........... ........ ........... .......... ......... .......... ........... ........ .... 9 1.1 Conten[...]

Intel ® IXP43X Product Line of Network Pr ocessors—Hardware De sign Guide lines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 4 Document Number: 316844; Revision: 001US 3.14 Power ... ........ ........... ........ ........... .......... ......... .......... ......... .......... ........... ........ .. 52 3.14.1 Decoupling Ca[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 5 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 11 HSS Interface Example ......... .. ......... .. .. .. .. ........ .. ... .. .......... ......... .. .. .. .. ......... .. .. .. ........ 42 12 Serial Flash a[...]

Intel ® IXP43X Product Line of Network Pr ocessors—Hardware De sign Guide lines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 6 Document Number: 316844; Revision: 001US 29 DDR Clock Timings ............. .......... ........... .......... ........... .......... ........... ........... ........ .... 75 30 DDRII-400 MHz Interfa[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 7 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors Revision History § § Date Revision Description April 2007 001 Initial release[...]

Intel ® IXP43X Product Line of Network Pr ocessors—Hardware De sign Guide lines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 8 Document Number: 316844; Revision: 001US[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 9 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 1.0 Introduction This design guide provides recommendation s for hardware and system designers who are developing with the Intel ® IXP43X Product Line of Netwo[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 10 Document Number: 316844; Revision: 001US 1.2 Related Documentation The reader of this design guide should also be familiar with the material and concept presented in the following documents: 1.3 Acron[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 11 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 1.4 Overview The Intel ® IXP43X Product Line of Network Processors is a highly integrated device, capable of interfacing with most common industry standard pe[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 12 Document Number: 316844; Revision: 001US • 16 GPIO (General Purpose Input Output) •P a c k a g i n g —4 6 0 - p i n P B G A — 31 mm by 31 mm — Commercial temperature (0° to 70° C) — Lead[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 13 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors Note: Figure 1 shows the Intel ® IXP435 Network Processor. For details on feature and SKU support listed by processor , see the Intel ® IXP43X Product Line o[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 14 Document Number: 316844; Revision: 001US 1.5 Typical Applications • SOHO-Small Business/Residential • Modular Router • Wireless Gateway(802.11a/b/g) • Network -A ttached Storage • Wired/Wire[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 15 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 2.0 System Architecture 2.1 System Architecture Description The Intel ® IXP43X Product Line of Network Processors is a multifunction processor that integrates[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 16 Document Number: 316844; Revision: 001US § § Figure 2. Example: Intel ® IXP43X Product Line of Ne twork Processors System Block Diagram Pow er Sup ply DDR SDRA M 16Mx 4x 16 512 Mby te (Fo ur C h i [...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 17 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 3.0 General Hardware Design Considerations This chapter contains information for imple menting and interfacing with major hardware blocks of the Intel ® IXP43[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 18 Document Number: 316844; Revision: 001US 3.2 DDRII/I SDRAM Interface The IXP43X network processors support unbuffered, DDRI-266 or DDRII-400 SDRAM technology , capable of addressing two memo ry banks [...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 19 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors The memory controller only corrects single bi t ECC errors on read cycles. The ECC is stored into the DDRII/DDRI SDRAM array along with the data and is checked[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 20 Document Number: 316844; Revision: 001US 3.2.2 DDRII/I SDRAM Initialization For instructions on DDRII/I SD RAM initialization, refer to DDR SDRAM Initialization subsection in the Memory Controller cha[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 21 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 3.3 Expansion Bus The Expansion Bus of the IXP43X network pr ocessors is specifically designed for compatibility with Intel-and Motorola* style microprocessor [...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 22 Document Number: 316844; Revision: 001US 3.3.2 Reset Configura tion Straps At power up or whenever RESET_IN_N is asserted, the Expansion-bus address outputs are switched to inputs and the state of the[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 23 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors EX_ADDR[10] IOWAIT_CS0 1 = EX_IOWAI T_N is sampled during the read/ write expansion bus cy cles for Chip Select 0. 0 = EX_IOWAIT_N is ignored for read an d wri[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 24 Document Number: 316844; Revision: 001US Note: The Intel XScale processor can operate at slower speeds than the factory programmed speed setting. This is done by placing a va lue on Expansion bus addr[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 25 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors Boot-str apping is required in certain address pi ns of the Expansion bus. If it is required to change access mode, after the system has booted, and during nor[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 26 Document Number: 316844; Revision: 001US 3.3.5 Flash Interface Figure 4 illustrates how a boot ROM is connected to the expansion bus. The flash (ROM) used in the block diagram is the Intel StrataFlash[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 27 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 3.4 UART Interface The UART interface are a 16550-compliant UAR T with the exception of tr ansmit and receive buffers. T ransmit and receive buff ers are 64 by[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 28 Document Number: 316844; Revision: 001US •C l e a r t o S e n d Note: The UAR T module does not support full mode m functionality . However , this can be implemented, by using GPIO ports to gene rat[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 29 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 3.5 MII Interface The IXP43X network processors support a maximum of two Ethernet MACs. Depending on the part number of the IXP43X network processors, v arious[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 30 Document Number: 316844; Revision: 001US 3.5.1 Signal Interface MII Table 9. MII NPE A Signal Recommendations Name Type Field Pull Up/ Down Recommendations ETHA_TXCLK I Ye s Tr a n s m i t C l o c k .[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 31 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 3.5.2 Device Connection, MII Figure 6 is a typical example of an Ethernet PHY device interfacing to one of the MACs via the MII hardware protocol. ETHC_rxclk I[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 32 Document Number: 316844; Revision: 001US 3.6 GPIO Interface The IXP43X network processors provide 16 general-purpose input/output pins to generate and capture application-specific inpu t and output si[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 33 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 3.6.1 Signal Interface 3.6.2 Design Notes The drive strength for GPIO[15:14] is limited t o 8 mA, while GPIO [13:0] can output up to 16 mA. When used for drivi[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 34 Document Number: 316844; Revision: 001US 3.7.1 Signal Interface Table 13. USB Host Signal Recommendations A typical implementation of a USB interface Host down-stream is sh own in Figure 9 . The Host [...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 35 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 2. If a 1.5-K Ω, pull-up resistor is connected to USB_P_NEG line, the USB port is identified as Low-speed mode. T o maintain signal integrity and minimize end[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 36 Document Number: 316844; Revision: 001US Figure 8. USB RCOMP and ICOMP Pin Requirement Figure 9. USB Host Down Stream Interface Ex ample In te l® IXP 4 3 X P roduc t Li n e o f N e two r k Pr o ce ss[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 37 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 3.8 UTOPIA Level 2 Interface The IXP43X network processors support th e industry-standard UTOPIA Level 2 bus interface. A dedicated Network Processor Engine (N[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 38 Document Number: 316844; Revision: 001US UTP_OP_DA TA[4] / ETHA_TXEN TRI No UTOPIA Level 2 Mode of Operation: UTOPIA Level 2 output data. Also known as UTP_TX_DA T A. Used to send data from the proces[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 39 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors UTP_IP_ FCI I Y es UTOPIA Lev el 2 Input Data flow control input signal. Als o known as RXEMPTY/ CLAV . Used to inform the pr ocessor of the ability of each po[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 40 Document Number: 316844; Revision: 001US UTP_IP_DA TA[5] / ETHA_COL IY e s UTOPIA Level 2 Mode of Operation: UTOP IA Level 2 input data. A lso known as RX_DA T A. Used by the processor to receive data[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 41 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 3.8.2 Device Connection The following example shown in Figure 10 shows a typical interface to an ADSL Framer via the UTOPIA bus. Notice that depending on the f[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 42 Document Number: 316844; Revision: 001US 3.9.1 Signal Interface 3.9.2 Device Connection Figure 11 shows a typical interface betwe en the IXP43X network processors and a SLIC CODEC, through the SSP and[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 43 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 3.10 SSP Interface The IXP43X network processors have a Sync hronous Serial P eripheral Interface (SSP) module. Its primary function is to prov ide connectivit[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 44 Document Number: 316844; Revision: 001US 3.10.1 Signal Interface 3.10.2 Device Connection There are a number of devices av ailable that can interface to SSP or SPI ports, these can range from R TC (R [...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 45 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 3.11 PCI Interface The PCI Controller of the IXP43X network processors is an industry-standard, 32-bit interface, high-performance bus that oper ates at 33 MHz[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 46 Document Number: 316844; Revision: 001US 3.11.1 Signal Interface Table 17. PCI Controll er (Sheet 1 of 2) Name Type Field Pull Up/ Down Recommendations PCI_AD[31:0] I/O Y es PCI Address/Data bus. When[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 47 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 3.11.2 PCI Interface Block Diagram While using the IXP43X network processors in Master mode, the PCI module can interface to up to four PCI cards (devices ) at[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 48 Document Number: 316844; Revision: 001US 3.11.3 PCI Option Interface The IXP43X network processors can be used in a design as a host or as an option device. This section describes how the IXP43X netwo[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 49 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors PCI_IRDY_N I/O Connect signal to same pin between the two devices. Connect a 10-K Ω pull-up resistor . I/O Initiator Ready PCI_STOP_N I/O Connect signal to sa[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 50 Document Number: 316844; Revision: 001US 3.11.4 Design Notes • The IXP43X network processors do not support the 5 V PCI signal interface by itself . Only the 3.3 V signal interface is supported with[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 51 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 3.12.1 Signal Interface 3.13 Input System Clock The IXP43X network processors require a 33.33-MHz reference clock to generate all internal clocks required incl[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 52 Document Number: 316844; Revision: 001US 3.13.3 Recommendations for Crystal Sel ection The parameters that sh ould be considered while selecting the crystal to be used are: Note: 1) The capacitance va[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 53 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 3.14 Power The IXP43X network processors have separ ate power supply domains for the processor core, DDRII/I SDRAM me mory , and input/ou tput peripherals to e[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 54 Document Number: 316844; Revision: 001US 3.14.1 Decoupling Capaci tance Recom mendatio ns It is common practice to place decoupling capacitors between the supply voltages and ground. Placement can be [...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 55 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors The IXP43X network processors can be configured at reset de- assertion via external, pull-down resistors on the address expa nsion bus signals EX_ADDR[23:21]. [...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 56 Document Number: 316844; Revision: 001US 4.0 General PCB Guide 4.1 PCB Overview Beginning with components selection, this chapter presents general PCB guidelines. In cases where it is too difficult to[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 57 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors • Place noisy parts (clock, processor , video , and so on.) at least 1.5 – 3 inches a way from the edge of the printed circuit board • Do not place noisy[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 58 Document Number: 316844; Revision: 001US • P oor routing density • Uncontrol led signal tr ace impedance • Lack of power/ground planes, re sulting in unacceptable crosstalk • R elatively high-[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 59 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors • F ast and slow tr ansmission line networks must be considered •P C B - b o a r d v e l o c i t i e s •B o a r d F R 4 ~ 4 . 3 • T arget impedance of [...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 60 Document Number: 316844; Revision: 001US 5.0 General Layout and Routing Guide 5.1 Overview This chapter provides routing and layout gu ides for hardware and systems based on the IXP43X network process[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 61 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors • Do not place high-frequency oscillators and switching network devices close to sensitive analog circuits. • Arrange the board so that return currents for[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 62 Document Number: 316844; Revision: 001US Figure 20 and Figure 21 show good and poor design pr actice s for via placement on surface-mount boards. Figure 22 shows minimum pad-to-pad clearance for surfa[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 63 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 5.2.2 Clock Signal Co ns iderations • Provide good return current paths for clock tr aces. • Keep clock tr aces away from the edge of the board and any oth[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 64 Document Number: 316844; Revision: 001US — Be aware of propagation delays be tween a microstrip and stripline. — Calculate capacitive loading of all comp onents and properly compensate with a seri[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 65 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors — Space within a group can be just 1 w. — Space between clock signals or clock to an y other signal should be 3 w. The coupled noise between adjacent trace[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 66 Document Number: 316844; Revision: 001US • Use at least one decoupling capacitor per power pin and place it as close as possible to the pin. • Minimize the number of traces routed across the air g[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 67 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 6.0 PCI Interface Design Considerations The IXP43X network processors have a single, 32-bit PCI device module that runs at 33 MHz. This chapter describes some [...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 68 Document Number: 316844; Revision: 001US 6.3 Clock Distribution T o meet timing and avoid clock ov erloading, it is recommended to use point -to-point clock distribution as shown in Figure 24 . Clock [...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 69 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 6.3.1 Trace Lengt h Limits Maximum trace lengths can be calculated for specific speeds at which the bus is intended to run. The limitations of the ma ximum tra[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 70 Document Number: 316844; Revision: 001US 6.3.2 Routing Guidelines It is recommended to route signals with respec t to an adjacent ground plane. If routing signals ov er power planes, ensure that the s[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 71 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 7.0 DDRII / DDRI SDRAM 7.1 Introduction This document is intended to be used as a guide for routing DDRII/DDRI SDRAM based on the Intel ® IXP435 Multi-Service[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 72 Document Number: 316844; Revision: 001US Table 24. DDRII/I Signal Groups Group Signal Name Description Clocks D_CK[2:0] / DDR_CK[2:0] DDRII/I SDRAM Differential Clocks D_CK_N[2:0] / DDR_CK_N[2:0] DDRI[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 73 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors Figure 25. Processor-DDR II/I SDRAM Interface DA T A [ 31: 0 ] A D D R ESS[ 13 : 0 ] CL OCK [ 2: 0] , C L O CK #[ 2: 0] CLO CK ENAB LE [1: 0 ] C H IP SEL EC T#[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 74 Document Number: 316844; Revision: 001US Table 25. Supported DDRI 32- bit SDRAM Configurations DDR SDRAM Technology DDR SDRAM Arrangement # Banks Address Size Leaf Select Total Memory Size a a. Table [...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 75 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors The DDR_RCOMP signal must be termin ated through resistors specified in Figure 26 . This allows the DDRII/I controller to make temper ature and process adjustm[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 76 Document Number: 316844; Revision: 001US 7.3 DDRII OCD Pin Requirements Figure 27 shows the requirement for the DDRRES1 and DDRRES2 pins. Note: Since the OCD calibr ation function is not en abled, DDR[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 77 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors Figure 29. DDR SDRAM Write Timings Figure 30. DDR SDRAM Read Timin gs CK DQ S DQ T VA 1 T VB 1 T VB 5 T VA 5 CS [1 :0 ]# T VB 3 T VA 3 AD D R / C T R L DQ S # [...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 78 Document Number: 316844; Revision: 001US Figure 31. DDR - Write Pr eamble/Postamble Duration Table 30. DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum Units Notes T [...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 79 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 7.3.1.0.1 Printe d Cir cuit Board Layer Stackup The layer stackup used for the Intel ® IXP435 Multi-Service Residential Gateway R eference Platform is a 6-lay[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 80 Document Number: 316844; Revision: 001US — T able 31 on page 79 Data Group to Strobe Summary: • The more restrictive data group to strobe timing occurs for read operations — T able 32 on page 80[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 81 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors Data D_CB0 / DDR_CB0 402.94 D_CB4 / DDR_CB4 3 85.50 D_CB1 / DDR_CB1 393.93 D_CB5 / DDR_CB5 4 19.24 D_CB2 / DDR_CB2 377.69 D_CB6 / DDR_CB6 3 98.22 D_CB3 / DDR_C[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 82 Document Number: 316844; Revision: 001US 7.3.3 Routing Guidelines 7.3.3.1 Clock Group The clock signal group includes the differential clock pairs D_CK[2:0] / DDR_CK[2:0] and D_CK_N[2:0] / DDR_CK_N[2:[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 83 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 7.3.3.2 Data an d Control Groups The data and control signal group includes D_CB[7:0]/DDR_CB[7:0], D_DQ[31:0] / DDR_DQ[31:0], D_DQS[4:0]/DDR_DQS[4:0], D_DM[4:0[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 84 Document Number: 316844; Revision: 001US internal layers, ex cept for pin escapes. It is recommended that pin escape vias be located directly adjacent to the ball pads on all signals. Surface layer ro[...]

Intel ® IXP43X Product Line of Network Processors April 2007 HDG Document Number : 316844; Revision: 001US 85 Hardware Design Guidelines—Intel ® IXP43X Product Line of Network Processors 7.3.3.3 Command Groups The command signal groups include all signals D_MA[13:0]/DDR_MA[13:0], D_BA[1:0]/DDR_BA[1:0], D_RAS/DDR_RAS, D_C AS/DDR_CA S and D_WE/DD[...]

Intel ® IXP43X Product Line of Network Processors—Hardware Design Guidelines Intel ® IXP43X Product Line of Network Proce ssors HDG April 2007 86 Document Number: 316844; Revision: 001US § § Series R esistor 2 0 Ω Nominal T race Width 1 Internal (Strip Line) 3.5 mils, External (Micro Strip) 5 mils Nominal Pair Spacin g (e dge to edge) 2 Inte[...]