National Instruments 320030-01 manual

© Copyright 1985, 1997 National Instruments Corporation. All Rights Reserved. GPIB-1014 User Manual March 1997 Edition Part Number 320030-01[...]

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Limited Warranty The GPIB-1014 is warranted against defects in materials and workmanship for a period of two years from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and [...]

Warning Regarding Medical and Clinical Use of National Instruments Products National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a pot[...]

FCC/DOC Radio Frequency Interference Compliance This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions in this manual, may cause interference to radio and television reception. This equipment has been tested and found to comply with the following two regulatory agencies: Fe[...]

© National Instruments Corporation vii GPIB-1014 User Manual Contents About This Manual ............................................................................................................ xiii Organization of This Manual ........................................................................................ xiii Conventions Used in This [...]

Contents GPIB-1014 User Manual viii © National Instruments Corporation Register Description .......................................................................................... 4-2 Register Description Format ................................................................. 4-3 Interface Registers ............................................[...]

Contents © National Instruments Corporation ix GPIB-1014 User Manual Going from Standby to Active Controller ......................................................... 5-4 Going from Active to Idle Controller ................................................................ 5-5 The GPIB-1014 as GPIB Talker and Listener ..............................[...]

Contents GPIB-1014 User Manual x © National Instruments Corporation 68450 DMAC ................................................................................................................ 6-14 DMAC Channel Operation ................................................................................ 6-15 Initialization and Transfer Phases ........[...]

Contents © National Instruments Corporation xi GPIB-1014 User Manual Data Lines .......................................................................................................... E-2 Handshake Lines ............................................................................................... E-2 NRFD (not ready for data) ................[...]

Contents GPIB-1014 User Manual xii © National Instruments Corporation Figure 6-3. Array Format for Linked Chaining Modes ...................................................... 6-21 Figure E-1. The GPIB Connector and Signal Assignments ................................................ E-4 Figure E-2. Linear Configuration ............................[...]

© National Instruments Corporation xiii GPIB-1014 User Manual About This Manual The GPIB-1014 User Manual describes the mechanical and electrical aspects of the GPIB-1014, the data transfer features, and contains information concerning its operation and programming. Organization of This Manual The GPIB-1014 User Manual is organized as follows: •[...]

About This Manual GPIB-1014 User Manual xiv © National Instruments Corporation • Appendix F, Mnemonics Key , contains a mnemonics key that defines the mnemonics (abbreviations) used throughout this manual for functions, remote messages, local messages, states, bits, registers, integrated circuits, system functions, and VMEbus operations and sign[...]

About This Manual © National Instruments Corporation xv GPIB-1014 User Manual • Motorola Semiconductor Technical Data MC68450 Advance Information Direct Memory Access Controller (DMAC) • Hitachi Microcomputer System HD68450 DMAC (Direct Memory Access Controller) Customer Communication National Instruments wants to receive your comments on our [...]

© National Instruments Corporation 1-1 GPIB-1014 User Manual Chapter 1 Introduction This chapter describes the GPIB-1014, lists the contents and oiptional equipment for your GPIB-1014 kit, and explains how to unpack the GPIB-1014 kit. The GPIB-1014 is a high-performance IEEE 488 interface for the VMEbus. This interface permits IEEE 488 compatible [...]

Introduction Chapter 1 GPIB-1014 User Manual 1-2 © National Instruments Corporation Figure 1-1 shows the GPIB-1014 interface board. Figure 1-1. GPIB-1014 Interface Board Art not available in PDF version of document.[...]

Chapter 1 Introduction © National Instruments Corporation 1-3 GPIB-1014 User Manual The GPIB-1014 interface kit includes hardware and programming examples to implement the GPIB functions. Optional cables are supplied for interconnection with other devices on the GPIB. What Your Kit Should Contain Your GPIB-1014 kit should contain the following com[...]

Introduction Chapter 1 GPIB-1014 User Manual 1-4 © National Instruments Corporation Unpacking Follow these steps when unpacking your GPIB-1014. 1. Verify that the pieces contained in the package you received match the kit parts list given earlier in this chapter. Do not remove the board from its plastic bag at this point. 2. Your GPIB-1014 board i[...]

© National Instruments Corporation 2-1 GPIB-1014 User Manual Chapter 2 General Description This chapter contains the electrical specifications for the GPIB-1014, the data transfer features, and describes the characteristics of key interface board components. Electrical Characteristics All integrated circuit drivers and receivers used on the GPIB-1[...]

General Description Chapter 2 GPIB-1014 User Manual 2-2 © National Instruments Corporation Table 2-1. GPIB-1014 Signals (continued) Driver Device Receiver Device Bus Signals Part Number Part Number BR0*-BR3* AS756 LS241 BBSY* AS756 LS240 IACKIN* – LS240 IACKOUT* F1241 – IRQ1*-IRQ7* 74145 – BERR* – F1241 SYSFAIL* AS756 – SYSRESET* – LS2[...]

Chapter 2 General Description © National Instruments Corporation 2-3 GPIB-1014 User Manual to generate its board select signal. It then decodes the lowest eight lines, A8 through A1, to address the following items: • The 68450 DMA Controller (DMAC) • The µ PD7210 GPIB Talker/Listener/Controller (TLC) • Two 8-bit, write-only Configuration Re[...]

General Description Chapter 2 GPIB-1014 User Manual 2-4 © National Instruments Corporation Table 2-3. 68450 Internal DMA Registers Ad dress (Base + Hex Offset) Mode Register Channel Size 0A R/W Memory Transfer Counter (MTCR0) 0 16 bits 0C R/W Memory Address Register (MAR0) 0 32 bits 29 R/W Memory Function Code (MFCR0) 0 8 bits 14 R/W Device Addres[...]

Chapter 2 General Description © National Instruments Corporation 2-5 GPIB-1014 User Manual Table 2-3. 68450 Internal DMA Registers (continued) Address (Base + Hex Offset) Mode Register Channel Size 85 R/W Operation Control (OCR2) 2 8 bits 86 R/W Sequence Control (SCR2) 2 8 bits 87 R/W Channel Control (CCR2) 2 8 bits AD R/W Channel Priority (CPR2) [...]

General Description Chapter 2 GPIB-1014 User Manual 2-6 © National Instruments Corporation Memory addresses generated by the GPIB-1014 are 24 bits wide and the VMEbus Address Modifier Lines (AM5 through AM0) are fully programmable using function code registers located in the 68450 and three hardware jumpers (W3, W4, and W5). (See Chapter 3 for ins[...]

Chapter 2 General Description © National Instruments Corporation 2-7 GPIB-1014 User Manual Data Transfer Bus (DTB) Requester The GPIB-1014 arbitrates for the DTB before each DMA transfer. The board is designed for you to select, through software, one of four VMEbus request lines (BR0* through BR3*) using two bits in Configuration Register 1. To ma[...]

General Description Chapter 2 GPIB-1014 User Manual 2-8 © National Instruments Corporation • GPIB Listener response time (DAV* low to NDAC* high) • GPIB Talker response time (NRFD* high to DAV* low) • GPIB-1014 transfer mode: Cycle Steal with hold, programmable timeout • T1 timing: high-speed Transfer rates of 250 to 350 kbytes/sec can be [...]

Chapter 2 General Description © National Instruments Corporation 2-9 GPIB-1014 User Manual 3 Lines Digital Voltmeter Able to Talk and Listen Device C Printer Able to Listen Device B Device A VMEbus Computer with GPIB-1014 Able to Talk, Listen, and Control 8 Lines 5 Lines DIO1-DIO8 DAV (Data Valid) NRFD (Not Ready for Data) NDAC (Not Data Accepted)[...]

General Description Chapter 2 GPIB-1014 User Manual 2-10 © National Instruments Corporation Computer Center Up to 300 Meters (RS-422) R&D Lab Microprocessor W ork Station Production & T esting VMEbus Computer with GPIB-1014 IEEE 488 Interface IBM PC with GPIB-PC IEEE 488 Interface S-100 Computer GPIB-696P IEEE 488 Interface PDP 1 1/44 with[...]

Chapter 2 General Description © National Instruments Corporation 2-11 GPIB-1014 User Manual Figure 2-3 is a block diagram of the GPIB-1014. GPIB µ PD7210 TLC 68450 DMAC Data T ransfer Bus Priority Interrupt DTB Arbitration Utility VMEbus Data T ransceivers Control T ransceivers Configuration Registers DMA Gating and Control GPIB Synchronization a[...]

General Description Chapter 2 GPIB-1014 User Manual 2-12 © National Instruments Corporation The interface consists of these major components, which are discussed in greater detail in Chapter 6. • VMEbus Interface Consists of the buffers, drivers, and transceivers for the address, data, status, and control lines used on the VMEbus, plus other log[...]

Chapter 2 General Description © National Instruments Corporation 2-13 GPIB-1014 User Manual Table 2-5 lists the capabilities of the GPIB-1014 in terms of the IEEE 488 standard codes. Table 2-5. GPIB-1014 IEEE 488 Interface Capabilities Capability Code Description SH1 Complete Source Handshake capability AH1 Complete Acceptor Handshake capability D[...]

General Description Chapter 2 GPIB-1014 User Manual 2-14 © National Instruments Corporation Table 2-5. GPIB-1014 IEEE 488 Interface Capabilities (continued) Capability Code Description DC1 Complete Device Clear capability with software interpretation DT1 Complete Device Trigger capability with software interpretation C1, C2, C3, C4, C5 Complete Co[...]

Chapter 2 General Description © National Instruments Corporation 2-15 GPIB-1014 User Manual • Receive control • Pass control • Conduct a Parallel Poll • Take control synchronously or asynchronously Table 2-6 contains the GPIB-1014 IEEE 1014 compliance levels. Table 2-6. GPIB-1014 IEEE 1014 Interrupter Compliance Levels Compliance Notation [...]

© National Instruments Corporation 3- 1 GPIB-1014 User Manual Chapter 3 Configuration and Installation This chapter describes the steps needed to configure and install the GPIB-1014 hardware. Configuration Before installing the GPIB-1014 in the VMEbus backplane, the following options must be configured with hardware jumpers that are located on the[...]

Configuration and Installation Chapter 3 GPIB-1014 User Manual 3- 2 © National Instruments Corporation Figure 3-1 shows the locations of the GPIB-1014 configuration jumpers and switches. Figure 3-1. Parts Locator Diagram Art not available in PDF version of document.[...]

Chapter 3 Configuration and Installation © National Instruments Corporation 3- 3 GPIB-1014 User Manual Access Mode The GPIB-1014 can be configured to respond to Supervisor (privileged) or User (non-privileged) access. Hardware jumper W2 is used to select the access mode that is automatically in effect upon a power-up or a system reset. The access [...]

Configuration and Installation Chapter 3 GPIB-1014 User Manual 3- 4 © National Instruments Corporation Set Base Address Using Jumper Block W1 Move the jumper to the side labeled 1 to select a logical one for the corresponding address bit, or to the side labeled 0 to select a logical zero. Figure 3-3 shows the configuration for a base address 2000 [...]

Chapter 3 Configuration and Installation © National Instruments Corporation 3- 5 GPIB-1014 User Manual DMA Address Modifier Code Output During a DMA cycle, the GPIB-1014 sends out a 6-bit Address Modifier (AM) code to the VMEbus lines AM5 through AM0. The correct code is obtained by both programming the DMAC and setting jumpers W3, W4, and W5. Fig[...]

Configuration and Installation Chapter 3 GPIB-1014 User Manual 3- 6 © National Instruments Corporation Table 3-1. Programming Values for Default Settings of W3, W4, and W5 FCR Bits AM Codes M2 through M0 29 000 2A 001 2D 100 2E 101 39 010 3A 011 3D 110 3E 111 If it is necessary to produce a code other than those listed in Table 3-1, you can produc[...]

Chapter 3 Configuration and Installation © National Instruments Corporation 3- 7 GPIB-1014 User Manual For example, to produce an AM code of 17 hex (a binary value of 010111), complete the following steps: 1. Set jumper W3 to 0. 2. Set jumper W4 to 0. 3. Set jumper W5 to AM(1). 4. Write the pattern 00000111 to the FCR of the DMAC. Other Configurat[...]

Configuration and Installation Chapter 3 GPIB-1014 User Manual 3- 8 © National Instruments Corporation Table 3-3. GPIB-1014 Pin Assignment on VMEbus Connector P1 Pin No. Signal Used Signal Not Used Pin No. Signal Used Signal Not Used A1 D00 A17 GND A2 D01 A18 AS* A3 D02 A19 GND A4 D03 A20 IACK* A5 D04 A21 IACKIN* A6 D05 A22 IACKOUT* A7 D06 A23 AM4[...]

Chapter 3 Configuration and Installation © National Instruments Corporation 3- 9 GPIB-1014 User Manual Table 3-4. GPIB-1014 Pin Assignment on VMEbus Connector P2 Signal Signal Signal Signal Pin No. Used Not Used Notes Pin No. Used Not Used Notes A1 CA15 1,4 A17 User I/O A2 CA13 1,4 A18 User I/O A3 CA11 1,4 A19 User I/O A4 CA9 1,4 A20 User I/O A5 U[...]

Configuration and Installation Chapter 3 GPIB-1014 User Manual 3- 10 © National Instruments Corporation Cabling Two options are available for GPIB I/O from the GPIB-1014: • A Front Panel Plug-In Connector • A VMEbus P2 Connector The Model GPIB-1014-1 interface board has a standard 24-pin IEEE 488 connector on the front panel of the board. A st[...]

© National Instruments Corporation 4-1 GPIB-1014 User Manual Chapter 4 Register Bit Descriptions This chapter contains a description of the register map, a list of interface registers, and a description of the DMA registers. Register Map The register map for the GPIB-1014 is shown in Table 4-1. This table gives the register name, the register addr[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-2 © National Instruments Corporation Table 4-1. GPIB-1014 Register Map (continued) Register Name Address (Hex) Type Size DMA Register Group: Address Registers Memory Address Register Base address + 0C Read/Write 32-bit Base Address Register Base address + 1C Read/Write 32-bit Device Addre[...]

Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-3 GPIB-1014 User Manual Register Description Format The remainder of this chapter discusses each of the GPIB-1014 registers in the order shown in Table 4-1. Each register group is introduced, followed by a detailed bit description of each register. The register bit map shows [...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-4 © National Instruments Corporation Interface Registers Twenty-one GPIB Interface registers, eight of which are readable and 13 of which are writable, are located within the NEC µ PD7210 Talker/Listener/Controller (TLC) integrated circuit. Each of the 21 interface registers is addressed[...]

Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-5 GPIB-1014 User Manual DIR CDOR (Contents of Read Register) (Contents of Write Register) Legend Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W R W R W R W R W R W R W R W DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 CDO7 CDO6 CDO5 CDO4 CDO3 CDO2 CDO1 CDO0 ISR1 IMR1 ISR2 IMR2 SPSR SP[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-6 © National Instruments Corporation Control Code Command Code When CNT2-CNT0 is: ICR is loaded with: PPR is loaded with: AUXRA is loaded with: AUXRB is loaded with: AUXRE is loaded with: W AUXMR CNT2 CNT1 CNT0 COM4 COM3 COM2 COM1 COM0 0 CLK3 CLK2 CLK1 CLK0 U S P3 P2 P1 BIN XEOS REOS HLDE[...]

Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-7 GPIB-1014 User Manual Data In Register (DIR) VMEbus Address: Base Address + 111 (hex) Attributes: Read Only, Internal to TLC 7 6 54 32 1 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 R The Data In Register (DIR) is used to move data from the GPIB to the computer when the interface is a[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-8 © National Instruments Corporation Command/Data Out Register (CDOR) VMEbus Address: Base Address + 111 (hex) Attributes: Write Only, Internal to TLC 7 6 54 32 1 0 CDO7 CDO6 CDO5 CDO4 CDO3 CDO2 CDO1 CDO0 The Command/Data Out Register (CDOR) is used to move data from the VMEbus to the GPI[...]

Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-9 GPIB-1014 User Manual Interrupt Status Register 1 (ISR1) VMEbus Address: Base Address + 113 (hex) Attributes: Read Only, Internal to TLC Bits are cleared when read Interrupt Mask Register 1 (IMR1) VMEbus Address: Base Address + 113 (hex) Attributes: Write Only, Internal to [...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-10 © National Instruments Corporation Bit Mnemonic Description undefined: GPIB command not automatically recognized and executed by TLC ACDS: GPIB Accept Data State CPT ENABLE: AUXRB[0]w UDPCF: Undefined Primary Command Function SCG: GPIB Secondary Command Group message pon: Power On Rese[...]

Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-11 GPIB-1014 User Manual Bit Mnemonic Description SCG: GPIB Secondary Command Group ACDS: GPIB Accept Data State pon: Power On Reset Read ISR1: Bit is cleared immediately after it is read The APT bit indicates that a secondary GPIB address has been received and is available i[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-12 © National Instruments Corporation Bit Mnemonic Description EOS: GPIB END Of String message REOS: Reception of GPIB EOS allowed, AUXRA[2]w ACDS: GPIB Accept Data State pon: Power On Reset read ISR1: Bit is cleared immediately after it is read The END RX bit is set when the TLC is a Lis[...]

Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-13 GPIB-1014 User Manual Bit Mnemonic Description write CDOR: Bit is set immediately after writing to the Command/Data Out Register SDYS to SIDS: Transition from GPIB Source Delay State to Source Idle State pon: Power On Reset read ISR1; Bit is cleared immediately after it is[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-14 © National Instruments Corporation Bit Mnemonic Description Notes LACS: GPIB Listener Active State ACDS: GPIB Accept Data State continuous mode: Listen in continuous mode auxiliary command in effect pon: Power On Reset read ISR1: Bit is cleared immediately after it is read finish Hands[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-14 © National Instruments Corporation Interrupt Status Register 2 (ISR2) VMEbus Address: Base Address + 115 (hex) Attributes: Read Only, Internal to TLC Bits are cleared when read Interrupt Mask Register 2 (IMR2) VMEbus Address: Base Address + 115 (hex) Attributes: Write Only, Internal to[...]

Bit Mnemonic Description ERR IE: Enable Interrupt on Error Bit END RX: End Received Bit END IE: Enable Interrupt on End Received Bit DEC: Device Clear Bit DEC IE: Enable Interrupt on Device Clear Bit DO: Data Out Bit DO IE: Enable Interrupt on Data Out Bit DI: Data In Bit DI IE: Enable Interrupt on Data In Bit SRQI: Service Request Input Bit SRQI I[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-16 © National Instruments Corporation Bit Mnemonic Description 5r LOK Lockout Bit LOK is used, along with the REM bit, to indicate the status of the TLC GPIB Remote/Local (RL) function. If set, the LOK bit indicates that the TLC is in Local With Lockout State (LWLS) or Remote With Lockout[...]

Bit Mnemonic Description 2r LOKC Lockout Change Bit 2w LOKC IE Lockout Change Interrupt Enable Bit LOKC is set by: any change in LOK LOKC is cleared by: pon + (read ISR2) Notes LOK: ISR2[5]r pon: Power On Reset read ISR2: Bit is cleared immediately after it is read LOKC is set when there is a change in the LOK bit, ISR2[5]r, (REMS +RELS). 1r REMC R[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-18 © National Instruments Corporation Bit Mnemonic Description Notes TA: Talker Active bit, ADSR[1]r LA: Listener Active bit, ADSR[2]r CIC: Controller-In-Charge bit, ADSR[7]r MJMN: Major/Minor bit, ADSR[0]r lon: Listen Only bit, ADMR[6]w ton: Talk Only bit, ADMR[7]w pon: Power On Reset re[...]

Serial Poll Status Register (SPSR) VMEbus Address: Base Address + 117 (hex) Attributes: Read Only, Internal to TLC Serial Poll Mode Register (SPMR) VMEbus Address: Base Address + 117 (hex) Attributes: Write Only, Internal to TLC R W 7 6 54 32 1 0 S8 S8 PEND rsv S6 S6 S5 S5 S4 S4 S3 S3 S2 S2 S1 S1 Bit Mnemonic Description 7r S8 Serial Poll Status Bi[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-20 © National Instruments Corporation Address Status Register (ADSR) VMEbus Address: Base Address + 119 (hex) Attributes: Read Only, Internal to TLC 75 6 4 32 10 R CIC ATN* SPMS LPAS TPAS LA TA MJMN The Address Status Register (ADSR) contains information that can be used to monitor the TL[...]

Bit Mnemonic Description 3r TPAS Talker Primary Addressed State Bit TPAS is used when the TLC is configured for extended GPIB addressing, and, when set, indicates that the TLC has received its primary GPIB talk address. In extended mode addressing (mode 3 addressing), TPAS=1 indicates that the secondary address being received as the next GPIB comma[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-22 © National Instruments Corporation Address Mode Register (ADMR) VMEbus Address: Base Address + 119 (hex) Attributes: Write Only, Internal to TLC W 7 6 54 32 1 ton 1on TRM1 TRM0 0 0 ADM1 ADM0 0 Bit Mnemonic Description 7w ton Talk Only Bit By setting ton programs, the TLC becomes a GPIB[...]

Bit Mnemonic Description 1-0w ADM[1-0] Address Mode Bits 1 through 0 These bits state the addressing mode currently in effect–that is, the manner in which the information in ADR0 and ADR1 is interpreted (see Address Register 0 and Address Register 1 later in this chapter). If both bits are zero, then the TLC does not respond to GPIB address comma[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-24 © National Instruments Corporation Bit Mnemonic Description ADM0 and ADM1 must be cleared when either of the two programmable bits ton or lon is set. For more information on the different addressing modes supported by the GPIB-1014, refer to the Addressed Implementation of Talker and L[...]

Command Pass Through Register (CPTR) VMEbus Address: Base Address + 11B (hex) Attributes: Read Only, Internal to TLC R 7 6 54 32 1 0 CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0 Bit Mnemonic Description 7-0r CPT[7-0] Command Pass Through Bits 7 through 0 These bits are used to transfer undefined multiline GPIB command messages from the GPIB DIO lines to[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-26 © National Instruments Corporation Table 4-3. Multiline GPIB Commands Recognized by the µ PD7210 (continued) Hex Number Message Description 15 PPU Parallel Poll Unconfigure 18 SPE Serial Poll Enable 19 SPD Serial Poll Disable 20-3E MLA My Listen Address 3F UNL Unlisten 40-5E MTA My Ta[...]

Auxiliary Mode Register (AUXMR) VMEbus Address: Base Address + 11B (hex) Attributes: Write Only, Internal to TLC Permits Access to Hidden Registers W 7 6 54 32 1 0 CNT1 CNT0 CNT2 COM4 COM3 COM2 COM1 COM0 The Auxiliary Mode Register (AUXMR) is used to issue auxiliary commands. It is also used to program the five hidden registers: • Auxiliary Regis[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-28 © National Instruments Corporation Table 4-4. Auxiliary Command Summary Function Code* (COM4-COM0) Hex 4 3 2 1 0 Code** Auxiliary Command 0 0 0 0 0 00 Immediate Execute pon 0 0 0 1 0 02 Chip Reset 0 0 0 1 1 03 Finish Handshake 0 0 1 0 0 04 Trigger 0 0 1 0 1 05 Return to Local 0 0 1 1 0[...]

Table 4-5 shows the functions that are executed when the AUXMR Control Code (CNT2 through CNT0) is loaded with 000 (binary) and the Command Code (COM4 through COM0) is loaded. Table 4-5. Auxiliary Commands: Detail Description Command Code (COM4-COM0) 4 3 2 1 0 Description 0 0 0 0 0 Immediate Execute Pon This command generates a local pon message th[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-30 © National Instruments Corporation Table 4-5. Auxiliary Commands: Detail Description (continued) Command Code (COM4-COM0) 4 3 2 1 0 Description 0 0 0 1 1 Finish Handshake (FH) The Finish Handshake command finishes a GPIB Handshake that was stopped because of a Holdoff on RFD or DAC. 0 [...]

Table 4-5. Auxiliary Commands: Detail Description (continued) Command Code (COM4-COM0) 4 3 2 1 0 Description 0 0 0 0 1 Clear Parallel Poll Flag 0 1 0 0 1 Set Parallel Poll Flag These commands set the Parallel Poll Flag to the value of COM3. The value of the Parallel Poll Flag is used as the local message ist when bit four of Auxiliary Register B is[...]

Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-32 © National Instruments Corporation Table 4-5. Auxiliary Commands: Detail Description (continued) Command Code (COM4-COM0) 4 3 2 1 0 Description 1 1 0 1 1 In continuous mode, the local message rdy is issued when the (continued) Acceptor Not Ready State (ANRS) is initiated unless data bl[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-33 GPIB-1014 User Manual Hidden Registers The hidden registers are loaded through the Auxiliary Mode Register (AUXMR). AUXMR[7-5] is loaded with the hidden register number, and AUXMR[4-0] is loaded with the data to be transferred to the hidden register. The hidden registers canno[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-34 © National Instruments Corporation Internal Counter Register (ICR) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 001 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC Accessed through AUXMR 43 2 1 0 W 0 CLK3 CLK2 CLK1 CLK0 Bit Mnemonic Description 4w 0 Reserved Bi[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-35 GPIB-1014 User Manual Parallel Poll Register (PPR) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 011 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC Accessed through AUXMR 43 2 1 0 W U S P3 P2 P1 This 5-bit command code determines the manner in whic[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-36 © National Instruments Corporation Bit Mnemonic Description 3w S Status Bit Polarity (Sense) Bit The S bit is used to indicate the polarity (or sense) of the TLC local ist message. If S=1, the status is in phase , meaning that if, during a Parallel Poll response, S=ist=1, and U=0, the TLC [...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-37 GPIB-1014 User Manual Auxiliary Register A (AUXRA) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 100 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC Accessed through AUXMR 43 2 1 0 W BIN XEOS REOS HLDE HLDA Writing to Auxiliary Register A (AUXRA) is[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-38 © National Instruments Corporation Bit Mnemonic Description 1-0w HLDE Holdoff on End Bit HLDA Holdoff on All Bit HLDE and HLDA together determine the GPIB data receiving mode. The four possible modes are as follows: HLDE HLDA Data Receiving Mode 0 0 Normal Handshake 0 1 RFD Holdoff on All [...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-39 GPIB-1014 User Manual Auxiliary Register B (AUXRB) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 101 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC Accessed through AUXMR 43 2 1 0 W ISS INV TRI SPEOI CPT ENABLE Writing to Auxiliary Register B (AUXR[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-40 © National Instruments Corporation Bit Mnemonic Description 2w TRI Three-State Timing Bit The TRI bit determines the TLC GPIB Source Handshake Timing, T1. TRI can be set to enable high-speed data transfers (T1 ≥ 500 nsec) when tri-state GPIB drivers are used. (The GPIB-1014D uses tri-sta[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-41 GPIB-1014 User Manual Auxiliary Register E (AUXRE) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 110 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC Accessed through AUXMR 43 2 1 0 W 0 0 0 DHDC DHDT Writing to Auxiliary Register E (AUXRE) is done vi[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-42 © National Instruments Corporation Address Register 0 (ADR0) VMEbus Address: Base Address + 11D (hex) Attributes: Read Only, Internal to TLC 76543210 X DT0 DL0 AD5-0 AD4-0 AD3-0 AD2-0 AD1-0 R Address Register 0 (ADR0) reflects the internal GPIB address status of the TLC as configured using[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-43 GPIB-1014 User Manual Address Register (ADR) VMEbus Address: Base Address + 11D (hex) Attributes: Write Only, Internal to TLC 76543210 ARS DT DL AD5 AD4 AD3 AD2 AD1 W The Address Register (ADR) is used to load the internal registers ADR0 and ADR1. Both ADR0 and ADR1 must be lo[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-44 © National Instruments Corporation Address Register 1 (ADR1) VMEbus Address: Base Address + 11F (hex) Attributes: Read Only, Internal to TLC 76543210 EOI DT1 DL1 AD5-1 AD4-1 AD3-1 AD2-1 AD1-1 R Address Register 1 (ADR1) indicates the status of the GPIB address and enable bits for the secon[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-45 GPIB-1014 User Manual End of String Register (EOSR) VMEbus Address: Base Address + 11F hex Attributes: Write Only, Internal to TLC W 7 6 54 32 1 0 EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0 The End Of String Register (EOSR) holds the byte used by the TLC to detect the end of a GP[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-46 © National Instruments Corporation DMA Registers The onboard DMA Controller is a 68450 DMAC. This chip is extremely flexible and uses four independent DMA channels. The DMAC can support single address (flyby) transfers or dual address (flowthrough) transfers. The GPIB-1014 uses two channel[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-47 GPIB-1014 User Manual Register Offset 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C 3E 15 0 Register Offset 01 03 05 07 09 0B 0D 0F 11 13 15 17 19 1B 1D 1F 21 23 25 27 29 2B 2D 2F 31 33 35 37 39 3B 3D 3F 87 CSR CER MTCR MAR MSB LS[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-48 © National Instruments Corporation The following paragraphs describe the channel configuration and status registers. More information on the 68450 can be found in the Motorola Semiconductor Technical Data MC68450 Advance Information Direct Memory Access Controller (DMAC) or the Hitachi Mic[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-49 GPIB-1014 User Manual Transfer Count Registers The Memory Transfer Counter Register (MTCR) and the Base Transfer Counter Register (BTCR) are 16-bit registers. The MTCR is used to specify how many operands will be transferred. (An operand can be either a byte (8 bits) or a word[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-50 © National Instruments Corporation Function Code Registers VMEbus Address: Base Address + 29 (hex) for Memory Function Code Base Address + 31 (hex) for Device Function Code Base Address + 39 (hex) for Base Function Code Attributes: Read/Write, Internal to DMAC 7 6 54 32 1 0 X XXXX M 2 M 1 [...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-51 GPIB-1014 User Manual Device Control Register VMEbus Address: Base Address + 04 (hex) Attributes: Read/Write, Internal to DMAC 7 6 54 32 1 0 XRM DTYP DPS 0 PCL R/W The Device Control Register (DCR) is a device-soriented control register. Bit Mnemonic Description 7-6r/w XRM Ext[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-52 © National Instruments Corporation Bit Mnemonic Description 2r/w 0 Reserved Bit Write a zero to this bit. 1-0r/w PCL Peripheral Control Line Bits 1 through 0 Each of the four DMAC channels has a Peripheral Control Line (called PCL0* through PCL3*). The two PCL bits define the function of e[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-53 GPIB-1014 User Manual Operation Control Register VMEbus Address: Base Address + 05 (hex) Attributes: Read/Write, Internal to DMAC 7 6 54 32 1 0 DIR 0 SIZE CHN REQG R/W The Operation Control Register (OCR) is an operation-oriented register. Bit Mnemonic Description 7r/w DIR Dir[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-54 © National Instruments Corporation 10 = Array Chaining 11 = Linked Chaining Bit Mnemonic Description In most GPIB applications, either no chaining or array chaining is used. See Chapter 5 for details. 1-0r/w REQG DMA Request Generation Bits 1 through 0 The DMA Request Generation method bit[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-55 GPIB-1014 User Manual Sequence Control Register VMEbus Address: Base Address + 06 (hex) Attributes: Read/Write, Internal to DMAC 7 6 54 32 1 0 0 0 0 0 MAC DAC R/W The Sequence Control Register (SCR) is used to define the sequencing of memory and device addresses. Bit Mnemonic [...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-56 © National Instruments Corporation Channel Control Register VMEbus Address: Base Address + 07 (hex) Attributes: Read/Write, Internal to DMAC 7 6 54 32 1 0 STR CNT HLT SAB EINT 0 0 0 R/W This register is used to control the operation of the channel. By writing to this register, a channel op[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-57 GPIB-1014 User Manual 0 = Channel operation not aborted 1 = Abort channel operation Bit Mnemonic Description 3r/w EINT Interrupt Enable Bit The Interrupt Enable bit in used to enable or disable interrupts from the channel. GPIB-1014 interrupts are discussed in more detail in C[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-58 © National Instruments Corporation Channel Status Register VMEbus Address: Base Address + 00 (hex) Attributes: Read/Write, Internal to DMAC 7 6 54 32 1 0 COC BTC NDT ERR ACT 0 PCT PCS R/W The Channel Status Register (CSR) bits are set automatically by DMAC. Bits are cleared by writing a on[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-59 GPIB-1014 User Manual Bit Mnemonic Description 4r/w ERR Error Bit The Error bit is used to report the occurrence of error conditions. It is set if any errors have been signaled. If bit ERR is set, the CER logs the exact cause of the error. If this bit is cleared, the CER is al[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-60 © National Instruments Corporation Channel Error Register VMEbus Address: Base Address + 01 (hex) Attributes: Read Only, Internal to DMAC 7 6 54 32 10 ERROR CODE 0 0 0 R The Channel Error Register (CER) is an error condition register. The ERR bit of the CSR indicates if there is an error. [...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-61 GPIB-1014 User Manual Channel Priority Register VMEbus Address: Base Address + 2D (hex) Attributes: Read/Write, Internal to DMAC 7 6 54 32 0 CP 0 0 0 0 0 0 R/W The Channel Priority Register (CPR) is used to define the priority level for each channel. The priority of a channel [...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-62 © National Instruments Corporation Interrupt Vector Registers Each channel has a Normal Interrupt Vector Register (NIVR) and an Error Interrupt Vector Register (EIVR), each consisting of eight bits. The CPU responds to an interrupt request from the DMAC by executing an Interrupt Acknowledg[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-63 GPIB-1014 User Manual General Control Register VMEbus Address: Base Address + FF (hex) Attributes: Read/Write, Internal to DMAC 7 6 54 32 1 0 0 0 0 0 BT BR R/W When the transfer mode is cycle steal with hold, the General Control Register (GCR) is used to define how long the DM[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-64 © National Instruments Corporation Configuration Registers The GPIB-1014 contains two 8-bit write-only registers that are used to configure some of the board operating parameters. Configuration Register 1 (CFG1) VMEbus Address: Base Address + 101 (hex) Attributes: Write Only, Internal to D[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-65 GPIB-1014 User Manual Bit Mnemonic Description 4-3w BRG Bus Request/Grant Bits The Bus Request/Grant bits are used to select which pair of the VMEbus request/grant lines are used by the GPIB-1014 to request and obtain control of the system bus. 00 = BR0*/BG0IN*-BG0OUT* selecte[...]

Register Descriptions Chapter 4 GPIB-1014 User Manual 4-66 © National Instruments Corporation Configuration Register 2 (CFG2) VMEbus Address: Base Address + 105 (hex) Attributes: Write Only, Internal to DMAC 7 6 54 32 1 0 0 0 0 0 SFL SUP LMR SC W Configuration Register 2 (CFG2) is an 8-bit write-only register that is used to set the board access m[...]

Chapter 4 Register Descriptions © National Instruments Corporation 4-67 GPIB-1014 User Manual Bit Mnemonic Description 1w LMR Local Master Reset Bit The Local Master Reset bit is used to reset the GPIB-1014 to a known state. Setting this bit to a 1 drives the local reset line active while clearing this bit releases the local reset line. The local [...]

© National Instruments Corporation 5-1 GPIB-1014 User Manual Chapter 5 Programming Considerations This chapter explains the initialization process, sending/receiving messages, and the serial/parallel poll process. Additional information on programming the µ PD7210 GPIB interface chip can be obtained from the µ PD7210 GPIB-IFC User Manual by NEC [...]

Programming Considerations Chapter 5 GPIB-1014 User Manual 5-2 © National Instruments Corporation • The Transit Receive Mode 0 (TRM0) and Transit Receive Mode 1 (TRM1) bits in the Address Mode Register (ADMR) are cleared. All other TLC register contents should be considered as undefined while the LMR bit is set and after LMR has been cleared. Wh[...]

Chapter 5 Programming Considerations © National Instruments Corporation 5-3 GPIB-1014 User Manual 9. Load the Parallel Poll response in the Parallel Poll Register (PPR) if local configuration is used. If using remote configuration, clear the PPR. 10. Clear power on (pon) by issuing the Immediate Execute pon auxiliary command to the TLC to bring th[...]

Programming Considerations Chapter 5 GPIB-1014 User Manual 5-4 © National Instruments Corporation Sending Remote Multiline Messages (Commands) The GPIB-1014 sends commands as Active Controller simply by writing to the Command/Data Out Register (CDOR) in response to the CO status bit in ISR2. DMA transfers are not supported when the TLC is GPIB Act[...]

Chapter 5 Programming Considerations © National Instruments Corporation 5-5 GPIB-1014 User Manual Case 2: The TLC, as a Listener, takes control upon receipt of the Take Control Synchronously auxiliary command. If programmed I/O is used, the Take Control Synchronously auxiliary command should be issued between seeing a DI status bit and reading the[...]

Programming Considerations Chapter 5 GPIB-1014 User Manual 5-6 © National Instruments Corporation The GPIB-1014 as GPIB Talker and Listener The TLC may be either GPIB Talker or Listener, but not both simultaneously. Either function is deactivated automatically if the other is activated. The TA, LA, and ATN* bits in the ADSR together indicate the s[...]

Chapter 5 Programming Considerations © National Instruments Corporation 5-7 GPIB-1014 User Manual Address Mode 2 Address Mode 2 is used when Talker Extended (TE) or Listener Extended (LE) functions are to be used. TE and LE functions require receipt of two addresses (primary and secondary) before setting TA or LA. The TLC GPIB primary address is i[...]

Programming Considerations Chapter 5 GPIB-1014 User Manual 5-8 © National Instruments Corporation 6. When the Valid auxiliary command is issued, the TLC assumes that the My Secondary Address (MSA) message has been received, which causes the following events to occur: • The LA bit to be set and the TA bit to be cleared (LADS=TIDS=1) if LPAS was s[...]

Chapter 5 Programming Considerations © National Instruments Corporation 5-9 GPIB-1014 User Manual In cycle steal without hold mode, upon receiving a DMA request from the TLC, the DMAC requests use of the VMEbus. Once the VMEbus is granted to the GPIB-1014, the DMAC performs the DMA transfer. Then it immediately releases the bus. In cycle steal wit[...]

Programming Considerations Chapter 5 GPIB-1014 User Manual 5-10 © National Instruments Corporation DMA Transfers without the Carry Cycle Data Block A Total = N bytes NO CHAINING OR Total = N bytes Data Block A Data Block B Data Block C CHAINING DMAC VMEbus interrupt TLC interrupt Bus Error GPIB Sync. PCL1 Channel 0 Figure 5-1. DMA Transfer without[...]

Chapter 5 Programming Considerations © National Instruments Corporation 5-11 GPIB-1014 User Manual b. A 0xFF (hex) must be written to the CSR of Channel 0 to clear any leftover error or status bits. c. The DCR of Channel 0 is loaded with the proper value to select the DMA transfer mode (cycle steal without hold or cycle steal with hold). The DTYP [...]

Programming Considerations Chapter 5 GPIB-1014 User Manual 5-12 © National Instruments Corporation 4. For array or linked chaining, load the MFCR of Channel 0 with the proper data to generate the required Address Modifier Code to access the data blocks. See Tables 3-1 and 3-2 for recommended values. 5. Set up the data blocks and the address & [...]

Chapter 5 Programming Considerations © National Instruments Corporation 5-13 GPIB-1014 User Manual DMA Transfers with the Carry Cycle Channel 0 Data Block A Total=N-1 bytes NO CHAINING OR Total=N-1 bytes Data Block A Data Bock B Data Block C CHAINING Channel 1 Block A Count=1 Block B Count=2 Carry Cycle byte + Nth data byte CHAINING (array or link[...]

Programming Considerations Chapter 5 GPIB-1014 User Manual 5-14 © National Instruments Corporation 2. Channel 0 must be configured to provide a flyby transfer for the n-1 data bytes between the GPIB and the VME system memory. The sequence is as follows: a. Write the CCR of Channel 0 with the SAB bit set to abort the channel operation in case it is[...]

Chapter 5 Programming Considerations © National Instruments Corporation 5-15 GPIB-1014 User Manual • For array or linked chaining, load the MFCR of Channel 0 with the proper data to generate the required Address Modifier Code to access the data blocks. See Tables 3-1 and 3-2 for recommended values. • Set up the data blocks and the address &[...]

Programming Considerations Chapter 5 GPIB-1014 User Manual 5-16 © National Instruments Corporation i. For array or linked chaining, load the MFCR of Channel 1 with the proper value to generate the desired address modifier code, which then accesses the data blocks. (See Tables 3-1 and 3-2 for recommended values.) Note: If you are using the array ch[...]

Chapter 5 Programming Considerations © National Instruments Corporation 5-17 GPIB-1014 User Manual 4. Once channels 0 and 1 have been configured properly, start the DMA channels. Start Channel 1 before starting Channel 0. The channels are started by writing to the CCRs with the STR bits set. (Channel 1 should also have the EINT bit set if you are [...]

Programming Considerations Chapter 5 GPIB-1014 User Manual 5-18 © National Instruments Corporation • An interrupt from the TLC • A bus or DMAC error that occurred during a DMA transfer • GPIB handshake synchronization To determine which condition caused the interrupt, you must first examine the CSR of Channel 1. If the ERR bit of Channel 1 i[...]

Chapter 5 Programming Considerations © National Instruments Corporation 5-19 GPIB-1014 User Manual accepted by all Listeners on the GPIB (indicating a GPIB synchronization). For this reason, Channel 1 is programmed to transfer two bytes to avoid a premature COC interrupt. After the last data byte (the nth byte) is transferred, the MTCR of Channel [...]

Programming Considerations Chapter 5 GPIB-1014 User Manual 5-20 © National Instruments Corporation Whether terminating on the END message or the EOS message (or whenever the DMA transfer does not complete properly), the DMAC must be stopped by issuing a software abort to Channels 0 and 1 by writing to the CCR with the SAB bit set. You then must wr[...]

Chapter 5 Programming Considerations © National Instruments Corporation 5-21 GPIB-1014 User Manual Interrupts If the GPIB-1014 is enabled for interrupts, there are three events that can cause an interrupt on the VMEbus. The first event is an interrupt from the TLC. The second event is a GPIB handshake synchronization that occurs when a DMA transfe[...]

Programming Considerations Chapter 5 GPIB-1014 User Manual 5-22 © National Instruments Corporation The TLC contains its own internal registers, which are used to control and enable interrupts. The interrupt output from the TLC, however, is sensed by the PCL of DMA Channel 1. If an interrupt operation is used, the DMAC Channel 1 must be configured [...]

Chapter 5 Programming Considerations © National Instruments Corporation 5-23 GPIB-1014 User Manual Serial Polls Conducting a Serial Poll The TLC, as CIC, can serial poll other devices as described in the IEEE 488 specification. From the programming point of view, the TLC must first become Active Controller to send the addressing and enabling comma[...]

Programming Considerations Chapter 5 GPIB-1014 User Manual 5-24 © National Instruments Corporation Although the Controller can obtain a Parallel Poll response quickly and at any time, there can be considerable front-end overhead during initialization to configure the devices to respond appropriately. This is contrasted with Serial Polls, where the[...]

Chapter 5 Programming Considerations © National Instruments Corporation 5-25 GPIB-1014 User Manual 2. Send the GPIB UNL message to unaddress all GPIB Listeners. 3. Send the listen address of the first device to be configured. 4. Send the GPIB PPC message to all devices followed by the PPE message for that device. 5. Repeat from the second step (UN[...]

© National Instruments Corporation 6-1 GPIB-1014 User Manual Chapter 6 Theory of Operation This chapter contains a functional overview of the GPIB-1014 board and explains the operation of each functional block making up the GPIB-1014. A brief description of the GPIB-1014 interface is given in Chapter 2 along with a functional block diagram (see Fi[...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-2 © National Instruments Corporation accomplished using an F245 8-bit data transceiver, which gates the upper data byte to the TLC. This data transceiver is automatically controlled by the DMAC signal HIBYTE*. When the data transfer is on VMEbus data lines D07 through D00, the HIBYTE* is not ac[...]

Chapter 6 Theory of Operation © National Instruments Corporation 6-3 GPIB-1014 User Manual Control Equations of Transceivers Table 6-1 lists the control equations for the address and data. Table 6-1. Control Equations of Transceivers VMEbus Signals Transceivers Control Equations A23 through A16 AS573 OC* = OWN* (output enable) C = UAS (input clock[...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-4 © National Instruments Corporation address. If DS* from the master is also asserted, local signal BRDEN* is asserted. Further decoding is necessary to determine which register is being addressed. Eight data lines (A8 through A1) are latched by an AS573 8-bit register at the start of every sla[...]

Chapter 6 Theory of Operation © National Instruments Corporation 6-5 GPIB-1014 User Manual control the timing of local signal DTACK* when the board is a slave and signal to control RD* and WR* to the TLC (see Timing State Machine later in this chapter). The VMEbus signal SYSRESET* is monitored by the GPIB-1014. It is received with an LS240 receive[...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-6 © National Instruments Corporation • Enabling the Release On Request feature. Writing a 0 to this bit (ROR*) enables the Release On Request feature while writing a 1 disables the Release On Request feature. This bit is set to 1 during reset or power up. This bit is used by the DTB Requester[...]

Chapter 6 Theory of Operation © National Instruments Corporation 6-7 GPIB-1014 User Manual Configuration Register 2 Four discrete 74LS74A D-type flip-flops are used to implement Configuration Register 2 (CFG2). Data is written into each bit of this register on the rising edge of the WR* signal generated by the Timing State Machine circuitry. The S[...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-8 © National Instruments Corporation corresponds to the read access time of the TLC. Local signal SACK is asserted to drive VMEbus signal DTACK* active to indicate that the data is valid on the VMEbus data lines D07 through D00. The data remains valid and the DTACK* signal remains asserted unti[...]

Chapter 6 Theory of Operation © National Instruments Corporation 6-9 GPIB-1014 User Manual DMA Gating and Control The DMA Gating and Control circuitry is designed to control the DMA request/acknowledge interface between the DMAC and the TLC. The circuitry consists of an LS74 flip-flop and miscellaneous logic gates to generate the DMA request signa[...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-10 © National Instruments Corporation If the carry cycle feature is not used in a DMA transfer, the CC bit in CFG1 is 0, and DMA Gating and Control circuitry directs all DMA requests from the TLC to DMAC Channel 0. DMAC Channel 1 is not used and must not be started. Interrupter The GPIB-1014 re[...]

Chapter 6 Theory of Operation © National Instruments Corporation 6-11 GPIB-1014 User Manual are some external requests for the bus. While the board is holding the bus and the DMAC requests the bus, the DMAC is immediately granted the bus, thus avoiding bus arbitration time. The circuitry consists of various components to drive and receive VMEbus s[...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-12 © National Instruments Corporation received. OWN* is asserted by the DMAC to indicate that it now has ownership of the bus. BUS_REL* is asserted by the DTB Requester and Controller circuitry to indicate that it is going to release the VMEbus. RESET* is asserted to reset all circuitry on the [...]

Chapter 6 Theory of Operation © National Instruments Corporation 6-13 GPIB-1014 User Manual 4. The outputs of the 74S139 are connected to four 74LS02 gates, along with the LBROUT* signal, to assert one of the four VMEbus bus request lines (BR3* through BR0*). 5. The DTB Requester waits for the appropriate Bus Grant In line (BG3IN* through BG0IN*) [...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-14 © National Instruments Corporation This PCL is used to detect interrupts from the GPIB-1014 that are not internal to the DMAC. A negative transition on the PCL sets the PCT bit in the CSR of DMAC Channel 1. If interrupts are enabled in the CCR of Channel 1 (EINT=1), the setting of the PCT bi[...]

Chapter 6 Theory of Operation © National Instruments Corporation 6-15 GPIB-1014 User Manual accepted the byte and the Talker may have already released DAV*. For this reason, the synchronization circuitry looks at the level of the DAV* line rather than for a transition. When the DAV* line is detected high, all devices have accepted the byte and a n[...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-16 © National Instruments Corporation 4. Clear IMR2. 5. Write a value to CFG1 to release PCL1 line (perhaps use the same value as the last write to CFG1). 6. Write a software abort to Channel 0. 7. Check, then clear the COC and ERR bits in CSR0. 8. Write a software abort to Channel 1 (if a carr[...]

Chapter 6 Theory of Operation © National Instruments Corporation 6-17 GPIB-1014 User Manual Device (TLC)/DMAC Communication. Communication between the TLC and the DMAC is accomplished mainly by two signals. Each of the four DMA channels has a DMA request input (REQ0* through REQ*3) and a DMA acknowledge output (ACK0* through ACK3*). The TLC reques[...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-18 © National Instruments Corporation DMA Requests. Internal or external requests activate the DMAC to transfer an operand. The REQG bits of the OCR determine the manner in which requests are generated. Requests can be externally generated by the device or internally generated by the DMAC using[...]

Chapter 6 Theory of Operation © National Instruments Corporation 6-19 GPIB-1014 User Manual Operands and Addressing. Three factors affect how the actual data is handled: device (destination) port size, operand (from source) size, and address sequencing. • Device Port Size The DCR is also used to program the device port size to be 8 or 16 bits. T[...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-20 © National Instruments Corporation address the device (VMEbus memory) in dual-address transfers. It is initiated before starting the channel operation. The BAR is used only in chaining or continue operations. Transfer Count Register Operation. The DMAC has two 16-bit transfer counter registe[...]

Chapter 6 Theory of Operation © National Instruments Corporation 6-21 GPIB-1014 User Manual to service the request for the halted channel. When this bit is reset, the channel resumes operation and services any request that may have been received while the channel was halted. The HLT bit must be cleared to zero when writing to the STR bit to avoid [...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-22 © National Instruments Corporation If the interrupt bit in the CCR is set when the BTC bit is set, an interrupt is generated. The interrupt handler can reload the BFCR, BAR, and BTCR with information describing the next data block if necessary, clear the BTC bit and set the CNT to repeat the[...]

Chapter 6 Theory of Operation © National Instruments Corporation 6-23 GPIB-1014 User Manual Start of array # of entries = 3 BAR BTC DMAC Memory Address A Transfer Count A Memory Address B Transfer Count B Memory Address C Transfer Count C Data Block A Data Block B Data Block C Address and Transfer Count Array Data Blocks Figure 6-2. Array Format f[...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-24 © National Instruments Corporation Start of array BAR BTC DMAC Data Block A Data Block B Data Block C Address and Transfer Count Array Data Blocks xxxx (not used) Memory Address A Transfer Count A Link to next entry Memory Address B Transfer Count B Link to next entry Memory Address B Transf[...]

Chapter 6 Theory of Operation © National Instruments Corporation 6-25 GPIB-1014 User Manual Sources of errors are as follows: • Configuration Error This occurs when any undefined or reserved bit pattern, or illegal device/operand size combination is programmed into a channel and an attempt is made to set the STR bit. This error occurs, for examp[...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-26 © National Instruments Corporation transfer, the Memory Address and Device Address Registers point to the location of the next operand and the Memory Transfer Counter contains the number of operands yet to be transferred. If an error occurs during a transfer, that transfer has not completed [...]

Chapter 6 Theory of Operation © National Instruments Corporation 6-27 GPIB-1014 User Manual request is enabled for the condition. An important fact to remember is that ISR1 and ISR2 are always cleared when read, even if the condition that caused the bit to be initially set remains true. Data to and from the GPIB is pipelined through the CDOR and D[...]

Theory of Operation Chapter 6 GPIB-1014 User Manual 6-28 © National Instruments Corporation limited assurance that the TLC and its associated circuitry are working and that the output signals can be manipulated properly. NDAC* is the GPIB Not Data Accepted signal. By programming the TLC to Listen or not Listen via the AUXMR, NDAC* can be asserted [...]

© National Instruments Corporation 7-1 GPIB-1014 User Manual Chapter 7 Diagnostic and Troubleshooting Test Procedures This chapter contains test procedures for determining if the GPIB-1014 is installed and operating correctly. The tests are similar to those used by National Instruments to verify correct hardware functioning. The method used is to [...]

Diagnostic and Troubleshooting Test Procedures Chapter 7 GPIB-1014 User Manual 7-2 © National Instruments Corporation 2. Examine any read and write routines being used in connection with the checkout procedure for errors. 3. Recheck the jumper settings described in Chapter 3. After these items have been carefully checked, if the interface is still[...]

Chapter 7 Diagnostic and Troubleshooting Test Procedures © National Instruments Corporation 7-3 GPIB-1014 User Manual 105 CFG2 = 08 Clear LMR 065 NIV1 = 55 065 NIV1 = 55? 067 EIV1 = 55 067 EIV1 = 55? 105 CFG2 = 0A Set LMR and turn LED green 105 CFG2 = 08 Clear LMR 065 NIV1 = 0F? 067 EIV1 = 0F? 5. Test ton, DO, ERR, CPTR, TA. 105 CFG2 = 0A Set LMR [...]

Diagnostic and Troubleshooting Test Procedures Chapter 7 GPIB-1014 User Manual 7-4 © National Instruments Corporation 11B AUXMR = 1E set IFC 11B AUXMR = 16 clear IFC 119 ADSR = 80? CIC 115 ISR2 = 9? CO + ADSC 11B AUXMR = 10 go to standby 119 ADSR = C0? CIC + ATN* 8. Test DMA Error. 105 CFG2 = 0A Set LMR and turn LED green 105 CFG2 = 08 Clear LMR 0[...]

Chapter 7 Diagnostic and Troubleshooting Test Procedures © National Instruments Corporation 7-5 GPIB-1014 User Manual daddr=FF Set data values at source locations daddr+1=FE ...... daddr+9=F6 087 CCR2=80 Start DMA on Channel 2 080 CSR2=81? DMA completed without error? Bit 4 = 1 if error daddr+0A=FF? Verify data values at destination locations dadd[...]

Diagnostic and Troubleshooting Test Procedures Chapter 7 GPIB-1014 User Manual 7-6 © National Instruments Corporation 00A MTC0 = 0001 one byte 004 DCR0 = A0 005 OCR0 = 82 006 SCR0 = 0 000 CSR0 = FF 040 CSR1 = FF 045 OCR1 = 0 029 MFC0 = 06 00C MAR0 = daddr 4-byte data address daddr= 0 clear data location 101 CFG1 = 19 BRG3*, IN, enable ROR feature [...]

Chapter 7 Diagnostic and Troubleshooting Test Procedures © National Instruments Corporation 7-7 GPIB-1014 User Manual 005 OCR0 = 02 045 OCR1 = 0A 006 SCR0 = 04 046 SCR1 = 04 029 MFC0 = 06 00C MAR0 = 00003000 4-byte address (00003000) of the first two data bytes 00A MTC0 = 0002 2-byte transfer count (0002) 069 MFC1 = 06 079 BFC1 = 06 05C BAR1 = 000[...]

Diagnostic and Troubleshooting Test Procedures Chapter 7 GPIB-1014 User Manual 7-8 © National Instruments Corporation 3000 data = 0000 clear two memory locations, these will be written over by data from GPIB 3002 data = 0081 clear memory location 3002 as it will be written over and put carry cycle byte (81 = HLDA) in location 3003 3004 data = 0000[...]

Chapter 7 Diagnostic and Troubleshooting Test Procedures © National Instruments Corporation 7-9 GPIB-1014 User Manual 113 ISR1 = 2? after transferred the first two bytes on Channel 0 and the carry cycle byte on Channel 1, check if DI is cleared before write the last data byte to DIR 111 DIR = 3 write the last data byte to TLC, since DIR is full, T[...]

© National Instruments Corporation A-1 GPIB-1014 User Manual Appendix A Hardware Specifications This appendix specifies the electrical, environmental, and physical characteristics of the GPIB-1014 board and the conditions under which it should be operated. Table A-1. Electrical Characteristics Characteristic Specification Transfer Rates DMA Over 5[...]

Hardware Specifications Appendix A GPIB-1014 User Manual A-2 © National Instruments Corporation Table A-3. Physical Characteristics Characteristic Specification Dimensions 6.3 in. by 9.2 in. I/O Connector GPIB-1014-1S IEEE 488 Standard 24-pin GPIB-1014-2 VMEbus P2 connector[...]

© National Instruments Corporation B-1 GPIB-1014 User Manual Appendix B Parts List and Schematic Diagrams This appendix contains the parts list and schematic diagrams for the GPIB-1014. Art not available in PDF version of document.[...]

© National Instruments Corporation C-1 GPIB-1014 User Manual Appendix C Sample Programs This appendix contains listings of routines in 68000 assembly language code that implement the essential elements of these major utility functions: • Initialize the GPIB-1014 interface (INIT). • Initialize the interface functions of the GPIB devices (IFC). [...]

Sample Programs Appendix C GPIB-1014 User Manual C-2 © National Instruments Corporation ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |; | GPIB-1014 Sample Functions for Driver: ; |; | INIT (Initialize the GPIB-1014) ; | IFC (Send Interface Clear) ; | REN (Set/Clear Remote Enable) ; | RCV (Receive) ; | READ (Read Data) ; [...]

Appendix C Sample Programs © National Instruments Corporation C-3 GPIB-1014 User Manual | ISR1 Bits DI = 001 (octal) | Data in DO = 002 | Data out ERR = 004 | Error ENDRX = 020 | END received | ISR2 Bits CO = 010 | Command out | ADSR Bits NATN = 0100 | Not ATN | ADMR Bits MODE1 = 001 | Address Mode 1 TRM = 060 | GPIB-1014 functions for T/R2 and T/[...]

Sample Programs Appendix C GPIB-1014 User Manual C-4 © National Instruments Corporation | CSR Bits CLRS = 0377 | Clear all status bits COC = 0200 | Channel operation complete CERR = 020 | Error in channel operation ACT = 010 | Channel active PCT = 002 | PCL transition occurred | CFG1 Bits ECC = 004 | Enable Carry Cycle feature IN = 001 | Accepting[...]

Appendix C Sample Programs © National Instruments Corporation C-5 GPIB-1014 User Manual | | * * * * * * * * * * * * * * * * | * INITIALIZE - INIT * | * * * * * * * * * * * * * * * * | | Summary: | - Initialize the GPIB-1014 hardware | | Assumptions on entry: | - User-specified constants MA, ADMC, and SC have | been initialized | - Mode 1 primary a[...]

Sample Programs Appendix C GPIB-1014 User Manual C-6 © National Instruments Corporation | 68000 Code | Comments | -------------------------------------------------------------------------------------------------------------------------------------------- INIT: movb #SLMR,CFG2 | Pulse Local Master Reset movb #CLMR,CFG2 | | movb #CRST,AUXMR | Chip R[...]

Appendix C Sample Programs © National Instruments Corporation C-7 GPIB-1014 User Manual | | * * * * * * * * * * * * * * * * * * * * * * | * INTERFACE CLEAR - IFC * | * * * * * * * * * * * * * * * * * * * * * * | | Summary: | - Initialize the interface function of other GPIB | devices | | Assumptions on entry: | - GPIB-1014 has been initialized | -[...]

Sample Programs Appendix C GPIB-1014 User Manual C-8 © National Instruments Corporation | | * * * * * * * * * * * * * * * * * * * * | * REMOTE ENABLE - REN * | * * * * * * * * * * * * * * * * * * * * | | Summary: | - Set or clear GPIB Remote Enable signal | | Assumptions on entry: | - User specified sre is non-zero if REN is to be | asserted and i[...]

Appendix C Sample Programs © National Instruments Corporation C-9 GPIB-1014 User Manual | | * * * * * * * * * * * * * * * | * RECEIVE - RCV * | * * * * * * * * * * * * * * * | | Summary: | - Called by READ to receive data if GPIB-1014 is | Controller-In-Charge | - Called directly from main program to receive data if | GPIB-1014 is Idle Controller [...]

Sample Programs Appendix C GPIB-1014 User Manual C-10 © National Instruments Corporation | 68000 Code | Comments -------------------------------------------------------------------------------------------------------------------------------------------- | RCV: movb #TMODE,DCR0 | Set DMA transfer mode movb #TMODE,DCR1 | | movb #GTM,OCR0 | Set contr[...]

Appendix C Sample Programs © National Instruments Corporation C-11 GPIB-1014 User Manual | RCV4: btst #COC,CSR0 | Calculate number of bytes transferred bne RCV5 | movw MTC0,d1 | subw d1,d0 | btst #ECC,CFG1 | If carry cycle, MTC0 was initialized to (d0)-1 beq RCV6 | subw #1,d0 | bra RCV6 | | RCV5: btst #ECC, CFG1 | If no carry cyle, leave d0 as is [...]

Sample Programs Appendix C GPIB-1014 User Manual C-12 © National Instruments Corporation | | * * * * * * * | * READ * | * * * * * * * | Summary: | - Called to read device-dependent (data) messages | when the GPIB-1014 is Controller-In-Charge (RCV | is called when the GPIB-1014 is Idle Controller) | | Assumptions on entry: | - GPIB-1014 is Controll[...]

Appendix C Sample Programs © National Instruments Corporation C-13 GPIB-1014 User Manual | 68000 Code | Comments -------------------------------------------------------------------------------------------------------------------------------------------- | READ: movb cmdbuf,cmdbuf+2 | Put Untalk and Unlisten commands before movb #UNT,cmdbuf | Talke[...]

Sample Programs Appendix C GPIB-1014 User Manual C-14 © National Instruments Corporation | | * * * * * * * * * * * * * * * * * * | * DATA SEND - DSEND * | * * * * * * * * * * * * * * * * * * | | Summary: | - Called directly from the main program if the | GPIB-1014 is not CIC | | Assumptions on entry: | - The GPIB-1014 is Standby or Idle Controller[...]

Appendix C Sample Programs © National Instruments Corporation C-15 GPIB-1014 User Manual | 68000 Code | Comments -------------------------------------------------------------------------------------------------------------------------------------------- | DSEND: movb #TMODE,DCR0 | Set DMA transfer mode movb #TMODE,DCR1 | | movb #MTG,OCR0 | Set con[...]

Sample Programs Appendix C GPIB-1014 User Manual C-16 © National Instruments Corporation DSEND4: btst #COC,CSR0 | Calculate number of bytes transferred bne DSEND5 | movw MTC0,d1 | subw d1,d0 | btst #ECC,CFG1 | beq DSEND6 | subw #1,d0 | bra DSEND6 | | DSEND5: btst #ECC,CFG1 | bne DSEND6 | movw MTC1,d1 | subw d1,d0 | addw #1,d0 | | DSEND6: movb #0,I[...]

Appendix C Sample Programs © National Instruments Corporation C-17 GPIB-1014 User Manual | | * * * * * * * * * | * WRITE * | * * * * * * * * * | | Summary: | - Called to send device-dependent (data) messages | when the GPIB-1014 is Controller-In-Charge | (DSEND is called when the interface is Idle | Controller) | | Assumptions on entry: | - GPIB-1[...]

Sample Programs Appendix C GPIB-1014 User Manual C-18 © National Instruments Corporation | 68000 Code | Comments -------------------------------------------------------------------------------------------------------------------------------------------- | WRITE: movw #4,cmdct | Put Untalk, Unlisten, MTA, and OLA movb #UNT,cmdbuf | commands in the [...]

Appendix C Sample Programs © National Instruments Corporation C-19 GPIB-1014 User Manual | | * * * * * * * * * * * * * * * * * * * * * * | * COMMAND SEND - CSEND * | * * * * * * * * * * * * * * * * * * * * * * | | Summary: | - Called by CMD to send interface messages | | Assumptions on entry: | - The GPIB-1014 is Active Controller | - The d0 regis[...]

Sample Programs Appendix C GPIB-1014 User Manual C-20 © National Instruments Corporation | | * * * * * * * * * * * * * * * | * COMMAND - CMD * | * * * * * * * * * * * * * * * | | Summary: | - Send GPIB interface or command messages | | Assumptions on entry: | - The GPIB-1014 is Controller-In-Charge | - The commands to be sent are in cmdbuf | - The[...]

Appendix C Sample Programs © National Instruments Corporation C-21 GPIB-1014 User Manual | | * * * * * * * * * * * * * * * * * * * * * * | * PASS CONTROL - PASSC * | * * * * * * * * * * * * * * * * * * * * * * | | Summary: | - Passes GPIB Controller-In-Charge status to another | device | | Assumptions on entry: | - The GPIB-1014 is Controller-In-C[...]

© National Instruments Corporation D- 1 GPIB-1014 User Manual Appendix D Multiline Interface Messages This appendix lists the multiline interface messages and describes the mnemonics and messages that correspond to the interface functions. These functions include initializing the bus, addressing and unaddressing devices, and setting device modes f[...]

Multiline Interface Messages Appendix D GPIB-1014 User Manual D- 2 © National Instruments Corporation Multiline Interface Messages Hex Oct Dec ASCII Msg Hex Oct Dec ASCII Msg 00 000 0 NUL 20 040 32 SP MLA0 01 001 1 SOH GTL 21 041 33 ! MLA1 02 002 2 STX 22 042 34 " MLA2 03 003 3 ETX 23 043 35 # MLA3 04 004 4 EOT SDC 24 044 36 $ MLA4 05 005 5 E[...]

Appendix D Multiline Interface Messages © National Instruments Corporation D- 3 GPIB-1014 User Manual Multiline Interface Messages Hex Oct Dec ASCII Msg Hex Oct Dec ASCII Msg 40 100 64 @ MTA0 60 140 96 ` MSA0,PPE 41 101 65 A MTA1 61 141 97 a MSA1,PPE 42 102 66 B MTA2 62 142 98 b MSA2,PPE 43 103 67 C MTA3 63 143 99 c MSA3,PPE 44 104 68 D MTA4 64 14[...]

© National Instruments Corporation E-1 GPIB-1014 User Manual Appendix E Operation of the GPIB This chapter describes the operation of the GPIB. Communication among interconnected GPIB devices is achieved by passing messages through the interface system. Types of Messages The GPIB carries device-dependent messages and interface messages. • Device[...]

Operation of the GPIB Appendix E GPIB-1014 User Manual E-2 © National Instruments Corporation Some bus configurations do not require a Controller. For example, one device may always be a Talker (called a Talk-only device) and there may be one or more Listen-only devices. A Controller is necessary when the active or addressed Talker or Listener mus[...]

Appendix E Operation of the GPIB © National Instruments Corporation E-3 GPIB-1014 User Manual NRFD (not ready for data) NRFD indicates when a device is ready or not ready to receive a message byte. The line is driven by all devices when receiving commands and by Listeners when receiving data messages. NDAC (not data accepted) NDAC indicates when a[...]

Operation of the GPIB Appendix E GPIB-1014 User Manual E-4 © National Instruments Corporation Physical and Electrical Characteristics Devices are usually connected with a cable assembly consisting of a shielded 24 conductor cable with both a plug and receptacle connector at each end. This design allows devices to be linked in either a linear or a [...]

Appendix E Operation of the GPIB © National Instruments Corporation E-5 GPIB-1014 User Manual Figure E-2. Linear Configuration[...]

Operation of the GPIB Appendix E GPIB-1014 User Manual E-6 © National Instruments Corporation Figure E-3. Star Configuration Configuration Requirements To achieve the high data transfer rate that the GPIB was designed for, the physical distance between devices and the number of devices on the bus are limited. The following restrictions are typical[...]

Appendix E Operation of the GPIB © National Instruments Corporation E-7 GPIB-1014 User Manual Bus extenders are available from National Instruments and other manufacturers for use when these limits must be exceeded. Related Documents For more information on topics covered in this section, consult the following manuals: • ANSI/IEEE Std 488-1978, [...]

© National Instruments Corporation F-1 GPIB-1014 User Manual Appendix F Mnemonics Key This appendix contains a mnemonics key that defines the mnemonics (abbreviations) used throughout this manual for functions, remote messages, local messages, states, bits, registers, integrated circuits, system functions, and VMEbus operations and signals. The mn[...]

Mnemonics Key Appendix F GPIB-1014 User Manual F-2 © National Instruments Corporation Mnemonic Type Definition A A[01-31] VBS Address Lines 1 through 31 ACDS ST Acceptor Data State (AH function) ACFAIL* VBS Power Fail Signal ACG RM Addressed Command Group ACK LS DMA Acknowledge Signal ACRS ST Acceptor Ready State ACT B Channel Active Bit AD[5-1] B[...]

Appendix F Mnemonics Key © National Instruments Corporation F-3 GPIB-1014 User Manual BG[0-3]OUT* VBS Bus Grant Out Lines BIN B Binary Bit BLT VBO Block Transfer BR[0-3]* VBS Bus Request Lines[...]

Mnemonics Key Appendix F GPIB-1014 User Manual F-4 © National Instruments Corporation C C F Controller CACS ST Controller Active State (C function) CADS ST Controller Addressed State CAWS ST Controller Active Wait State CDOR R Control/Data Out Register CDO[7-0] B Control/Data Out Bits 7 through 0 CIC B Controller-In-Charge Bit CIDS ST Controller I[...]

Appendix F Mnemonics Key © National Instruments Corporation F-5 GPIB-1014 User Manual DEN* LS Data Enable DET B Device Execute Trigger Bit DET IE B Enable Interrupt on Device Execute Trigger Bit DHDC B DAC Holdoff on DCAS DHDT B Data Accepted Holdoff on Device Trigger Active State Bit DI B Data In Bit DI [7-0] B Data In Bits 7 through 0 DI IE B En[...]

Mnemonics Key Appendix F GPIB-1014 User Manual F-6 © National Instruments Corporation F FH LM Finish Handshake FIN LS GPIB DMA Transfer Finished G GET RM Group Execute Trigger GND VBS Ground GTL RM Go To Local gts LM Go to Standby H HLDA B Holdoff on All Bit HLDE B Holdoff on End Bit I IA[1-3] LS Interrupt Priority Code Bits IACK* VBS Interrupt Ac[...]

Appendix F Mnemonics Key © National Instruments Corporation F-7 GPIB-1014 User Manual L L F Listener LA B Listener Active Bit LACS ST Listener Active State (L function) LADS ST Listener Addressed State (L function) LAG RM Listener Address Group LD[0-7] LS Local Data Bus LDTACK LS Local DTACK LE F Listener Extended LIDS ST Listener Idle State LLO R[...]

Mnemonics Key Appendix F GPIB-1014 User Manual F-8 © National Instruments Corporation O OSA RM Other Secondary Address OTA RM Other Talk Address P P[3-1] B Parallel Poll Response Bits 3 through 1 PACS ST Parallel Poll Addressed to Configure State PCG RM Primary Command Group PE LM Pull-up Enable PEND B Pending Bit pof LM Power Off pon LM Power On [...]

Appendix F Mnemonics Key © National Instruments Corporation F-9 GPIB-1014 User Manual rsv LM Request Service rtl LM Return To Local RWD B Release When Done Bit RWLS ST Remote With Lockout State S S B Status Bit Polarity (Sense) Bit S8, S[6-1] B Serial Poll Status Bits 8 and 6 through 1 SACS ST System Control Active State SCG RM Secondary Command G[...]

Mnemonics Key Appendix F GPIB-1014 User Manual F-10 © National Instruments Corporation SYSCLK* VBS System Clock SYSFAIL* VBS System Fail SYSRESET* VBS System Reset T T F Talker TA B Talker Active Bit TACS ST Talker Active State (T function) TADS ST Talker Addressed State TAG RM Talk Address Group tca LM Take Control Asynchronously tcs LM Take Cont[...]

Appendix F Mnemonics Key © National Instruments Corporation F-11 GPIB-1014 User Manual U U B Unconfigure Bit UAT VBO Unaligned Transfer UCG RM Universal Command Group UDPCF LM Undefined Primary Command Function UNL RM Unlisten command UNT RM Untalk command V V[0-7] LS Interrupt Vector Bits W WR* LS TLC Write Signal WRITE* VBS Read/Write Line X XEO[...]

© National Instruments Corporation G- 1 GPIB-1014 User Manual Appendix G Customer Communication For your convenience, this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation. Filling out a copy of the Technical[...]

Technical Support Form ____________________________________________________ Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support hel[...]

GPIB-1014 Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Update this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration. National Instruments Products • NI-488M Software V[...]

• Type of other boards installed and their respective hardware settings: Board Type Base I/O Address Interrupt Level DMA Channel[...]

Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: GPIB-1014 User Manual Edition Date: March 1997 Part Number: 320030-01 Please comment on the completeness, clarity, and organization of the manual. If[...]

© National Instruments Corporation Glossary-1 GPIB-1014 User Manual Glossary ___________________________________________________ Prefix Meaning Value n- µ - m- k- M- nano- micro- milli- kilo- mega- 10 - 9 10 - 6 10 - 3 10 3 10 6 ≤ is less than or equal to ≥ is greater than or equal to ° degrees A amperes ANSI American National Standards Inst[...]

GPIB-1014 User Manual Index- 1 © National Instruments Corporation Index Numbers 0 (Reserved Bit) Channel Error Register, 4-60 Channel Priority Register, 4-61 Channel Status Register, 4-59 Configuration Register 2 (CFG2), 4-66 Device Control Register, 4-52 General Control Register, 4-63 Operation Control Register, 4-53 Sequence Control Register, 4-[...]

Index © National Instruments Corporation Index- 2 GPIB-1014 User Manual Memory Address Register (MAR), 4-48 theory of operation, 6-17 Address Status Register (ADSR), 4-20 to 4-21 addressed implementation of Talker and Listener, 5-6 to 5-8 ADM[1-0] (Address Mode Bits 1 through 0), 4-23 to 4-24 ADMR. See Address Mode Register (ADMR). ADR. See Addres[...]

Index GPIB-1014 User Manual Index- 3 © National Instruments Corporation C cabling, 3-10 capability codes for GPIB-1014, 2-13 to 2-15 CC (Carry Cycle Bit), 4-65 CCR. See Channel Control Register (CCR). CDO[7-0] (Command/Data Out Bits 7 through 0), 4-7 CDOR. See Command/Data Out Register (CDOR). CER. See Channel Error Register (CER). chaining operat[...]

Index © National Instruments Corporation Index- 4 GPIB-1014 User Manual commands or command messages, E-1 multiline GPIB commands (table), 4-25 to 4-26, D-2 to D-3 compare address lines location of, 3-3 setting base address, 3-4 compliance levels for GPIB-1014 IEEE 1014 interrupter, 2-15 configuration access mode, 3-3 base address, 3-3 to 3-4 DMA [...]

Index GPIB-1014 User Manual Index- 5 © National Instruments Corporation VMEbus, 6-3 data or data messages, E-1 DATA SEND-DSEND sample program, C-14 to C-16 data transfer bus (DTB) requester description of, 2-7 VMEbus modules not provided, 2-7 data transfer features. See also DMA data transfers. programmed I/O transfers, 2-8 throughput, 2-7 to 2-8 [...]

Index © National Instruments Corporation Index- 6 GPIB-1014 User Manual DMA gating and control circuitry, 6-7 to 6-8 DMA registers 68450 internal DMA registers (chart), 2-5 Address Registers, 4-48 Base Address Register (BAR), 4-48 Base Transfer Counter Register (BTCR), 4-48 Channel Control Register (CCR), 4-56 to 4-57 Channel Error Register (CER),[...]

Index GPIB-1014 User Manual Index- 7 © National Instruments Corporation continue mode of operation, 6-18 halt, 6-18 initiating the operation, 6-18 interrupt enable, 6-19 software abort, 6-18 overview, 6-15 DMAI (DMA Input Enable Bit), 4-16 DMAO (DMA Out Enable Bit), 4-16 DO (Data Out Bit), 4-12 DO IE (Data Out Interrupt Enable Bit), 4-12 documenta[...]

Index © National Instruments Corporation Index- 8 GPIB-1014 User Manual E EINT (Interrupt Enable Bit), 4-57, 4-62, 6-19 electrical characteristics. See physical and electrical characteristics. END IE (End Received Interrupt Enable Bit), 4-10 to 4-11 End of String Register (EOSR), 4-45 END or EOS, sending/receiving, 5-17, 5-20 END RX (End Received [...]

Index GPIB-1014 User Manual Index- 9 © National Instruments Corporation parts list and schematic diagrams, B-1 to B-9 theory of operation 68450 DMAC, 6-14 to 6-23 address decoding, 6-3 to 6-4 clock and reset circuitry, 6-4 to 6-5 Configuration registers, 6-5 to 6-6 DMA gating and control, 6-7 to 6-8 DTB requester and controller, 6-9 to 6-12 GPIB i[...]

Index © National Instruments Corporation Index- 10 GPIB-1014 User Manual GPIB-1014 compatibility, 1-1 GPIB-1014 compliance levels, 2-15 IFC (interface clear) line, E-3 Immediate Execute Pon command codes for, 4-28 description, 4-29 IMR1. See Interrupt Mask Register 1 (IMR1). initialization of GPIB-1014, 5-1 to 5-3 INITIALIZE-INIT sample program, C[...]

Index GPIB-1014 User Manual Index- 11 © National Instruments Corporation register map, 4-1 Serial Poll Mode Register (SPMR), 4-19 Serial Poll Status Register (SPSR), 4-19 writing to hidden registers, 4-4 Internal Counter Register (ICR), 4-34 interrupt control. See GPIB Synchronization and Interrupt Control. Interrupt Mask Register 1 (IMR1), 4-8 to[...]

Index © National Instruments Corporation Index- 12 GPIB-1014 User Manual LMR (Local Master Reset Bit), 4-67 Local Unlisten command codes for, 4-28 description, 4-32 LOK (Lockout Bit), 4-16 LOKC (Lockout Change Bit), 4-17 LOKC IE (Lockout Change Interrupt Enable Bit), 4-17 lon (Listen Only Bit), 4-22 LPAS (Listener Primary Addressed State Bit), 4-2[...]

Index GPIB-1014 User Manual Index- 13 © National Instruments Corporation OCR. See Operation Control Register. operands and addressing, DMAC channel operation, 6-17 operating environment, A-1 Operation Control Register (OCR), 4-53 to 4-54 optional equipment for GPIB-1014, 1-3 P P[3-1] (Parallel Poll Response Bits 3 through 1), 4-36 Parallel Poll Re[...]

Index © National Instruments Corporation Index- 14 GPIB-1014 User Manual COMMAND SEND-CSEND, C-19 DATA SEND-DSEND, C-14 to C-16 GPIB-1014 Sample Functions for Driver, C-2 to C-4 INITIALIZE-INIT, C-5 to C-6 INTERFACE CLEAR-IFC, C-7 overview, C-1 PASS CONTROL-PASSC, C-21 READ, C-12 to C-13 RECEIVE-RCV, C-11 REMOTE ENABLE-REN, C-8 WRITE, C-17 to C-18[...]

Index GPIB-1014 User Manual Index- 15 © National Instruments Corporation overview, 5-6 programmed implementation, 5-6 R READ sample program, C-12 to C-13 RECEIVE-RCV sample program, C-11 receiving messages. See sending/receiving messages. registers Configuration registers definition of, 2-12 DMA Configuration registers, 4-64 to 4-67 GPIB-1014 Conf[...]

Index © National Instruments Corporation Index- 16 GPIB-1014 User Manual Interrupt Status Register 1 (ISR1), 4-8 to 4-13 Interrupt Status Register 2 (ISR2), 4-14 to 4-18 µ PD7210 internal GPIB interface registers (chart), 2-3 overview, 4-3 Serial Poll Mode Register (SPMR), 4-19 Serial Poll Status Register (SPSR), 4-19 writing to hidden registers,[...]

Index GPIB-1014 User Manual Index- 17 © National Instruments Corporation SCR. See Sequence Control Register. SDC (Selected Device Clear) command, 4-25 Send EOI (SEOI) command codes for, 4-28 description, 4-30 sending/receiving messages using direct memory access DMA transfers with carry cycle, 5-13 to 5-17 DMA transfers without carry cycle, 5-10 t[...]

Index © National Instruments Corporation Index- 18 GPIB-1014 User Manual REN (remote enable), E-3 SRQ (service request), E-3 VMEbus signals chart of, 2-1 to 2-2 control signals, 6-2 operation, 6-1 to 6-3 SIZE (Size Bits 5 through 4), 4-53 slave-addressing, VMEbus, 2-2 to 2-3 slave cycles, Timing State Machine, 6-6 to 6-7 slave-data, VMEbus, 2-5 sl[...]

Index GPIB-1014 User Manual Index- 19 © National Instruments Corporation codes for, 4-28 description, 4-31 Talker/Listener/Controller (TLC). See also Controller function; DMAC channel operation. addressed implementation Address Mode 1, 5-6 Address Mode 2, 5-6 to 5-7 Address Mode 3, 5-7 to 5-8 definition, 2-12 GPIB interface, 6-23 to 6-24 initializ[...]

Index © National Instruments Corporation Index- 20 GPIB-1014 User Manual definition of, 2-12 theory of operation DMA cycles, 6-7 overview, 6-6 slave cycles, 6-6 to 6-7 TLC. See Talker/Listener/Controller (TLC). ton (Talk Only Bit), 4-22 TPAS (Talker Primary Addressed State Bit), 4-21 transceivers for GPIB-1014 component designations, 2-2 control e[...]

Index GPIB-1014 User Manual Index- 21 © National Instruments Corporation troubleshooting test procedures DMA stand alone testing, 6-24 GPIB interface testing, 6-24 hardware installation tests, 7-2 to 7-8 interpreting test procedures, 7-1 overview, 7-1 verification of GPIB-1014 before installation, 3-10 U U (Parallel Poll Unconfigure Bit), 4-35 UNL[...]

Index GPIB-1014 User Manual Index- 23 © National Instruments Corporation X X (Don't Care Bit), 4-42, 4-50 XEOS (Transmit END with EOS Bit), 4-37 XRM (External Request Mode Bits 7 through 6), 4-51[...]