Panasonic MN101C00 manual

MICROCOMPUTER MN101C00 MN101C1 15/1 17 LSI User ’ s Manual Pub. No. 2141 1-01 1E[...]

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If you have any inquiries or questions about this book or our semiconductors, please contact one of our sales offices listed at the back of this book or Matsushita Electronics Corporation's Sales Department. Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) An ex[...]

How to Read This Manual–1 The MN101C11x incorporates more than one ROM/RAM to meet a variety of applications. An EPROM version as well as a Mask ROM version is available so users can write a program by themselves. ■ Organization In this LSI manual, the MN101C117 functions are presented in the following order: overview, CPU basic functions, port[...]

How to Read This Manual–2 ■ Manual Configuration Each section of this manual consists of a title, summary, main text, supplemental information, precautions and warnings. The layout and definition of each section are shown below. Subtitle Sub-subtitle The smallest block in this manual. Main text Summary Introduction to the section. Key informati[...]

■ Finding Desired Information This manual provides four methods for finding desired information quickly and easily. (1) Consult the index at the front of the manual to locate the beginning of each section. (2) Consult the table of contents at the front of the manual to locate desired titles. (3) Consult the list of figures at the front of the man[...]

0 Contents 1 Chapter 1 Overview 2 Chapter 2 Basic CPU Functions 3 Chapter 3 Port Functions 4 Chapter 4 T imer Functions 5 Chapter 5 Serial Functions 6 Chapter 6 A/D Conversion Functions 7 Chapter 7 AC Zero-Cross Circuit/Noise Filter 8 Appendices[...]

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0 Contents[...]

Contents Chapter 1 Overview 1-1 Product Overview ...........................................................................................................2 1-1-1 Overview ..........................................................................................................2 1-1-2 Product Summary ...............................................[...]

Chapter 3 Port Functions 3-1 Overview ......................................................................................................................38 3-2 Port Control Registers ..................................................................................................41 3-2-1 Overview ................................................[...]

Chapter 5 Serial Functions 5-1 Overview ......................................................................................................................92 5-2 Synchronous Serial Interface .......................................................................................94 5-2-1 Overview ...................................................[...]

Appendices 8-1 EPROM V ersions .......................................................................................................130 8-1-1 Overview ......................................................................................................130 8-1-2 Cautions on Use .....................................................................[...]

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1 1 Chapter 1 Overview[...]

Chapter 1 Overview 2 1-1 Product Overview 1-1-1 Overview The MN101C00 series of 8-bit single-chip microcomputers incorporate several types of peripheral functions. This chip series is well suited for VCR, MD, TV, CD, LD, printer, telephone, home automation, pager, air conditioner, PPC, remote control, fax machine, musical instrument, and other appl[...]

Chapter 1 Overview 3 Hardware Functions 1-2 Hardware Functions ROM/RAM Size: <Single chip mode> Internal ROM ∗ 2 16,384 × 8-bit* 3 Internal RAM ∗ 2 512 × 8-bit Machine Cycles: High speed mode 0.10µ s/20MHz (4.5V to 5.5V) 0.25µ s/8MHz(2.7V to 5.5V) 1.00µ s/2MHz(2.0V to 5.5V) Low speed mode 125µ s/32KHz(2.0V to 5.5V)* 4 Interrupts: 12[...]

Chapter 1 Overview 4 Timers 2 and 3 can be cascaded. Timer 4 16-bit timer Square wave output, 16-bit PWM output are possible. Clock source: fosc, fs/4, fs/16, TM4IO pin input Input capture function Time base timer Clock source: fosc, fs/4, fx* 4 , fx/2 13 * 4 or fosc/2 13 XIOat 32kHz, can be set to measure one minute intervals* 4 Can operate indepe[...]

Chapter 1 Overview 5 Pins 1-3 Pins 1-3-1 Pin Diagram Figure 1-3-1 Pin Diagram (42-SDIP: TOP VIEW) TXD,SBO0,P00  RXD,SBI0,P01  SBT0,P02  BUZZER, P06 RMOUT,P10  P11  TM2IO,P12  TM3IO,P13  TM4IO,P14  IRQ0,P20  IRQ1,P21  IRQ2,P22  P60  P61  P62  P63  P64  P6[...]

Chapter 1 Overview 6 Figure 1-3-2 Pin Diagram (44-QFP: TOP VIEW) MN101C117/115 LED3,P83  LED2,P82  LED1,P81  LED0,P80  AN6,PA6 AN0,PA0  AN1,PA1  AN2,PA2  AN3,PA3  AN4,PA4  AN5,PA5 P63  P62  P61  P60  P11 P22,IRQ2  P21,IRQ1,SENS  P20,IRQ0  P14,TM4IO ?[...]

Chapter 1 Overview 7 Pins Figure 1-3-3 Pin Diagram (48-QFH: TOP VIEW) LED3,P83  LED2,P82  LED1,P81  LED0,P80  NC  AN6,PA6 AN0,PA0  AN1,PA1  AN2,PA2  AN3,PA3  AN4,PA4  AN5,PA5 P63  P62  P61  P60  P11 P23,IRQ3  P22,IRQ2  P21,IRQ1,SENS  P20,IRQ0 ?[...]

Chapter 1 Overview 8 1-3-2 Pin Function Summary *The pin numbers in the list correspond to the QFH package(Refer to Figure 1-3-3 Pin connection.) Be careful when using SDIP and QFP packages. Table 1-3-1 Pin Function Summary (1/4) Pins Pin No. Name Type Dual Function Function Description 17 VSS – Power supply pins Apply 2.0V to 5.5V to VDD and 0V [...]

Chapter 1 Overview 9 Table 1-3-1 Pin Function Summary (2/4) 41 to 42 P70 to P71 I/O I/O port 7 2-bit CMOS tri-state I/O port. Each individual bit can be switched to an input or output by the P7DIR register. A pull-up or pull-down resistor for each bit can be selected individually by the P7PLUD register. However, pull-up and pull-down resistors cann[...]

Table 1-3-1 Pin Function Summary (3/4) 22 Buzzer I/O P06 Buzzer output Chapter 1 Overview 10 Pins Pin No. Name Type Dual Function Function Description 20 TXD Output SBO0(P00) UART transmit data output pin 21 RXD Input SBI0(P01) UART receive data input pin 20 SBO0 Output TXD(P00) Transmit data output pin for serial interfaces 0. The output configura[...]

Chapter 1 Overview Pins Table 1-3-1 Pin Function Summary (4/4) 11 Pin No. Name Type Dual Function Function Description The valid edge for these external interrupt input pins can be selected with the IRQnICR registers. IRQ1 is an external interrupt pin that is able to determine AC zero crossings. It can also be used as a normal external interrupt. W[...]

Chapter 1 Overview 12 Overview of Function 1-4 Overview of Functions 1-4-1 Block Diagram Figure 1-4-1 Block Diagram of Functions) CPU MN101C00 System clock oscillator Sub-clock oscillator ROM 16 KB RAM 512 bytes 8-bit timer 2 8-bit timer 3 16-bit timer 4 Time base timer 5 Serial interface 0 Watchdog timer External interrupt A/D conversion OSC1 OSC2[...]

Chapter 1 Overview 13 Electrical Characteristics 1-5 Electrical Characteristics 1-5-1 Absolute Maximum Ratings ∗ 2 ∗ 3 Note: ∗ 1 Applicable even for an interval of 100ms. *2 Insert at least one bypass capacitor of 0.1 µ F or more between a power source pin and GND to prevent from latchup. *3 Absolute maximum ratings indicate the allowable li[...]

Chapter 1 Overview 14 Electrical Characteristics 1-5-2 Operating Conditions Ta=–40 to +85°C V DD =2.0 to 5.5V V SS =0V Note: *1. Only for 48-QFH package ∗ 2 t c1 , t c2 , t c3 : OSC1 is the CPU clock t c4 : XI is the CPU clock Parameter Symbol Conditions Rating Unit MIN TYP MAX Supply voltage 1V DD1 fosc ≤ 20.0MHz 4 . 5 5. 5 2 Supply voltage[...]

Chapter 1 Overview 15 Electrical Characteristics ∗ 1 Set the clock duty ratio to 45 to 55%. *2 Applicable only for 48-pin QFH package Parameter Symbol Conditions Rating Unit MIN TYP MAX External clock input 1 OSC1 (OSC2 is unconnected) 18 Clock frequency f OSC 1.0 20.0 MHz 19 High level pulse width ∗ twh 1 ∗ 1 20.0 30.0 ns 20 Low level pulse [...]

Chapter 1 Overview 16 Electrical Characteristics Figure 1-5-3 OSC1 Timing Chart Figure 1-5-4 XI Timing Chart twh1 twl1 0.9V DD 0.1V DD twf1 twr1 twh2 twl2 0.9V DD 0.1V DD twf2 twr2[...]

1-5-3 DC Characteristics Ta=–40 to +85°C V DD =2.0 to 5.5V V SS =0V Notes: ∗ 1 Measured under conditions of Ta=25°C and no load. The supply current during operation, I DD1 (I DD2 ), is measured under the following conditions: After all I/O pins are set to input mode and the oscillation is set to <NORMAL mode>, the MMOD pin is fixed at V[...]

Chapter 1 Overview 18 Electrical Characteristics Ta=–40 to +85°C V DD =2.0 to 5.5V V SS =0V Parameter Symbol Conditions Rating Unit MIN TYP MAX Input pin 1 MMOD 8 Input high voltage 1 V IH1 0.8V DD V DD V 9 Input high voltage 2 V IH2 V DD =4.5 to 5.5V 0.7V DD V DD V 10 Input low voltage 1 V IL1 0 0.2V DD V 11 Input low voltage 2 V IL2 V DD =4.5 [...]

Chapter 1 Overview 19 Electrical Characteristics SENS pin Figure 1-5-5 Operation of AC Zero-Cross Detection Circuit Ta=–40 to +85°C V DD =2.0 to 5.5V V SS =0V ← trs → Input voltage level 1 → Input voltage level 2 → (Input) (Output) V DD V DHL V DHH V DLL V DLH V SS ← tfs → 27 Rise time trs Fig. 1-5-5 30 µs 28 Fall time tfs 30 Parame[...]

Chapter 1 Overview 20 Electrical Characteristics Ta=–40 to +85°C V DD =2.0 to 5.5V V SS =0V Parameter Symbol Conditions Rating Unit MIN TYP MAX I/O pin 5 P27 (RST) 36 Input high voltage V IH7 0.9V DD V DD V 37 Input low voltage V IL7 0 0.2V DD V 38 Input leakage current I LK7 VIN = 0 to V DD ±10 µ A 39 Input high current Iih -30 -100 -300 µ A[...]

Chapter 1 Overview Ta=–40 to +85°C V DD =2.0 to 5.5V V SS =0V 1-5-4 A/D Converter Characteristics Ta=–40 to+85°C V DD =2.0 to 5.5V V SS =0V Parameter Symbol Conditions Rating Unit MIN TYP MAX 1 Resolution 10 Bits 2 Nonlinear error 1 ±3 LSB 3 Differential linear error 1 ±3 LSB 4 Nonlinear error 2 ±5 LSB 5 Differential linear error 2 ±5 LSB[...]

Chapter 1 Overview 1-6 Option 1-6-1 ROM Option The product equipped with this LSI or an EPROM with this LSI controls the oscillation mode after resetting as well as the runaway-detection watchdog timer, using bits 2 to 0 of the last address of the built-in ROM. ■ Option bits Figure 1-6 ROM Option ( Address:X'7FFF' ) 22 Option 0 1 2 43 N[...]

Chapter 1 Overview 23 Chapter 1 Overview 1-6-2 Option Form 1. Oscillation mode MN101C Model Name Customer Approval Date: SE No. Type A Type B 2. Watchdog timer period setting Detection Period fs/2 16 fs/2 18 fs/2 20 Not used Selection Note: Type A: Operation begins from the reset cycle in the NORMAL mode. Type B: Operation begins from the reset cyc[...]

Chapter 1 Overview 24 External Dimensions 1-7 Outline Drawings Body Material: Epoxy Resin Lead Material:Fe Ni Lead Finish Method:Soldering dip Figure 1-7-1 42-SDIP The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office. Package code: SDIP042-P-0600 Unit: mm[...]

Chapter 1 Overview Body Material: Epoxy Resin Lead Material:Fe Ni Lead Finish Method:Soldering dip Figure 1-7-2 44-QFP Package code: QFP044-P-1010 Unit: mm The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office. External Dimensions) 25[...]

Chapter 1 Overview Material: Epoxy Resin Lead Material:Fe Ni-42 Alloy Lead Finish Method:Soldering dip Figure 1-7-3 48-QFH Package code: QFH048-P-0707 Unit: mm The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office. 26 External Dimensions[...]

27 2 Chapter 2 Basic CPU Functions[...]

Chapter 2 Basic CPU Functions 28 Overview/Address Space 2-1 Overview Basic CPU functions are in conformance with the MN101C00 series manual (architecture manual). This chapter describes specifications unique to the MN101C117/115. 2-2 Address Space 2-2-1 Memory Configuration Figure 2-2-1 Memory Map ∗ Differs depending upon the model. MN101C115 Int[...]

Chapter 2 Basic CPU Functions 29 Address Space 2-2-2 Special Function Registers Memory control register(MEMCTR) is a 4-bit register which set up the base Table 2-2-1 Register Map 01 2345 67 89 A B C D E F 03F0X 03F1X 03F2X 03F3X 03F4X 03F5X 03F6X 03F7X 03F8X 03F9X 03FAX 03FBX 03FCX 03FDX 03FEX 03FFX CPUM MEMCTR WDCTR DLYCTR SC0MD0 SC0MD1 SC0CTR SC0[...]

2-3 Bus Interface 2-3-1 Overview The MN101C117, unlike other MN101C series microcomputers, does not support memory expansion mode and processor mode. 2-3-2 Control Registers The memory control register is a four-bit register that sets up wait-count at a time of access to a base address of interrupt vector table and a special register zone. (1) Memo[...]

Chapter 2 Basic CPU Functions 31 Interrupts PSW New SP (after interrupt is accepted) 7 0 PC8 to 1 PC16 to 9 PC18,17 HA7 to 0 HA15 to 8 PC0 Old SP (before interrupt is accepted) Low Address High 2-4 Interrupts 2-4-1 Accepting and Returning from Interrupts In the MN101C00 series, when an interrupt is accepted, the hardware pushes the program's r[...]

Chapter 2 Basic CPU Functions 32 Interrupts ■ Operation when Returning from Interrupt After the program POPs the register and other values saved by the interrupt service routine, an RTI instruction is implemented to return to the program that was being executed when the interrupt was received. The processing sequence for the return from interrupt[...]

2-4-2 Interrupt Sources and V ector Addresses In addition to reset, there are 20 interrupt vectors that indicate the starting addresses of interrupt programs. These vectors are located in the 80-byte ROM address area X'04004' to X'04053'. Table 2-4-1 Interrupt Control Registers Chapter 2 Basic CPU Functions 33 Interrupts 0 1 2 3[...]

2-4-3 Interrupt Control Registers Interrupt control registers consist of the following: a non-maskable interrupt control register (NMICR), external interrupt control registers (IRQnICR), and internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR). ■ Non-maskable Interrupt Control Register (NMICR) Non-maskable interrupt factors[...]

■ Internal Interrupt Control Registers (TMnICR, TBICR, SCOICR, ATCICR, ADICR) The internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR) control the interrupt levels of internal interrupts, timer interrupts, serial interrupts, A/D conversion complete interrupts, and interrupt request/enable. Be sure to disable all interrupts [...]

Chapter 2 Basic CPU Functions 36 Reset 2-5 Reset The CPU contents are reset and registers are initialized when the RST pin is pulled to low. ■ Initiating a Reset There are two methods to initiate a reset. (1) Drive the RST pin low for at least four clock cycles. Figure 2-5-1 Minimum Reset Pulse Width (2) Set bit 7 (P2OUT7 flags) of the P2OUT regi[...]

37 3 Chapter 3 Port Functions[...]

Chapter 3 Port Functions 38 Overview 3-1 Overview A total of 39 pins on the MN101C117, including those shared with special function pins, are allocated for the 7 ports of P0 to P2, P6 to P8, and PA. Each I/O port is assigned according to the special function register area in memory. I/O ports are operated in byte or bit units in the same way as RAM[...]

Chapter 3 Port Functions 39 Overview ■ Port 1 (P1) 5-bit CMOS tri-state I/O port. Table 3-1-3 Port 1 Functions ■ Port 2 (P2) 4-bit CMOS tri-state input port. Table 3-1-4 Port 2 Functions ■ Port 6 (P6) 8-bit CMOS tri-state I/O port. Table 3-1-5 Port 6 Functions P10 to P14 I/O RMOUT, TM2IO to TM4IO Each bit can be set individually as either an [...]

■ Port 7 (P7) 8-bit CMOS tri-state I/O port. Table 3-1-6 Port 7 Functions ■ Port 8 (P8) 8-bit CMOS tri-state I/O port. Table 3-1-7 Port 8 Functions ■ Port A (PA) 8-bit CMOS tri-state input port. Table 3-1-8 Port A Functions Pin Name Type Dual Function Description P70 to P71 I/O Each individual bit can be switched to an input or output by the [...]

Chapter 3 Port Functions 41 Port Control Registers 3-2 Port Control Registers 3-2-1 Overview 28 registers control the I/O ports. See table 3-2-1. Table 3-2-1 I/O Port Control Registers (1/2) Name Address R/W Function P0OUT P1OUT P2OUT P6OUT P7OUT P8OUT P0IN P1IN P2IN P6IN P7IN P8IN PAIN P0DIR P1DIR X'03F10' X'03F11' X'03F12[...]

Table 3-2-1 I/O Port Control Registers (2/2) Chapter 3 Port Functions 42 Port Control Registers Name Address R/W Function P6DIR P7DIR P8DIR P1OMD PAIMD P0PLU P1PLU P2PLU P6PLU P7PLUD P8PLU PAPLUD FLOAT1 X'03F36' X'03F37' X'03F38' X'03F39' X'03F3A' X'03F40' X'03F41' X'03F42&a[...]

Chapter 3 Port Functions 43 Port Control Registers Figure 3-2-1 Port Control Registers (1/2) 0 1 2 4 5 6 73 P0OUT (at reset: -0---000) P1OUT (at reset: ---00000) P0IN (at reset: -X---XXX) P1IN (at reset: ---XXXXX) P2IN (at reset: ----XXX) P0DIR (at reset: -0---000) P1DIR (at reset: ---00000) P1OMD (at reset: ---00000) P0PLU (at reset: -0---000) P1P[...]

Figure 3-2-1 Port Control Registers (2/2) Chapter 3 Port Functions 44 Port Control Registers 0 1 2 4 5 6 73 P7OUT (at reset: - - - - - - 00) P8OUT (at reset: 00000000) P7IN (at reset: - - - - - - XX) P8IN (at reset: XXXXXXXX) PAIN (at reset: XXXXXXXX) P7DIR (at reset: - - - - - - 00) P8DIR (at reset: 00000000) PAIMD (at reset: 00000000) P7PLUD (at [...]

Chapter 3 Port Functions 45 Port Control Registers 3-2-2 I/O Port Control Registers This section describes the special function registers that control the MN101C117's I/O ports. ■ Data Registers • PnOUT registers Data registers to output to the ports. Data written to these registers is output from the ports. • PnIN registers Data registe[...]

Chapter 3 Port Functions 46 Port Control Registers ■ Port Output/Input Mode Registers • PnOMD/PnIMD registers These register settings determine whether the port pins(P10 to P14, PA0 to PA5) are used as I/O ports or as special function pins (dual function). If the special (dual) functions used, the PnDIR, PnPLU, PnPLUD, and other registers must [...]

Chapter 3 Port Functions 47 I/O Port Configuration and Functions 3-3 I/O Port Configuration and Functions ■ P00,P02,P10 to P14 R D L Q Reset Write Read Read R D L Q Reset Write Read R D L Q Reset Write Read Pull-up resistor control I/O direction control Port output data Special function input data Port input data Data bus Schmidt trigger input Sp[...]

Chapter 3 Port Functions 48 I/O Port Configuration and Functions ■ P01 Figure 3-3-2 Configuration and Functions of P01 R D L Q Write Read Read R D L Q Reset Write Read R D L Q Reset Write Read Pull-up resistor control I/O direction control Port output data Special function input data Port input data Data bus Reset Schmitt trigger input P0PLU1 P0P[...]

Chapter 3 Port Functions 49 ■ PA0 to PA7 Figure 3-3-3 Configuration and Functions of PA0 to PA7 R D L Q Reset Write Read R D L Q Reset Write Read Read R D L Q Reset Write Read Pull-up/pull-down resistor control Pull-up/pull-down resistor selection Input mode control Analog input Port input data Data bus Data bus PAPLUD0 PAPLUD (X'03F4A'[...]

Chapter 3 Port Functions 50 I/O Port Configuration and Functions ■ Pin Configuration for P20, P22 to P23 Figure 3-3-4 Configuration and Functions of P20, P22, P23 R D L Q Reset Write Read Read Schmitt trigger input Pull-up resistor control Port input data Special function input data Data bus P2PLU0 P2PLU2 P2IN0 P2IN2 P2PLU (X'03F42') P2[...]

Chapter 3 Port Functions 51 ■ P21 Figure 3-3-5 Configuration and Functions of P21 Data bus R D L Q Reset Read Read Read Schmitt trigger input R D L Q Reset Read Read Pull-up resistor control Port input data Special function input data Special function input data AC zero-cross detection circuit P2PLU1 P2IN1 P21IM P2PLU (x'03F42') P2IN (x[...]

Chapter 3 Port Functions 52 I/O Port Configuration and Functions ■ P27 Figure 3-3-6 Configuration and Functions of P27 Schmitt trigger input S D L Q Reset Write Port output data Reset signal input Data bus RST P2OUT7 P2OUT (x'03F12') Soft reset output Special input Register (address) Special function output Special function Control bit [...]

Chapter 3 Port Functions 53 ■ P70 to P71 Figure 3-3-7 Configuration and Functions of P70 Read R D L Q Reset Write Read R D L Q Reset Write Read R D L Q Reset Write Read Read R D L Q Reset Write Pull-up/pull-down resistor control Pull-up/pull-down resistor selection I/O direction control Port output data Port input data Data bus I/O Port Configura[...]

Chapter 3 Port Functions 54 I/O Port Configuration and Functions ■ P60 to P67,P80 to P87 Figure 3-3-8 Configuration and Functions of P60 to P67 Figure 3-3-9 Configuration and Functions of P80 to P87 R D L Q Reset Write Read Read R D L Q Reset Write Read R D L Q Reset Write Read Pull-up resistor control I/O direction control Port output data Port [...]

55 4 Chapter 4 T imer Functions[...]

Chapter 4 Timer Functions 56 Overview 4-1 Overview The MN101C117 contains three 8-bit timers, one 16-bit timer, a watchdog timer, a time base timer, and circuits for remote control output and buzzer output. Table 4-1-1 Summary of Timer Functions Timer 2 (8-bit) Timer 3 (8-bit) Timer 4 (16-bit) Timer 5 (8-bit) Time Base Interrupt TM2IRQ TM3IRQ TM4IR[...]

Chapter 4 Timer Functions 57 Overview fs fs/4 fx TM2IO input MUX MUX MUX MUX Synchro- nization MUX MUX MUX MUX MUX MUX Synchro- nization MUX fosc f s/4 f s/16 TM3IO input TM2OC TM3CK0 TM3CK1 TM3CK2 TM2CK0 TM2CK1 TM2CK2 TM2PWM TM2EN TM3PWM TM3EN TM3OC TM3MD TM2MD TM3IRQ TM3IO output/ PWM2/ Remote control carrier output/ Serial transfer clock output [...]

Chapter 4 Timer Functions 58 Overview Figure 4-1-2 Timer 4 Block Diagram fosc fs/4 fs/16 TM4IO input MUX MUX Synchro- nization Synchro- nization MUX MUX MUX MUX IRQ0 IRQ1 IRQ2 TM4OCL TM4CK0 T4 I CT0 TM4C K2 T4 I CT1 TM4EN TM4PWM TM4CK1 RSTIO TM4MD 1/2 Read/Write Read/Write TM4PWM Read Read Read Read R RR S Q TM4OCH Pulse-added timing generation Pul[...]

Chapter 4 Timer Functions 59 Overview Figure 4-1-3 Timer 5/Time Base Block Diagram MUX MUX MUX MUX MUX MUX MUX f osc f s/4 f osc f x 250ms (32kHz) 0.977ms (8MHz) 1min (32kHz),250ms (8.38MHz) 3.9ms, 7.8ms, 15.6ms, 31.2ms (32kHz) 1/2 f x TM5CK0 TM5MD TM5CK1 TM5CK2 TM5CK3 TM5IR0 TM5IR1 TM5IR2 TM5CLRS 1/2 TM5IRQ TBIRQ TM5BC Read/Write Read 8-bit counte[...]

Chapter 4 Timer Functions 60 Overview Figure 4-1-4 Watchdog Timer, Buzzer Block Diagram 1/2 1/4 WDCTR DL YCTR MUX MUX 14 12 1/2 11 1/2 10 1/2 9 1/2 fs 1/2 1/2 R S R R 1/4 1/4 DLYS0 WDEN – – – – – – – 0 7 DLYS1 BUZS0 – 0 7 – – BUZS1 BUZOE 10 1/2 fosc fosc fosc 6 14 Internal reset release WDIRQ Buzzer Overflow ROM option Overflow [...]

Chapter 4 Timer Functions 61 Overview Figure 4-1-5 Remote Control Transmission Block Diagram Synchronization circuit MUX RMCTR Remote control output 1/3 duty 1/2 duty RMDTY0 – RMOEN – – – – – 0 7 Timer 3 output[...]

Chapter 4 Timer Functions 62 4-2 8-bit T imer Operation (timers 2, 3) 4-2-1 Overview Functions for timers 2 and 3 are listed below. Table 4-2-1 Summary of 8-bit Timer Functions Timer 2 (8-bit) Timer 3 (8-bit) TM2IRQ TM3IRQ Remote control carrier pulse generation × × × Interrupt Event counter Timer pulse output Serial transmission clock PWM outpu[...]

Chapter 4 Timer Functions 63 8-bit Timer Operation (timers 2, 3) 4-2-2 Operation ■ Timer Operation (timers 2, 3) Settings for timer operation are listed below. Timer 2 is used as an example. (1) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2. ( 2 ) Set the TM2CK2 0 flags of the TM2M[...]

Chapter 4 Timer Functions 64 8-bit Timer Operation (timers 2, 3) If TM2IO input is selected as the clock source and the value of binary counter 2 is to be read during operation, select synchronized TM2IO input to avoid reading data that may be incomplete during count-up transitions. However, with synchronized TM2IO input, it is not possible to retu[...]

Chapter 4 Timer Functions 65 The period of a signal output to the port is 1/2 of the period set in the TM2OC register. If port 1 is to be used as a pulse output pin, it is necessary to set the port 1 output direction control register (P1DIR) and the port 1 pull-up/pull-down resistor control register (P1PLU). ■ Timer Pulse Output Function (timers [...]

Chapter 4 Timer Functions 66 If the TM3PWM flag of the TM3MD register is set to "1" and timer 2 PWM output is selected, the PWM output of timer 2 will also be output from the TM3IO pin. If port 1 is to be used as a PWM output pin, the P1DIR and P1PLU registers must be set. ■ PWM Output Function (Timer 2) Settings for the PWM output func[...]

Figure 4-2-5 PWM Output Timing (when TM2OC register is X'00') Figure 4-2-6 PWM Output Timing (when TM2OC register is X'FF') Chapter 4 Timer Functions 67 8-bit Timer Operation (timers 2, 3) Clock PWM output Binary counter 2 PWM output Matches TM2OC register Overflow[...]

Chapter 4 Timer Functions 68 The clock source for the serial interface has a frequency that is 1/2 of the overflow output of timer 3. For serial interface settings, refer to the chapter on serial functions. Disable the timer 2 interrupt. ■ Serial Transfer Clock Function(timer 3) Settings for the serial transfer clock function are listed below. (1[...]

Chapter 4 Timer Functions 69 16-bit Timer Operation (timer 4) 4-3 16-bit T imer Operation (timer 4) 4-3-1 Overview Timer 4 is a 16-bit programmable counter that can be used as an event counter. A signal with a frequency of 1/2 of the timer 4 overflow signal can be output from the TM4IO pin. An input capture function and pulse added type PWM output [...]

Figure 4-3-1 Binary Counter 4 (TM4BC) Count Timing Chapter 4 Timer Functions 70 Clock TM4EN Binary counter 4 Write to registers TM4OCH, TM4OCL 05 04 06 07 08 09 00 If the TM4EN flag of the TM4MD register is changed simultaneously with other bits, the switching operation may cause binary counter 4 to be incremented. If the value of the TM4OCH, TM4OC[...]

Chapter 4 Timer Functions 71 16-bit Timer Operation (timer 4) If TM4IO input is selected as the clock source and the value of binary counter 4 is to be read during operation, select synchronized TM4IO input to avoid reading data that may be incomplete during count-up transitions. However, with synchronized TM4IO input, it is not possible to return [...]

Chapter 4 Timer Functions 72 ■ Timer Pulse Output Function Settings for the timer pulse output function are listed below. (1) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" so that the count operation of timer 4 is stopped. ( 2 ) Set bit 4 of the port 1 output/input mode register (P1OMD) to the special function pin setti[...]

■ Pulse Added Type PWM Output Function In the pulse added method, a 1-bit output is appended to the basic component of the 8-bit PWM output. Precise control is possible based on the number of PWM repetitions (256 times) to which this bit is appended. Settings for the pulse added type PWM output function are listed below. (1) Set the TM4EN flag of[...]

Chapter 4 Timer Functions 74 16-bit Timer Operation (timer 4) [ ☞ 5-2-3 "Serial Interface Transfer Timing"] ■ Setting the Added Pulse Position The upper 8 bits of compare register 4 (TM4OCH) set the position of the added pulse. If the TM4OCH register is set to X'00', an additional bit is not appended to the basic PWM compone[...]

Chapter 4 Timer Functions 75 16-bit Timer Operation (timer 4) ■ Capture Function Settings for the capture function are listed below. (1) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4. (2) Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the clock so[...]

Chapter 4 Timer Functions 76 8-bit Timer Operation (timers 2, 3) 4-4 8-bit T imer Operation (timer 5) 4-4-1 Overview Timer 5 is an 8-bit timer that can have fosc, fs/4, fx, or time base output as its clock source. 4-4-2 Operation ■ Timer Operation Settings for timer operation are listed below. (1) Set the TM5CLRS flag of the timer 5 mode register[...]

4-5 T ime Base Operation 4-5-1 Overview The clock source for the time base timer can be set to fosc or fx. Also, the interrupt period for time base timer (TBIRQ) can be set to 1/2 7 , 1/2 8 , 1/2 9 , 1/2 10 , or 1/2 13 of the clock source. 4-5-2 Operation ■ Time Base Function Settings for the time base function are listed below. (1) Use the TM5CK[...]

Chapter 4 Timer Functions 78 4-6 W atchdog Timer Operation 4-6-1 Overview The watchdog timer is controlled by the watchdog control register (WDCTR) and can be used for runaway program detection. 4-6-2 Setup and Operation (1) Set the WDEN flag of the watchdog timer control register (WDCTR) to "1" to start the watchdog timer. (2 ) Operate t[...]

4-7 Remote Control Output Operation 4-7-1 Overview A remote control carrier pulse can be generated using the overflow of timer 3. Two duty ratios of 1/2 or 1/3 can be selected. 4-7-2 Setup and Operation (1) Set the RMOEN flag of the remote control carrier output control register (RMCTR)to "0" so that the remote control carrier output is s[...]

Chapter 4 Timer Functions 80 4-8 Buzzer Output 4-8-1 Buzzer Output Setup and Operation The square wave having a frequency 1/2 9 to 1/2 12 of the system clock can be output from the P06/BUZZER pin. (1) Set the BUZOE flag of the oscillation stabilization wait control register (DLYCTR) to "0" so that the buzzer output is turned off. ( 2 ) Se[...]

Chapter 4 Timer Functions 81 Overview 4-9 T imer Function Control Registers 4-9-1 Overview 19 registers control the timers. See table 4-9-1. Table 4-9-1 Timer Control Registers R/W: Readable and writable R: Read only Name Address R/W X’03F72’ X’03F62’ X’03F82’ X’03F73’ X’03F63’ X’03F83’ X’03F64’ X’03F74’ X’03F75’[...]

Chapter 4 Timer Functions 82 Timer Function Control Registers 4-9-2 Programmable Timer/Counters Timers 2~5 all contain a programmable 8-bit timer/counter (16-bit in timer 4). Programmable timer/counters consist of a compare register and a binary counter. (1) Compare register 2 (TM2OC) Figure 4-9-1 Compare Register 2 (TM2OC: X'03F72', R/W)[...]

(5) Compare register 4 (TM4OCL) (lower 8 bits) Figure 4-9-5 Compare Register 4 (TM4OCL: X'03F74', R/W) (6) Compare register 4 (TM4OCH) (upper 8 bits) Figure 4-9-6 Compare Register 4 (TM4OCH: X'03F75', R/W) (7) Binary counter 4 (TM4BCL) (lower 8 bits) Figure 4-9-7 Binary Counter 4 (TM4BCL: X'03F64', R) (8) Binary counte[...]

Chapter 4 Timer Functions 84 Timer Function Control Registers (9) Input capture register (TM4ICL) (lower 8 bits) Figure 4-9-9 Input Capture Register (TM4ICL: X'03F66', R) (10) Input capture register (TM4ICH) (upper 8 bits) Figure 4-9-10 Input Capture Register (TM4ICH: X'03F67', R) (11) Compare register 5 (TM5OC) Figure 4-9-11 Co[...]

Chapter 4 Timer Functions 85 Timer Function Control Registers 4-9-3 T imer Mode Registers Four readable and writable 6-byte timer mode registers. Control timers 2, 3, 4, 5, and the time base. (1) Timer 2 mode register (TM2MD) Figure 4-9-13 Timer 2 Mode Register (TM2MD: X'03F82', R/W) 0 1 2 4 5 6 73 (at reset: ---00XXX) ––– TM2MD TM2[...]

(2) Timer 3 mode register (TM3MD) Figure 4-9-14 Timer 3 Mode Register (TM3MD: X'03F83', R/W) Chapter 4 Timer Functions 86 Timer Function Control Registers TM3CK1 0 0 1 1 0 0 1 fosc fs/4 fs/16 TM3IO input Cascade connection with timer 2 Synchronous TM3IO input 1 1 x 0 1 Clock source selection TM3CK0 0 1 Halt the count P13 output selection [...]

(3) Timer 4 mode register (TM4MD) Figure 4-9-15 Timer 4 Mode Register (TM4MD: X'03F84', R/W) Chapter 4 Timer Functions 87 Timer Function Control Registers 0 1 2 4 5 6 7 – 3 (at reset: -0000XXX) TM4MD TM4CK0 TM4CK1 TM4CK2 0 1 0 1 1 0 0 0 1 fosc fs/4 fs/16 TM4IO input Synchronous TM4IO input 1 1 1 Halt the count TM4 count control TM4 oper[...]

(4) Timer 5 mode register (TM5MD) Figure 4-9-16 Timer 5 Mode Register (TM5MD: X'03F88', R/W) Chapter 4 Timer Functions 88 Timer Function Control Registers TM5CK3 X 0 TM5CK2 0 1 1 fs/4 (Use Prohibited) Output of time base timer Timer 5 clock source selection fosc 0 0 1 1 (Use Prohibited) Synchronous time base timer output 0 1 TM5CK1 TM5IR1[...]

4-9-4 T imer Control Registers (1) Watchdog timer control register (WDCTR) Figure 4-9-17 Watchdog Timer Control Register (WDCTR: X'03F02', R/W) (2) Oscillation stabilization wait control register (DLYCTR) Figure 4-9-18 Oscillation Stabilization Wait Counter Control Register (DLYCTR: X'03F03', R/W) Chapter 4 Timer Functions 89 Ti[...]

(3) Remote control carrier output control register (RMCTR) Figure 4-9-19 Remote Control Carrier Control Register (RMCTR: X'03F89', R/W) Chapter 4 Timer Functions 90 Timer Function Control Registers 0 1 2 4 5 6 73 RMCTR – –– – – – RMDTY0 RMOEN Enable remote control carrier output 0 1 Output low level Output remote control carri[...]

91 5 Chapter 5 Serial Functions[...]

Chapter 5 Serial Functions 92 Overview 5-1 Overview The MN101C117 contains a serial interface that can operate in synchronous and simple UART modes. An overview of serial functions is shown below. Table 5-1-1 Overview of Serial Functions Interrupt Serial 0 Synchronous Simple UART Clock selection 1/8 period of clock SC0ICR fs/2 fs/4 fs/16 BC3X1/2 Ex[...]

Chapter 5 Serial Functions 93 Overview Figure 5-1-1 Serial 0 Block Diagram fs/2 fs/4 fs/16 BC3 × 1/2 SBI0/RXD/P01 SBO0/TXD1/P00 SC0RXB SC0TRB SBT0/P02 SC0IRQ Shift register SWAP Start condition transmission Receive buffer SC0PEK SC0FEF – SC0BSY SC0CMD – SC0ORE 0 7 0 7 – SC0SBTS 0 7 0 7 SC0SBIS SC0SBOS SC0SBTM SC0SBOM SC0IOM – – SC0TRI SC[...]

Chapter 5 Serial Functions 94 5-2 Synchronous Serial Interface 5-2-1 Overview A serial interface begins operation when data is written to the shift buffer. A bit counter is incremented at each 1-bit transfer. The transfer is complete when the counter overflows. Bit transfers of an arbitrary 1 to 8 bits can be performed. The transfer bit count must [...]

Chapter 5 Serial Functions 95 Synchronous Serial Interface When the clock source is an external clock (SBT0 pin input): • Set the SC0SBTM flag of the SC0MD3 register. • Set bit 2 of the P0DIR register to input mode. • Set the P0PLU register, if necessary. (7) Select the SC0SBOM flag of the SC0MD3 register. (8) Select the SC0IOM flag of the SC[...]

Chapter 5 Serial Functions 96 Figure 5-2-1 Synchronous Serial Interface Transmission Timing (falling edge) Figure 5-2-2 Synchronous Serial Interface Transmission Timing (rising edge) Clock Start condition enabled Start condition disabled SC0BSY Interrupt SC0LNG2 to 0 SBT SBO SBO ts 012345670 Synchronous Serial Interface SBT SBO SBO Clock Start cond[...]

Chapter 5 Serial Functions 97 ■ Reception (1) Select the synchronous serial interface by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "0." (2 ) Select the transfer bit count with the SC0LNG2 to 0 flags of the serial interface 0 mode register 0 (SC0MD0). The transfer bit count can be set as 1 to 8 bits. [...]

Chapter 5 Serial Functions 98 Figure 5-2-3 Synchronous Serial Interface Reception Timing (reception at rising edge) Figure 5-2-4 Synchronous Serial Interface Reception Timing (reception at falling edge) Synchronous Serial Interface Clock Start condition disabled Start condition enabled SC0BSY start condition enabled SC0BSY start condition disabled [...]

Chapter 5 Serial Functions 99 Synchronous Serial Interface 5-2-3 Serial Interface T ransfer Timing Serial interface 0 uses the SC0CE0 and SC0CE1 flags of serial interface 0 mode register 0 (SC0MD0), to control the edge at which transmission data is output and the edge at which reception data is input. During transmission, when the SCnCE1 flag is &q[...]

Chapter 5 Serial Functions 100 When serial interface 0 is used for simultaneous transmission and reception, set the SCnCE0 and SCnCE1 flags of the SCnMD0 register to "00" or "01", so that the reception data input edge is opposite in polarity to the transmit data output edge. Also, the polarity of the reception data input edge is[...]

Chapter 5 Serial Functions 101 5-3 Half-duplex UART Serial Interface 5-3-1 Overview Setup and operation of UART transmission and reception are described below. 5-3-2 Setup and Operation ■ Transmission (1) Select UART by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "1." (2 ) Specify the first bit to be t[...]

Chapter 5 Serial Functions 102 (7) If parity is enabled by the SC0NPE flag of the SC0MD2 register, set the SC0PM1~0 flags of the SC0MD2 register to specify the added parity bit. (8) Set the SC0FM1 to 0 flags of the SC0MD2 register to specify the frame mode. ( 9) Set the SC0BRKE flag of the SC0MD2 register to control break status transmission. (10) [...]

Chapter 5 Serial Functions 103 When the serial port is enabled and the SC0CE1 to 0 flags of the SC0MD0 register are toggled, the transfer bit count may change. The TXD pin goes to a high level after reception is complete. Serial interface 0 begins operation when the SC0SBOS or SC0SBIS flag is set to "1." Set the SC0SBOS or SC0SBIS flag af[...]

Chapter 5 Serial Functions 104 Figure 5-3-2 UART Reception Timing Half-duplex UART Serial Interface RXD RXD Parity enabled Parity disabled Parity bit Stop bit Stop bit Stop bit Stop bit SC0BSY Parity disabled SC0BSY Parity enabled Interrupt Parity disabled Interrupt Parity enabled[...]

5-3-3 How to Use the Baud Rate Timer Refer to the following when using the baud rate timer to set the UART transfer speed. (1) Specifying the timer clock source The clock source is specified by the TM3CKS3 to 1 flags of the timer 3 mode register (TM3MD). (2) Setting the compare register The compare register value is set in the timer 3 compare regis[...]

Chapter 5 Serial Functions 106 Serial Interface Control Registers 5-4 Serial Interface Control Registers 5-4-1 Overview 7 registers control the serial interface. See table 5-4-1. Table 5-4-1 Serial Interface Registers Name Address R/W Function SC0MD0 X'03F50' R/W Serial interface 0 mode register 0 SC0MD1 X'03F51' R/W Serial inte[...]

Chapter 5 Serial Functions 107 Serial Interface Control Registers 5-4-2 T ransmit/Receive Shift Registers, Receive Data Buffer (1) Serial interface 0 transmit/receive shift register (SC0TRB) This 8-bit, writable register shifts the transmission data and the reception data. The direction of transfer can be specified as LSB first or MSB first. Figure[...]

Chapter 5 Serial Functions 108 5-4-3 Serial Interface Mode Registers (1) Serial interface 0 mode register (SC0MD0) Figure 5-4-3 Serial Interface 0 Mode Register 0 (SC0MD0: X'03F50', R/W) Serial Interface Control Registers (at reset: -00XX000) 0 1 2 43 SC0MD0 SC0LNG0 SC0LNG1 SC0LNG2 SC0LNG0 SC0LNG1 SC0LNG2 SC0STE SC0CE1 SC0DIR SC0CE0 – 5[...]

Chapter 5 Serial Functions 109 Serial Interface Control Registers (2) Serial interface 0 mode register 1 (SC0MD1) Figure 5-4-4 Serial Interface 0 Mode Register 1 (SC0MD1: X'03F51', R/W) 0 1 2 43 (at reset: --X00000) SC0MD1 SC0ERE SC0TRI SC0BRKF SC0CK0 SC0CKM SC0CK1 – – 5 6 7 0 1 Transmit interrupt request Transmit/receive interrupt re[...]

Chapter 5 Serial Functions 110 Serial Interface Control Registers (3) Serial interface 0 mode register 2 (SC0MD2) Figure 5-4-5 Serial Interface 0 Mode Register 2 (SC0MD2: X'03F52', R/W) 0 1 2 43 (at reset: --000XXX) SC0MD2 SC0NPE Break status transmit control Data Break SC0BRKE Added bit specification SC0PM1 SC0PM0 SC0PM1 SC0FM0 SC0FM1 SC[...]

Chapter 5 Serial Functions 111 Serial Interface Control Registers (4) Serial interface 0 mode register 3 (SC0MD3) Figure 5-4-6 Serial Interface 0 Mode Register 3 (SC0MD3: X'03F53', R/W) SBI0 input control "1" input Serial input SC0SBIS 0 1 SBO0 pin function selection Port Serial communication SC0SBOS 0 1 SBT0 pin configuration s[...]

Chapter 5 Serial Functions 112 5-4-4 Serial Interface Control Register (1) Serial interface 0 control register (SC0CTR) Figure 5-4-7 Serial Interface 0 Control Register (SC0CTR: X'03F54', R) (R/W available with SC0CMD only) Serial Interface Control Registers 0 1 2 43 (at reset: 00XX000X) SC0CTR SC0ORE – SC0PEK SC0FEF –– SC0CMD SC0BS[...]

113 6 Chapter 6 A/D Conversion Functions[...]

Chapter 6 A/D Conversion Functions 114 Overview 6-1 Overview The MN101C117 has an internal A/D converter with 10-bit resolution. A sample-and-hold circuit is contained on-chip and software can switch the analog input between channels 0 to 7 (AN0 to AN7). When the A/D converter is stopped, power consumption can be reduced by turning off the internal[...]

Chapter 6 A/D Conversion Functions 115 A/D Conversion 6-2 A/D Conversion The procedures for operating the A/D conversion circuit are listed below. (1) Set the ANCHS2 to ANCHS0 flags of A/D control register 0 (ANCTR0) to specify one of pins AN7 to AN0 (PA7 to PA0) as the analog input. ( 2 ) Set the ANCK1 and ANCK0 flags of A/D control register 0 to [...]

Chapter 6 A/D Conversion Functions 116 A/D Converter Control Registers The following items must be implemented to maintain the accuracy of the A/D converter: 1. Use a maximum input pin impedance, R, of 500k Ω ∗ 1 with an external capacitor, C, that is minimum 1,000pF and maximum 1µF ∗ 1 . 2. Take the RC time into consideration when setting t[...]

117 Chapter 6 A/D Conversion Functions A/D Converter Control Registers 6-3 A/D Converter Control Registers 6-3-1 Overview Four registers control the A/D converter. See table 6-3-1. Table 6-3-1 A/D Converter Control Registers Name Address R/W Function ANCTR0 X'03F90' R/W A/D control register 0 ANCTR1 X'03F91' R/W A/D control regi[...]

Chapter 6 A/D Conversion Functions 118 A/D Converter Control Registers 6-3-2 A/D Control Register (ANCTR) This readable and writable 8-bit register controls the operation of the A/D converter. (1) A/D control register 0 (ANCTR0) ∗ 1: Specify that where the period of the A/D conversion clock is greater than 800ns. ∗ 2: Sample-and-hold time is de[...]

Chapter 6 A/D Conversion Functions 119 A/D Converter Control Registers (2) A/D conversion control register 1 (ANCTR1) Figure 6-3-2 A/D Control Register 1 (ANCTR1: X'03F91', R/W) A/D conversion status 0 1 2 43 ANST ANCTR1 5 6 7 (at reset: 0-------) 0 1 A/D conversion completed or stopped A/D conversion started or in progress ANST[...]

Chapter 6 A/D Conversion Functions 120 A/D Converter Control Registers 6-3-3 A/D Buffers (ANBUF) These read-only registers store the A/D conversion results. (1) A/D buffer 0 (ANBUF0) This register stores the lower 2 bits of the A/D conversion results. Figure 6-3-3 A/D Buffer 0 (ANBUF0: X'03F92', R) (2) A/D buffer 1 (ANBUF1) This register [...]

121 7 Chapter 7 AC Zero-Cross Circuit/Noise Filter[...]

Chapter 7 AC Zero-Cross Circuit/Noise Filter 122 Overview 7-1 Overview The P21/SENS pin is the input pin for the AC zero-cross detection circuit. The AC zero-cross detection circuit outputs a high level when the input is at an intermediate level, and a low level at all other times. AC zero-cross detection circuit P21 input/IRQ1 to noise filter (See[...]

Chapter 7 AC Zero-Cross Circuit/Noise Filter 123 AC Zero-Cross Circuit Operation 7-2 AC Zero-Cross Circuit Operation 7-2-1 Setup and Operation Settings for zero-cross circuit operation are listed below. (1) Set the REDG1 flag of the IRQ1ICR register to select the valid edge for IRQ1. (2) Set the NF1EN and NF1CK1 to 0 flags of the NFCTR register to [...]

Chapter 7 AC Zero-Cross Circuit/Noise Filter 124 7-3 Noise Filter 7-3-1 Overview External interrupt pins IRQ0 and IRQ1 contain noise filtering circuit. This circuitry can be used for remote control signal reception. Figure 7-3-1 Noise Filtering Circuit Block Diagram Noise Filter Data bus NFCTR NF1EN NF1CKS0 fs/2 8 fs/2 2 fs/2 9 fs/2 10 MUX Noise fi[...]

Chapter 7 AC Zero-Cross Circuit/Noise Filter 125 Noise Filter 7-3-2 Example Input and Output W aveforms for Noise Filter When the noise filter is used, the waveform input to the IRQ0 pin is sampled based on the clock specified by the NF0CKS0 and NF0CKS1 flags of the noise filter control register (NFCTR). The waveform input to the IRQ1 pin is also s[...]

Chapter 7 AC Zero-Cross Circuit/Noise Filter 126 [ ☞ 2-4-3 "Interrupt Control Registers ■ External Interrupt Control Registers"] [ ☞ 3-2-2 "I/O Port Control Registers ■ Pin Control Registers"] 7-4 AC Zero-Cross Control Register 7-4-1 Overview Four registers control the AC zero-cross circuit. Table 7-4-1 AC Zero-Cross Con[...]

Chapter 7 AC Zero-Cross Circuit/Noise Filter 127 AC Zero-Cross Control Register 7-4-2 Noise Filter Control Register (NFCTR) This 6-bit readable and writable register controls the noise filter. Figure 7-4-1 Noise Filter Control Register (NFCTR: X'03F8A', R/W) 0 1 0 1 0 1 IRQ1 noise filter sampling period selection 0 1 2 4 5 6 73 NFCTR NF0E[...]

Chapter 7 AC Zero-Cross Circuit/Noise Filter 128[...]

129 8 Appendices[...]

Chapter 8 Appendices 130 EPROM Versions 8-1 EPROM V ersions 8-1-1 Overview EPROM version is microcomputer which was replaced with the mask ROM of the MN101C11 with an electronically programmable 16-KB EPROM. Because the MN101CP117**(**=DP,BF,HP) is sealed in plastic, once data is written to the internal PROM it cannot be erased. Because the PX-AP10[...]

8-1-2 Cautions on Use EPROM Versions differs from the MN101C11* in some of its electrical characteristics. The user should be aware of these differences. (1) To prevent data from being erased by ultraviolet light after a program is written, affix seals impermeable to UV rays to the glass sections at the top and side sections of the CPU. (PX-AP101C1[...]

Chapter 8 Appendices 132 EPROM Versions 8-1-3 Erasing Written Data in W indowed Packages In an internal EPROM with windowed packaging, data is erased("0" → "1") when UV light at 253.7nm permeates the window to irradiate the chip. The recommended exposure is 10W · s/cm 2 . This coverage can be achieved by using a commercial UV[...]

Chapter 8 Appendices 133 EPROM Versions 8-1-4 Characteristics of EPROM V ersion The MN101C11*(mask ROM version) and the Microcomputer with internal EPROM version have the following differences. Table 8-1-1 Difference between MN101C*(Mask ROM version) and Internal EPROM version) There are no other functional differences. MN101C11 ＊（ ROM ver. ）[...]

8-1-5 W riting to Microcomputer with Internal EPROM ■ Fit in the writing adapter and position the No.1 pin. Figure 8-1-1 Mount on the writing adapter and position of No.1 pin. Chapter 8 Appendices 134 EPROM Versions 1 2 39 40 No.1 pin must be matched to this position. *The socket of an adapter varies according to the package types. Package type P[...]

Chapter 8 Appendices 135 EPROM Versions ■ ROM writer Selection The device names should be set up as listed below. Table 8-1-2 Device selection The above settings are based on the standard samples. When you use the other equipment than the ones listed, contact the nearest semiconductor design center.(Refer to the sales office table attached at the[...]

Chapter 8 Appendices 136 EPROM Versions 8-1-6 Cautions on Operating the ROM Writer ■ Cautions on operating the ROM writer (1)The Vpp programming voltage for the EPROM versions is 12.5V. Programming with a 21-volt ROM writer can lead to damage. The ROM writer specifications must match those for standard 1-megabit EPROMS:Vpp=12.5V V;tpw=0.2ms. (2)M[...]

Chapter 8 Appendices 137 EPROM Versions 8-1-7 Option Bit The MN101C117 and the MN101CP117 control the oscillation mode after resetting as well as the runaway-detection watch dog timer, using bit 2 to 0 of the last address (X'7FFF) of the built-in ROM. ■ Option bit Fig. 8-1-2 Option bit(Address: X'07FFF') 0 1 2 4 5 6 73 0 1 Slow mod[...]

Chapter 8 Appendices 138 EPROM Versions 8-1-8 W riting Adapter Connection Package Code SDIP042-P-0600 Fig. 8-1-3 MN1-1CP117-DP(DC)EPROM Writing Adapter Connections VSS VSS NOE VSS A14 VSS VSS VSS VSS VPP VSS NCE A0 A1 A2 A3 A4 A5 A6 A7 VSS VSS VSS VSS VCC VSS VSS A13 A[...]

Chapter 8 Appendices 139 EPROM Versions Package code: QFP044-P-1010 Pin pitch: 0.8mm Fig. 8-1-4 MN101CP117-BL(BC)EPROM Writing Adapter Connections MN101CP117 ４４- ＱＦＰ D3 D2 D1 D0 A8 A9 A10 A11 A12 A13 VSS A3 A2 A1 A0 NCE VSS VPP VSS VSS VSS VSS D4 D5 D6 D7 VDD VS[...]

Chapter 8 Appendices 140 EPROM Versions Package code: QFH048-P-0707 Pin pitch: 0.5mm Fig. 8-1-5 MN101CP117-HP EPROM Writing Adapter connections P83  P82  P81  P80  NC  PA6 PA0  PA1  PA2  PA3  PA4  PA5 P63  P62  P61  P60  P11 P23 P22 P21 P20 P14 P13 P12 MN101CP117 P6[...]

Chapter 10 Appendices 141 Instruction Set 8-2 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Data move instructions Mnemonic Operation Affected Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes Page 1 23456789 1 0 1 1 Expand MOV –––– 21 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 [...]

Chapter 10 Appendices 142 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes Page 1 23456789 1 0 1 1 Expand PUSH Dn PUSH SP-1 → SP,Dn → mem8(SP) –––– 23 1111 10Dn PUSH An SP-2 → SP,An → mem16(SP) –––– 25 0001 011A POP Dn POP mem8(SP) [...]

Chapter 10 Appendices 143 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes Page 1 23456789 1 0 1 1 Expand ∗ 1   d4 sign extended ∗ 2   d7 sign extended ∗ 3   d11 sign extended NOT   Dn NOT _ Dn → Dn 00 32 0010 10Dn 0010 89 92 ASR   Dn ASR[...]

Chapter 10 Appendices 144 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes Page 1 23456789 1 0 1 1 Expand ∗ 1   d4 sign extended ∗ 2   d7 sign extended 107 108 108 109 109 BGT label Bcc if((VF^NF)|ZF=0),PC+6+d11(label)+H → PC –––– 63 / 4 [...]

Chapter 10 Appendices 145 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes Page 1 23456789 1 0 1 1 Expand TBNZ (abs8)bp,label if(mem8(abs8)bp=1),PC+8+d11(label)+H → PC 00 8 126 127 127 129 129 130 130 131 6/7 0001 1bp. <abs 8..> <d11 .... ...H 0[...]

Chapter 10 Appendices 146 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes Page 1 23456789 1 0 1 1 135        REP imm3 REP ※1 imm3→RPC − − − − 32 0001 1 r e p ?[...]

Chapter 10 Appendices 147 Instruction Map 8-3 Instruction Map 0 0 NOP RTS MOV #8,(io8) RTI CMP #8,(abs8)/(abs12) POP An ADD #8,Dm MOVW #8,DWm MOVW #8,Am 1 JSR d12(label) JSR d16(label) MOV #8,(abs8)/(abs12) PUSH An OR #8,Dm AND #8,Dm 2 When the extension code is b'0010' When the extension code is b'0011' 3 4 MOV (abs12),Dm MO[...]

Chapter 10 Appendices 148 Instruction Map 0  0 TBZ (abs8)bp,d7 TBZ (abs8)bp,d11 1 TBNZ (abs8)bp,d7 TBNZ (abs8)bp,d11 2 CMP Dn,Dm 3 ADD Dn,Dm 4 TBZ (io8)bp,d7 TBZ (io8)bp,d11 5 TBNZ (io8)bp,d7 TBNZ (io8)bp,d11 6 OR Dn,Dm 7 AND Dn,Dm 8 BSET (io8)bp BCLR (io8)bp 9 JMP abs18(label) JSR abs18(label) A XOR Dn,Dm / XOR #8,Dm B ADDC Dn,Dm C BSET (abs16)[...]

Chapter 10 Appendices 149 Summary of Special Function Registers Address X’ 3F00’ X’ 3F01’ X’ 3F02’ X’ 3F03’ X’ 3F10’ X’ 3F11’ X’ 3F12’ X’ 3F13’ X’ 3F14’ Register Bit 7 Bit 6 Bit 5 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 STOP HALT OSC1 OSC0 STOP transfer request HALT transfer request Oscilla[...]

Chapter 10 Appendices 150 Summary of Special Function Registers Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X’ 3F31’ X’ 3F35’ X’ 3F33’ X’ 3F34’ X’ 3F36’ X’ 3F37’ X’ 3F38’ X’ 3F39’ X’ 3F3A’ X’ 3F3C’ X’ 3F40’ X’ 3F41’ P1DIR Disables to use P6DIR P[...]

Chapter 10 Appendices 151 Summary of Special Function Registers Bit Symbol Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X’ 3F52’ X’ 3F50’ X’ 3F51’ X’ 3F46’ X’ 3F47’ X’ 3F48’ X’ 3F4A’ X’ 3F4B’ X’ 3F4C’ X’ 3F53’ X’ 3F54’ X’ 3F55’ X’ 3F56’ X?[...]

Chapter 10 Appendices 152 Summary of Special Function Registers Bit Symbol Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0            Binary counter 5 TM5BC7 TM5BC6 TM5BC5 TM5BC4 TM5BC3 TM5BC2 TM5BC1 TM5BC0 TM4BCH6 Binary counter4 (Upper 8 bits） TM4BCH7 TM4BCH5 TM4BCH4 TM4BCH3 TM4BCH2 TM4BCH1 T[...]

Chapter 10 Appendices 153 Summary of Special Function Registers Bit Symbol Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address X’ 3FF2’ X’ 3FF1’ X’ 3FF0’ X’ 3FEF’ X’ 3FEE’ X’ 3FED’ X’ 3FEC’ X’ 3FEB’ X’ 3FEA’      IRQ3ICR Disables to use TM3ICR TM4ICR TM5ICR D[...]

Chapter 10 Appendices 154 Summary of Special Function Registers Bit Symbol Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address X’ 3FF2’ X’ 3FF1’ X’ 3FF0’ X’ 3FEF’ X’ 3FEE’ X’ 3FED’ X’ 3FEC’ X’ 3FEB’ X’ 3FEA’      IRQ3ICR Disables to use TM3ICR TM4ICR TM5ICR D[...]

MN101C115 / 117 LSI User's Manual August,1999 1st Edition 1st Printing Issued by Matsushita Electric Industrial Co., Ltd. Matsushita Electronics Corporation © Matsushita Electric Industrial Co., Ltd. © Matsushita Electronics Corporation[...]

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