Texas Instruments 28xxx manual

TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide Literature Number: SPRU791D November 2004 – Revised October 2007[...]

2 SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback[...]

Contents Preface ............................................................................................................................... 9 1 Introduction ............................................................................................................. 13 1.1 Introduction ..........................................................[...]

3.4 Controlling Multiple Buck Converters With Same Frequencies ............................................. 75 3.5 Controlling Multiple Half H-Bridge (HHB) Converters ........................................................ 78 3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ........................................... 80 3.7 Practi[...]

List of Figures 1-1 Multiple ePWM Modules ................................................................................................... 15 1-2 Submodules and Signal Connections for an ePWM Module ......................................................... 16 1-3 ePWM Submodules and Critical Internal Signal Interconnects ........................[...]

2-43 Event-Trigger SOCB Pulse Generator .................................................................................. 67 3-1 Simplified ePWM Module .................................................................................................. 70 3-2 EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave .........................[...]

List of Tables 1-1 ePWM Module Control and Status Register Set Grouped by Submodule .......................................... 18 2-1 Submodule Configuration Parameters ................................................................................... 20 2-2 Time-Base Submodule Registers ............................................................[...]

List of Tables 8 SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback[...]

Preface SPRU791D – November 2004 – Revised October 2007 Read This First This guide describes the Enhanced Pulse Width Modulator (ePWM) Module. It includes an overview of the module and information about each of the sub-modules: • Time-Base Module • Counter Compare Module • Action Qualifier Module • Dead-Band Generator Module • PWM Cho[...]

www.ti.com Related Documentation From Texas Instruments SPRU790— TMS320x28xx, 28xxx Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide describes the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine in high performance motion and p[...]

www.ti.com Related Documentation From Texas Instruments SPRA958— Running an Application from Internal Flash Memory on the TMS320F28xx DSP covers the requirements needed to properly configure application software for execution from on-chip flash memory. Requirements for both DSP/BIOS™ and non-DSP/BIOS projects are presented. Example code project[...]

Read This First 12 SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback[...]

Chapter 1 SPRU791D – November 2004 – Revised October 2007 Introduction The enhanced pulse width modulator (ePWM) peripheral is a key element in controlling many of the power-related systems found in both commercial and industrial equipments. These systems include digital motor control, switch mode power supply control, uninterruptible power sup[...]

www.ti.com 1.1 Introduction 1.2 Submodule Overview Introduction An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand and use. The ePWM unit described here addresses these requirements by alloca[...]

www.ti.com PIE TZ1 toTZ6 Peripheral Frame1 ePWM1module ePWM2module ePWMxmodule SYNCO SYNCI SYNCI SYNCO SYNCI SYNCO ADC GPIO MUX xSYNCI xSYNCO xSOC EPWMxA EPWMxB EPWM2A EPWM2B EPWM1A EPWM1B EPWM1INT EPWM1SOC EPWM2INT EPWM2SOC EPWMxINT EPWMxSOC T oeCAP1 Submodule Overview Figure 1-1. Multiple ePWM Modules The order in which the ePWM[...]

www.ti.com EPWMxINT EPWMxTZINT EPWMxSOCA EPWMxSOCB EPWMxSYNCI EPWMxSYNCO T ime-base (TB) module Counter-compare (CC) module Action-qualifier (AQ) module Dead-band (DB) module PWM-chopper (PC) module Event-trigger (ET) module T rip-zone (TZ) module Peripheral bus ePWM module TZ1 to TZ6 EPWMxA EPWMxB PIE ADC GPIO MUX Submodule Overview Figure 1-2. Su[...]

www.ti.com Action qualifier (AQ) T ime-base (TB) Dead band (DB) Counter compare (CC) T rip zone (TZ) Event trigger and interrupt (ET) PWM chopper (PC) TZ1 to TZ6 TBPRD shadow (16) TBPRD active (16) CTR = PRD CTR = ZERO CTR = CMP A CTR = CMPB CTR_Dir TBCTL[SWFSYNC] (software forced sync) TBPHS active (16) Counter UP/DWN (16 bit) TBCTR active (16) Sy[...]

www.ti.com Register Mapping Table 1-1. ePWM Module Control and Status Register Set Grouped by Submodule Size Name Offset (1) (x16) Shadow Description Time-Base Submodule Registers TBCTL 0x0000 1 No Time-Base Control Register TBSTS 0x0001 1 No Time-Base Status Register TBPHSHR 0x0002 1 No Extension for HRPWM Phase Register (2) TBPHS 0x0003 1 No Time[...]

Chapter 2 SPRU791D – November 2004 – Revised October 2007 ePWM Submodules Seven submodules are included in every ePWM peripheral. Each of these submodules performs specific tasks that can be configured by software. Topic .................................................................................................. Page 2.1 Overview ........[...]

www.ti.com 2.1 Overview Overview Table 2-1 lists the seven key submodules together with a list of their main configuration parameters. For example, if you need to adjust or control the duty cycle of a PWM waveform, then you should see the counter-compare submodule in Section 2.3 for relevant details. Table 2-1. Submodule Configuration Parameters Su[...]

www.ti.com Overview Table 2-1. Submodule Configuration Parameters (continued) Submodule Configuration Parameter or Option Event-trigger (ET) • Enable the ePWM events that will trigger an interrupt. • Enable ePWM events that will trigger an ADC start-of-conversion event. • Specify the rate at which events cause triggers (every occurrence or ev[...]

www.ti.com Overview Example 2-1. Constant Definitions Used in the Code Examples (continued) #define DB_ACTV_LO 0x3 // PCCTL (chopper control) / / ========================== // CHPEN bit #define CHP_ENABLE 0x0 #define CHP_DISABLE 0x1 // CHPFREQ bits #define CHP_DIV1 0x0 #define CHP_DIV2 0x1 #define CHP_DIV3 0x2 #define CHP_DIV4 0x3 #define CHP_DIV5 [...]

www.ti.com 2.2 Time-Base (TB) Submodule CTR = CMPB CTR = CMP A CTR_Dir CTR = 0 CTR = PRD Dead Band (DB) Counter Compare (CC) Action Qualifier (AQ) EPWMxA EPWMxB CTR = CMPB CTR = 0 EPWMxINT EPWMxSOCA EPWMxSOCB EPWMxA EPWMxB TZ1 to TZ6 CTR = CMP A T ime-Base (TB) CTR = PRD CTR = 0 CTR_Dir EPWMxSYNCI EPWMxSYNCO EPWMxTZINT PWM- chopper (PC) Event T rig[...]

www.ti.com 2.2.2 Controlling and Monitoring the Time-base Submodule TBCTL[SYNCOSEL] TBPRD PeriodActive TBPRD PeriodShadow 16 TBCTL[SWFSYNC] CTR=PRD TBPHS PhaseActiveReg Counter UP/DOWN 16 Sync Out Select EPWMxSYNCO Reset Load 16 TBCTL[PHSEN] CTR=Zero CTR=CMPB Disable X EPWMxSYNCI TBCTL[PRDLD] TBCTR[15:0] Mode TBCTL[CTR[...]

www.ti.com 2.2.3 Calculating PWM Period and Frequency Time-Base (TB) Submodule Table 2-3. Key Time-Base Signals Signal Description EPWMxSYNCI Time-base synchronization input. Input pulse used to synchronize the time-base counter with the counter of ePWM module earlier in the synchronization chain. An ePWM peripheral can be configured to use or igno[...]

www.ti.com PRD 4 4 4 PRD 4 1 2 3 0 1 2 3 0 1 2 3 0 Z 1 2 3 4 0 1 2 3 CTR_dir 1 2 3 4 0 1 2 3 0 Up Down Down Up T PWM = (TBPRD + 1) x T T BCLK For Up Count and Down Count For Up and Down Count F PWM = 1/ (T PWM) T PWM = 2 x TBPRD x T TBCLK F PWM = 1 / (T PWM) 1 2 3 4 0 1 2 3 4 0 1 2 3 0 T PWM Z T PWM T PWM T PWM 2.2.3.1 Time-Base Period Shadow Regis[...]

www.ti.com 2.2.3.2 Time-Base Counter Synchronization EPWM2SYNCI ePWM2 EPWM2SYNCO EPWM1SYNCO ePWM1 EPWM1SYNCI GPIO MUX EPWM3SYNCO ePWM3 EPWM3SYNCI ePWMx EPWMxSYNCI SYNCI eCAP1 EPWMxSYNCO Time-Base (TB) Submodule A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM module has a synchronization input (EPWMxSYNCI) [...]

www.ti.com EPWM1SYNCI ePWM1 EPWM1SYNCO GPIO MUX EPWM2SYNCI ePWM2 EPWM2SYNCO EPWM3SYNCI ePWM3 EPWM3SYNCO EPWM4SYNCI ePWM4 EPWM4SYNCO EPWM5SYNCI ePWM5 EPWM5SYNCO EPWM6SYNCI ePWM6 EPWM36YNCO EPWM7SYNCI ePWM7 EPWM7SYNCO EPWM9SYNCI ePWM9 EPWM9SYNCO EPWM10SYNCI ePWM10 EPWM10SYNCO EPWM1 1SYNCI ePWM1 1 EPWM1 1SYNCO EPWM13SYNCI ePWM13 EPWM13SYnCO EPWM14SYNC[...]

www.ti.com EPWM1SYNCO ePWM1 EPWM1SYNCI GPIO MUX SYNCI eCAP1 EPWM2SYNCI ePWM2 EPWM2SYNCO EPWM3SYNCO ePWM3 EPWM3SYNCI EPWM2SYNCI ePWM4 EPWM2SYNCO EPWM3SYNCO ePWM5 EPWM3SYNCI ePWM6 EPWMxSYNCI EPWMxSYNCO Time-Base (TB) Submodule Figure 2-6. Time-Base Counter Synchronization Scheme 3 Each ePWM module can be configured to use or ignore the synchronizatio[...]

www.ti.com 2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules 2.2.5 Time-base Counter Modes and Timing Waveforms 0000 EPWMxSYNCI TBCTR[15:0] CTR_dir CTR = zero CNT_max CTR = PRD 0xFFFF TBPHS (value) TBPRD (value) Time-Base (TB) Submodule The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM mo[...]

www.ti.com 0x000 0xFFFF TBCTR[15:0] TBPHS (value) TBPRD (value) EPWMxSYNCI CTR_dir CTR = zero CNT_max CTR = PRD 0x0000 0xFFFF TBCNT[15:0] UP DOWN UP DOWN UP DOWN UP TBPHS (value) TBPRD (value) EPWMxSYNCI CTR_dir CTR = zero CNT_max CTR = PRD Time-Base (TB) Submodule Figure 2-8. Time-Base Down-Count Mode Waveforms Figure 2-9. Time-Base Up-Down-Count [...]

www.ti.com 0x0000 0xFFFF TBCNT[15:0] UP DOWN UP DOWN UP DOWN TBPHS (value) TBPRD (value) EPWMxSYNCI CTR_dir CTR = zero CNT_max CTR = PRD 2.3 Counter-Compare (CC) Submodule CTR = CMPB CTR = CMP A CTR_Dir CTR = 0 CTR = PRD Dead Band (DB) Counter Compare (CC) Action Qualifier (AQ) EPWMxA EPWMxB CTR = CMPB CTR = 0 EPWMxINT EPWMxSOCA EPWMxSOCB EPWMxA EP[...]

www.ti.com 2.3.1 Purpose of the Counter-Compare Submodule 2.3.2 Controlling and Monitoring the Counter-Compare Submodule TBCTR[15:0] Time Base (TB) Module 16 CMP A[15:0] 16 16 16 CMP A CompareAActiveReg. CTR=CMP A CTR=CMPB Action Qualifier Module Digital comparatorB CMPB[15:0] TBCTR[15:0] CTR=PRD CTR=0 CMPCTL[L OADA[...]

www.ti.com 2.3.3 Operational Highlights for the Counter-Compare Submodule 2.3.4 Count Mode Timing Waveforms Counter-Compare (CC) Submodule The key signals associated with the counter-compare submodule are described in Table 2-5 . Table 2-5. Counter-Compare Submodule Key Signals Signal Description of Event Registers Compared CTR = CMPA Time-base cou[...]

www.ti.com 0x0000 0xFFFF CTR=CMP A TBCTR[15:0] CMP A (value) CMPB (value) TBPHS (value) TBPRD (value) CTR=CMPB EPWMxSYNCI TBCTR[15:0] 0x0000 0xFFFF CTR=CMP A CMP A (value) CMPB (value) TBPHS (value) TBPRD (value) CTR=CMPB EPWMxSYNCI Counter-Compare (CC) Submodule • Up-down-count mode: used to generate a symmetrical PWM wav[...]

www.ti.com 0x0000 0xFFFF TBCTR[15:0] CTR = CMP A CMP A (value) CMPB (value) TBPHS (value) TBPRD (value) CTR = CMPB EPWMxSYNCI 0x0000 0xFFFF TBCTR[15:0] CMP A (value) CMPB (value) TBPHS (value) TBPRD (value) CTR = CMP A CTR = CMPB EPWMxSYNCI Counter-Compare (CC) Submodule Figure 2-15. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] C[...]

www.ti.com 2.4 Action-Qualifier (AQ) Submodule CTR = CMPB CTR = CMP A CTR_Dir CTR = 0 CTR = PRD Dead Band (DB) Counter Compare (CC) Action Qualifier (AQ) EPWMxA EPWMxB CTR = CMPB CTR = 0 EPWMxINT EPWMxSOCA EPWMxSOCB EPWMxA EPWMxB TZ1 to TZ6 CTR = CMP A T ime-Base (TB) CTR = PRD CTR = 0 CTR_Dir EPWMxSYNCI EPWMxSYNCO EPWMxTZINT PWM- chopper (PC) Even[...]

www.ti.com Action-qualifier(AQ)Module AQCTL A[15:0] Action-qualifiercontrolA EPWMA EPWMB TBCLK CTR=PRD CTR=Zero CTR=CMP A CTR=CMPB CTR_dir AQCTLB[15:0] Action-qualifiercontrolB AQSFRC[15:0] Action-qualifierS/Wforce AQCSFRC[3:0](shadow) continuousS/Wforce AQCSFRC[3:0](active) continuousS[...]

www.ti.com Z Z Z CA CA CA Z T CB T P T CA T CB P CB CB P Do Nothing Clear Low Set High T oggle P Zero Comp A Comp B Period TB Counter equals: Actions S/W force SW SW SW SW T Action-Qualifier (AQ) Submodule Actions are specified independently for either output (EPWMxA or EPWMxB). Any or all events can be configured to generate actions on a given out[...]

www.ti.com 2.4.3 Action-Qualifier Event Priority Action-Qualifier (AQ) Submodule It is possible for the ePWM action qualifier to receive more than one event at the same time. In this case events are assigned a priority by the hardware. The general rule is events occurring later in time have a higher priority and software forced events always have t[...]

www.ti.com 2.4.4 Waveforms for Common Configurations Action-Qualifier (AQ) Submodule Table 2-11. Behavior if CMPA/CMPB is Greater than the Period Counter Mode Compare on Up-Count Event Compare on Down-Count Event CAU/CBU CAU/CBU Up-Count Mode If CMPA/CMPB ≤ TBPRD period, then the event Never occurs. occurs on a compare match (TBCTR=CMPA or CMPB).[...]

www.ti.com UP DOWN UP DOWN 2 0 3 4 1 2 3 1 2 0 3 4 1 2 0 3 1 TBCNTR TBCNTRDirection EPWMxA/EPWMxB Case2: CMP A =3,25%Duty Case3: CMP A =2,50%Duty Case3: CMP A =1,75%Duty Case4: CMP A =0,100%Duty Case1: CMP A =4,0%Duty EPWMxA/EPWMxB EPWMxA/EPWMxB EPWMxA/EPWMxB EPWMxA/EPWMxB Mode:Up[...]

www.ti.com TBCTR EPWMxA EPWMxB TBPRD value CA Z P CB Z P CB CA Z P Z P CA Z P CA Z P CB CB Action-Qualifier (AQ) Submodule Figure 2-21. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB—Active High A PWM period = (TBPRD + 1 ) × T TBCLK B Duty modulation for EPWMxA is set by CMPA, and is active high (that is, h[...]

www.ti.com TBCTR EPWMxA EPWMxB TBPRD value CB CA P P P P CB CA P P Action-Qualifier (AQ) Submodule Figure 2-22. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB—Active Low A PWM period = (TBPRD + 1 ) × T TBCLK B Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proport[...]

www.ti.com TBCTR EPWMxA EPWMxB TBPRD value Z T Z T Z T Action-Qualifier (AQ) Submodule Example 2-3. Code Sample for Figure 2-22 // Initialization Time / / ======================= = EPwm1Regs.TBPRD = 600; // Period = 601 TBCLK counts EPwm1Regs.CMPA.half.CMPA = 350; // Compare A = 350 TBCLK counts EPwm1Regs.CMPB = 200; // Compare B = 200 TBCLK counts[...]

www.ti.com Action-Qualifier (AQ) Submodule Example 2-4. Code Sample for Figure 2-23 // Initialization Time / / ======================= = EPwm1Regs.TBPRD = 600; // Period = 601 TBCLK counts EPwm1Regs.CMPA.half.CMPA = 200; // Compare A = 200 TBCLK counts EPwm1Regs.CMPB = 400; // Compare B = 400 TBCLK counts EPwm1Regs.TBPHS = 0; // Set Phase register [...]

www.ti.com TBCTR EPWMxA EPWMxB TBPRD value CA CA CA CA CB CB CB CB CB Action-Qualifier (AQ) Submodule Figure 2-24. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB — Active Low A PWM period = 2 x TBPRD × T TBCLK B Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty[...]

www.ti.com CA CA CA CA CB CB CB CB TBCTR EPWMxA EPWMxB TBPRD value Action-Qualifier (AQ) Submodule Figure 2-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB — Complementary A PWM period = 2 × TBPRD × T TBCLK B Duty modulation for EPWMxA is set by CMPA, and is active low, i.e., low time duty propo[...]

www.ti.com Z P Z P TBCTR EPWMxA EPWMxB CA CA CB CB Action-Qualifier (AQ) Submodule Figure 2-26. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active Low A PWM period = 2 × TBPRD × TBCLK B Rising edge and falling edge can be asymmetrically positioned within a PWM cycle. This allows for pulse placement techni[...]

www.ti.com 2.5 Dead-Band Generator (DB) Submodule CTR = CMPB CTR = CMP A CTR_Dir CTR = 0 CTR = PRD Dead Band (DB) Counter Compare (CC) Action Qualifier (AQ) EPWMxA EPWMxB CTR = CMPB CTR = 0 EPWMxINT EPWMxSOCA EPWMxSOCB EPWMxA EPWMxB TZ1 to TZ6 CTR = CMP A T ime-Base (TB) CTR = PRD CTR = 0 CTR_Dir EPWMxSYNCI EPWMxSYNCO EPWMxTZINT PWM- chopper (PC) E[...]

www.ti.com 2.5.3 Operational Highlights for the Dead-Band Submodule 0 1 S2 1 0 S1 RED Out In Risingedge delay (10-bit counter) (10-bit counter) delay Fallingedge In Out FED 1 0 S3 0 S0 1 EPWMxA EPWMxB DBCTL[POLSEL] DBCTL[OUT_MODE] S5 DBCTL[IN_MODE] 1 0 S4 0 1 EPWMxA in EPWMxBin Dead-Band Generator (DB) Submodule The following sections prov[...]

www.ti.com Dead-Band Generator (DB) Submodule action-qualifier submodule to generate the signal as shown for EPWMxA. • Mode 6: Bypass rising-edge-delay and Mode 7: Bypass falling-edge-delay Finally the last two entries in Table 2-13 show combinations where either the falling-edge-delay (FED) or rising-edge-delay (RED) blocks are bypassed. Table 2[...]

www.ti.com Original (outA) Rising Edge Delayed (RED) Falling Edge Delayed (FED) Active High Complementary (AHC) Active Low Complementary (ALC) Active High (AH) Active Low (AL) RED FED Period Dead-Band Generator (DB) Submodule Figure 2-29 shows waveforms for typical cases where 0% < duty < 100%. Figure 2-29. Dead-Band Waveforms for Typical Cas[...]

www.ti.com Dead-Band Generator (DB) Submodule The dead-band submodule supports independent values for rising-edge (RED) and falling-edge (FED) delays. The amount of delay is programmed using the DBRED and DBFED registers. These are 10-bit registers and their value represents the number of time-base clock, TBCLK, periods a signal edge is delayed by.[...]

www.ti.com 2.6 PWM-Chopper (PC) Submodule CTR = CMPB CTR = CMP A CTR_Dir CTR = 0 CTR = PRD Dead Band (DB) Counter Compare (CC) Action Qualifier (AQ) EPWMxB EPWMxA CTR = CMPB CTR = 0 EPWMxINT EPWMxSOCA EPWMxSOCB EPWMxA EPWMxB TZ1 to TZ6 CTR = CMP A T ime-Base (TB) CTR = PRD CTR = 0 CTR_Dir EPWMxSYNCI EPWMxSYNCO EPWMxTZINT PWM- chopper (PC) Event T r[...]

www.ti.com Start Clk One shot Pulse-width PCCTL [OSHTWTH] PWMA_ch Bypass Dividerand dutycontrol PSCLK OSHT EPWMxA PCCTL [CHPEN] EPWMxA /8 SYSCLKOUT Pulse-width Start shot Clk One PCCTL [OSHTWTH] 1 OSHT PCCTL[CHPFREQ] PCCTL[CHPDUTY] PWMB_ch Bypass EPWMxA EPWMxB 1 0 0 2.6.4 Waveforms PSCLK EPWMxA EPWMxB EPWMxA EPWMxA PWM-Chopper (PC) Submodule [...]

www.ti.com 2.6.4.1 One-Shot Pulse PSCLK OSHT EPWMxA in EPWMxA out Prog. pulse width (OSHTWTH) Start OSHT pulse Sustaining pulses PWM-Chopper (PC) Submodule The width of the first pulse can be programmed to any of 16 possible pulse width values. The width or period of the first pulse is given by: T 1stpulse = T SYSCLKOUT × 8 × OSHTWTH Where T SYSC[...]

www.ti.com 2.6.4.2 Duty Cycle Control Duty 1/8 Duty 2/8 Duty 3/8 Duty 4/8 Duty 5/8 Duty 6/8 Duty 7/8 PSCLK 12.5% 25% 37.5% 50% 62.5% 75% 87.5% PSCLK Period PSCLK period PWM-Chopper (PC) Submodule Pulse transformer-based gate drive designs need to comprehend the magnetic properties or characteristics of the transformer and associated circuitry. Satu[...]

www.ti.com 2.7 Trip-Zone (TZ) Submodule CTR = CMPB CTR = CMP A CTR_Dir CTR = 0 CTR = PRD Dead Band (DB) Counter Compare (CC) Action Qualifier (AQ) EPWMxA EPWMxB CTR = CMPB CTR = 0 EPWMxINT EPWMxSOCA EPWMxSOCB EPWMxA EPWMxB TZ1 to TZ6 CTR = CMP A T ime-Base (TB) CTR = PRD CTR = 0 CTR_Dir EPWMxSYNCI EPWMxSYNCO EPWMxTZINT PWM- chopper (PC) Event T rig[...]

www.ti.com 2.7.2 Controlling and Monitoring the Trip-Zone Submodule 2.7.3 Operational Highlights for the Trip-Zone Submodule Trip-Zone (TZ) Submodule The trip-zone submodule operation is controlled and monitored through the following registers: Table 2-17. Trip-Zone Submodule Registers Register Name Address offset Shadowed Description (1) TZSEL 0x0[...]

www.ti.com Trip-Zone (TZ) Submodule Table 2-18. Possible Actions On a Trip Event TZCTL[TZA] EPWMxA Comment and/or and/or TZCTL[TZB] EPWMxB 0,0 High-Impedance Tripped 0,1 Force to High State Tripped 1,0 Force to Low State Tripped 1,1 No Change Do Nothing. No change is made to the output. Example 2-8. Trip-Zone Configurations Scenario A: A one-shot t[...]

www.ti.com 2.7.4 Generating Trip Event Interrupts Latch cyc−by-cyc mode (CBC) CTR=zero TZFRC[CBC] TZ1 TZ2 TZ3 TZ4 TZ5 TZ6 Sync Clear Set Set one-shot Latch (OSHT) mode Clear TZSEL[CBC1toCBC6] TZCLR[OST] TZSEL[OSHT1toOSHT6] TZFRC[OSHT] Sync TZ6 TZ5 TZ4 TZ3 TZ2 TZ1 Trip logic Trip Trip CBC tripevent OSHT tripevent EPWMxA EPWMxB EP[...]

www.ti.com Generate interrupt pulsewhen input=1 Clear Set TZCLR[INT] EPWMx_TZINT (PIE) Latch Clear Set Clear Set Latch Latch TZFLG[CBC] TZFLG[OST] TZEINT[CBC] TZCLR[CBC] CBC tripevent TZEINT[OST] OSHT tripevent TZCLR[OST] TZFLG[INT] 2.8 Event-Trigger (ET) Submodule CTR=CMPB CTR=CMP A CTR_Dir CTR=0 CTR=PRD Dead Ba[...]

www.ti.com 2.8.1 Operational Overview of the Event-Trigger Submodule EPWM1INT EPWM1SOCA EPWM1SOCB EPWM1 module EPWM2SOCB EPWM2SOCA EPWM2INT EPWM2 module EPWMxSOCB EPWMxSOCA EPWMxINT EPWMx module PIE SOCB SOCA ADC Event-Trigger (ET) Submodule The following sections describe the event-trigger submodule's operational highlights. Each ePWM module [...]

www.ti.com PIE Event T rigger Module Logic CTR=Zero CTR=PRD CTR=CMP A EPWMxINTn CTR=CMPB CTR_dir Direction qualifier CTRU=CMP A ETSEL reg EPWMxSOCA /n /n /n EPWMxSOCB ADC clear count count clear count clear CTRD=CMP A CTRU=CMPB CTRD=CMPB ETPS reg ETFLG reg ETCLR reg ETFRC reg Event-Trigger (ET) Submodule Figure 2-40. Event-Trigger Submodule Showing[...]

www.ti.com Latch Generate interrupt pulse when input = 1 2-bit Counter Set Clear 1 0 0 Clear CNT Inc CNT ETPS[INTCNT] ETPS[INTPRD] ETCLR[INT] EPWMxIN T ETFRC[INT] ETSEL[INT] ETFLG[INT] ETSEL[INTSEL] 000 001 010 01 1 100 101 1 1 1 101 0 0 CTRU=CMP A CTRD=CMP A CTRU=CMPB CTRD=CMPB CTR=Zero CTR=PRD Event-Trigger (ET) Submodule The number of events tha[...]

www.ti.com Latch Generate SOC pulse when input=1 2-bit Counter Set Clear ClearCNT IncCNT ETPS[SOCACNT] ETPS[SOCAPRD] ETCLR[SOCA] SOCA ETFRC[SOCA] ETSEL[SOCAEN] ETFLG[SOCA] ETSEL[SOCASEL] 000 001 010 01 1 100 101 1 1 1 101 0 0 CTRU=CMP A CTRD=CMP A CTRU=CMPB CTRD=CMPB CTR=Zero CTR=PRD Latch Generate SOC pulse when input=1 2-bit [...]

ePWM Submodules 68 SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback[...]

Chapter 3 SPRU791D – November 2004 – Revised October 2007 Applications to Power Topologies An ePWM module has all the local resources necessary to operate completely as a standalone module or to operate in synchronization with other identical ePWM modules. Topic ...................................................................................[...]

www.ti.com 3.1 Overview of Multiple Modules CTR = 0 CTR=CMPB X EN SyncOut Phase reg EPWMxA EPWMxB SyncIn Φ =0 ° 3.2 Key Configuration Capabilities Overview of Multiple Modules Previously in this user's guide, all discussions have described the operation of a single module. To facilitate the understanding of multiple modules working together [...]

www.ti.com CTR=0 CTR=CMPB X EN SyncOut Phase reg Ext SyncIn (optional) EPWM1A EPWM1B SyncOut Phase reg CTR=CMPB CTR=0 X EN EPWM2B EPWM2A Slave Master SyncIn SyncIn 1 2 Φ =0 ° Φ =0 ° 3.3 Controlling Multiple Buck Converters With Independent Frequencies Controlling Multiple Buck Converters With Independent Frequencies Figure 3-2. EPWM1 Configured[...]

www.ti.com CTR=zero CTR=CMPB X En SyncOut Phase reg Ext SyncIn (optional) EPWM1A EPWM1B SyncOut Phase reg CTR=CMPB CTR=zero X En EPWM2B EPWM2A Master2 Master1 SyncIn CTR=zero CTR=CMPB SyncOut X EPWM3B Phase reg Master3 En EPWM3A 1 2 3 Φ =X Φ =X Φ =X CTR=zero CTR=CMPB SyncOut X EPWM4B Phase reg Master4 En EPWM4A 3 Φ =X Buck #1 V out1 Vin1 EPWM1A[...]

www.ti.com P CA CB A P CA P Pulse center EPWM1A 700 950 1200 P CA CB A P CA 700 1 150 1400 EPWM2A CA P CA CB A P CA P 500 650 800 EPWM3A P Indicates this event triggers an interrupt CB A I P I P I P I Indicates this event triggers an ADC start of conversion Controlling Multiple Buck Converters With Independent Frequencies Figure 3-4. Buck Waveforms[...]

www.ti.com Controlling Multiple Buck Converters With Independent Frequencies Example 3-1. Configuration for Example in Figure 3-4 //===================================================================== // (Note: code for only 3 modules shown) // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 1200; // Period[...]

www.ti.com 3.4 Controlling Multiple Buck Converters With Same Frequencies CTR=zero CTR=CMPB X En Φ =0 ° SyncOut Phase reg Ext SyncIn (optional) EPWM1A EPWM1B SyncOut Phase reg CTR=CMPB CTR=zero X Φ =X En EPWM2B EPWM2A Slave Master Buck #1 V out1 Vin1 EPWM1A Buck #2 Vin2 EPWM1B V out2 Buck #4 Buck #3 Vin3 EPWM2B Vin4 EPWM2A V out3 V out4 SyncIn S[...]

www.ti.com 200 400 600 400 200 300 500 300 500 EPWM1A EPWM1B EPWM2B EPWM2A Z I A P CA CA Z I Z I A P CA CA CB CB CB CB CA CA CA CA CB CB CB CB Controlling Multiple Buck Converters With Same Frequencies Figure 3-6. Buck Waveforms for Figure 3-5 (Note: F PWM2 = F PWM1) ) 76 Applications to Power Topologies SPRU791D – November 2004 – Revised Octob[...]

www.ti.com Controlling Multiple Buck Converters With Same Frequencies Example 3-2. Code Snippet for Configuration in Figure 3-5 //===================================================================== // Config //===================================================================== // Initialization Time //======================== // EPWM Module 1 c[...]

www.ti.com 3.5 Controlling Multiple Half H-Bridge (HHB) Converters CTR=zero CTR=CMPB X En SyncOut Phase reg Ext SyncIn (optional) EPWM1A EPWM1B SyncOut Phase reg CTR=CMPB CTR=zero X En EPWM2B EPWM2A Slave Master V o ut1 EPWM1A SyncIn SyncIn V DC_b us EPWM1B EPWM2B EPWM2A V DC_b us V o ut2 Φ =0 ° Φ =0 ° Controlling Multiple Half H-Bridge (HHB) C[...]

www.ti.com EPWM1A EPWM1B EPWM2A EPWM2B 600 200 400 400 200 250 500 500 250 Pulse Center A CB CA Z Z I Z I Z I Z I A CB CA Z Z A CB CA Pulse Center Z A CB CA A CB CA Z A CB CA Z A CB Z CA A CB Z CA Controlling Multiple Half H-Bridge (HHB) Converters Figure 3-8. Half-H Bridge Waveforms for Figure 3-7 (Note: Here F PWM2 = F PWM1 ) SPRU791D – Novembe[...]

www.ti.com 3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) Example 3-3. Code Snippet for Configuration in Figure 3-7 //===================================================================== // Config //===================================================================== /[...]

www.ti.com Φ =0 ° CTR=zero CTR=CMPB X En SyncOut Phase reg Ext SyncIn (optional) EPWM1A EPWM1B SyncOut Phase reg CTR=CMPB CTR=zero X En EPWM2B EPWM2A Slave Master EPWM1A EPWM1B EPWM2A EPWM2B EPWM3B EPWM3A V AB VCD VEF 3 phase motor EPWM4B EPWM5B V AB EPWM4A VCD EPWM5A EPWM6B 3 phase motor VEF EPWM6A 3 phase inverter #1 3 phase inverter #2 1 2 CTR[...]

www.ti.com RED FED FED FED RED RED RED FED EPWM1A EPWM1B EPWM2A EPWM2B EPWM3A EPWM3B Φ 2=0 Φ 3=0 800 500 500 600 600 700 700 Z I A P CA CA Z I A P CA CA CA CA CA CA CA CA CA CA Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) Figure 3-10. 3-Phase Inverter Waveforms for Figure 3-9 (Only One Inverter Shown) 82 Applications to Power Topo[...]

www.ti.com Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) Example 3-4. Code Snippet for Configuration in Figure 3-9 //===================================================================== // Configuration //===================================================================== // Initialization Time //========================// EPWM Mo[...]

www.ti.com 3.7 Practical Applications Using Phase Control Between PWM Modules CTR=zero CTR=CMPB X En SyncOut Phase reg Ext SyncIn (optional) EPWM1A EPWM1B SyncOut Phase reg CTR=CMPB CTR=zero X En EPWM2B EPWM2A Slave Master SyncIn SyncIn 1 2 Φ =0 ° Φ =120 ° Practical Applications Using Phase Control Between PWM Modules So far, none of the exampl[...]

www.ti.com 0000 FFFFh TBPRD TBCTR[0-15] time CTR = PRD (SycnOut) Master Module Φ 2 Phase = 120 ° 0000 FFFFh TBPRD TBCTR[0-15] time SyncIn Slave Module TBPHS 600 600 600 600 200 200 3.8 Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter Figure 3-12. Timing Waveforms Associated With Phase Control Bet[...]

www.ti.com CTR=zero CTR=CMPB X En SyncOut Phase reg Ext SyncIn (optional) EPWM1A EPWM1B SyncOut Phase reg CTR=CMPB CTR=zero X En EPWM2B EPWM2A Slave Master EPWM1A SyncIn SyncIn EPWM1B CTR=zero CTR=CMPB SyncOut X EPWM3B Phase reg Slave En SyncIn EPWM3A 1 2 3 V IN EPWM2B EPWM2A EPWM3A EPWM3B V OUT Φ =0 ° Φ =120 ° Φ =120 ° Φ =240 ° Controlling[...]

www.ti.com 285 450 285 EPWM1A EPWM1B RED RED RED FED FED FED 300 TBPHS (=300) 300 EPWM2A EPWM2B TBPHS (=300) EPWM3A EPWM3B Φ 2=120 ° Φ 2=120 ° Z I Z I Z I Z I Z I A P CA CA A P CA CA A P CA CA Controlling a 3-Phase Interleaved DC/DC Converter Figure 3-14. 3-Phase Interleaved DC/DC Converter Waveforms for Figure 3-13 SPRU791D – November 2004 ?[...]

www.ti.com Controlling a 3-Phase Interleaved DC/DC Converter Example 3-5. Code Snippet for Configuration in Figure 3-13 //===================================================================== // Config // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 450; // Period = 900 TBCLK counts EPwm1Regs.TBPHS = 0; /[...]

www.ti.com 3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter CTR=zero CTR=CMPB X En SyncOut Phase reg Ext SyncIn (optional) EPWM1A EPWM1B SyncOut Phase reg CTR=CMPB CTR=zero X En EPWM2B EPWM2A Slave Master V out EPWM1A SyncIn SyncIn V DC_b us EPWM1B EPWM2A EPWM2B Φ =0 ° Φ =V ar ° V ar = V ariable Controlling Zero Voltage Switc[...]

www.ti.com Power phase EPWM1A EPWM1B RED 300 Φ 2=variable TBPHS =(1200− Φ 2) RED EPWM2A EPWM2B Power phase FED 200 600 1200 FED ZVS transition ZVS transition Z CA Z I Z I Z I Z CB A CA CB A Z Z CB A CA Z Z CB A CA Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter Figure 3-16. ZVS Full-H Bridge Waveforms 90 Applications to Power To[...]

www.ti.com Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter Example 3-6. Code Snippet for Configuration in Figure 3-15 //===================================================================== // Config //===================================================================== // Initialization Time //======================== // EPWM Modu[...]

Applications to Power Topologies 92 SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback[...]

Chapter 4 SPRU791D – November 2004 – Revised October 2007 Registers This chapter includes the register layouts and bit description for the submodules. Topic .................................................................................................. Page 4.1 Time-Base Submodule Registers ................................................ 94[...]

www.ti.com 4.1 Time-Base Submodule Registers Time-Base Submodule Registers Figure 4-1 through Figure 4-5 and Table 4-1 through Table 4-5 provide the time-base register definitions. Figure 4-1. Time-Base Period Register (TBPRD) 15 0 TBPRD R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-1. Time-Base Period Register (TBPR[...]

www.ti.com Time-Base Submodule Registers Figure 4-4. Time-Base Control Register (TBCTL) 15 14 13 12 10 9 8 FREE, SOFT PHSDIR CLKDIV HSPCLKDIV R/W-0 R/W-0 R/W-0 R/W-0,0,1 76543210 HSPCLKDIV SWFSYNC SYNCOSEL PRDLD PHSEN CTRMODE R/W-0,0,1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-11 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-4. Time-Bas[...]

www.ti.com Time-Base Submodule Registers Table 4-4. Time-Base Control Register (TBCTL) Field Descriptions (continued) Bit Field Value Description 6 SWFSYNC Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0. 1 Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the [...]

www.ti.com 4.2 Counter-Compare Submodule Registers Counter-Compare Submodule Registers Figure 4-5. Time-Base Status Register (TBSTS) 15 8 Reserved R-0 7 3210 Reserved CTRMAX SYNCI CTRDIR R-0 R/W1C-0 R/W1C-0 R-1 LEGEND: R/W = Read/Write; R = Read only; R/W1C = Read/Write 1 to clear; -n = value after reset Table 4-5. Time-Base Status Register (TBSTS)[...]

www.ti.com Counter-Compare Submodule Registers Table 4-6. Counter-Compare A Register (CMPA) Field Descriptions Bits Name Description 15-0 CMPA The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a "time-base counter equal to counter com[...]

www.ti.com 4.3 Action-Qualifier Submodule Registers Action-Qualifier Submodule Registers Figure 4-8. Counter-Compare Control Register (CMPCTL) 15 10 9 8 Reserved SHDWBFULL SHDWAFULL R-0 R-0 R-0 76543210 Reserved SHDWBMODE Reserved SHDWAMODE LOADBMODE LOADAMODE R-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after[...]

www.ti.com Action-Qualifier Submodule Registers Figure 4-9. Action-Qualifier Output A Control Register (AQCTLA) 15 12 11 10 9 8 Reserved CBD CBU R-0 R/W-0 R/W-0 76543210 CAD CAU PRD ZRO R/W-0 R/W-0 R/W-0 RW-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-9. Action-Qualifier Output A Control Register (AQCTLA) Field Descript[...]

www.ti.com Action-Qualifier Submodule Registers Figure 4-10. Action-Qualifier Output B Control Register (AQCTLB) 15 12 11 10 9 8 Reserved CBD CBU R-0 R/W-0 R/W-0 76543210 CAD CAU PRD ZRO R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-10. Action-Qualifier Output B Control Register (AQCTLB) Field Descr[...]

www.ti.com Action-Qualifier Submodule Registers Figure 4-11. Action-Qualifier Software Force Register (AQSFRC) 15 8 Reserved R-0 76543210 RLDCSF OTSFB ACTSFB OTSFA ACTSFA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-11. Action-Qualifier Software Force Register (AQSFRC) Field Descriptions Bit [...]

www.ti.com 4.4 Dead-Band Submodule Registers Dead-Band Submodule Registers Table 4-12. Action-qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions Bits Name Value Description 15-4 Reserved Reserved 3-2 CSFB Continuous Software Force on Output B In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow[...]

www.ti.com Dead-Band Submodule Registers Table 4-13. Dead-Band Generator Control Register (DBCTL) Field Descriptions Bits Name Value Description 15-6 Reserved Reserved 5-4 IN_MODE Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 2-28 . This allows you to select the input source to the fallin[...]

www.ti.com 4.5 PWM-Chopper Submodule Control Register PWM-Chopper Submodule Control Register Figure 4-14. Dead-Band Generator Rising Edge Delay Register (DBRED) 15 10 9 8 Reserved DEL R-0 R/W-0 7 0 DEL R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-14. Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descr[...]

www.ti.com 4.6 Trip-Zone Submodule Control and Status Registers Trip-Zone Submodule Control and Status Registers Table 4-16. PWM-Chopper Control Register (PCCTL) Bit Descriptions (continued) Bits Name Value Description 10-8 CHPDUTY Chopping Clock Duty Cycle 000 Duty = 1/8 (12.5%) 001 Duty = 2/8 (25.0%) 010 Duty = 3/8 (37.5%) 011 Duty = 4/8 (50.0%) [...]

www.ti.com Trip-Zone Submodule Control and Status Registers Figure 4-17. Trip-Zone Select Register (TZSEL) 15 14 13 12 11 10 9 8 Reserved OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 76543210 Reserved CBC6 CBC5 CBC4 CBC3 CBC2 CBC1 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = va[...]

www.ti.com Trip-Zone Submodule Control and Status Registers Table 4-17. Trip-Zone Submodule Select Register (TZSEL) Field Descriptions (continued) Bits Name Value Description 1 CBC2 Trip-zone 2 ( TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module 0 CBC1 Trip-zone 1 ( TZ1) Selec[...]

www.ti.com Trip-Zone Submodule Control and Status Registers Table 4-19. Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions (continued) Bits Name Value Description 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT PIE interrupt. (1) 1 CBC Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle inte[...]

www.ti.com 4.7 Event-Trigger Submodule Registers Event-Trigger Submodule Registers Figure 4-21. Trip-Zone Clear Register (TZCLR) 15 8 Reserved R-0 7 3210 Reserved OST CBC INT R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-21. Trip-Zone Clear Register (TZCLR) Field Descriptions Bits Name Value Descripti[...]

www.ti.com Event-Trigger Submodule Registers Figure 4-23. Event-Trigger Selection Register (ETSEL) 15 14 12 11 10 8 SOCBEN SOCBSEL SOCAEN SOCASEL R/W-0 R/W-0 R/W-0 R/W-0 7 4 3 2 0 Reserved INTEN INTSEL R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-23. Event-Trigger Selection Register (ETSEL) Field Descripti[...]

www.ti.com Event-Trigger Submodule Registers Table 4-23. Event-Trigger Selection Register (ETSEL) Field Descriptions (continued) Bits Name Value Description 2-0 INTSEL ePWM Interrupt (EPWMx_INT) Selection Options 000 Reserved 001 Enable event time-base counter equal to zero. (TBCTR = 0x0000) 010 Enable event time-base counter equal to period (TBCTR[...]

www.ti.com Event-Trigger Submodule Registers Table 4-24. Event-Trigger Prescale Register (ETPS) Field Descriptions (continued) Bits Name Description 9-8 SOCAPRD ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be gener[...]

www.ti.com Event-Trigger Submodule Registers Table 4-25. Event-Trigger Flag Register (ETFLG) Field Descriptions Bits Name Value Description 15-4 Reserved Reserved 3 SOCB Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB. The [...]

www.ti.com 4.8 Proper Interrupt Initialization Procedure Proper Interrupt Initialization Procedure When the ePWM peripheral clock is enabled it may be possible that interrupt flags may be set due to spurious events due to the ePWM registers not being properly initialized. The proper procedure for initializing the ePWM peripheral is as follows: 1. D[...]

Registers 116 SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback[...]

Appendix A SPRU791D – November 2004 – Revised October 2007 Revision History This document was revised to SPRU791D from SPRU791C. The scope of the revision was limited to technical changes as shown in Table A-1 . Table A-1. Changes for Revision D Location Modifications, Additions, and Deletions Figure 2-12 Modified the Detailed View of the Count[...]

www.ti.com Appendix A Table A-1. Changes for Revision D (continued) Location Modifications, Additions, and Deletions Table 4-13 Modified the "10" description of the Dead-Band Generator Control Register OUT_MODE field. Table 4-14 Modified the bit numbers of the Dead-Band Generator Rising Edge Delay Register Reserved field Table 4-15 Modifi[...]

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