Texas Instruments PCI445X manual

                                August 2000 PCI Bus Solutions Implementation Guide SCPU007[...]

IMPORT ANT NOTICE T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify , before placing orders, that information being relied on is current and complete. All product[...]

Notational Conventions iii Preface Read This First About This Manual This manual is intended to assist the designer who is attempting to implement a solution using the PCI4450 or PCI4451. Much, but not all, of the information contained herein can also be found elsewhere. However , the smaller size of this manual, as well as its organization by topi[...]

Contents iv enter from items that the system displays (such as prompts, command output, error messages, etc.). Here is a sample program listing: 0011 0005 0001 .field 1, 2 0012 0005 0003 .field 3, 4 0013 0005 0006 .field 6, 3 0014 0006 .even Here is an example of a system prompt and a command that you might enter: C: csr –a /user/ti/simuboard/uti[...]

T rademarks v This syntax shows that .byte must have at least one value parameter , but you have the option of supplying additional value parameters, separated by commas. Related Documentation From T exas Instruments PCI4450 GFN/GJG PC Card and OHCI Controller Data Sheet , SCPS046 PCI4451 GFN/GJG PC Card and OHCI Controller Data Manual , SCPS054 OH[...]

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Contents vii Contents 1 PCI445X Device 1–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 System Features Selection 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Package T ypes 1-3 . . . . . . . . [...]

Contents viii A Global Reset Only Bits, PME Context Bits A-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1 Global Reset Only Bits/PME Context Bits A-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B PME and RI Behavior B-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

Contents ix Figures 1–1 T ypical System Architecture 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Serialized Interrupt Signal 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 EEPROM 2-Wire Interface 1-10 . . . [...]

Contents x T ables 1–1 Registers and Bits Loadable Through Serial EEPROM 1-1 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 PC Card Interface Pullup Register List 1-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 PCI Bus Interface Pullup Register List 1-17 . . . . . . . . . . . . . . .[...]

1-1 PCI445X Device This implementation guide assists platform hardware developers designing with the PCI445X dual socket PC card and 1394 open host controller interface (OHCI) link layer controller (LLC). The PCI445X designation refers to any device in the PCI445X family , for example, the PCI4450 or PCI4451 device. The document includes an overvie[...]

1-2 Figure 1–1 illustrates a platform using the PCI445X device along with the TSB41L V03 3-port PHY , which provides the necessary interface to implement a 3-port IEEE1394 node. Figure 1–1. T ypical System Architecture TSB41L V03A PHY CPU Memory North Bridge PCI Bus Graphics Controller South Bridge Sound Controller Power Switch PC Card Socket P[...]

System Features Selection 1-3 PCI445X Device 1.1 System Features Selection This section explains selectable system features. Feature selection is required for GPIO and MFUNC terminal assignments and PCI445X register initialization. Detailed system implementation methods are described in the following sections. All functions cannot necessarily be us[...]

System Features Selection 1-4 automatically assigned on the dedicated SDA and SCL terminals. A pullup resistor (typically 10 k Ω) must be added on SDA and SCL when using an EEPROM. The value of the pullup resistor can vary for dif ferent EEPROMs. Refer to the EEPROM data sheet or contact the manufacturer for the recommended pullup resistor value.[...]

System Features Selection 1-5 PCI445X Device 1.1.10 Socket Activity LEDs Socket activity signals can be assigned on MFUNC4 (slot 1), MFUNC3 (slot 2), MFUNC5 (OHCI_LED), MFUNC6 (OHCI_LED), and MFUNC7 (OHCI_LED). 1.1.1 1 MFUNC7–MFUNC0 T erminal Assignments After selecting required functions for the system, multifunction terminals MFUNC7–MFUNC0 ar[...]

System Features Selection 1-6 1.1.12.3 Asynchronous CSC Interrupt Generation The ASYNC_CSC bit (diagnostic register , PCI offset 93h, bit 0) controls the CSC interrupt signaling method. If this bit is set to 0, then CSC is generated synchronously to PCLK (recommended). By default this bit is set to 1, which is the asynchronous mode. 1.1.12.4 CardBu[...]

System Features Selection 1-7 PCI445X Device CCLK can be slowed down rather than stopped by CCLKRUN . If CCLKRUN is set, the CLKCTRLEN (CardBus socket 20h, bit 16) and CLKCTR (CardBus socket 20h, bit 0) bits are both set to 1. The clock is slowed down to 1/16. In this mode the PCI clock is not allowed to stop. 1.1.12.9 SMI A PC card power change ev[...]

System Implementation 1-8 1.2 System Implementation This section describes signal connection for each interface, PCI bus, PC card interface, I 2 C interface, P 2 C interface, ZV interface, interrupt interface (parallel and serial), miscellaneous signals, and the PHY -Link interface. It also explains pullup/pulldown resistor requirements. 1.2.1 Clam[...]

System Implementation 1-9 PCI445X Device IDSEL, there is no alternative. If another AD line is to be used for IDSEL, then the system designer must leave the pullup off LA TCH and use MFUNC7 to route IDSEL. Also, if AD23 is used, then the resistive coupling should not be used. Refer to the Implementation Note: System Generation of IDSEL in the PCI L[...]

System Implementation 1-10 1.2.3 PC Card Interface The PC Card interface has two modes: the 16-bit interface mode and the CardBus 32-bit interface mode.  Damping resistor on CCLK terminal A series-damping resistor is recommended on the CCLK signal. The damping resistor is system dependent. If line impedance is in the 60 – 90- Ω range, a 47- [...]

System Implementation 1-1 1 PCI445X Device T able 1–1. Registers and Bits Loadable Through Serial EEPROM Register Offset Register Bits Loaded From EEPROM The following are configuration registers for the OHCI function (function 2) PCI register (2Ch) PCI subsystem ID 15–0 PCI register (2Dh) PCI vendor ID 15–0 PCI register (3Eh) PCI maximum lat[...]

System Implementation 1-12 1.3 Sample PCI445X EEPROM Data File Following is an example EEPROM data file used with the PCI445X device: ;PCI4450 default EEPROM Data File ;Register 0xXX Binary Description ;–––––––– –––– –––––– ––––––––––– 00 0x43 ;01000011 PCI max_lat (lower 4 bits)/PCI min gnt[...]

System Implementation 1-13 PCI445X Device 1D 0xFF ;11111111 1E 0xFF ;11111111 1F 0xFF ;11111111 20 0x00 ;00000000 Flag Byte (if 0xFF do not load Function 0 and 1) 21 0x12 ;00010010 SubSys Byte 3 ** Insert your SSVID MSB 22 0x34 ;00110100 SubSys Byte 2 ** Insert your SSVID LSB 23 0x56 ;01010110 SubSys Byte 1 ** Insert your SSID MSB 24 0x78 ;01111000[...]

System Implementation 1-14 1.3.1 P 2 C Interface for TPS22X6 Power Switch The interface between the PCI445X device and TPS22X6 power switch is serialized to reduce the number of signal lines. The P 2 C interface requires only three lines to control the switch. As a PCI445X default, the CLOCK signal is selected from an external source. It is usually[...]

System Implementation 1-15 PCI445X Device If the third ZV source is not implemented, ZVPCLK and ZVST A T are not required. T o support ZV audio, an audio codec device is required for L and R sound decoding. 1.3.3 Interrupt Signaling Interface  Serialized Interrupt Interface The serialized interrupt (ISA and PCI) interface is a single-line interf[...]

System Implementation 1-16 Figure 1–6. Distributed DMA Signal Connection PCGNT PCREQ PCI445X South Bridge (ex., PIIX4) 1.3.5 Requirement of Pullup/Pulldown Resistors Note: The PCI445X device has integrated pullup resistors and does not require external pullups. T able 1–2. PC Card Interface Pullup Resistor List † ‡ T erminal Name (16-bit Me[...]

System Implementation 1-17 PCI445X Device T able 1–3. PCI Bus Interface Pullup Resistor List PCI Signal Pull-Up V oltage FRAME V CCP TRDY V CCP IRDY V CCP DEVSEL V CCP STOP V CCP SERR V CCP PERR V CCP LOCK V CCP INT A INTB INTC V CCP CLKRUN V CCP PRST V CCP G_RST V CCP PME System dependent The pullup/pulldown on MFUNC depends on how it is impleme[...]

System Implementation 1-18 T able 1–5. Required Pullup/Pulldown Resistors Signal Resistor Recommended V alue ( Ω ) Condition LPS Pulldown (Default) 1.0 k Required Note: All pullup/pulldown resistor value recommendations are provided as guidelines only . The best value for an individual design varies depending upon board characteristics, standar[...]

System Implementation 1-19 PCI445X Device 1.4 BIOS Considerations 1.4.1 Initialization This section explains which registers require initialization, but does not discuss detailed information about the registers themselves. Refer to the corresponding specifications. Reference white paper: http://www .microsoft.com/hwdev/busbios/cardbus1.htm 1.4.1.1 [...]

System Implementation 1-20 against unexpected overwriting. The values are system and vendor dependent.  PC Card 16-bit I/F legacy mode base address register (PCI offset 44h: 32-bit) Set to 0000 03E1h (16-bit mode) and set to 0000 0001 (CardBus mode) in response to a disable call.  Power management capabilities register (PCI offset A2h: 16-bit[...]

System Implementation 1-21 PCI445X Device 2) Register save/restore Register content is not preserved in the sleeping state (it depends on the system implementation). Therefore, BIOS should restore the register content. Under Windows98, most of the register content is saved and restored by the pci.vxd and cbss.vxd. 3) T roubleshooting tips for sleep[...]

Important Information 1-22 1.5 Important Information This section clarifies important system implementation. 1.5.1 G_RST Clamping Rail G_RST is clamped to V CCP , so removing V CCP causes assertion of G_RST . Figure 1–7. G_RST and V CCP Relationship V CCP G_RST V CCP = 0 V CCP removed G_RST All other signals with clamping rails behave the same wa[...]

Global Reset Only Bits/PME Context Bits A-1 Global Reset Only Bits, PME Context Bits Global Reset Only Bits, PME Context Bits T opic Page A.1 Global Reset Only Bits/PME Context Bits A-2 Appendix A[...]

Global Reset Only Bits/PME Context Bits A-2 A.1 Global Reset Only Bits/PME Context Bits T able A–1. Global Reset Only Cleared Bits Register Name Space Offset Bit Subsystem IDs PCI 40h 31–0 PC card 16-bit legacy mode base address PCI 44h 31–1 System control PCI 80h 31–29, 27–24, 22–14, 6–3, 1–0 Multimedia control PCI 84h 7–0 Genera[...]

Global Reset Only Bits/PME Context Bits A-3 Global Reset Only Bits, PME Context Bits T able A–2. PME Context Bits Register Name Space Offset Bit Bridge control PCI 3Eh 6 Power management capabilities PCI A2h 15 Power management control/status PCI A4h 15, 8 ExCA power control ExCA 802h, 842h 4, 3, 1, 0 ExCA interrupt and general control ExCA 803h/[...]

A-4[...]

B-1 PME and RI Behavior PME and RI Behavior This appendix clarifies PME and RI signal behavior . These signals are important to support the wake-up event from a PC Card (CardBus and 16-bit cards.) T opic Page B.1 PME and RI Behavior B-2 Appendix B[...]

B-2 B.1 PME and RI Behavior T able B–1. CardBus CTSCHG and Wake-Up Signals T ruth T able RINGEN RIMUX RIENB PME_EN PME_ST A T RI_OUT/PME MFUNC7 0 0 0 0 Latched ––– ––– 0 0 0 1 Latched Latched CSTSCHG ––– 0 0 1 0 Latched ––– ––– 0 0 1 1 Latched ––– ––– 0 1 0 0 Latched ––– ––– 0 1 0 1 Latched La[...]

PCI445X Buffer T ypes C-1 PCI445X Buffer T ypes PCI445X Buffer T ypes T opic Page C.1 PCI445X Buffer T ypes C-2 Appendix C[...]

PCI445X Buffer T ypes C-2 C.1 PCI445X Buffer T ypes T able C–1. PCI445X T erminal Function Assignment and Buffer T ypes Signal Name T erminal T ype Signal Name T erminal T ype A_CAD0 B8 TS A_CAD28 N2 TS A_CAD1 A7 TS A_CAD29 N3 TS A_CAD2 C8 TS A_CAD30 P1 TS A_CAD3 A6 TS A_CAD31 D9 TS A_CAD4 B7 TS A_CAUDIO M1 I A_CAD5 B6 TS A_CBLOCK D2 P A_CAD6 C7 [...]

PCI445X Buffer T ypes C-3 PCI445X Buffer T ypes T able C–1. PCI445X T erminal Function Assignment and Buffer T ypes (Continued) Signal Name T erminal T ype Signal Name T erminal T ype A_CVS2 G1 I/O AD25 N20 TS A_RSVD A5 TS AD26 M17 TS A_RSVD B1 TS AD27 M18 TS A_RSVD P2 TS AD28 M19 TS AD0 V13 TS AD29 M20 TS AD1 Y14 TS AD30 L19 TS AD2 W14 TS AD31 L[...]

PCI445X Buffer T ypes C-4 T able C–1. PCI445X T erminal Function Assignment and Buffer T ypes (Continued) Signal Name T erminal T ype Signal Name T erminal T ype B_CAD22 C14 TS B_CSERR B1 1 STS B_CAD23 A14 TS B_CSTOP A20 STS B_CAD24 A13 TS B_CSTSCHG A1 1 I B_CAD25 D12 TS B_CTRDY C17 STS B_CAD26 C12 TS B_CVS1 B12 I/O B_CAD27 C10 TS B_CVS2 C15 I/O [...]

PCI445X Buffer T ypes C-5 PCI445X Buffer T ypes T able C–1. PCI445X T erminal Function Assignment and Buffer T ypes (Continued) Signal Name T erminal T ype Signal Name T erminal T ype GND U8 P PHY_DA T A6 U9 TS GND U13 P PHY_DA T A7 V9 TS GND U17 P PHY_LREQ Y5 O GNT K20 I PME/RI_OUT Y13 OD IDSEL/MFUNC7 P20 I/O PRST K19 I IRDY T17 STS REQ L20 O IR[...]

PCI445X Buffer T ypes C-6 T able C–1. PCI445X T erminal Function Assignment and Buffer T ypes (Continued) Signal Name T erminal T ype Signal Name T erminal T ype VCC3.3 U6 P ZV_UV4 W1 TSO VCC3.3 U10 P ZV_UV5 Y1 TSO VCC3.3 U15 P ZV_UV6 W2 TSO ZV_HREF P3 TSO ZV_UV7 Y2 TSO ZV_LRCLK V4 TSO ZV_VSYNC R2 TS ZV_MCLK W4 TSO ZV_Y0 T1 TSO ZV_PCLK Y3 TSO ZV_[...]

PCI445X Buffer T ypes C-7 PCI445X Buffer T ypes T able C–2. Buffer T ype Abbreviations Buffer T ype Description I/O Standard input/output I Standard input only O Standard output only OD Open drain P Power , GND, or clamp rail STS Sustained 3-state bidirectional. An active-low signal must be driven high for one cycle before deasserting. TS 3-state[...]

C-8[...]