Xilinx ML561 manual

R Vir te x-5 FPGA ML561 Memor y Interfaces De velopment Boar d User Guide UG199 (v1.2) Ap ril 19, 2008[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com UG199 (v1.2) April 19 , 2008 Xilinx is disclosing this user gui de, manual, rel ease note, and/or specification (the "Documentation") to y ou solely for use in the de velopment of designs to operate with Xilinx hardw are devices. Y ou may not re produce, distribu te, repub lish, downl oad, di[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 3 UG199 (v1.2) Apr il 19, 2008 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

4 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 R Seven-Segment Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Light Emitting Diodes (LE Ds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pushbuttons . . . . .[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 5 UG199 (v1.2) Apr il 19, 2008 R Appendix B: Bill of Materials Appendix C: LCD Interface General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Display Hardware Design . . . . . . . . . . . . . . . . . . . . . [...]

6 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 R[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 7 UG199 (v1.2) Apr il 19, 2008 R Pr eface About This Guide This user guide describes the V irtex ® -5 FPGA ML561 Memory Interfaces Development Board. Comple te and up-to-date documentat ion of the V irtex-5 family of FPGAs is available on the Xilinx website at http://www .xilinx.com/virtex5 . Guide Co[...]

8 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Pref ace: About This Guide R - Configurable Logic Block s (CLBs) -S e l e c t I O ™ R e s o u r c e s - SelectIO Logic Resources - Advanced SelectIO Logic Resour ces • V irtex-5 FPGA RocketIO GTP T ransceiver User Guide This guide describes the Rocket IO™ GTP tran[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 9 UG199 (v1.2) Apr il 19, 2008 Con ventions R Con ventions This document uses the following convention s. An example illustrates each convention. T ypographical This document uses the following typographica l conventions. An example illustrates each convention. Online Document The following conventions[...]

10 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Pref ace: About This Guide R Hard ware Measurements These measurements ar e the actual real-time measurements of an eye diagram and a segment of the test pattern (PRB S6) waveform captured on ML561 hardware at the designated probe point using an Agilent scope. Inter-Sy[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 11 UG199 (v1.2) Apr il 19, 2008 R Chapter 1 Intr oduction This chapter introduces the V irtex ® -5 FPGA ML561 re ference design. It contains the following secti ons: • “About the V irtex-5 FPGA ML561 Memory Interfaces T ool Kit” • “V irtex-5 FPGA ML561 Memory Interfaces Development Boa r d?[...]

12 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 1: Introd uction R Vir te x-5 FPGA ML561 Memory Interfaces Development Boar d A high-level functional bloc k diagram of the V irtex-5 FPGA ML561 Memory Interfaces Development Board is shown in Figur e 1- 1 . The V irtex-5 FPGA ML561 Development Boar d includes [...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 13 UG199 (v1.2) Apr il 19, 2008 Virtex-5 FPGA ML5 61 Memory Interfaces Development Boar d R Figur e 1-2 shows the V irtex-5 FPGA ML561 Development Board and indicates the locations of the reside nt memory devi ces. Figure 1- 2: Vir te x-5 FPGA ML561 Devel opment Boar d S A i l N 10 t hit / d h d F/L DD[...]

14 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 1: Introd uction R[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 15 UG199 (v1.2) Apr il 19, 2008 R Chapter 2 Getting Started This chapter describes the items needed to configure the V irtex-5 FPGA ML561 Memory Interfaces Development Boar d. The V irtex-5 FPGA ML561 Development Boar d is tested at the factory after assembl y and should be r eceived in working conditi[...]

16 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 2: Getting Star ted R 5. Insert the CompactFlash card included in th e kit into socket J27 on the V irtex-5 FPGA ML561 Development Board. T o select the startu p file, check that SW8 is set to position 0. Appl ying P ower to the Boar d The V irtex-5 FPGA ML561 [...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 17 UG199 (v1.2) Apr il 19, 2008 R Chapter 3 Hardwar e Description This chapter describes the major har dware blocks on the V irtex-5 FPGA ML 561 Development Board and provides useful des ign consideration. It contains the following sections: • “Hardwar e Overview” • “Memory Details” • “[...]

18 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R FPGA The ML561 uses three V irtex-5 XC5VLX50T -FFG1 136 devices, each in a 1 136-pin, 35 mm x 35 mm BGA package. Figure 1- 1, page 12 shows the memory devices associated with the three FPGAs. Refer to Appendix A, “FPGA Pinouts ,”[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 19 UG199 (v1.2) Apr il 19, 2008 Har dware Ov erview R Memories Ta b l e 3 - 1 lists the typ es of memories that the ML561 board supports. When a larger data/s trobe ratio is implemented, for example, a x36 QDRII device, the smaller configurations can also be demonstr ated by programming the FPGA for a [...]

20 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R DDR2 SDRAM Components The ML561 board contains two 333 MHz Micron M T47H32M16CC-3 (16-bit ) DDR2 SDRAM components that provide a 32-bit inte rface to FPGA #1. Each 16-bit device is packaged in an 84-ball FBGA package, with a common a[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 21 UG199 (v1.2) Apr il 19, 2008 Memory Deta ils R Memory Details DDR400 and DDR2 Component Memor ies The FPGA #1 de vice on the V irt ex-5 FPGA ML 561 Development Board is connected to DDR and DDR2 component memories, as s hown in Figure 3-3 . Figur e 3-3 summarizes the distribution of DDR and DDR2 dis[...]

22 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Ta b l e 3 - 3 describes all si gnals associated with DDR400 Component memories. Ta b l e 3 - 4 describes all signals associated with DDR2 Compone nt memories. For a complete list of FPGA #1 signals and their pin locations, refer to [...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 23 UG199 (v1.2) Apr il 19, 2008 Memory Deta ils R DDR2 SDRAM DIMM The FPGA #2 de vice on the V irt ex-5 FPGA ML 561 Development Board is connected to DDR2 memories. The DDR2 memory interface in cludes a 144-bit wide DIMM connection to up to five 240-pin DDR2 DIMM sockets. For the 144-bit wide DIMM data[...]

24 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Ta b l e 3 - 5 describes all the signals ass ociated with DDR2 DIMM component memories. For the Deep DIMM interface to four DIMMs , th e individual dedicate d control signal s are listed at the bottom of Ta b l e 3 - 5 . XAPP858 , Hi[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 25 UG199 (v1.2) Apr il 19, 2008 Memory Deta ils R QDRII and RLDRAM II Memories Figur e 3-5 summarizes the distribution of QDRI I and RLDRAM II component interface signals among the differ ent ba nks of the FPGA #3 device. Figure 3-5: FPGA #3 Banks for QDRII SRAM and RLDRAM II Interfaces (T op Vie w) BA[...]

26 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Ta b l e 3 - 6 describes all the signals associated with QDRII component memories. X APP 853 : QDR II SRAM Interface for V i rtex-5 Devices and its corresponding demo are included on the CD shipped with the ML561 T ool Kit. For a com[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 27 UG199 (v1.2) Apr il 19, 2008 External Inte rfaces R External Interfaces The external interfaces of the V irtex-5 FP GA ML561 Development Board are described in this section. RS-2 3 2 The ML561 board pr ovides an RS-2 32 serial interface using a Maxim MAX3316ECUP device. The maximum speed of this d e[...]

28 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R 200 MHz L VPECL Cloc k The 200 MHz L VPECL clock source is an Epson EG-2121CA200M-PCHS oscillator (Y1) with a differ entia l output. The oscillator runs at 200 MHz ± 100 PPM with an operating voltage of 2.5V ±5%. This outp ut is fe[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 29 UG199 (v1.2) Apr il 19, 2008 External Inte rfaces R 33 MHz System A CE Controller Oscillator A single-ended 33 MHz Epson SG-8002CA oscill ator is provided on the board (Y3) as a clock sour ce for System ACE functionality . GTP Clocks T wo SMA connectors are pr ovided for the input of an of f-board d[...]

30 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Se ven-Segment Displa ys One seven-segment display per FPGA (for a tot al of three) is available for use. The red Stanley-Electric NAR131SB displays ar e active Low , using seven inputs to display a character or number plus another i[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 31 UG199 (v1.2) Apr il 19, 2008 External Inte rfaces R P ow er On or Off Slide Switch The power on or of f slide switch is a DPST slide swi tch used to apply input power to the board. While the boar d contains two such swit ches, the 5V switch is primarily used to supply 5V power to the boar d, whereas[...]

32 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Liquid Cr ystal Displa y Connector Previous memory boar ds such as the ML 461 had a DisplaytechQ 64128E-FC-BC-3LP 64x128 LCD panel. This display was r e moved from the ML561, but the connection is still available for use with embedde[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 33 UG199 (v1.2) Apr il 19, 2008 P ower Regulat ion R The product specification at http://www .displaytech.com.hk/p d f/graphic/64128e%20series-v10.PDF provides more information. Appendix C, “LCD Interface,” describes the LCD operation in detail. Po w e r R e g u l a t i o n This section describe s [...]

34 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R also be supplied from a bench supply using the two banana jacks: J25 (RED) for +5V and J24 (BLACK) for GND. The Rev-A assembly of the V irtex-5 FPGA ML561 Development Board does not support the +12V input via jack J23 or via banana j[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 35 UG199 (v1.2) Apr il 19, 2008 P ower Regulat ion R The FPGA can drive VMARGIN_DN_xxxx_N and VMARGIN_UP_xxxx_N signals, where xxxx indicates one of the six main power regulators: SSTL2, HS TL, SSTL18, VCC1V0, VCC2V5, and VCC3V3. If both voltage-margining inputs to the power regulator are pulled Low , [...]

36 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Ta b l e 3 - 1 8 summarizes the inhibit headers. Boar d Design Considerations UG086 , Memory Interface Generator (MIG) User Guide includes PCB imple mentation rules and guidelines to be fo llowed for designing a board for a MIG refer[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 37 UG199 (v1.2) Apr il 19, 2008 Board Design Considerations R For W rite data and terminations at the memory , if the trace length from the r eceiver pin to the termination resistor can be guaranteed to be within 0.3 inches, then the fly-by termination scheme is implemented. Otherwis e, the non-fly-by [...]

38 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 3: Har dware De scription R Ta b l e 3 - 1 9 shows the details of the dielectric mate rial and constr uction for each layer and the contro lled impedance values for the signal layers. T able 3-19: ML561 Re vision A PCB Controlled Impedanc e Seq # La yer Name Ty[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 39 UG199 (v1.2) Apr il 19, 2008 R Chapter 4 Electrical Requir ements This chapter provides the electrical re quirements for the V irtex -5 FPGA ML561 Development Board . It contains the following sections: • “Power Consumption” • “FPGA Internal Power Budget” P o wer Consumption Ta b l e 4 -[...]

40 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 4: Electrical Requ irements R T able 4-1: ML561 P ower Consumption Device Description Quantity V olta g e (V) Current (mA) Pow e r (W) Sour ce T otal A vailable P ower 5V Power Supply 1 5.0 8000 40. 0 Bellus Power SPD-050-5 12V Power Supply 1 12.0 5000 60.0 CUI[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 41 UG199 (v1.2) Apr il 19, 2008 P ower Consumptio n R P ower Modules Capacity V CCINT Power Plane (1.0V) 1 1.00 15000 15.0 T I PTH05010 15A Module Da ta Sheet HSTL FPGA Power Plane (1.8V) 1 1.80 15000 27.0 HSTL Memory Power Plane (1.8V) 1 1.80 6000 10.8 TI PTH05000 6A Module Data Sheet HSTL _VREF Power[...]

42 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 4: Electrical Requ irements R Ta b l e 4 - 2 lists the 12 differe nt power planes on the V irtex-5 FPGA ML 561 Development Board. For the SSTL2, SSTL18, and HSTL power , separate power modules are implemented for V CCO to FPGA, and V DD to memory , allowing for[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 43 UG199 (v1.2) Apr il 19, 2008 P ower Consumptio n R current can support a voltage swing of up to (16 mA * 50 Ω ) = 800 mV , which is s uf ficient to meet the output voltage spec ification s for SSTL18, SSTL2, and HSTL18 I/O standar ds. Ta b l e 4 - 3 sepa rates the power cons umption information fro[...]

44 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 4: Electrical Requ irements R SSTL18 FPGA Power Plane (1.8V) Capacity 1 1.8 15000 27.0 17.5 TI PTH05010 15A Module Data Sheet DDR2 x16 Memory 2 1.8 250 0.9 Micron DDR2 Com ponent Data Sheet DDR2 DIMM 2 1.8 1755 6.3 Micron DDR2 DIMM D ata Sheet SSTL18_Mem Power [...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 45 UG199 (v1.2) Apr il 19, 2008 P ower Consumptio n R System ACE Controller 1 3.3 200 0.7 DS080 , System ACE CompactFlash Solution 33 MHz Oscillator 2 3.3 45 0.3 Epson SG-8002CA Data Sheet 3.3V Power Plane Capacity 1 3.3 15000 49.5 47.8 TI PTH05010 15A Module Data Sheet T otal P ower Consumed 53.2 12V [...]

46 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 4: Electrical Requ irements R FPGA Internal P o wer Budget Ta b l e 4 - 4 summarizes power consumption estimates by each of the three XC5VLX50T-FFG1 136 FPGA s on the V irtex-5 FPGA ML56 1 Development Board. This estimate derives the FPGA utilization informa ti[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 47 UG199 (v1.2) Apr il 19, 2008 R Chapter 5 Signal Integrity Recommendations T ermination and T ransmission Line Summaries The following are common r ecommendations for the si gnal termination scheme to all external memories implemented on the V irtex-5 FPGA ML561 Development Boar d: • Single-ended s[...]

48 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 5: Signal Integrity Recommendatio ns R T able 5-1: DDR400 SDRAM Component T erminations Signal FPGA Driver T ermination at FPGA T ermination at Memory Data (DQ) SSTL2_II_DCI No termination 50 Ω pull-up to 1.3V Data Strobe (DQS) SSTL2_II_DCI No termination 50 ?[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 49 UG199 (v1.2) Apr il 19, 2008 T ermination and T ransmission Line Summaries R T able 5-4: QDRII SRAM T erminat ions Signal FPGA Driver T ermination at FPGA T ermination at Memory W rite Data (D) HSTL_I_18 No termination 50 Ω pull-up to 0.9V Read Data (Q) HSTL_I_DCI_18 No termination No termination W[...]

50 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 5: Signal Integrity Recommendatio ns R[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 51 UG199 (v1.2) Apr il 19, 2008 R Chapter 6 Configuration This chapter provides a brief description of th e FPGA configuration methods used on the V irtex-5 FPGA ML561 Development Board. This chapter contains the following sections: • “Configuration Modes” • “JT AG Chain” • “JT AG Port?[...]

52 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 6: Configuration R JT A G Chain Four devices (the Syst em ACE chip and th ree XC5VLX50T -FFG1 136 FPGAs) are connected via a JT AG chain on the V irtex-5 FPGA ML561 Development Boar d. The or der of the four devices in the JT AG chain is System ACE chip (U 45),[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 53 UG199 (v1.2) Apr il 19, 2008 System A CE Interf ace R Ta b l e 6 - 2 shows the System ACE interface signal names, descriptions, and pin assignments . T able 6-2: System A CE Interface Signal Descripti ons System A CE Pin Number Signal Name 70 SYSACE_MP A0 69 SYSACE_MP A1 68 SYSACE_MP A2 67 SYSACE_MP[...]

54 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 6: Configuration R[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 55 UG199 (v1.2) Apr il 19, 2008 R Chapter 7 ML561 Hardwar e-Simulation Corr elation This chapter contains the following sections: • “Introduction” • “T est S etup” • “Signal Integrity Corr elation Results” • “Summary and Recommendations” • “How to Generate a User -Specific F[...]

56 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R illustrated here for these s ignals can be easily adopted to perform SI analysis for any other memory interface signal on the ML561 boar d. This chapter presents the SI res ults for the following six data bit signals[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 57 UG199 (v1.2) Apr il 19, 2008 T est Setup R strobe, a random value can be applied to data bits from one cycle to anoth er . A 63-bit PRBS6 (1) (PRBS of or der 6) test pattern stimulus is used for this analysis. The value of this PRBS6 string is 63’h03F5_66ED _2717_9461 , that is: 63’b000001111110[...]

58 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R ♦ DDR2 mask (for nominal VDDQ = 1.8V and VREF = 0.9V): - VIH(ac)-min = VREF + 200 mV = 1.1V - VIH(dc)-min = VREF + 125 mV = 1.025V - VIL(ac)-max = VREF – 200 mV = 0.7V - VIL(dc)-max = VREF – 12 5 mV = 0.775V ?[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 59 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R DDR2 Component Write Operation This subsection shows the test r esults for the DDR2_DQ_BY2_B3 signal from FPGA1 (U7) to the DDR2 memory component (U12) measure d at 333 MHz (667 Mb/s), where the unit interval (UI) = 1.5 ns. Figure [...]

60 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R DDR2 DQ is a bidirectional signal. T o pe rform hardwar e measur ements for a W rite operation that is not interrupte d by a Read response or a Re fresh operation, the testbench on FPGA1 is contr olled by DIP switche[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 61 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 4: DDR2 Component Write HW Measurement - Eye Scope Shot at Probe P oint (DDR2 Memory Via) UG199_c7_04_071107 Figure 7- 5: DDR2 Component Write Correlation - Ey e Scope Shot at Probe P oint (Slo w Corner) 0.000 400.0 800.0[...]

62 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-6: DDR2 Component Write HW Measurement - W avef orm Scope Shot at Pr obe P oint (DDR2 Memor y Via) UG199_c7_06_071107 Figure 7- 7: DDR2 Component Write Correlation - W aveform Scope Shot at Prob e P oint (Sl[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 63 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 8: DDR2 Component Write Extrapolation - Ey e Scope Shot at Receiver IOB (Slow Co rner) -200.0 200.0 600.0 Time (ps) Voltage (mV) 1000.0 1400.0 1800.0 -200.0 0.000 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 1800.0[...]

64 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-10: DDR2 Component Write Extrapolatio n - Eye Scope Shot at Rece iver IOB (Fast Corner) UG199_c7_10_071007 -100.0 100.0 300.0 500.0 700.0 900.0 1100.0 1300.0 Voltage (mV) 1500.0 1700.0 1900.0 800.0 1200.0 16[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 65 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R DDR2 Component Read Operation This subsection shows the test re sults fo r the DDR2_DQ_BY2_B3 signal fr om the DDR2 memory component (U12) to FPGA1 (U7) me asured at 333 MHz (667 Mb/s), wher e the unit interval (UI) = 1.5 ns. T o p[...]

66 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-13: DDR2 Component Read HW Measurement - Eye Scope Shot at Pr obe Po int (FPGA1 Via) UG199_c7_13_071107 Figure 7-14 : DDR2 Component Read Correlation - Eye Scope Shot at Pr obe P oint (Slo w Corner) 800.0 12[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 67 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7-15 : DDR2 Component Read HW Measurement - W avef orm Scope Shot at Probe P oint (FPGA1 Via) UG199_c7_15_071107 Figure 7-16: DDR2 Component Read Corre lation - W avef orm Scope Shot at Pr obe P oint (Slow Corner) 65.000 75.[...]

68 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-17: DDR2 Component Read Extrap olation - Eye Scope Shot at Receiver IOB ( Slow Corner) 800.0 1200.0 1600.0 2000.0 2400.0 2800.0 -100.0 100.0 300.0 500.0 700.0 900.0 1100.0 1300.0 1500.0 1700.0 1900.0 UG199_c[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 69 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7-19: DDR2 Component Read Extr apolation - Eye Scope Shot at Rece iver IOB (Fast Corner) 800.0 1200.0 1600.0 2000.0 2400.0 2800.0 -100.0 100.0 300.0 500.0 700.0 900.0 1100.0 1300.0 1500.0 1700.0 1900.0 UG199_c7_19_071007 Tim[...]

70 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R DDR2 DIMM Write Operation This subsection shows the test re sults for the DDR2_DIMM_DQ_BY2_B3 signal fr om FPGA2 (U5) to the DDR2 DIMM (XP2) measured at 333 MHz (667 Mb/s), wher e the unit interval (UI) = 1.5 ns. The[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 71 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R DDR2 DQ is a bidirectional signal. T o pe rform hardwar e measur ements for a W rite operation that is not interrupte d by a Read response or a Re fresh operation, the testbench on FPGA2 is contr olled by DIP switches (SW1) as indi[...]

72 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7- 22: DDR2 D IMM Write HW Measurement - Eye Scope Sh ot at Probe P oint #1 (DDR2 Memor y Via) UG199_c7_22_071107 Figure 7-23 : DDR2 DIMM Write Correlation - Eye Scope Shot at Pr obe P oint #1 (Slow Corner) 80[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 73 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7-24: DDR2 DIMM Write HW Measur ement - W avef orm Scope Shot at Pr obe P oint #1 (DDR2 Memory Via) UG199_c7_24_071107 Figure 7-25: DDR2 DIMM Write Correlation - W avef orm Scope Shot at Probe P oint #1 (Slow Corner) 95.000 [...]

74 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-26: DDR2 DIMM Write Extrapolation - Eye Scope Shot at Receiver IOB (S low Corner) 1000.0 1400.0 1800.0 2200.0 2600.0 -200.0 0.000 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 1800.0 UG199_c7_26_071007[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 75 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 28: DDR2 D IMM Write Extrapolation - Eye Scop e Shot at Receiver IOB (F ast C orner) 400.0 800.0 1200.0 1600.0 2000.0 2400.0 -200.0 0.000 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 1800.0 UG199_c7_28_071007 Time [...]

76 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R DDR2 DIMM Read Operation This subsection shows the test re sults fo r the DDR2_DIMM_DQ_BY2_B3 s ignal from the DDR2 DIMM (XP2) to FPGA2 (U5) measured at 333 MHz (667 Mb/s), wher e the unit interval (UI) = 1.5 ns. T o[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 77 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 31: DDR2 DIMM Read HW Measurement - Eye Sc ope Shot at Probe P oint (FPGA1 Via) UG199_c7_31_071107 Figure 7- 32: DDR2 DIMM Read Correlation - Ey e Scope Shot at Pr obe P oint (Slow Co rner) 2000.0 2400.0 2800.0 3200.0 360[...]

78 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-33: DDR2 DIMM Read HW Measurement - Wa veform Scope Shot at Probe P oint (FPGA1 Via) UG199_c7_33_071107 Figure 7- 34: DDR2 D IMM Read Correlation - W avef orm Scop e Shot at Probe P oint (Slow Corner) 25.000[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 79 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 35: DDR2 D IMM Read Extrapolation - Eye Scop e Shot at Receiver IOB (Slow Corner) 2000.0 2400.0 2800.0 3200.0 3600.0 4000.0 -200.0 0.000 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 1800.0 Time (ps) Voltage (mV) UG[...]

80 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-37: DDR2 DIMM Read Extrapolat ion - Eye Scope Shot at Receiver IOB (F ast Corner) 400.0 800.0 1200.0 1600.0 2000.0 2400.0 -200.0 0.000 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 1800.0 Time (ps) Vol[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 81 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R QDRII Write Operation This subsection shows the test re sults for the QDR2_D_BY0_B5 signal from FPGA3 (U34) to QDRII memory (U35) measured at 300 M Hz (600 Mb/s), where the unit interval (UI) = 167 ns. Figure 7- 39: Post-La yout IB[...]

82 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7- 40: QDRII Write HW Measurement - Eye Scope Shot at Pr obe P o int (QDRII Memory Via) UG199_c7_40_071107 Figure 7-41: QDRII Write C orrelation - Eye Scope Shot at Probe P oint (Slow Corner) 0.000 400.0 800.0[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 83 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 42: QD RII Write HW Measurement - W aveform Scope Shot at Pr obe P oint (Q DRII Memory Via) UG199_c7_42_071107 Figure 7-43: QDRII Write Correla tion - W aveform Scope Shot at Probe P oint (S low Corner) 110.000 120.000 13[...]

84 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-44: QDRII Write Extrapola tion - Eye Scope Shot at Receiver IO B (Slow Corner) 0.000 400.0 800.0 1200.0 1600.0 -200.0 0.000 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 1800.0 Time (ps) Voltage (mV) U[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 85 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7- 46: QDRII Write Extrapolation - Eye Scope Shot at Receiver IOB (F ast Corner) 800.0 1200.0 1600.0 2000.0 2400.0 2800.0 -1900.0 -1400.0 -900.0 -400.0 100.0 600.0 1100.0 1600.0 2100.0 2600.0 3100.0 Time (ps) Voltage (mV) UG[...]

86 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R QDRII Read Operation This subsection shows the test re sults for the QDR2_Q_BY0_B5 signal from QDRII memory (U35) to FPGA 3 (U34) measur ed at 300 MHz (600 Mb/s), wher e the unit int erval (UI) = 1.67 ns. Figure 7-48[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 87 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7-49: QDRII Read HW M easurement - Eye Diagram Scope Shot at Probe P oint (FPGA3 Via) UG199_c7_49_071107 Figure 7-50: QDRII Read Corr elation - Ey e Diagram Scope Sho t at Pr obe P oint (Slo w Corner) 800.0 1200.0 1600.0 200[...]

88 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7-51 : QDRII Read HW Measurement - W a veform Sc ope Shot at Pr obe P oint (FPGA3 Via) UG199_c7_51_071107 Figure 7-52: QDRII Read Correlation - W avef orm Scope Shot at Probe P oint (Slow Corne r) 20.000 30.00[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 89 UG199 (v1.2) Apr il 19, 2008 Signal Integrity Correlatio n Results R Figure 7-53: QDRII Read Extra polation - Eye Scope Shot at Re ceiver IOB (Slow Corner) 1000.0 1400.0 1800.0 2200.0 2600.0 -200.0 0.000 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 1800.0 Time (ps) Voltage (mV) UG199_c7_53_07[...]

90 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Figure 7- 55: QDRII Read Extrapolation - Ey e Scope Shot at Receiver IOB (F ast Corner) 1200.0 1600.0 2000.0 2400.0 2800.0 -200.0 0.000 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 1800.0 Time (ps) Voltage (mV[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 91 UG199 (v1.2) Apr il 19, 2008 Summary and Recommendations R Summary and Recommendations The first objective of this exer cise is to establish correlation between hard ware measurements and the simulation at the pr ob e point. The intention was to validate the simulation model for the targeted signal.[...]

92 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R Ta b l e 7 - 1 6 summarizes the extrapolated SI char acteristics of al l six test signals. Here ar e some observations about extrapolated SI characteristics among these test signals: • The Data V alid W indow (DVW)[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 93 UG199 (v1.2) Apr il 19, 2008 How to Generate a Us er-Specific FPGA IBIS Model R How to Generate a User -Specific FPGA IBIS Model The following steps indicate how to generate an IBIS model: 1. Under ISE, open your fully compiled pr oject. 2. Go to the Tc l S h e l l tab, and issue an ibiswriter comma[...]

94 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Chapter 7: ML561 Har dware-Sim ulation Correlation R[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 95 UG199 (v1.2) Apr il 19, 2008 R Appendix A FPGA Pinouts This appendix provides the pinouts for th e thr ee FPGAs on the V irtex-5 FPGA ML561 Development Boar d. The toolkit CD shipped with every ML561 contains sample UCFs for each memory interface. These UCFs ar e for pinout re ference only and do no[...]

96 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R DDR400 Component Interface (cont.) DDR1_DQ_BY0_B4 AM32 DDR1_DQ_ BY2_B4 R32 DDR1_DQ_BY0_B5 AM33 DDR1_DQ_ BY2_B5 R33 DDR1_DQ_BY0_B6 AL33 DDR1_DQ_BY2_B6 R34 DDR1_DQ_BY0_B7 AL34 DDR1_DQ_BY2_B7 T33 DDR1_DQ_BY1_B0 Y34 DDR1 _DQ_BY3_B0 D34 DDR1_DQ_BY[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 97 UG199 (v1.2) Apr il 19, 2008 FPGA #1 Pinout R DDR2 Component Interface (cont.) DDR2_WE_N J21 DDR2_DQ_BY2_B2 N25 DDR2_DM_BY0 U30 DDR2_DQ_BY2_B3 P25 DDR2_DM_BY1 L29 DDR2_DQ_BY2_B4 P24 DDR2_DM_BY2 K27 DDR2_DQ_ BY2_B5 N24 DDR2_DM_BY3 J27 DDR2_DQ_BY2_B6 P27 DDR2_DQ_BY0_B0 T25 DDR2_DQ_BY2_B7 P26 DDR2_DQ_B[...]

98 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R FPGA #1 MII Link Interface FPGA2_TO_FPGA1_MII_TX_CLK J10 FPGA3_TO_FPGA1_MII_TX_CLK D10 FPGA2_TO_FPGA1_MII_TX_DA T A0 C1 3 FPGA3_TO_FPGA1_MII_TX_DA T A0 H10 FPGA2_TO_FPGA1_MII_TX_DA T A1 B13 FPGA3_T O_FPGA1_MII_TX_DA T A 1 C12 FPGA2_TO_FPGA1_M[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 99 UG199 (v1.2) Apr il 19, 2008 FPGA #1 Pinout R FPGA #1 T est Display Signals FPGA1_7SEG_0_N AG17 FPGA1_7SEG_6_N AF19 FPGA1_7SEG_1_N AH18 FPGA1_7SEG_DP_N AG21 FPGA1_7SEG_2_N AE18 FPGA1_ LED0 AD19 FPGA1_7SEG_3_N AF18 FPGA1_LED1 AE19 FPGA1_7SEG_4_N AG16 FPGA1_LED2 AE17 FPGA1_7SEG_5_N AH17 FPGA1_LED3 AF1[...]

100 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R FPGA #2 Pinout Ta b l e A - 2 lists the connections for FPGA #2 (U5). T able A- 2: FPGA #2 Pinout Signal Name Pin Signal Name Pin DDR2 DIMM Deep Interface DDR2_DIMM_A0 AG30 DDR2_DIMM1_CK0_N M26 DDR2_DIMM_A1 AH29 DDR2_DIMM1_CK0_P M25 DDR2_DIM[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 101 UG199 (v1.2) Apr il 19, 2008 FPGA #2 Pinout R DDR2 DIMM Deep Interface (cont.) DDR2_DIMM3_CK2_P AA25 D DR2_DIMM_DQ_BY0_B4 R27 DDR2_DIMM3_CKE0 AE28 DDR2_DIMM_DQ_BY0_B5 R26 DDR2_DIMM3_CKE1 AH28 D DR2_DIMM_DQ _BY0_B6 U28 DDR2_DIMM3_CS0_N W25 DDR2_DIMM_DQ_BY0_B7 U 27 DDR2_DIMM3_CS1_N V25 DDR2_DIMM_DQ_B[...]

102 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R DDR2 DIMM Deep Interface (cont.) DDR2_DIMM_DQ_BY4_B4 V34 DDR2_DIMM_DQ_BY7_B7 Y32 DDR2_DIMM_DQ_BY4_B5 W34 DD R2_DIMM_DQ_CB0_7_B0 D34 DDR2_DIMM_DQ_BY4_B6 V33 DD R2_DIMM_ DQ_CB0_7_B1 C34 DDR2_DIMM_DQ_BY4_B7 V32 DD R2_DIMM_ DQ_CB0_7_B2 D32 DDR2_[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 103 UG199 (v1.2) Apr il 19, 2008 FPGA #2 Pinout R DDR2 DIMM Wide Interface (cont.) DDR2_DIMM5_CS0_N V24 DDR2_DIMM_DQ_BY1 1_B5 G6 DDR2_DIMM5_CS1_N W24 DDR2_DIMM_DQ_BY1 1_B6 T1 1 DDR2_DIMM5_ODT0 AA9 DDR2_DIMM_DQ_BY1 1_B7 T10 DDR2_DIMM5_ODT1 AA8 DDR 2_DIMM_DQ_BY12_B0 J6 DDR2_DIMM_ LB_BK12 F5 DDR2_DIMM_DQ_[...]

104 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R DDR2 DIMM Wide Interface (cont.) DDR2_DIMM_DQ_BY15_B5 AD5 DDR2_DIMM_DQ_CB8_15_B4 N7 DDR2_DIMM_DQ_BY15_B6 AD4 DDR2_DIMM_DQ_CB8_15_B5 N8 DDR2_DIMM_DQ_BY15_B7 Y8 DDR2_DIMM_DQ_CB8_15_B6 M5 DDR2_DIMM_DQ_BY8_B0 G13 DDR2_DIMM_DQ_CB8_15_B7 M6 DDR2_D[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 105 UG199 (v1.2) Apr il 19, 2008 FPGA #2 Pinout R DDR2 DIMM Miscellaneous Signals (cont.) DDR2_DIMM5_CNTL_P AR AB8 DDR2_DIMM2_SA2 N24 DDR2_DIMM5_CNTL_P AR_ERR A M12 DDR2_DIMM3_SA0 P27 DDR2_DIMM5_NC_019 AC9 DDR2_DIMM3_SA1 P26 DDR2_DIMM5_NC_102 AL1 1 DDR2_DIMM3_SA2 N28 DDR2_DIMM_SCL W31 DDR2_DIMM4_SA0 K2[...]

106 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R FPGA #2 T est and Deb ug Signals FPGA2_DIP0 AG18 FPGA2_SOFTTOUCH_BY1_B7 H17 FPGA2_DIP1 AG15 FPGA2_SPYHOLE_BK15 P29 FPGA2_DIP2 AH15 FPGA2_SPYHOLE_BK18 W9 FPGA2_DIP3 AG20 FPGA2_TEST_HDR_BY0_B0 AE23 FPGA2_SOFTTOUCH_BY0_B0 H20 FPGA2_TEST_HDR_BY0[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 107 UG199 (v1.2) Apr il 19, 2008 FPGA #2 Pinout R FPGA #2 External Interfaces (cont.) FPGA2_TXN0_BK120 B3 FPGA2_USB_CTS_N L15 FPGA2_TXN1_BK120 D2 FPGA2_USB_DSR_ N K16 FPGA2_TXP0_BK120 B4 FPGA2_U SB_DTR_N J15 FPGA2_TXP1_BK120 E2 FPGA2_USB_RST_N L21 FPGA2_RS232_CTS K14 FPGA2_USB_RTS_N L16 FPGA2_RS232_RT [...]

108 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R FPGA #3 Pinout Ta b l e A - 3 lists the connections for FPGA #3 (U34). T able A- 3: FPGA #3 Pinout Signal Name Pin Signal Name Pin QDRII Memory Interface QDR2_CK_BY0_3_N K34 QDR2_SA1 1 AB26 QDR2_CK_BY0_3_P G28 QDR2_SA12 AB25 QDR2_CK_BY0_3_P [...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 109 UG199 (v1.2) Apr il 19, 2008 FPGA #3 Pinout R QDRII Memory Interface (cont.) QDR2_D_BY0_B5 M31 QD R2_D_BY4_B1 AH29 QDR2_D_BY0_B6 P30 QD R2_D_BY4_B2 AH30 QDR2_D_BY0_B7 P31 QD R2_D_BY4_B3 AJ30 QDR2_D_BY0_B8 L31 QDR2_D_BY4_B4 AF30 QDR2_D_BY1_B0 J27 QDR2_D_BY4_B5 AF29 QDR2_D_BY1_B1 M26 QD R2_D_BY4_B6 A[...]

110 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R QDRII Memory Interface (cont.) QDR2_D_BY7_B6 U28 QDR2_Q_BY3_B2 G27 QDR2_D_BY7_B7 U27 QDR2_Q_BY3_B3 F26 QDR2_D_BY7_B8 T29 QDR2_Q_BY3_B4 F25 QDR2_Q_BY0_B0 J34 Q DR2_Q_BY3_B5 H24 QDR2_Q_BY0_B1 H34 QDR2_Q_BY3_B6 H25 QDR2_Q_BY0_B2 H33 QDR2_Q_BY3_[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 111 UG199 (v1.2) Apr il 19, 2008 FPGA #3 Pinout R QDRII Memory Interface (cont.) QDR2_Q_BY6_B7 V33 QDR2_Q_BY7_B4 W 29 QDR2_Q_BY6_B8 V32 QDR2_Q_BY7 _B5 Y31 QDR2_Q_BY7_B0 AB31 QDR2_Q_BY7_B6 W31 QDR2_Q_BY7_B1 Y29 QDR2_Q_BY7_B7 V27 QDR2_Q_BY7_B2 Y28 QDR2_Q_BY7_B8 V28 QDR2_Q_BY7_B3 V29 RLDRAM II Memory Inte[...]

112 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R RLDRAM II Memory Interface (cont.) RLD2_D_BY0_B5 F8 RLD2_DM_BY2_3_N T9 RLD2_D_BY0_B6 F9 R LD2_DQ_BY0_B0 G13 RLD2_D_BY0_B7 E8 RLD2_DQ_BY0_B1 F13 RLD2_D_BY0_B8 E9 RLD2_DQ_BY0_B2 N9 RLD2_D_BY1_B0 R1 1 RLD2_DQ_BY0_B3 N10 RLD2_D_BY1_B1 R7 R LD2_D[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 113 UG199 (v1.2) Apr il 19, 2008 FPGA #3 Pinout R RLDRAM II Memory Interface (cont.) RLD2_DQ_BY3_B4 M7 RLD2_DQ_BY3_B7 M5 RLD2_DQ_BY3_B5 N7 RLD2_DQ_BY3_B8 M6 RLD2_DQ_BY3_B6 N8 FPGA #3 Clock and Reset Signals CLK_TO_FPGA3_MGT_N D4 EXT_CLK_TO_FPGA3_N AG13 CLK_TO_FPGA3_MGT_P E4 EXT_CLK_TO_FPGA3_P AH12 DIRE[...]

114 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix A: FPGA Pinouts R FPGA #3 T est and Debug Signals (cont.) FPGA3_TEST_HDR_BY1_B4 AC24 FPGA3_TEST_HDR_BY1_B6 AE26 FPGA3_TEST_HDR_BY1_B5 AC25 FPGA3_TEST_HDR_BY1_B7 AE27 FPGA #3 T est Display Signals FPGA3_7SEG_0_N AG17 FPGA3_7SEG_6_N AF19 FPGA3_7SEG_1_N AH18 FPG[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 115 UG199 (v1.2) Apr il 19, 2008 R Appendix B Bill of Materials This appendix lists the bill of materials (B OM) for many of the components used for the assembly of the V irtex- 5 FPGA ML561 Development Boar d, Revision A. Wher ever feasible and practical, the associated r eference desi gnators ar e al[...]

116 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix B: Bill of Materials R Power 15A Power Module T exas Instrumen ts PTH05010-W AZ VR1, VR6, VR9 , VR10, VR12, VR 13 6A Power Module T exas Instruments PTH05000-W AZ VR2, VR4, VR1 4 4A LDO Maxim MAX8556ETE VR3, VR5, VR7, VR8 1.5A VLDO Regulator Linear T echnolog[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 117 UG199 (v1.2) Apr il 19, 2008 R Switch DIP (T est Inputs) ITT_INDUSTRIES SDA04H1KD SW1, SW2, SW6 System Reset (Black) Panasonic EVQ 1 1L07K SW4 Config uration Re set (Red) Panasoni c EVQ 1 1L05K SW7 Power Input (12V an d 5V) APEM 25336N A SW3, SW5 Rotary 8-position Digikey GH331 1-N D SW8 Capacitor [...]

118 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix B: Bill of Materials R[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 119 UG199 (v1.2) Apr il 19, 2008 R Appendix C LCD Interface This appendix describes the LCD interface for the V irtex-5 FPGA ML 561 Development Board. General The V irtex-5 FPGA ML561 Development Boar d has a full graphical LCD panel. This display was chosen because of its possible use in e mbedded sys[...]

120 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Ta b l e C - 1 summarizes the controller specificati ons. The on-chip RAM size is 65 x 132 = 8580 bits. Har dware Sc hematic Diagram Figure C-1 illustra tes the schematic for the display . Ta b l e C - 1 : Display Co ntrol ler Specification[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 121 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R P eripheral De vice KS071 3 Figure C-2 is a block dia gram of the Samsung KS0713. Figure C-2: KS0713 Bloc k Diagram V/C Circ u it V/R Circ u it V/F Circ u it P a ge Addre ss Circ u it Line Addre ss Circ u it Di s pl a y D a t a RAM 65 x132 =[...]

122 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Figure C-3 shows only the signals of interest for the LCD contr oller . The data sheet fr om the Samsung web pages provides a complete signal list ing. Figure C-4 shows the dimensions for the 64128EFCBC-XLP LCD panel. Figure C-3: 64128EFCBC[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 123 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R Controller – Operation The pixels for the LCD panel ar e stored in the contr oller data RAM. This RAM is a 65-row by 132-column array . Each display pixel is represented by a single bit in the RAM array . The interface to the RAM array goe[...]

124 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R 0010 DB0 Page 2 10H DB1 11 H DB2 12H DB3 13H DB4 14H DB5 15H DB6 16H DB7 17H 0011 DB0 Page 3 18H DB1 19H DB2 1AH DB3 1BH DB4 1CH DB5 1DH DB6 1EH DB7 1FH 0100 DB0 Page 4 20H DB1 21H DB2 22H DB3 23H DB4 24H DB5 25H DB6 26H DB7 27H 0101 DB0 Pa[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 125 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R When a page is address ed, all the bits repr es enting dots on the LCD panel can be accessed in that page. An array of 8x132 bits is availabl e. The line addr ess dictates what line of the RAM is going to be displayed on the first li ne of t[...]

126 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Controller – P o wer Supply Circuits Figure C-5 shows the power supply cir cuits. The po wer supply is used in the five times boost mode, where VDD is 3.3V and VOUT is 16.5V . VOUT is the operating voltage of t he operational amplifier de[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 127 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R The voltage and contrast settings must be co nfigur ed befor e the LCD panel is r eady for operation. Figure C-6 s hows the initializati on procedur e require d to set up the LCD controller . Operation Example of the 64128EFCBC- 3 LP The KS0[...]

128 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R • The voltage follower and voltage regulator are set to: ♦ Five times boost mode ♦ The V4, V3, V2, V1 , and V0 outputs de pend on the bias set tings of 1/9 or 1/7. Because of these default settings, the following disp lay controller c[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 129 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R After the SHL bit is configur ed, these settings normally ar e not changed. • Select the LCD bias settin gs. ♦ The duty cycle is selected as 1/65 by ha r dwiring the controller IC pads on the display P CB. ♦ The LCD bias is set to: - 1[...]

130 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Instruction Set Ta b l e C - 6 shows the instruction set for the LCD panel. T able C- 6: Display Instruct ions Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read display data 1 1 Read Data 8-bit data specified by the column and page add[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 131 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R Set page addr ess 0 0 1 0 1 1 P3 P2 P1 P0 This instruction s ets the address of the display data page. A ny RA M data bit can be accessed whe n its page address an d column a ddr ess ar e specified. Changing the Page Addr ess does not af fec[...]

132 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R R e v e r s e d i s p l a y O N / O F F 0 0 1010011 R E V REV RAM bit data = '1' RAM bit data = '0' 0 Pixel ON Pixel OFF 1 Pixel OFF Pixel ON E n t i r e d i s p l a y O N / O F F 0 0 1 010010 E O N This instruction for [...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 133 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R Read/Write Character istics (6800 Mode) Ta b l e C - 7 list the read and wr ite timing para meters in 6800 mode. The associated waveforms for these parameters are illustrated in Figur e C-7 . Ta b l e C - 7 : Read/Write Characteristi cs in 6[...]

134 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Design Examples LCD P anel Used in Full Graphics Mode The LCD controller RAM has eight 132-byte page s (in fact, there ar e nine pages; page 9 is special). Each page is one byte wide. If all the pages ar e put in one memory block, the neede[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 135 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R LCD P anel Used in Character Mode This design example r equir es a byte r epr esen ting a command or data to be displayed as input. • When the Enable signal is Low , nothing happens. The display interface design is locked. • When the Ena[...]

136 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Displa y Data Byte The supplied byte must be a valid ASCII repr esentation of a character as shown in Figure C-9 . The character set is stored in block RAM (used as ROM). The CharacterSet.xls file contains the layout of the block RAM charac[...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 137 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R When presenting byte va lue 30 hex, character 0 must be displayed. Shifting the value 001 10000b (30h) up three positions gives the value 180h or 348d. Because each character uses ei ght byte locations, character 0 in the charact er set star[...]

138 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R Figure C-1 1 shows a block diagram of the LCD char acter generator controller . Character data is latched and then shifted left three positi ons. This shifted value is the start byte for a counter that outputs an address to the bloc k RAM. [...]

Virtex-5 FPGA ML561 User Guide www .xilinx.com 139 UG199 (v1.2) Apr il 19, 2008 Hardware Schematic Diagram R Arra y Connector Numbering Figure C-12 shows the LCD connections for Bank 0. Figure C-12: LCD Connections (Bank 0) B a nk 0 Connector Pin ABCDE FG H I D9 LCD_D0 10 D7 LCD_D4 9 D5 LCD_D5 8 D3 LCD_D6 7 D1 LCD_D7 6 E10 LCD_R S T 5 E 8 LCD_D1 4 [...]

140 www .xilinx.com Vir tex-5 FPGA ML5 61 User Gu ide UG199 (v1.2) April 19, 2008 Appendix C: LCD Interface R[...]