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Agilent Technologies FS4100 manuel d'utilisation

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Table des matières du manuel d’utilisation

  • Page 1

    FuturePlus Systems Corporation USB Analysis Probe Users Manual-FS4100 For Agilent Logic Analyzers Revision 2.7 FuturePlus Systems is a trademark of FuturePlus Systems Corporat ion Copyright 1998 FuturePlus Systems Corporation[...]

  • Page 2

    HOW TO REACH US 4 PRODUCT WARRANTY 5 Limitation of w arranty 5 Exclusive Remedies 6 Assistance 6 INTRODUCTION 7 How to Use This Manual 7 ANALYZING THE UNIVERSAL SERIAL BUS 9 Duplicating the Master Diskette 9 Accessories Supplied 9 Minimum Equipment Required 10 Revisions 10 Signal Naming Conventions 10 The USB Analysis Probe Switches and Diodes 10 T[...]

  • Page 3

    The STAT variable 19 The ADDR and DATA variables 19 The PID variable 19 The CTLCMD variable 21 COMBINATION MODE 22 Bad EOP Detection 22 Low Speed/High Speed detection 23 STATE ANALYSIS 25 Installation Quick Reference 25 Acquiring Data 26 The State Display 26 Analysis Probe related error messages 27 USB CRC and Serial Bit Errors 27 Installation Quic[...]

  • Page 4

    How to reach us For Technical Support: FuturePlus Systems Corporation 36 Olde English Road Bedford NH 03110 TEL: 603-471-2734 FAX: 603-471-2738 On the web http://www.futureplus.com For Sales and Marketing Support: FuturePlus Systems Corporation TEL: 719-278-3540 FAX: 719-278-9586 On the web http://www.futureplus.com FuturePlus Systems has technical[...]

  • Page 5

    Product Warranty This FuturePlus Systems product has a warranty against defects in material and workmanship for a period of 1 year from the date of shipment. During the warranty period, Future Plus Systems will, at its option, either replace or r epair products proven to be defective. For warranty servic e or repair, this product must be returned t[...]

  • Page 6

    product, or improper site pr eparation or maintenance. NO OTHER WARRANTY IS EXPRESSED OR IMPLIED. FUTUREPLUS SYSTEMS SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REMEDIES PROVIDED HEREIN ARE BUYER’S SOLE AND EXCLUSIVE REMEDIES. FUTUREPLUS SYSTEMS SHALL NOT BE LIABLE FOR ANY DIRECT, IND[...]

  • Page 7

    Introduction The USB Analysis Probe module provides a complete interface between any poi nt on the USB and an Agilent Logic Analyzer. T he Analysis Probe interface receives the USB serial bit stream and converts it to an understandable parallel bus that is then acquired by the logic analyzer. The USB Analysis Probe is a passive bus monitor which do[...]

  • Page 8

    • The State Analysis chapter explains how to configure the USB Analysis Probe to perform state analysis on your USB . • The Timing Analysis chapter explains how to configure the USB Analysis Probe to perform timing analysis on your USB . • The General Information chapter provides some general information including the operating characteristic[...]

  • Page 9

    Analyzing the Universal Serial Bus This chapter introduces you to the USB Analysis Probe and lists the minimum equipment required and accessories supplied for Universal Serial Bus analysis. This chapter also contains information that is common to both state and timing analysis. Before you use the USB Analysis Probe software, make a duplicate copy o[...]

  • Page 10

    The minimum equipment required for analysis of a Universal Serial Bus consists of the following equipment: Minimum Equipment Required • A 166x, 167x , 1680/90, 1671x , 1674X, 1655x or 1675x logic analyzer • The USB Analysis Probe Product • A USB target wire Revisions This manual applies to Hardware revisions ACE or later and software revision[...]

  • Page 11

    The following explains how to connect the logic analyzer to the USB Analysis Probe for either state or timing analysis: Connecting to the USB Analysis Probe 1. Remove the probe tip assemblies from the logic analyzer cables. 2. Plug the logic analyzer cables into the USB Analysis Probe cable headers as shown in the appropriate following tables. Logi[...]

  • Page 12

    The logic analyzer can be configured for USB analysis by loading the USB configurati on file. Loading this file will load the Universal Serial Bus inverse assembler and configure your logic analyzer for USB analysis. Setting up the Analyzers installed in the 16500 mainframe. 1. Install the 16500 U SB Analysis Probe Software for the FS4100 flexible [...]

  • Page 13

    configuration file yourself, see table below for a list of analyzers and corresponding configuration files. Note: The Logic Analysis System’s Operating System must be version A.01.40.00 with patches 034 and 035 or higher to be compatible with the software provided on the installation diskette for the 167xx. The 1680/90/900 Analyzer is a PC based [...]

  • Page 14

    the menu bar at the top of the screen and select the decoder from the list. After loading the configuration file of choice, go into the format specification of the configuration by choosing Setup from the menu bar and then selecting Bus/Signal in the drop down menu. When the format specification appears press Define Probes at the bottom of the scre[...]

  • Page 15

    1680/90/900, 167xx Configuration files 167xx Analyzer 169xx Analyzer File Name 16550 / 16710/1/2 CUSB41_1 16555/6/7 CUSB41_2 16715/6/7, 1674x, 1675x CUSB41_3 1680/90 (State) 1680/90, 16750/1/2, 1691x (State) CUSB41_6 1680/90 (Timing) 1680/90, 16750/1/2, 1691x (Timing) CUSB41_7 Offline Analysis Data that is saved on a 167xx analyzer in fast binary f[...]

  • Page 16

    will be a series of questions, answer the first question asking which startup option to use, select Continue Offline. On the analyzer type question, select cancel. When the application comes all the way up you should have a blank screen with a menu bar and tool bar at the top. For data from a 1680/90/900 analyzer, open the .ala file using the File,[...]

  • Page 17

    picture; please choose the appropriate decoder for the trace you are working with. After the decoder has loaded, select Preferences if required, from the overview screen and set the preferences to their correct value in order to decode the trace properly. This is a general requirement, some decoders do not have preferences, if this is the case then[...]

  • Page 18

    The Format Menu The USB Analysis Probe diske tte sets up the format menu as shown in the followi ng table. This format is the same for both Timing and State Analysis. Pods 1 and 2 are for STATE analysis and POD 3 is useful for Timing analysis. Label Pod 4 Pod 3 Pod 2 Pod 1 STAT 15:11 16 ADDR 10:0 DATA 15:0 15:0 ADR 10:4 ENDPNT 3:0 PID 15:11 16 CTLC[...]

  • Page 19

    The STAT variable is used by the USB inverse assembler to decode USB transactions. It should not be changed or deleted from the format m enu. The STAT variable The ADDR and DATA variables The ADDR variable is the address and endpoint as decoded from the USB serial bit stream. The DATA variable is the Data associated with a Dat a0 or Data1 packet. F[...]

  • Page 20

    Symbol Binary Code Comment RESET END 111001 RESET DEASSERTS INVALID 011101 INVALID PID RECEIVED BAD PID 011110 BAD PID RECEIVED SUSPEND 111110 SUSPEND CONDITION DETECTED RESUME 111101 RESUME CONDITION DETECTED KEEP ALIVE 111011 KEEP ALIVE SETUP SBS ERROR 001001 SETUP PACKET WITH SERIAL BIT STUFFED ERROR DETECTED IN SBS ERROR 001010 IN PACKET WITH S[...]

  • Page 21

    Symbol Binary Code Comment ERROR DETECTED SOF CRC ERROR 010100 START OF FRAME PACKET WITH CRC ERROR DETECTED OUT CRC ERROR 010011 OUT PACKET WITH CRC ERROR DETECTED CRC DATA CRC ERR 010111 CRC DATA WITH CRC ERROR DETECTED ANY ERROR 111000 ERROR SUMMARY BIT SLOW SOF 011111 SOF TOKEN DETECTED AT SLOW SPEED RESUME SE0 111100 SE0 SENT AT END OF RESUME [...]

  • Page 22

    Standard Device Requests GET_CONFIGURATION SET_CONFIGURATION GET_INTERFACE SET_INTERFACE SYNCH_FRAME COMBINATION MODE The default mode set up by the software shipped with the Analysis Probe is the following configuration. Bad EOP Detection If the FS4100 operating in full speed mode, detects a valid SE0 for at least 60ns but a valid J_STATE does not[...]

  • Page 23

    3. Pass a “POSSIBLE BAD EOP” status to the Analyzer. A status of “POSSIBLE BAD EOP” should be treated as cautionary and the user would be advised to view the received signals in timing mode by doing the following. 1. Attach POD 3 of the analyzer to POD 3 of the USB Analysis Probe. 2. Attach a flying lead set to stake pins RCV, VP and VM. 3.[...]

  • Page 24

    Sequence 2 1. Detection of a PREAMBLE - switch to low speed 2. Look for IN packet and a following DATA packet and then switch back to high speed. If a DATA packet is not received wit hin the time-out period (18 bit times), the Analysis Probe will switch back to high speed. 3. In high speed look for PREAMBLE and handshake If the Analysis Probe is pl[...]

  • Page 25

    State Analysis This chapter explains how to configure the USB Analysis Probe to perform state analysis on the Universal Serial Bus. T he configuration software on the flexible diskette sets up the format specification menu of the logic analyzer for compatibility with the USB Analysis Probe. The nex t chapter explains how to configure the USB Analys[...]

  • Page 26

    Probe OUT connector can be connected down stream to either a Hub or device or it can be left unconnected. 4. Turn on the logic anal yzer so that the VCC and READY LEDs on the USB Analysis Probe are lit. NOTE: Connect the USB Analysis Probe to the USB wire as described in step 2 prior to powering up the logic analyzer. 5. Load the USB Analysis Probe[...]

  • Page 27

    Analysis Probe related error messages The following Analysis Probe related error messages are reported by the USB inverse assembler. FAILED TO IDENTIFY PID This error will be reported by the inverse assembler if the USB Analysis Probe hardware reports a status code that is undefined. If this error occurs please contact the FuturePlus Systems factor[...]

  • Page 28

    The USB Analysis Probe will also detect invalid PIDS, bad PIDS and SOF tokens s ent at slow speed. The Analysis Probe implements an error summary status called ANY ERROR, this st atus will be sent to the Analyzer if any of the above error conditions is detected by the Analysis Probe. 28[...]

  • Page 29

    Timing Analysis Pod 3 of the USB Analysis Probe contains signals that describe in more detail the actual state of the USB wire. Installation Quick Reference The following procedure describes the major steps required to perform timing analysis measurements with the USB Analysis Probe module. 1. After removing the probe tip assemblies, plug logic ana[...]

  • Page 30

    Acquiring Data Touch RUN and the logic analyzer will begin to acquire data. The analyzer will continue to acquire data and will display the data when the analyzer memory is full, the trigger specification is TRUE or when you touch STOP. The logic analyzer will flash “Waiting for Trigger” or “occurrences remaining in level x” where x is numb[...]

  • Page 31

    POD 3 channel Signal Name Description 14 SOFTIC Start of Frame. 1 millisecond timer generated from recovered start of frame 13:11 EOP2_0 End of Packet state machine 10:7 LBC3_0 Load Byte State Machine 6:4 RSRVD Reserved 3 FEOPR End of packet 2 FEOSYN End of Sync 1 LSDET Low Speed Detect 0 unused The end of packet state machine state encodings are a[...]

  • Page 32

    State Name State Encoding Description EOPR_STATE 001 J state transition detected. Valid end of packet SLOW_SEO_FI RST 101 First slow speed single ended zero condition detected SLOW_SEO_S ECOND 011 First slow speed single ended zero condition detected BAD_EOPR_ST ATE 111 Incorrect transition for single ended zero detected. NOTE: FEOPR will be genera[...]

  • Page 33

    DELAY_1 0010 State delayed by one clock tic DELAY_2 0011 State delayed by two clock tics SOF_OR_ADR 0100 Receiving address for token packet or Frame number SOF_OR_EP 0101 Receiving endpoint for token packet or the remainder of the frame number for start of frame CRC 0110 Receiving CRC data PRE_DATA 0111 About to receive data DATA 1000 Receiving dat[...]

  • Page 34

    POD 4 Description the transceiver is generating in response to the USB traffic. POD 4 channel Signal Name Description 0 RCV Differential data signal from the USB transceiver 1 VM VM Signal from the USB transceiver 2 VP VP Signal from the USB transceiver. The Waveform Display Captured data is displayed as shown in the following figure. 34[...]

  • Page 35

    General Information This chapter provides additional reference information including the characteristics and signal connections for the USB Analysis Probe module. Characteristics The following operating characteristics are not specifications, but are typi cal operating characteristics for the USB Analysis Probe. Standards Supported The Universal Se[...]

  • Page 36

    Environmental Temperature Operating: 0 to 55 degrees C (+32 to +131 degrees F) Non operating:-40 to +75 degrees C (-40 to +167 degrees F) Altitude Operating: 4,6000m (15,000 ft) Non operating: 15,3000m (50,000 ft) Up to 90% non condensing. Avoid sudden, extreme temperature changes which would cause condensation on the Analysis Probe module. Humidit[...]

  • Page 37

    Analysis Probe Cable Header and Pin number Logic Analyzer channel number USB Analysis Probe Signal name Header 3 pin 3 CLK/16 CLK12 5 no connect 7 15 MDATA 9 14 SOFTIC 11 13 EOP<2> 13 12 EOP<1> 15 11 EOP<0> 17 10 LBC<3> 19 9 LBC<2> 21 8 LBC<1> 23 7 LBC<0> 25 6 Reserved 27 5 Reserved 29 4 Reserved 31 3 FEOPR[...]

  • Page 38

    Analysis Probe Cable Header and Pin number Logic Analyzer channel number USB Analysis Probe Signal name Header 2 pin 3 CLK/16 MCLK 5 no connect 7 15 STAT4 9 14 STAT3 11 13 STAT2 13 12 STAT1 15 11 STAT0 17 10 ADR06 19 9 ADR05 21 8 ADR04 23 7 ADR03 25 6 ADR02 27 5 ADR01 29 4 ADR00 31 3 ENDPNT03 33 2 ENDPNT02 35 1 ENDPNT01 37 0 ENDPNT00 38[...]

  • Page 39

    Analysis Probe Cable Header and Pin number Logic Analyzer channel number USB Signal name Header 1 pin 3 CLK/16 STAT5 5 no connect 7 15 D15 9 14 D14 11 13 D13 13 12 D12 15 11 D11 17 10 D10 19 9 D09 21 8 D08 23 7 D07 25 6 D06 27 5 D05 29 4 D04 31 3 D03 33 2 D02 35 1 D01 37 0 D00 39[...]