AMD Am186TMER manuel d'utilisation

D RA F T Am186  ER and Am188  ER Micr ocontr ollers User’ s Manual[...]

© 1997 Advanced Mi cro Devices, Inc. All rights reserved. Adva nced Micr o Devices, Inc. (“AMD”) re serves the right to ma ke changes in its prod ucts with out notice in order to impr ove design or performance characterist ics. The information in thi s publication is believed to be accurate at the time of publi cation, but AMD makes no represe[...]

iii IF YOU HAVE Q UESTIONS, WE’RE HERE TO HELP YOU. Cust om e r Ser vice The AMD customer service net work i ncludes U.S. offices, intern ational offices, and a customer tr aining center. Expert t echnical assista nce is available fr om the worldwide staff of AMD field appli cat ion engineers and factory support staf f t o answer E86™ family ha[...]

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T able of Contents v TABLE OF CONTENTS PREFACE INTRODUCTION AND OVERV IEW Design Phil osophy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii Purpose of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii Intended A udience . . . . . . . . . . . . .[...]

T able of Contents vi CHAPTER 5 CHIP SELEC T UNIT 5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 Chip Sele ct T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 Ready and W ait-State Programming. . . . . . . . . . . . . . . . .[...]

T able of Contents vii 8.2 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.2.1 Fully Nes ted Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.2.2 Cascade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.2.3 Special Ful ly N[...]

T able of Contents viii CHAPTER 10 DMA CONTROLLER 10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10- 1 10.2 DMA Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 -1 10.3 Programmabl e DMA Registe rs . . . . . . . . . . . . . . . . . [...]

T able of Contents ix LIST OF FI GURES Figure 1-1 Am186ER M icrocontroller Bl ock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -4 Figure 1-2 Am188ER M icrocontroller Bl ock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -5 Figure 1-3 Basic Func tional System Design . . . . . . . . . . . . . . . . . . . . [...]

T able of Contents x Figure 8-25 Specifi c End-of-Interrupt Reg ister (EOI, offset 22h) . . . . . . . . . . . . . . . . . . . . . 8-36 Figure 8-26 Interrupt V ector Re gister (INTVE C, offset 20h) . . . . . . . . . . . . . . . . . . . . . . . . 8-37 Figure 9-1 Timer 0 and Timer 1 Mode an d Control Regi sters (T0CON , T1CON, offsets 56h and 5Eh) . .[...]

T able of Contents xi LIST OF TABLE S T able 2-1 Instruction S et . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 T able 2-2 Segment Re gister Selectio n Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -8 T able 2-3 Memory Add ressing Mode Examples . . . . . . . . .[...]

T able of Contents xii[...]

Introduction and Overview xiii PREFACE INTRODUCTION AND OVERVIEW DESIGN P HILOSOPHY AMD’s Am186™ and Am188Q™ fami ly of microcont rollers is base d on the archite cture of the origi nal 8086 and 8088 micro contr olle rs, and cu rr ently i ncludes t he 80C18 6, 80C188, 80L186, 80L188, Am186 ER, Am188ER, Am186EMLV, Am188EMLV, Am186ES, Am188ES, [...]

Introduction and Overview xiv n Chapter 4 provid es a desc ri p ti on of the peripheral cont rol block along with power management and r eset configuration. n Chapter 5 provid es a desc ri p ti on of the chip select unit . n Chapter 6 provid es a desc ri p ti on of the int ernal memory . n Chapter 7 provid es a desc ri p ti on of the refresh contro[...]

Features and Performance 1-1 CHAPTER 1 FEATURES AND PERFORMANCE Compar ed to the 80 C186/188 microcontro llers, the Am1 86™ER an d Am188™ER microco ntroller s enable desi gners to incre ase performan ce and funct ionality , wh ile reduci ng the c ost, siz e, and p ower consump tion of e mbedded sy stems. T he Am186ER a nd Am188ER microco ntroll[...]

Features and Performance 1-2 The Am186ER and Am188ER microcontroller s are part of the AMD E86 family of embedded micr ocontroll ers and microproc essors based on the x8 6 archite cture. The 16-b it member s of th e E86 fami ly, re ferr ed to thr oughou t this manual a s the A m186 and Am188 fami ly, in clude t he 80C186, 80C188, 80L186, 80L188, A [...]

Features and Performance 1-3 n Familiar 80 C186 peripherals: – Two independent DMA channels – Pr ogra mmable interrupt co ntr oller with six ext ernal interrupts – Three programmable 16-bi t timers – Progra mmable memory and peripheral chip-selec t logic – Progra mmable wait-state generat or – Power-s ave clock divider n Software-compat[...]

Features and Performance 1-4 Figu re 1- 1 Am1 86ER Micr ocont rol ler Block Diag ram Notes: 1. All PIO si gnals are shared wi th other physic al pins. See the pin des criptions in Chapter 3 and T ab le 3-1 on pag e 3-10 for info rmation on sha red function s. Regist ers Control S2 Interrupt Control Unit Timer Control Unit DMA Unit Bus Interface Uni[...]

Features and Performance 1-5 Figu re 1- 2 Am1 88ER Micr ocont rol ler Block Diag ram Notes: 1. All PIO si gnals are shared wi th other physic al pins. See the pin des criptions in Chapter 3 and T ab le 3-1 on pag e 3-10 for info rmation on sha red function s. 20-Bit Source Poi nte rs Interrupt Control Unit Timer Control Unit DMA Unit Bus Interface [...]

Features and Performance 1-6 1.3 APPLICATION CONSIDERAT IONS The integr ation enhancements of the Am186ER and Am188ER microcontr ollers provide a high-perf or mance, low-system-cos t solution for 16-bi t embedde d microcontroller des igns. The inter nal 32-Kbyte RAM allows the manuf acture of a c om p lete embedded system usi ng only one exter nal [...]

Features and Performance 1-7 1.3. 2 Memor y Inte rface The integrat ed memory c ontr oller logic of the Am186ER and Am188ER microcontroll ers provides a direct addr ess bus interface to memory devices. The use of an external address latch c ontrolled by t he address latc h enable (ALE) signal is n ot required. Individual byte write-enabl e signals [...]

Features and Performance 1-8 1.4 THIRD-PARTY DEVELOPMENT SUPPORT PRODUCTS Th e Fu s io nE 86 Pr ogram of Part nershi ps fo r Ap plicat ion Sol uti ons pr ovides the c ustomer with an arr ay of produc ts de signed to meet criti cal t ime-t o-marke t nee ds. P roduct s and s oluti ons avai lable from the AMD Fu sio nE86 part ners i nclud e emulat ors[...]

Programming 2-1 CHAPTER 2 PROGRAMMING All members of the Am186 and Am188 fami ly of microcontr ollers, includi ng the Am186ER and Am188ER, con tain the same basic set of registers, i nstructions, and addr essing modes, and are c ompatible with the original industry-standard 186/188 parts. 2.1 REGISTER SET The base arch it ecture of the Am186ER and [...]

Programming 2-2 Figu re 2- 1 Regi ster Set 2.1.1 Proce ssor Status Flags Registe r The 16-bit processor Status Flags Register ( Figure 2-2) reco rds specific c haracteristics of the resu lt of logical and arithmetic instructions (bits 0, 2, 4, 6, 7, and 11) and controls the operatio n of the micr ocontroller wi thin a given oper ating mode (bi ts 8[...]

Programming 2-3 Bit 9: Inter rupt-Enable Flag (IF) —When set, enables maskable interrupts to cause the CPU to transfer cont ro l to a location specified by an interrupt vector. Bit 8: Tra ce Flag (TF) —When set, a tr ace interrupt occur s af ter instructi ons execute. TF is cl eared by th e trace interr upt after t he processor st atus flags ar[...]

Programming 2-4 Figure 2-3 Phy s ical Addres s Ge nerat ion 2.3 I/ O SPACE The I/O space consist s of 64K 8-bit or 32K 16-bit port s. The IN and OUT instructions address the I/O space wit h eit her an 8-bit port address spec ified in the instruc tion, or a 16-bit port address i n the DX Regist er. Eight-bit por t addresses ar e zero-extended so tha[...]

Programming 2-5 Table 2-1 Instr uction Set Mnemonic Instruction Name AAA ASCII adjus t for addition AAD ASCII adj ust for division AAM ASCII adj ust for multiplicat ion AAS ASCII adj ust for subtraction ADC Add byte or word with carry ADD Add byte or word AND Logical AND byte or word BOUND Detect s values outs ide prescribed range CALL Call proce d[...]

Programming 2-6 JB/JNAE Jump if below/not ab ove or equal JBE/JN A Jump if below or equa l/not above JC Jump if c arry JCXZ Jump if register CX = 0 JE/JZ Jump if equal/zero JG/JNLE Jump if greater/not l ess or equal JGE/JNL Jump if greater or equal/ not les s JL/JNGE Jump if less/not gr eater or equal JLE/JNG Jump if less or eq ual/not great er JMP[...]

Programming 2-7 OR Logical inclusiv e OR byte or word OUT Output byte or word POP Pop word off stack POP A Po p all gen eral registe r off stack POPF Pop fl ags off stack PUSH Push word onto stack PUSHA Push al l general r egisters onto stack PUSHF Push flags onto stack RCL Rotate left throu gh carry byte or word RCR Rotate right through carry byt [...]

Programming 2-8 2.5 SEGM ENTS The Am186ER a nd Am188ER microcontrolle rs use four segment registers: 1. Data Segment ( DS): The pr ocessor assumes th at all acces ses to the program’s variables a re from the 64K spac e pointed to by t he DS Register. The data segment holds data, ope rands, etc. 2. Code Segment (CS): This 6 4K space is the def aul[...]

Programming 2-9 n String —A c ontiguous sequ ence of bytes or words. A stri ng can contain from 1 b yte up to 64 K b y t e . n Pointe r —A 16-bit or 32-bit quanti ty, composed of a 16-bi t offset component or a 16-bi t segment base component plus a 16-bi t offs et component. In general, indi vi dual data elements must fit within defi ned segmen[...]

Programming 2-10 2.7 ADDRESSING MO DES The Am186ER and Am18 8ER microcontrollers u se eight catego ries of addressing modes to specify operands. Two addressing modes are pro vid ed for inst ruct ions that operate on registe r or immediate operands; six modes are provided to specif y the loc ation of an operand in a memory segment. Registe r and Imm[...]

System Ov erv iew 3-1 CHAPTER 3 SYSTEM OVERVIEW This chapter contai ns descr iptions of the Am186ER and Am188ER microcontroll er pins, the bus int erface unit, the clock and p ower management unit, and the power-save operation. 3.1 PIN DESCRIPTIONS Pin T erminology The followi ng ter ms ar e used to descr ib e the pins: Input —An inpu t-only pin.[...]

System Ov erv iew 3-2 The address phase of these pins can be di sabled. See the ADEN descript ion with the BHE /ADEN pin. When WLB is not asser ted, these pins ar e three-stated during t 2 , t 3 , and t 4 . During a bus hold or reset condition, t he address and dat a bus is in a high-impeda nce state. During a power-on res et, the address and data [...]

System Ov erv iew 3-3 AO8 and AD7–AD0 for the Am188ER mic rocontroller). The addr ess is guaranteed to be val id on the trailing edge of ALE. This pin is three- stated during ONCE mode. ARDY Asynchronous Ready (input, a synchronous, level-sensi tive) This pin indicat e s to the mic rocontroller that the addres sed memory space or I/O device will [...]

System Ov erv iew 3-4 functio nali ty in this instance. See T able 3-1 on page 3-10.) The pin is sampled wit hi n thr ee c rystal c loc k cycl es after t he ris ing edge of RE S. BHE/ADEN is three -stated during bu s holds and ONCE mode. See section 5.5.1 and se cti on 5.5.2 for additional i nfor mation on enabling and di sabling the AD bus during [...]

System Ov erv iew 3-5 When the external bus master has finished using the local bus, it indicate s thi s to the microcontroller b y deasser ting HOLD. The microcontr oller responds by deasserting HLDA. If the micro controller requi res access to the bu s (e.g., for ref resh), it will deassert HLDA bef ore t he external bus master deasserts HOLD. Th[...]

System Ov erv iew 3-6 INT2/ INT A 0 Maskabl e Int errupt Request 2 (input, asynchronous) Interrupt Ack nowledge 0 (output, sy nchronous) INT2 — This pi n indi cates to the microcontrol ler that an interrupt re quest has occurred. If the INT2 pin is not maske d, the microcontro ller transfers program exec ution to the location spe cified by the IN[...]

System Ov erv iew 3-7 LCS /ONCE 0 Lower Memory Chip Select ( output, synchronous, internal pullup) ONCE Mode Request 0 (input) LCS —This pin indicates to the system th at a memory access is in progress to the lower memory block. The size of the lo wer memory block is p rogrammable up to 512 Kbyte. LCS is held High during a bus hold condition. ONC[...]

System Ov erv iew 3-8 executing NMI interrupt service r outine. As with all hard ware interrupts , the IF (int errupt flag) is cleared when the processor ta kes the interrupt, disabling the maskabl e interrupt sources. However , if maskable interr upts are re-enabled by sof tware in the NMI inter rupt service routine (via t he STI instruction for e[...]

System Ov erv iew 3-9 Note: Unlike the UCS and LCS chip selects, the PCS output s assert with t he multiplexed AD add ress bus. Note also that each pe ripheral chip select as sert s over a 256-byte address range, which is twice the address rang e covered by peripher al chip selects in the original 80C186 and 80C188 microcontroller s. A2 —When the[...]

System Ov erv iew 3-10 Table 3-1 PIO Pin Assignmen ts—Numeri c Listing Notes: 1. These pin s are used by emulators. ( Emulators al so use S 2–S 0, RE S , NMI, CLKOUT A, BHE, ALE, AD 15–AD0, and A 16–A0.) 2. These pins rev ert to normal oper ation if BHE /ADEN (Am186ER mi crocontrol ler) or RFSH2/ADE N (Am188E R microcontrol ler) is held Low[...]

System Ov erv iew 3-1 1 Table 3-2 PIO P in Assignment s—Alphabetic L isting Notes: 1. These pin s are used by emulators. ( Emulators al so use S 2–S 0, RE S , NMI, CLKOUT A, BHE, ALE, AD 15–AD0, and A 16–A0.) 2. These pins rev ert to normal oper ation if BHE/AD EN (Am186ER mic rocontroller) or RFSH2/ADEN (Am188E R microcontrol ler) is held [...]

System Ov erv iew 3-12 RD Read Strobe (output, s ynchronous , three-state) RD —This pin indicates to t he sy stem that the microcontr oll er is performi ng a memory or I/O read cycl e. RD is guaranteed not to be asserted befo re the address and data bus is three-stated du ri ng the address-t o-data transiti on. RD is three- stated durin g bus hol[...]

System Ov erv iew 3-13 S 2 Bus Cycle Status (output , thr ee-state, synchronous) S 2 —This pin i ndicates to the system the t ype of bus cycl e in progress. S 2 can be used as a logic al memo ry or I/O in dicator . S 2 – S 0 are th ree-sta ted duri ng bus hol ds, ho ld ackn owledge s, an d ONCE mode. Dur i ng r es et , these pins ar e pullups. [...]

System Ov erv iew 3-14 If CLKSEL 1 is held Low during power-on reset , the chip enters the Divide by T wo clocking mode where the fundamental cl ock is derived by dividing the exte rnal clock input by two. If Divide by T wo mode is selected, the PLL is dis abled. See T able 3-4, “Clocking Modes,” on page 3-16. This pin is l atched within thr ee[...]

System Ov erv iew 3-15 TMRIN1 Ti mer Input 1 (input, synchronous, edge-s ensitive) This pin suppli es a clock or control signa l to the internal microcont roller timer 1. After in ternally synchron izing a Low-to-High transi ti on on TMRIN1, the microcon troller increments t he ti m er . TMRIN1 must be tied High if not bein g used. TMROUT0 Timer Ou[...]

System Ov erv iew 3-16 If CLKSEL 2 is held Low during power-on reset , the processor enters T imes One mode. See T able 3-4. This pin is l atched within thr ee crystal clock cycles af ter the rising edge of RES . Note that clock selec tion must be stable four clock cycl es prior to ex iting reset (i. e., RES goi ng High). UZI /CLKSEL 2 i s three-st[...]

System Ov erv iew 3-17 WR Wr it e Strobe (output, synchronous) WR —This pin indic ates to th e system that the data on t he bus is to be writte n to a memory or I/O device. WR is three-stated dur ing a bus hold or reset condition. X1 Crystal Input (input) This pi n and the X2 pin pr ovide connections for a fundamental mode crystal used by the int[...]

System Ov erv iew 3-18 3.2 BU S OPERATION The indust ry-standard 80C186 and 80C188 microcontr ollers use a mul tiplexed address and data (AD) bus. The add ress is prese nt on the AD bus only during the t 1 clo ck pha se. The Am18 6ER and Am1 88ER microc ontrollers continue to provid e the mul tiplexed AD b us and, in add ition, provi de a no nmulti[...]

System Ov erv iew 3-19 Figure 3-1 Am 186ER M icroco nt r oller Add ress Bus—N o rmal Read and W r i t e Ope r ati on Figur e 3-2 Am1 86ER Mi crocontr oller —Read and W rite with Addr ess Bus Disab le In Ef fect CLKOUT A t 1 t 2 t 3 t 4 AD15–AD0 (Rea d) Dat a AD15–AD0 (W rite) LCS or UCS Address Data Address Address Phase Da ta Phase A19–A[...]

System Ov erv iew 3-20 Figure 3-3 Am 188ER M icroco nt r oller Add ress Bus—N o rmal Read and W r i t e Ope r ati on Figur e 3-4 Am188 ER Micr ocontro ller—Read an d Write with Addr ess Bus Disable In Eff ect CLKOUT A t 1 t 2 t 3 t 4 AD7–AD0 (Read ) Data AO15–AO8 (Rea d or Write) AD7–AD0 (Wri te) Address Address Data Address Address Phase[...]

System Ov erv iew 3-21 3.3 BU S INTERFACE UNIT The bus interf ace uni t controls all access es to external peripheral s and memory devices. External accesses include those to memory d evices, as well as those to memory- mapped and I/O-mapped peripherals and the p eripheral control block. The Am186ER and Am188ER microcont rollers provide an enhanced[...]

System Ov erv iew 3-22 The refresh contr ol unit must be programmed before accessing PSRAM in LCS space. The refresh counter in the Clock Prescaler ( CDRA M) Register must be configured wit h the required r efresh inter val value. The ending address of LCS space and the ready and wait- state generati on in the LMCS Register must al so be progr amme[...]

System Ov erv iew 3-23 3.4 CLOCK A ND POWE R MANA GEMENT UNIT The clock and power management unit of the Am186ER and Am188ER microcontrollers includes a phase- lo cked loop (PLL) and a second programmable system cl ock output (CLKOUTB). 3.4.1 Phase- Locked Loop (PLL) In a tradi tional 80C186/188 design, the cr ystal frequency is tw ice that of the [...]

System Ov erv iew 3-24 3.4. 2 Crysta l- Drive n Cl ock Sour c e The inte rnal oscillator ci rcu it of the microcontro ll er is designed to function wit h a parallel resonant funda mental crystal. Because of the PLL, th e cryst al frequency can be twice, equal to, or one quarter of the processor fr equency. Do not replace a cr ystal with an LC o r R[...]

System Ov erv iew 3-25 3.4.4 System Clock s Figure 3-6 sho w s the organization of the clock s. The 80C186 microcontroll er system clock has been r enamed CLKOUTA. CLKOUTB is provided as an additional output. Figur e 3-6 Clock O rganization CLKOUTA and CLKOUTB operat e at either the CPU cl ock (power-save) frequency or the fundamental cl ock (PLL o[...]

System Ov erv iew 3-26[...]

Peripheral Control Block 4-1 CHAPTER 4 PERIPHERAL CONTR OL BLOCK 4.1 OVERVIEW The Am186ER a nd Am188ER microcontrolle r integrated per ipherals are co ntrolled by 16-bit rea d/write registers. The peri pheral registers are cont aine d within an internal 256- byte cont rol block—the peripher al control block (PCB). Register s are physically loca t[...]

Peripheral Control Block 4-2 Figure 4- 1 P er i pheral Control B l ock Reg i ster Map Chapter 4 Chapter 7 Chapter 10 Chapter 5 Chapter 1 1 PCS and MC S Auxiliary Registe r A8 DA Memory Pa rtition Register E0 PDCON Register F0 Reset Confi gurat io n Regis ter F6 Peripheral Co ntrol Block Rel ocation Regi ster FE Register N ame ww ww ww ww ww F4 Offs[...]

Peripheral Control Block 4-3 Chapter 1 3 Chapter 9 Chapter 8 Chapter 1 2 Offset (Hexadec imal) INT2 Control Register INT1 Contro l Regist er INT0 Con trol Regist er DMA 1 Inte rrupt Control Registe r DMA 0 Inter rupt Co ntrol Re giste r T imer Interrup t Control Register Interrupt St atus Register Interrupt Request Reg ister In-se rvice Regi ster P[...]

Peripheral Control Block 4-4 4.1.1 Per ipheral Control Block Relocatio n Register (RELR EG, Offset FEh) The peripheral control block is mapped into either memory or I /O space by progr amming the Peripher al Control Block Relocation (RELREG) Registe r (see Figure 4-2). This regis ter is a 16-bit r egister at offset FEh f rom the control block bas e[...]

Peripheral Control Block 4-5 4.1.2 R eset C onfigurati o n Register (RESC ON, Offset F 6h) The Reset Configuration (RESCON) Register (see Figure 4-3) in the perip heral contr ol block l atches system-co nfiguration inf ormation that is presented to t he processor on the address/dat a bus (AD15–AD0 for the Am186ER or AO15–AO8 and AD7–AD1 for t[...]

Peripheral Control Block 4-6 4.1. 3 Proc essor Re lease Le vel Re gister (PRL, Offset F4h) The Processor Releas e Level (PRL) Register (Figure 4-4) is a read- only register that specifies the pr ocessor version. The for mat o f the Proc essor Release Level Register is shown in Figure 4-4. Figure 4-4 Proce s sor Rele as e Level Re gister ( PRL, offs[...]

Peripheral Control Block 4-7 4.1.4 Power - Save Control Regi ster (PDCON, Offset F0h) Figure 4-5 Pow er-Save Co ntrol Regis t er (PDCO N, offset F0h) The value of the PDCON Register is 0000h at reset. Bit 15: Enable Power-Save Mode (PSEN) —When set to 1, enables Power-Save mode and divi des the inter nal operating cl ock by the value in F2–F0. [...]

Peripheral Control Block 4-8 Bits 2–0: Clock Divisor Select (F2–F0) — Cont r ols the division fact or when Power-Save mode is en abled. Allowabl e values are as follows: 4.2 INITIALIZATION AND PROCESSOR RESET Processor ini tial izat ion or start up is acco mplished by drivi ng the RES input pin Low. RES must be Low during power-up to ensu re [...]

Peripheral Control Block 4-9 Table 4 -2 Initial Register St ate After Rese t Note: Registers not listed i n this table a re undefined at reset. Register Name Mnemonic Val ue at Reset Comments Process or Status Flags F F002h Interru pts disabled Instructio n Pointer IP 0000h Code Segment CS FFFFh Boot address is FFFF0h Data Segme nt DS 00 00h DS = E[...]

Peripheral Control Block 4-10[...]

Chip Select Unit 5-1 CHAPTER 5 CHIP SELECT UNIT 5.1 OVERVIEW The Am186ER and Am188ER microcontrol lers contai n logi c that prov ides pr ogrammable chip sel ect generati on for both memories and peripherals. In addition, the logic c an be programmed to pr ovide ready or wait -state generation and l atched address bits A1 and A2. The chip s elect li[...]

Chip Select Unit 5-2 Except for the UCS chip sel ect, which is activ e on reset as di scussed in section 5.5.1, external memory chip sel e ct s are not act ivated until the asso ci ated registers have been accessed by a wr ite operati on. The LCS chip sel ect is activated when the LMCS Register is written, the MCS chip selec ts are activated after [...]

Chip Select Unit 5-3 When overla pping an addit ional chip select with eit her the LCS or UCS chip sele cts, it must be noted that settin g the Disable Addres s (DA) bit in the LMCS or UM CS Register wil l disable the address from b eing driven on the AD bus for all accesses f or which the associate d chi p sel ect is ass ert ed, includi ng any a c[...]

Chip Select Unit 5-4 5.5.1 Upp er Memory Chip Sele ct Registe r (UMCS, Offset A0h) The Am186ER and Am188ER microcontrolle r s provi de the UCS chip selec t pin fo r the top of memory. On r eset, the microcontr oller begins fetc hing and executing inst ructions starti ng at memory locat ion FFFF0h, so upper memory i s usually used as i nstr ucti on [...]

Chip Select Unit 5-5 Bits 11–8: Reserved Bit 7: Disable Addre ss (DA) —The DA bit enables or disables th e AD15–AD0 bus during the addres s phase of a b us cycle when UCS is assert ed. If DA is se t to 1, AD15–AD0 is not driven during th e address phase of a bus cycle when UCS is assert ed. If D A is s et to 0, AD15–AD0 is driven duri ng [...]

Chip Select Unit 5-6 5.5.2 L ow Memory Ch ip Select Register (L MCS, Offset A2h) The Am186ER and Am188ER microcontrollers provide the LCS chip select pin for the bottom of memory. Because th e interrupt vector table i s located at 00000h at the bottom of memory, the LCS pin has been provided to fac ilitate this usage. The LCS pin is not active on r[...]

Chip Select Unit 5-7 Bits 11–8: Reserved— Set to 1. Bit 7: Disable Addre ss (DA) —The DA bit enables or disables th e AD15–AD0 bus during the addres s phase of a b us cycle when LCS is asserted. If DA is set to 1, AD15–AD0 i s not driven during th e address phase of a bus cycle when LCS is asser ted. If DA is set to 0, AD15–AD0 is drive[...]

Chip Select Unit 5-8 5.5.3 Midr ang e Memory Chip Select Regi ster (MMCS, Offset A6h) The Am186ER and Am188ER microcontrol lers provide four chip select pins, MCS 3 –MCS 0, for use withi n a user-locatable memory block. The base address of the memory block can be located anywhere within the 1-Mbyte memory address space, excl usive of the areas as[...]

Chip Select Unit 5-9 be active in t his case. Use of the MCS chip se lects to acc ess low memory all ows the timing of these access es to follow the AD address bus rat her than the A address bus. Locat ing a 512K MMCS block at 80000h always conflict s with the range of the UCS chip select and is not allo wed. Bits 8–3: Reserved —Set to 1. Bit 2[...]

Chip Select Unit 5-10 5.5. 4 P CS and MC S Auxiliary Reg ister (MPCS, Offset A8h) The PCS and MCS Auxiliary (MPCS) Register (see Figure 5-4 ) differs from the other chip select control regist ers in that i t contains fi elds that perta in to more t han one type of chip select. The MPC S Regi ster fields prov ide program informati on for MCS 3 –MC[...]

Chip Select Unit 5-1 1 Bit 7: Pin Selector (EX) —This bi t determines whether the PCS 6–PCS 5 pins are conf igured as chip selects or as alternate outp uts for A2–A1. When this bit i s set to 1, PCS 6–PCS 5 are confi gured as peripheral chip select pins. When EX is set to 0, PCS 5 b ecomes address bit A1 and PCS 6 becomes address bit A2. Bi[...]

Chip Select Unit 5-12 5.5.5 Per i pheral Chi p Select Regist er (PACS, Offset A4h) Unlike the UCS and LCS chip sele cts, the PCS output s assert with the same t iming as the multiplexed AD address bus. Also, each peripheral chip sel ect asserts over a 256-byte address range, which is twi ce the address range covered by peripheral chi p selects in t[...]

Chip Select Unit 5-13 microcont roller in which bit 6 was set with a meaningful value would not produce t he address expected on the Am186ER. When the PCS chip selects are mapped to I/ O space, BA19 –16 must be prog rammed to 0000b be cause the I/O addres s bus is onl y 16-bits wide. Table 5-5 PCS A ddress Ranges Bits 6–4: Reserved —Set to 1.[...]

Chip Select Unit 5-14[...]

Internal Memory 6-1 CHAPTER 6 INTERNAL MEMORY 6.1 OVERVIEW The Am186ER a nd Am188ER microcontrolle rs provide 32 Kbyt e of on-chip RAM. The integrat i on of memor y helps r educe a system design’s overall cost, si ze, and power consumption. The internal RAM for the Am186ER microcon troller is a 16K x 16-bit-wide arr ay, which provides the same pe[...]

Internal Memory 6-2 6.3 EMULATOR AND DEBUG MODE S There are t w o debug modes associated with the inte rnal memory. One mode allows users to disable t he in t ernal RAM, and the other mode makes it possible to drive data on the external data bus duri ng internal RAM read cycles. Normal opera ti on of i nte rnal RAM has all contr ol si gnals f or re[...]

Internal Memory 6-3 6.4 INTERNAL MEMORY CHIP SELECT REGISTER (IMCS, OFFSET ACh) The Inter nal Memory Chip S elect (IMCS) Regi ster provides programmable chip select generati on for the in ternal RAM. It al lows the base addr ess of the inter nal memory space to be placed o n any 32- Kbyte boundar y. The regi ster als o contains a cont rol bi t to e[...]

Internal Memory 6-4[...]

Refresh Control Unit 7-1 CHAPTER 7 REFRESH CONTROL UNIT 7.1 OVERVIEW The Refresh Control Un it (RCU) automat ically generates refresh bus cyc les. After a programmable period of t ime, the RCU generates a memory read request to the bus interf ace uni t. The RCU is fi xed to three wait states for the PSRAM auto refresh mode. The Refresh Cont rol Uni[...]

Refresh Control Unit 7-2 7.1.2 Clo ck Prescaler Register (CDRA M, Offset E2h) Figur e 7-2 Clock P rescale r Register ( CDRAM, of fset E2h) The CDRAM Register is undefined on reset . Bits 15–9: Reserved —Read back as 0. Bits 8–0: Refresh Counter Reload Value (RC8–RC0) —Contains the value of the desi red clock count in ter val between refre[...]

Interrupt Control Unit 8-1 CHAPTER 8 INTERRUPT CONTROL UNIT 8.1 OVERVIEW The Am186ER and Am 188 ER m icr ocontrollers can receive inter rupt requests from a variety of sources, both int ernal and external. The in ter nal interrupt control ler arranges these requests by prio ri ty and presents them one at a time to the CPU. There are six exte rnal i[...]

Interrupt Control Unit 8-2 The process or calculates the index to t he interrupt ve ctor table b y shifting the interrupt type left 2 bits (mult i plying by 4). 8.1. 1.3 Maskab le and Non maskable I nterrupt s Interr upt types 08h through 1Fh a re maskable. Of the se, only 08h thro ugh 14h are actually in use (se e Table 8-1 ). The maskable int err[...]

Interrupt Control Unit 8-3 8.1. 1.8 Soft ware Exc eptions A software exception interru pt occurs when an ins truction causes an i nterrupt due t o some conditi on in the processor. Interrupt ty pes 00h, 01h, 03h, 04h, 05h, 06h, and 07h are software exc eption interrup ts. Software exceptions ar e not maskable and are not affec ted by the s etting o[...]

Interrupt Control Unit 8-4 8.1. 2 Inter rupt C onditi ons and Sequenc e Interr upts are general ly service d as foll ows. 8.1. 2.1 Nonm askable Inte rrupts Nonmaskable inte rr upts—the trace interrupt, the NMI int errupt, and software interr upts (inclu ding both user- defined INT stat ements and softwar e exceptions)—are serviced regardles s o[...]

Interrupt Control Unit 8-5 8.1. 3 Inter rupt Prio rity Table 8-1 shows the predef ined types and overal l priority st ructure for t he Am186ER and Am188ER microcontroll ers. Nonmaskable i nterrupts (inter rupt types 0–7) ar e always higher priori ty than maskable interrupts. Maskabl e int errupts have a programmable priorit y that can overr ide t[...]

Interrupt Control Unit 8-6 8.1.4 Sof tware Except io ns, Traps, and NMI The foll owing predefined i nterrupts cannot be masked by progr amming. 8.1.4. 1 Divi de Error Exce pt i on (Inter rupt Type 00 h) Generated when a DIV or I DIV inst ructi on qu otient cannot be ex pressed i n th e number of destinat ion bits. 8.1. 4.2 Trace Interrupt (Inter ru[...]

Interrupt Control Unit 8-7 8.1. 4.4 Break point Int errupt (I nterrupt T ype 03h) An inter rupt caused by the 1-byte ve rsion of th e INT instructi on (INT3). 8.1. 4.5 INTO De tected O verflow Exc eption (In terrupt Type 04h) Generated by an INTO ins truction if the OF bit is set in t he Processor Status Flags (FLAGS) Register. 8.1.4 . 6 Arra y BOU[...]

Interrupt Control Unit 8-8 8.1. 5 Inter rupt A cknowle dge Interr upts can be a cknowledged in two different ways—the int ernal interrupt contr oller can provide t he int errupt type or an extern al i nterr upt control ler can pr ovide t he inte rr upt type. The processor requ ires the interrupt type as an index into the interrupt vecto r table. [...]

Interrupt Control Unit 8-9 8.1. 6 Inter rupt Con troller Re set Cond itions On reset, the interr upt controller pe rforms the f ollowing nine act ions: 1. All specia l fully nested mode (SFNM) bits are reset, implyi ng fully nested mode. 2. All priori ty (PR) bits in the various control registers are set to 1. This places all sources at the lowe st[...]

Interrupt Control Unit 8-10 8.2 MASTER MODE OP ERATION This sect ion describes Mast er mode operati on of the in ternal interr upt controller. See section 8.4 on page 8-29 for a d escription of Slave mode operation. Six pins are provided f or external interrupt s ource s. One of these pins is NMI, the nonmaskable int errupt. NMI is generally used f[...]

Interrupt Control Unit 8-1 1 8.2.2 C ascad e Mode The Am186ER and Am188ER microc ontrollers have fiv e interrupt pins, two of which (INT2 and INT3) have dual func tions. In fully nested mode, the fi ve pins are used as direct interrupt inputs and the correspo nding interrupt ty pes are generated internall y. In Cascade mode, four of the five pi ns [...]

Interrupt Control Unit 8-12 8.2.3 Spe cial Fully Nested Mode Special fully nested mode is entered by setting th e SFNM bit in the INT0 or INT1 co ntrol registe rs. (See section 8.3.1 on page 8-14.) It enabl es complete nesting with external 82C59A masters or multipl e in t errupts from the same external int err upt pin when not in Cascade mode. In [...]

Interrupt Control Unit 8-13 8.3 MASTER MODE INTE RRUPT CONTROLLER REGISTERS The inter rupt controller registers for Master mode are shown in Ta ble 8-2. All the registers can be r ead and written unless otherwise specified. Registers ca n be redefi ned in Slave mode. See section 8.4 on page 8-29 for det ail ed informat ion regarding Slave mode regi[...]

Interrupt Control Unit 8-14 8.3.1 INT 0 and INT1 Contr ol Registers (I0CON , Offset 38h, I1CO N, Offset 3Ah) (Master Mo de) The INT0 i nterrupt i s assigned to in terrupt type 0Ch. The INT1 inter rupt is as signed to interr upt t ype 0Dh. When Cascade mode is enabled fo r INT0 by se tting t he C bit of I0 CON to 1, the I NT2 pin becomes INTA 0, t h[...]

Interrupt Control Unit 8-15 Bits 2–0: Priority Level (PR2–PR0) —This fi eld determines t he priority of INT0 or INT1 relati ve to the ot her inter rupt signals, a s shown in Tab le 8-3, “Pri ority Level ,” on page 8-1 5. Table 8 -3 Priority Level Priority PR2 –PR0 (High) 0 0 0 0b 10 0 1 b 20 1 0 b 30 1 1 b 41 0 0 b 51 0 1 b 61 1 0 b (Lo[...]

Interrupt Control Unit 8-16 8.3.2 INT 2 and INT3 Contr ol Registers (I2CON, Offse t 3Ch, I3 CON, Offset 3Eh) (Master Mo de) The INT2 interr upt i s a ssigned to interrupt type OEh. The INT3 in ter rupt is assigned to interr upt t ype 0Fh. The INT2 and INT3 pins can be configured as inte rrupt acknowledge pins INTA 0 and INTA1 when Cascade mode is i[...]

Interrupt Control Unit 8-17 8.3.3 INT 4 Control Re gi ster (I4CON, Off set 40h) (Master Mo de) The Am186ER a nd Am188ER microcontrolle rs provide INT4, an additional external interr upt pi n. This input behaves like INT3–I N T 0 on th e 80C186 /188 mic rocontroller with the except ion that INT4 i s only intended for use as a nested-mode interru p[...]

Interrupt Control Unit 8-18 8.3.4 Ti m er and DMA Interr upt Control Regist er s (TCUCON, Offset 32h, DMA0 CON, Offset 34h, DMA1CON, Offset 36h) (Master Mo de) The three t imer interrupts are as signed to inter rupt types 08h, 12h, and 13h. All three t imer interr upts are configured th rough TCUCON, offset 32h. The DMA0 int errupt is assigned to i[...]

Interrupt Control Unit 8-19 8.3.5 Watc hdo g Timer Interrupt Con trol Register (WDCO N , Offset 42h) (Master Mo de) The watch dog t imer is implemented by co nnecting the TMROUT1 output to an additional internal interrupt to cr eate the watchdog timer i nterrupt. This int errupt is assigned to i nterrupt type 11h. The contro l regi ster format is s[...]

Interrupt Control Unit 8-20 8.3.6 Serial Port In terrupt Co ntrol Reg ister (SPICON, Offse t 44h) (Master Mo de) The Serial Port Inte rrupt Control (SPICON) Register cont rols the operation of the asynchronous ser ial port interrupt source ( SPI, bit 10 in the Interrupt Request Reg ist er ). This inter rup t is assigned to interrupt type 14h. The c[...]

Interrupt Control Unit 8-21 8.3.7 Interrupt Status Register (INTSTS, Offset 30h) (Master Mo de) The Interr upt Status (INTSTS) Register indi cat es the interrupt request status of the three time rs. Figure 8-10 Interrupt Stat us Reg ister (INTSTS, offset 30h) Bit 15: DMA Halt (DHLT) —When set to 1, hal ts any DMA activity. Thi s bit is automatica[...]

Interrupt Control Unit 8-22 8.3. 8 Inter rupt R equest Regist er (REQS T, Offse t 2Eh) (Master Mo de) The hardware inter ru pt sources have interrupt reques t bits inside the interr upt co ntroller. A read from this regist er yields the status of these bits. The Inte rrupt Request (REQST) Register is a read-on ly register. The form at of th e Inter[...]

Interrupt Control Unit 8-23 8.3. 9 In-Ser vice Re gist er (INSER V, Offse t 2Ch ) (Master Mo de) The bits in the In Service (INSERV) Regist er are set by the interrupt controller when the interr upt is taken. Each bit in the re gister is c lear ed by writing the c orresponding int e r rupt type to the End-of-Inter rupt (EOI) Reg ister. See Table 8-[...]

Interrupt Control Unit 8-24 8.3.10 Priori ty Mask Regi ster (PRIMSK, O ffset 2Ah) (Master Mo de) The Priori ty Mask (PRI MSK) Regist er provides the value that deter m ines t he minimum priori ty level at which maskable interru pts can generate an interrupt. Figur e 8-13 Pr iority Mas k Register ( PRIMSK, of fset 2Ah) The value of PRIMSK at reset i[...]

Interrupt Control Unit 8-25 8.3.1 1 Inte rrupt Mask Re gister (IMASK, Offset 28h) (Master Mo de) The Interru pt Mask (IMASK) Register is a read/write register. Progr am ming a bit in the IMASK Register has the ef fect of programming the MSK bit in the associated control registe r. The format of the IMASK Register is shown in Figure 8-14. Do not wr [...]

Interrupt Control Unit 8-26 8.3.12 Poll St at us Register (POLLST, Offset 26 h) (Master Mo de) The Poll Status (POLLST) Regist er mirrors t he current st ate of the Poll Register. The POLLST Register can be read without af fecting the curren t interrupt reque st. But when the Poll Register is read, the current int errupt is acknowledged and the nex[...]

Interrupt Control Unit 8-27 8.3. 13 Poll R egiste r (POLL , Offs et 24h) (Master Mo de) When the Poll Register is rea d, the current interrupt is acknowl edged and the next interrupt takes its place in the Poll Regi st er. The Poll Statu s Reg ist er mirrors the current state of t he Poll Register, but the Pol l St atus Register can be read without[...]

Interrupt Control Unit 8-28 8.3.14 End-of- Interrupt Regist er (EOI, Offset 22h) (Master Mo de) The End-of- Interrupt (EOI) Register is a write-only re gister. The in-service flags in the In - Service Registe r (see section 8.3.9 on page 8- 23) are reset by writin g to t he E OI Regis ter. Before execut ing the IRET instr uction that ends an int er[...]

Interrupt Control Unit 8-29 8.4 SLAVE MODE OPERA TI ON When Slave mode is used, the microcontr oller’s internal int errupt controller is used as a slave con troller to a n external mast er interrupt controller. The internal int errupts are monitored by t he internal i nterrupt cont roller, wh ile the exter nal controll er functions as the system [...]

Interrupt Control Unit 8-30 8.4.3 Ti m er and DMA Interr upt Control Regist er s (T0INTCON, Offse t 32h, T1INTCON, Offset 38h, T2INTCON , Offset 3Ah, DMA0CON, Offset 34h, DM A1CON, Offset 36h) (Slave Mode) In Slave mode , there ar e three s eparate regi sters for the three timers. I n Master mod e, all three timers are masked and prior itized in on[...]

Interrupt Control Unit 8-31 8.4.4 Interrupt Status Register (INTSTS, Offset 30h) (Slave Mode) The Inter rupt Status Register control s DMA activity when nonmaskable inter rupts occur and indi cates the current interrupt st atus of the three timers. Figure 8-20 Interrupt Stat us Reg ister (INTSTS, offset 30h) The INTSTS Register is se t to 0000h on [...]

Interrupt Control Unit 8-32 8.4. 5 Inter rupt R equest Regist er (REQS T, Offse t 2Eh) (Slave Mode) The in ternal inte rrupt sources hav e interrupt request bits inside the interrupt controller. A read from this regi ster yields the status of these bits. The Int er rupt Request Register is a read-only regi ster. The format of the Interr upt Reques [...]

Interrupt Control Unit 8-33 8.4. 6 In-Ser vice Re gist er (INSER V, Offse t 2Ch ) (Slave Mode) The format of the In-S ervice Register is shown in F igure 8-22. The bi ts in the In -Service Register ar e set by t he interrupt control le r when the interrupt is take n. The in-service bits are cleared by wri ting to the End-of-Interrup t (EOI) Registe[...]

Interrupt Control Unit 8-34 8.4.7 Priori t y Mask R egister (PRIMSK, Offset 2Ah ) (Slave Mode) The format of the Prior ity Mask Register is shown in Figure 8-23. The Prior ity Mask Register provides the value that de termines the minimum priority level at which maskable interr upts can generat e an interr upt. Figur e 8-23 Priority Mask Regi ster ([...]

Interrupt Control Unit 8-35 8.4. 8 Inter rupt Mask Regis ter (IMASK , Offset 28h) (Slave Mode) The format of the Inte rrupt Mask Register is shown i n Figure 8-24. Th e Interrupt Mask Register is a read/ write r egister. Programming a bit in t he Interr upt Mask Register has the effect of progra mming the MSK bit in the associated control re gister[...]

Interrupt Control Unit 8-36 8.4.9 Speci fic End-of-Interrupt Register (EOI, Offset 22h ) (Slave Mode) In Slave mode , a write to the EOI Register reset s an in-service bit of a spec ific priority. The user suppli es a three-bit priori ty-level value that poi nts to an in-service bit to be res et. The command i s executed by writ ing the correct val[...]

Interrupt Control Unit 8-37 8.4.1 0 Inte rrupt Vect or Register (INTVEC, Off set 20h) (Slave Mode) Vector generat io n in Slave mode is exactly like th at of an 8259A or 82C59A slav e. The interr upt cont roller generates an 8-bit int errupt type that the CPU shifts left two bits (multi plies by four) to generat e an offset into the inter rupt vect[...]

Interrupt Control Unit 8-38[...]

Timer Control Unit 9-1 CHAPTER 9 TIMER CONTROL UNIT 9.1 OVERVIEW There are three 16- bit p rogrammable timers in the Am186ER and Am188ER microcont rollers. Timers 0 and 1 are highly versat ile and are each connected to two external pins (each one has an input and an output ). These two timers can be used to count or time external events, or they ca[...]

Timer Control Unit 9-2 Each timer also has a correspond ing maximum-count register that defi nes the maximum value for the t imer. When the timer reaches the maximum value, it reset s to 0 during the same clock cycl e. (The value in the ti mer-count registe r never equals the maximum-count registe r.) In additi on, timers 0 and 1 h ave a secondary [...]

Timer Control Unit 9-3 9.2.2 Timer 0 and Timer 1 Mode and Contr ol Reg isters (T0CON, Offset 56h, T1CON, Offset 5Eh ) These regist ers cont rol the functionali ty of ti mer 0 and timer 1. See Figure 9- 1. Figure 9-1 Timer 0 and Timer 1 Mo de and Con tr o l Registers (T0CON, T1 CON, of fsets 56h and 5Eh) The value of T0CON and T1CON at reset is 0000[...]

Timer Control Unit 9-4 Bit 2: External Clock Bit (EXT) —When set to 1, an external clock is used. When set to 0, the i nternal clock i s used. When the int ernal clock is us ed, the timer input pin i s available for use as a programmable I/ O pin. Bit 1: Al ternate Compare Bit (A LT) —W he n set to 1, the timer counts to maxcount compare A, the[...]

Timer Control Unit 9-5 9.2.3 Ti m er 2 Mode and Contr ol Register (T2CON, Offset 66h) This regis ter controls the funct ionality of timer 2. See Figure 9-2 . Figur e 9-2 Timer 2 Mode and Co ntrol Register (T2 CON, off set 66h) The value of T2CON at reset is 0000h. Bit 15: Enable Bit (EN) —When EN is set to 1, the ti me r is enabled. When set to 0[...]

Timer Control Unit 9-6 9.2.4 Ti m er Count Registe rs (T0CNT, Offset 5 0h, T1CN T, Offset 58h, T2CNT, Offset 60h) These registe rs can be incremented by one every four inter nal processo r cloc ks. Timer 0 and timer 1 can also be configured to increment based on the TMRIN0 and TMRIN1 external signals, o r they can be prescaled by t imer 2. See Figu[...]

Timer Control Unit 9-7 9.2.5 Timer Ma xcount Compare Registers (T0CMPA , O ffset 52h, T0CMPB, Off s et 5 4h, T1CMPA, O ffset 5Ah, T1CMPB, Offset 5Ch, T2CMPA, Offset 62h) These regist ers ser ve as c omparat ors for their associat ed c ount re gisters. Timer 0 and timer 1 each have two maxi mum count compare r egisters. See Fi gure 9-4. Timer 0 and [...]

Timer Control Unit 9-8[...]

DMA Controller 10-1 CHAPTER 10 DMA CONTROLLER 10.1 OVERVIEW Direct mem ory access (DMA) p ermits transfe r of data between memory and periphe rals without CPU i nvolvement. The DMA unit in t he Am186ER and Am188ER microcontrollers provides two high-s peed DMA channel s. D at a t ra n sf er s c a n o cc ur be t we en me mo r y a nd I/ O space s (e.g[...]

DMA Controller 10-2 Figure 10 -1 DMA Un it Bloc k Diagr am 10.3 PROGRAMMABLE DMA REGISTERS The secti ons on the following pages describe the control register s that are used to configure and operate the two DMA channels. Source Addre ss Ch. 1 Source Addre ss Ch. 0 20-bit Add er/Subtractor DMA Control Logic Request Selectio n Logic Adde r Control Lo[...]

DMA Controller 10-3 10.3.1 DMA Control Registers (D0CON, O ffset CAh, D1CON, Offset DAh) The DMA control regi sters (see Figure 10-2) dete rmine the mode of operation for t he DMA channels. These r egis ters specify the following opt ions: n Whether th e destination address is memory or I/O space n Whether the d estination address i s incremented, [...]

DMA Controller 10-4 Bit 11: Source Decrement (SDEC) —When SDEC is set to 1, the source addre ss is automatica lly decremented after each trans fer . The address decrements by 1 or 2 depending on the byt e/word bit (B /W, bit 0) . The address remains constant if the increment and decrement bits are set to the s am e value (00 b or 11b). Bit 10: So[...]

DMA Controller 10-5 10.3.2 DMA Transfe r Count Registers (D0TC, Offset C8h, D1TC, Offset D8h) Each DMA channel maintains a 16-bit DMA Transfer Count register (DTC). This regi ster is decremented af ter ev ery DMA cycle , regardless of the state of the TC bit in the DMA Control regi ster. However, if the TC bit in the DMA control word is set or i f [...]

DMA Controller 10-6 10.3.3 DMA Dest ination Address High Register (High Orde r Bits) (D0DSTH, Offset C6 h, D1DSTH, Offset D6h) Each DMA channel maintain s a 20-bi t destination and a 20-bit sour ce register. Each register takes up two full 16 -bit registers (the high regi st er and the low register) in the peripher al control block. For each DMA ch[...]

DMA Controller 10-7 10.3.4 DMA Dest ination Ad dress Low Regi ster (Low Order Bi ts) (D0DSTL, Offset C4h, D 1DSTL, Of fset D4h) Figure 10 -5 shows the DMA Dest ination Address L ow register. The sixteen bi ts of this registe r are combined with the fou r bits of the DMA Destination Address High register (see Figure 10 -4) to produce a 20-bit desti [...]

DMA Controller 10-8 10.3.5 DMA Source A ddres s High Regi ster (High Order Bits) (D0SRCH, Offset C2h, D1SRCH, Offset D2h) Each DMA channel maintain s a 20-bi t destination and a 20-bit sour ce register. Each register takes up two full 16 -bit registers (the high regi st er and the low register) in the peripher al control block. For each DMA channel[...]

DMA Controller 10-9 10.3.6 DM A Source Addres s Low Regist er (Low Order Bi ts) (D0SRCL, Offset C0h, D1SR CL, Offset D0h) Figure 10-7 shows t he DMA Source Address Low regist er. The sixteen bits of this register are combine d with the f our bits of t he DMA Source Address High register (see Figure 10- 6) to produce a 20-bi t source addres s. Figur[...]

DMA Controller 10-10 10.4 DMA REQUES TS Data tran sfers c an be either sour ce or desti nati on synchro niz ed—eith er the source of the data or the destinati on of the da ta can request the data tr ansfer. DMA transfe rs can also be unsynchroniz ed (i.e., the transfer takes pl ace cont inually until the cor rect num b er of transfer s has occur [...]

DMA Controller 10-1 1 10.4. 1 Synchr onization Ti ming DRQ1 or DRQ0 must be deasserted befo re the end of the DMA transfer t o p revent another DMA cycle fro m occurring. The t i ming for the required deassertion depends on whether the tr ansfer is so urce-synchron ized or destinat ion-synchro nized. 10.4.1.1 Sou rce Synchro nization Ti mi ng Figur[...]

DMA Controller 10-12 Figur e 10-9 Destinat ion Sync hroni zed DMA T ransfer s Notes: 1. This dest ination-sy nchronized transfer is n ot followed im mediately b y another DM A transfer. 2. This desti nation-synch ronized transf er is immediate ly followed by anoth er DMA transfer be cause DRQ is n ot deasserted s oon enoug h. 10.4. 2 DMA Ac knowled[...]

DMA Controller 10-13 Each DMA register can be modified whil e the channel is operating. I f the CHG bit i s set to 0 when the control regist er is writ ten , th e ST bit of the contr ol register wi ll not be modified by the wri te. If multi ple channel registe rs are modified, an internally LOCKed string tran sfer should be used to prevent a DMA t [...]

DMA Controller 10-14[...]

Asynchronous Serial Port 11 - 1 CHAPTER 11 ASYNCHRONOUS SERIAL PORT 11.1 OVERVIEW The Am186ER and Am188ER microcontrollers pr ovide an asynchronous serial port . The asynchronous ser ial port is a two-pin interf ace that permits full-dup lex bidirectional data transfer . The asynchrono us serial port supports the following featu res: n Full-du plex[...]

Asynchronous Serial Port 11 - 2 11.2.1 Serial P ort Control Re gister (SPCT , Offset 80h) The Serial Port Control register controls both the transmit and receive sectio ns of the serial port. The for m at of the Ser ial Port Control register i s shown in Figu re 11-1. Figur e 11-1 Serial P or t Control Register (SP CT , of fset 80h) The value of SP[...]

Asynchronous Serial Port 11 - 3 Bits 6–5: Par ity Mode (PMODE) —This field specifi es how parity generati on and checking are performed dur ing t ransmission and reception, as shown in Table 11-2 . Table 11-2 Parity Mode Bi t Settings If parity checki ng and generation is selected, a parit y bit is received or sent in additi on to the specified[...]

Asynchronous Serial Port 11 - 4 11.2.2 Serial P ort Status Register (SPSTS, Offset 82h) The Serial Port Status regi ster indic ates the st atus of t he tr ansmit a nd r eceive sect ions of the serial p ort . The format of the Serial Port Status regi ster is shown in Figure 11-2. Figure 11-2 Seria l Por t Status Register (SPSTS, offset 82h) Bits 15?[...]

Asynchronous Serial Port 11 - 5 11.2.3 Serial P ort Transmit Data Register (SPTD, Offset 84h) Software writes this register (Figure 11-4) wit h data t o be transmitted on the serial port. The transmit ter is double- buffered, and t he transmit sect ion copie s data from the transmit data regist er to the transmit shift regis ter (which is not acces[...]

Asynchronous Serial Port 11 - 6 11.2.4 Serial Por t Receive Data Regis ter (SPRD, Offset 86h) This regis ter (Figure 11-4 ) cont ains data received ove r the ser ial port. The receiv er i s double-buf fered, and the receive sectio n can be recei ving a subsequent frame of data in the recei ve shift regist er (which is not ac cessible to software) w[...]

Asynchronous Serial Port 11 - 7 11.2.5 Serial Port Baud Rate Divisor Re gister (SPBAUD, Offset 88h) This regis ter (Figure 11-5 ) speci fies a clock divisor for the generation of the seri al cl ock that cont rols the seri al port . The serial clock rat e is 16 times the baud rate of transmissi on or recepti on of data. The SPBAUD register specifies[...]

Asynchronous Serial Port 11 - 8[...]

Synchronous Serial Interface 12-1 CHAPTER 12 SYNCHRONOUS SERIAL I NTERFACE 12.1 OVERVIEW The synchro nous serial i nterface enables the Am186ER and Am188ER micr ocontrollers to communicate wit h appli cation-specific int egrated circuits (ASI Cs) that require programmabilit y but are short on pins. The four-pin inte rface permits half-dupl ex, bidi[...]

Synchronous Serial Interface 12-2 12.1.1 Fou r-P in Interf ac e The SDEN1–SDEN0 pins can be used to enable data transfer indiv idually for as many as two peri pheral devices. Transmit and receive oper ations are synchr onized between t he master (Am186ER or Am188ER microcontrol ler) and slave (peripheral) b y means of the SCLK output. SCLK is der[...]

Synchronous Serial Interface 12-3 12.2.1 Synchronous Ser ial Status Register (SSS, Offset 10h) This read-o nly register in dic ates t he sta te of the SSI port. The forma t of the Synchr onous Serial Stat us reg ister is shown in Figure 12-1. Figur e 12-1 Synchr onous Seri al Status Re gister (SSS, offse t 10h) The value of the SSS register at re s[...]

Synchronous Serial Interface 12-4 12.2.2 Synchrono us Serial Control Reg ister (SSC, Offset 12h) This read/wr ite register controls the operation of the SDEN0–SDEN1 outputs and the transfer rat e of the SSI port . The SDEN0 and SDEN1 outputs are asserte d when a 1 is writte n to the correspo nding bit. However, in the case when both DE0 and DE1 a[...]

Synchronous Serial Interface 12-5 12.2.3 Synchrono us Serial Transmit 1 Regi ste r (SSD1, Offset 14h) Synchrono us Serial Transmit 0 Registe r (SSD0, Offset 16h) The Synchronous Serial Transmit 1 and 0 regis t er s contain data t o be transferred from the processor to the pe ri pheral on a write operation. Only the leas t-significant 8 bits of t he[...]

Synchronous Serial Interface 12-6 12 . 2 .4 Synchronous Serial Receive Register (SSR, Offset 18h) The Synchronou s Seri al Recei ve (SSR) r egister contains the data transf erred from the periphera l to the processor on a read operation. Only the leas t- significant 8 bits of the register are used. The format of the SSR regis ter is shown in Figure[...]

Synchronous Serial Interface 12-7 12.3 SSI PROG RAMMING The SSI i nterface allows for a variety of software and hardware protocol s. n Signaling a read/wri te —In general, softwa re uses the first wri te to the SSI to t ransmit an address or count to th e per i pheral. This value can include a read/wri t e fla g in t he case where the device supp[...]

Synchronous Serial Interface 12-8 Figure 12- 5 Synchrono us Serial Int e rfac e Multiple Writ e Figure 12- 6 Synchrono us Serial Int e rfac e Multiple R ea d SCLK SDEN SDA T A Wr ite to SSC bit D E=1 Wr ite to SSD Poll SSS fo r PB=0 Wr ite to SSD Poll SSS for PB=0 Wr ite to SSD Wri te to SSC bi t DE=0 Poll SSS for PB=0 PB=0 DR/DT=0 PB= 1 DR/DT=0 PB[...]

Programmable I/O Pins 13-1 CHAPTER 13 PROGRAMMABLE I/O PINS 13.1 OVERVIEW Thirty-two pins on the Am186ER and Am188ER microcontr ol lers are available as user- programmable I/ O signa ls (PIOs). Each of these pins can be used as a PIO if the normal functio n of the pin is not needed. If a pin is enabled t o function as a PIO si gnal, the normal func[...]

Programmable I/O Pins 13-2 Table 13 - 1 PIO Pin As s i gnments an d Register B its Notes: 1. These pin s are used by emulators. ( Emulators al so use S 2–S 0, RE S , NMI, CLKOUT A, BHE, ALE, AD 15–AD0, and A 16–A0.) 2. These pins revert to normal ope ratio n if BHE /ADEN (Am186ER) or RFSH 2/ ADEN (Am188E R) is held Low during po wer -on reset[...]

Programmable I/O Pins 13-3 13.2 PIO MODE REGISTE RS Table 13-2 shows the possi ble setting s for the PIO Mode and PIO Direction bits. The Am186ER and Am188ER microcontroll er s de fault the 32 PIO pins to either 00b (normal operatio n) or 01b (PIO input with weak internal pul lup or pulldown enabled). Pins tha t default t o active Hig h outputs at [...]

Programmable I/O Pins 13-4 13.3 PIO DIRECTION REG ISTERS Each PIO is individuall y programmed as an input or output by a bit in o ne of the PIO Directi on registe rs (see Figure 13-4 and Figure 13-5 ). Tabl e 13-2, “PIO Mode and PIO Direct ion Settings,” on page 3 shows the values that the PIO mode bit s and the PIO dire cti on bits can encode.[...]

Programmable I/O Pins 13-5 13.4 PIO DATA REGISTE RS If a PIO pin is ena bled as an outpu t, the valu e in the corresp onding bit in o ne of the PIO Data registers ( see F igure 13-6 and Figure 13-7) is driv en on the pin wit h no inver sion (Low=0, Hi gh=1 ). If a PIO pin i s enabled as an input, the val ue on the PI O pin is r efl ected in the val[...]

Programmable I/O Pins 13-6[...]

Register Summary A-1 APPENDIX A REGISTER SUMMARY This appendi x summarizes the pe ripheral cont rol block regi sters. Table A- 1 lists all the registe rs. Figure A-1 shows the layout of each of the internal regi sters. The column titled Comment in Tabl e A-1 is used to identify the specific us e of interr upt registe rs when there is a mix of maste[...]

Register Summary A-2 Table A-1 Interna l Register Summary Hex Offset Mnem o nic Register De scription Comment FE RELREG Periph eral contr ol block rel ocation re gister F6 RESCO N Reset configur ati on regis te r F4 PRL Pr ocessor rel ease level register F0 PDCO N Power-save co ntrol regist er E4 EDRA M Enable RCU regi ster E2 CDRAM Clock prescaler[...]

Register Summary A-3 Table A -1 Intern al Register Sum mary (con tinued) Hex Offset Mnem o nic Register De scription Comment 5C T1C MPB T imer 1 maxcoun t compa re B regi ster 5A T1CMP A Timer 1 max count compare A register 58 T1CN T T imer 1 co unt re gister 56 T0CON T imer 0 m ode/control register 54 T0CMP B Ti mer 0 maxc ount c ompare B regist e[...]

Register Summary A-4 Figure A-1 Inter nal Re gister Summa ry 15 7 0 Res S/M R19–R8 Res M/IO Peripheral Con trol Block Relocation Register (RELREG) Page 4-4 Offset (Hexadecim al) FE Reset Configu ration Register (RESCON) Page 4-5 F6 15 7 0 RC Processor Release Level R egister (PRL) Page 4-6 F4 15 7 0 PRL Reserved CAF CAD 15 7 0 CBD Power-Save Cont[...]

Register Summary A-5 Figure A-1 Inter nal Re gister Summa ry (con tinued) 15 7 0 M6–M0 RA 19 RA13 0 Memory Partition Register (MDRAM) Page 7-1 E0 15 7 0 TC15–TC0 DMA 1 T ransfer Count Register (D1 TC) Page 10-5 D8 15 7 0 DDA15–DDA0 DMA 1 Destinat ion Address Low Registe r (D1DSTL) Page 10-7 D4 15 70 Reserved DSA19–DSA16 DMA 1 Source Address[...]

Register Summary A-6 Figure A-1 Inter nal Re gister Summa ry (con tinued) 15 7 0 DIN C DDEC SM/IO SINC SDEC B /W ST CHG Res TC INT SYN P TDRQ DMA 0 Control Register (D0CON) Page 10-3 CA DM/IO 15 7 0 TC15 –TC0 DMA 0 T ransfer Cou nt Register ( D 0TC) Page 10-5 C8 15 7 0 Reserved DD A 19–DDA16 DMA 0 Destination Address High Register (D0 DSTH) Pag[...]

Register Summary A-7 Figure A-1 Inter nal Re gister Summa ry (con tinued) 15 7 0 Reserved BA19– BA15 Internal Me mory Chip Select Reg ister (IMCS) Page 6-3 AC RE SR 15 7 0 MS EX M6–M0 11 1 1 R 1 – R 0 PCS and MCS Aux iliary Register (MPCS) Page 5-10 A8 R2 15 7 0 BA19– BA13 1 1 1 R1–R0 11 1 A6 Midrange Mem ory Chip Select Register (M MCS) [...]

Register Summary A-8 Figure A-1 Inter nal Re gister Summa ry (con tinued) Serial Port Receive Data Register (SPRD) Page 1 1-6 86 15 7 0 Reserved RDA T A Serial Port T ransmit Data Register (SPTD) Page 1 1-5 84 15 70 Reserved TDA T A Serial Port Status R egister (SPSTS) Page 1 1-4 82 15 7 0 Reserved TEM T THRE RDR BRKI OER PER FER Serial Port Contro[...]

Register Summary A-9 Figure A-1 Inter nal Re gister Summa ry (con tinued) PIO Mode 1 Regist er (PIOMODE1) Page 13-3 76 15 7 0 PMODE31–PMODE16 PIO Data 0 Register (PDA T A0) Page 13-5 74 PDA T A15–PDA T A0 15 7 0 PIO Direction 0 Regi ster (PDIR0) Page 13-4 72 15 7 0 PDIR15–PDIR0 PIO Mode 0 Register (PIOMODE0) Page 13-3 70 15 7 0 PMODE15–PMOD[...]

Register Summary A-10 Figure A-1 Inter nal Re gister Summa ry (con tinued) 15 70 TC15– TC0 60 Timer 2 Co unt Register (T2CNT) Page 9-6 15 7 0 EN INT INH RIU 0 P EXT MC RTG AL T CONT 00 0 0 0 5E Time r 1 Mode/Control Register ( T1CON) Page 9-3 15 7 0 TC15 –TC0 5C Timer 1 Maxcount Com pare B Register (T1CMPB) Page 9-7 15 70 TC15 –TC0 5A Timer 1[...]

Register Summary A-1 1 Figure A-1 Inter nal Re gister Summa ry (con tinued) 15 7 0 TC15 –TC0 52 Timer 0 Maxcount Com pare A Register (T0CMP A) Page 9-7 15 70 TC15–TC0 50 Timer 0 Co unt Register (T0CNT) Page 9-6 Serial Port Interrupt C o ntrol Register (SPICON) Master M ode Page 8-20 44 15 70 MSK Res PR2–PR0 Reserved (1) W atchdog Timer Int er[...]

Register Summary A-12 Figure A-1 Inter nal Re gister Summa ry (con tinued) 15 70 Reserved PR2–PR0 MSK LT M INT2 Control Regi ster (I2CON) 3C Master M ode Page 8-16 15 70 Reserved MSK LT M C SFNM INT1 Contr ol Re gister (I1C ON) 3A Master Mode Page 8-14 PR2–PR0 MSK 15 70 PR2–PR0 Timer 2 I nterrupt Control Register (T2INTCON) 3A Slave Mo de Pag[...]

Register Summary A-13 Figure A-1 Inter nal Re gister Summa ry (con tinued) 15 70 PR2–PR0 MSK DMA 0 Interrupt C ontrol Re gister (DMA0CON) 34 Master M ode—Page 8-18 Slave Mod e—Page 8-30 Reserved 15 70 PR2–PR0 MSK 32 Timer Inte rrupt Control Register (TCUCON) Master Mode —Page 8-18 Timer 0 I nterrupt Control Register (T0INTCON) Slave Mo de[...]

Register Summary A-14 Figure A-1 Inter nal Re gister Summa ry (con tinued) In-Service Regi ster (INSERV) 2C 15 70 Reserved Res TMR D0 D1 I0 I1 I2 I3 I4 WD SPI Master M ode Page 8-23 15 70 Reserved D0 D1 TMR1 TMR2 Res TMR0 In-Service Regi ster (INSERV) 2C Slave Mode Page 8-33 2A Master M ode—Page 8-24 Slave Mod e—Page 8-34 15 70 Reserved PRM2–[...]

Register Summary A-15 Figure A-1 Inter nal Re gister Summa ry (con tinued) 15 70 S4–S0 IREQ Poll Status Re gister (POLLST) 26 Master Mode Page 8-26 Reserved 15 70 S4–S0 IREQ Poll Register (POLL) 24 Master Mode Page 8-27 Rese rved 15 70 S4–S0 NSP EC End-of-Interrupt Regis ter (EOI) 22 Master Mode Page 8-28 Reserved 15 70 L2–L0 Specific End -[...]

Register Summary A-16 Figure A-1 Inter nal Re gister Summa ry (con tinued) Synchronous Se rial Receive Register (SSR) Page 12-6 18 15 70 Reserved SR Synchronous Se rial T ransmit 0 Regi ster (SSD0) Page 12-5 16 15 70 Reserved SD Synchronous Se rial T ransmit 1 Regi ster (SSD1) Page 12-5 14 15 7 0 Reserved SD Synchronous Se rial Control Register (SS[...]

Index I-1 INDEX A A1 signa l (Latched Address B it 1), 3-8 A19-A0 signals ( Address Bus ), 3-1 A2 signa l (Latched Address B it 2), 3-9 AD15-AD8 signals (A ddress and Data Bus), 3-2 AD7-AD0 signals (Ad dress and D ata Bus), 3-1 Addres s generatio n, 2-3 Addres sing modes, 2-10 ADEN sig nal (Addres s Enable), 3- 3, 3-12 AF bit (Auxilia ry Carry) Pro[...]

I-2 Index DHL T (DMA Halt), 8-21, 8-31 DINC (Destinat ion Increment) , 10-3 DM/IO (Destina tion Address Space Select), 1 0-3 DR/DT (Data Re ceive/T rans mit Complete), 12-3 DSA15-DS A0 (DMA Sour ce Address Low), 10-9 DSA19-DSA 16 (DMA Source A ddress High), 1 0-8 E (Enable RCU), 7-2 EN (Enab le Bit), 9-3, 9-5 EX (Pi n Selector ), 5-11 EXT (Exter na[...]

Index I-3 ZF ( Zero Fl ag), 2 -3 Block dia gr am, 1-4 –1 -5 BRK bit (Se nd Break), 11 -2 BRKI bit (Bre ak Interrupt), 11-4 BRKV A L bit (Break V alue), 11- 2 Bus interfac e unit, 3-21 nonmultip lexed addres s, 3-21 oper ation , 3-18 read and write timing, 3- 19–3-20 Byte wri te enable s, 3-21 C C bit (Cas cade Mode), 8- 14 CAD bit (C LKOUT A Dr[...]

I-4 Index DMA 1 Dest ination A ddress High Re gister, 10-6 DMA 1 Dest ination A ddress Low Regi ster, 10-7 DMA 1 Inter rupt Control Re gister Master m ode, 8-18 Slave m ode, 8-30 DMA 1 Sou rce Address Hi gh Register , 10-8 DMA 1 Source Ad dress Low Registe r, 10-9 DMA 1 Transfer Coun t Register, 10- 5 Documenta tion, iii, x iv Double word d ata typ[...]

Index I-5 Master m ode, 8-16 INT2 signal ( Maskable Interr upt Request 2), 3 -6 INT3 Control Reg ister Master m ode, 8-16 INT3 signal ( Maskable Interr upt Request 3), 3 -6 INT4 Control Reg ister Master m ode, 8-17 INT4 signal ( Maskable Interr upt Request 4), 3 -6 INT A0 si gnal (Inter rupt Acknowl edge 0), 3-6 INT A1 si gnal (Inter rupt Acknowl e[...]

I-6 Index Midrang e Memory Chip S elect Register , 5-8 MS bit ( Memory/I/O Space Sele ctor), 5-11 MSK bit (I nterrupt Mas k) descripti on, 8-2 DMA Interru pt Control Register s, 8-18 T imer Interrupt Contr ol Register s, 8-18 MSK bit ( Mask) DMA Interru pt Control Register s, 8-30 INT0 Contro l Regist er, 8- 14 INT1 Contro l Regist er, 8- 14 INT2 C[...]

Index I-7 Process or Status Fla gs Register (F LAGS), 2-2 Produc t support bulletin board se rvice, iii documenta tion and lite rature, iii technical s upport hotline , iii PSE bit (PSRAM Mode Enable) , 5-7 Pseudo S tatic RAM (PS RAM) suppo rt, 3-21 Pullup/p ulldown res istor, 13- 3 Q Quad word d ata type, 2-8 R R19-R8 fie ld (Relocat ion Address B[...]

I-8 Index Power-Sav e Control (PDC ON, Offset F0h), 4 -7 Priority Mask (PRI MSK, Offset 2Ah), 8- 24, 8-34 Process or Release Lev el (PRL, Offset F4 ), 4-6 Reset Confi guration ( RESCON, Offset F6h), 4-5 Serial Po rt Baud Rate Div isor (SPBAUD, Offset 88h), 11-7 Serial Po rt Control (S PCT , Offset 80h) , 11-2 Serial Po rt Interrupt Con trol (SPICON[...]

Index I-9 DEN (Data E nable), 3-4 DRQ1-DRQ0 (DM A Requests), 3- 4 DT/R (Data Transmit or Re ceive), 3-4 HLDA (Bus Ho ld Acknowledg e), 3-4 HOLD (Bus Hold Req uest), 3-5 IMDIS (Int ernal Memory Disable), 3- 13 INT0 (Maskable Interrupt Reques t 0), 3-5 INT1 (Maskable Interrupt Reques t 1), 3-5 INT2 (Maskable Interrupt Reques t 2), 3-6 INT3 (Maskable [...]

I-10 Index T imer 1 Count Registe r, 9-6 T imer 1 Interrupt Control Reg ister Slave m ode, 8-30 T imer 1 Maxcount Co mpare A Regi ster, 9-7 T imer 1 Maxcount Co mpare B Regi ster, 9-7 T imer 1 Mode and Contr ol Registe r, 9-3 T imer 2 Count Registe r, 9-6 T imer 2 Interrupt Control Reg ister Slave m ode, 8-30 T imer 2 Maxcount Co mpare B Regi ster,[...]