AMD SC2200 manuel d'utilisation

AMD Geode™ SC2200 Processor Data Book AMD Geode™ SC2200 Processor Data Book Marc h 2006 Publicat ion ID: 32580B[...]

2 AMD Geode™ SC2200 Processor Data Book © 2006 Advanced Micr o Devices, Inc. All rights reser ved. The contents of this docu ment are pr ovid ed in connection with Adv anced Mi cro Devices , Inc. (“AMD”) products. AMD mak e s no representations or warr anties with respect to the accuracy or completeness of the contents of this publication an[...]

AMD Geode™ SC2200 Processor Data Book 3 Contents 32580B Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.0 Overview .[...]

4 AMD Geode™ SC2200 Processor Data Book Contents 32580B 6.0 Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 6.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 6.2 Module Arch itectur[...]

AMD Geode™ SC2200 Processor Data Book 5 List of Figures 32580B List of Figures Figure 1-1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3-1. Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

6 AMD Geode™ SC2200 Processor Data Book List of Figures 32580B Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer . . . . . . . . . . . . . . . . . . 325 Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Bu ffers . . . . . . . . . . . . . . . 326 Figure 7-7. Video Block Diagr am . . . . . . . . . . . . . . . [...]

AMD Geode™ SC2200 Processor Data Book 7 List of Figures 32580B Figure 9-45. ECP Forward Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 Figure 9-46. ECP Reverse M ode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 Figure 9-47. AC97 [...]

8 AMD Geode™ SC2200 Processor Data Book List of Figures 32580B[...]

AMD Geode™ SC2200 Processor Data Book 9 List of T ables 32580B List of T ab l es Table 2-1. SC2200 Memo ry Controller Reg ister Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 2-2. SC2200 Memo ry Controller Reg isters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 8 Tabl[...]

10 AMD Geode™ SC2200 Processor Data Book List of T ables 32580B Table 5-28. Bank 1 - CEIR Wakeup Configur ation and Control R egister Map . . . . . . . . . . . . . . . . . . . . 124 Table 5-29. Banks 0 and 1 - Common Cont rol and Status Re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 5-30. Bank 1 - CEIR Wakeup Configur [...]

AMD Geode™ SC2200 Processor Data Book 11 List of T ables 32580B Table 6-21. F2BAR4: IDE Co ntroller Support Re gisters Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 6-22. F3: PCI Heade r Registers for Au dio Support Summa ry . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1 Table 6-23. F3BAR0: Audio Support [...]

12 AMD Geode™ SC2200 Processor Data Book List of T ables 32580B Table 9-9. Balls with PU/PD Re sistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Table 9-10. PLL4 (48 M Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

AMD Geode™ SC2200 Processor Data Book 13 1 Overview 32580B 1.0 Ov er vie w 1.1 General Description The AMD Geode™ SC2200 processor is a member of the AMD Geode processor family of fully integrated x86 system chips. The SC2200 processo r includes: • The Geode GX1 processor module combines advanced CPU performance with MMX™ suppor t, fully ac[...]

14 AMD Geode™ SC2200 Processor Data Book Overview 32580B 1.2 Features General Features ■ 32-Bit x86 processor , up to 300 MHz, with MMX instruction set suppor t ■ Memory controller with 64-bit SDRAM interf ace ■ 2D graphics accelerator ■ CRT controller with hardw are video accelerator ■ CCIR-656 video input por t with direct video for f[...]

AMD Geode™ SC2200 Processor Data Book 15 Overview 32580B ■ General Pur pose I/Os (GPIOs): — 27 multiplex e d GPIO signals ■ Low Pin Count (LPC) Bus Interface: — Specification v1.0 compatible ■ PCI Bus Interface: — PCI v2.1 compliant with wak eup capability — 32-Bit data path, up to 33 MHz — Glueless interface f or an e xter nal PC[...]

16 AMD Geode™ SC2200 Processor Data Book Overview 32580B[...]

AMD Geode™ SC2200 Processor Data Book 17 2 Architecture Overview 32580B 2.0 Architecture Ov er vie w As illustrated in Figure 1-1 on pa ge 13, the SC2200 pro- cessor contains the following modules in one integrated device: • GX1 Module : — Combines advanced CPU perf or mance with MMX suppor t, fully accelerated 2D graphics, a 64-bit synchrono[...]

18 AMD Geode™ SC2200 Processor Data Book Architecture Overview 32580B T able 2-1. SC2200 Memory Contr oller Regist er Summary GX_B ASE+ Memory Offset Width (Bits) T ype Name/Function Reset V alue 8400h-8403h 32 R/W MC_MEM_CNTRL1. Memory Controller Control Register 1 248C0040h 8404h-8407h 32 R/W MC_MEM_CNTRL2. Memory Controller Control Register 2 [...]

AMD Geode™ SC2200 Processor Data Book 19 Architecture Overview 32580B 5 2CLKADDR (T wo Clock Ad dress Setup). Asser t memor y address f or one extra cloc k before CS# is asserted. 0: Dis able. 1: Enable . This can be used to compensate for addres s setup at high frequencies and/or high loads. 4 RFSHTST (T est Refresh). This bit, when set high, ge[...]

20 AMD Geode™ SC2200 Processor Data Book Architecture Overview 32580B GX_BASE+8408h-840Bh MC_BANK_CFG (R/W) Reset Value: 41104110h 31:16 RSVD (Reserved). Write as 0070h 15 RSVD (Reserved). Write as 0. 14 SODIMM_MOD_BNK (SODIMM Module Banks - Banks 0 and 1). Selects number of module banks installed per SODIMM for SODIMM: 0: 1 Module bank (Bank 0 o[...]

AMD Geode™ SC2200 Processor Data Book 21 Architecture Overview 32580B 11 RSVD (Reserved). Write as 0. 10:8 RRD (ACT(0) to A CT(1) Command Period, tRRD). Minimum number of SDRAM cloc ks between A CT and ACT command to two different component banks within the same module bank . The memor y controller does not perf orm back-to-back Acti- vate comman[...]

22 AMD Geode™ SC2200 Processor Data Book Architecture Overview 32580B 2.1.2 Fast-PCI Bus The GX1 module co mmunicates with the Core Logic mod- ule via a F ast-PCI bus that c an wo rk at up to 6 6 MHz. Th e F ast-PCI bus is internal for the SC2200 and is connecte d to the General Configuration Block (see Section 4.0 on page 75 f or details on the [...]

AMD Geode™ SC2200 Processor Data Book 23 Architecture Overview 32580B 2.3 Core Logic Module The Core Logic module is described in detail in Section 6.0 "Core Logic Module" on page 149. The Core Logic module is co nnected to the F ast-PCI b us. It uses signal AD28 as the IDSEL f or all PCI configuration functions except f or USB which us[...]

24 AMD Geode™ SC2200 Processor Data Book Architecture Overview 32580B 2.5 Cloc k, Timers, and Reset Logic In addition to the four main modules (i.e., GX1, Core Logic , Video Processor and SIO) that make up the SC2200, th e f ollowing blocks of logic ha ve also been integrated into the SC2200: • Clock Generators as described in Section 4.5 "[...]

AMD Geode™ SC2200 Processor Data Book 25 3 Signal Definitions 32580B 3.0 Signal Definitions This section defines the signal s and describes the externa l interf ace of the SC2200 processor. Figure 2-1 sho ws the signals organized by their functional groups. Where signals are multiple xed, the def ault signal name is listed first and is separated [...]

26 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B Figure 3-1. Signal Groups (Continued) The remaining subsectio ns of this chapter describe: • Section 3.1 "Ball Assignments": Provides a ball assign- ment diagram and tables listing the signals sor ted according to ball number and alphabetica lly b y signal name. • S[...]

AMD Geode™ SC2200 Processor Data Book 27 Signal Definitions 32580B 3.1 Ball Assignments The SC2200 is high ly configurable as illustrated in Figure 3-1 on page 25. Strap optio ns and register programming are used to set v ari ous modes of operation and specific signals on specific balls. This section describes which sig- nals are availab le on wh[...]

28 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B Figure 3-2. BGU4 81 Ball Assignment Diagr am S S S S S S S S S 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL A B C D E F G H J K L M N P R T U V W Y AA AB [...]

AMD Geode™ SC2200 Processor Data Book 29 Signal Definitions 32580B T able 3-2. BGU481 Ball Assignme nt - Sort ed b y Ball Number Ball No. Signal Name I/O (PU/PD) Buffer 1 Ty p e Pow er Rail Configuration A1 V SS GND --- --- --- A2 V IO PWR --- --- --- A3 AD30 I/O IN PCI , O PCI V IO Cycle Multiple xed D6 I/O IN PCI , O PCI A4 PCICLK0 O O PCI V IO[...]

30 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B B6 AD23 I/O IN PCI , O PCI V IO Cycle Multiple xed A23 O O PCI B7 V SS GND --- --- - -- B8 RD# O O 3/5 V IO --- CLKSEL0 I (PD 100 ) IN STRP Strap (See T ab le 3-4 on page 45.) B9 WR# O O 3/5 V IO B10 V SS GND --- - -- --- B11 VSYNC O O 1/4 V IO --- B12 RED O WIRE AV C- CCRT --- B[...]

AMD Geode™ SC2200 Processor Data Book 31 Signal Definitions 32580B C16 A V SSPLL2 G ND - -- --- --- C17 6,2 SLCT I IN T V IO PMR[23] 3 = 0 and (PMR[27] = 0 and FPCI_MON = 0) TFTD15 O O 1/4 PMR[23] 3 = 1 and (PMR[27] = 0 and FPCI_MON = 0) F_C/BE3# O O 1/4 PMR[23] 3 = 0 and (PMR[27] = 1 or FPCI_MON = 1) C18 PD4 I/O IN T , O 14/14 V IO PMR[23] 3 = 0[...]

32 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B D13 V SS GND --- --- --- D14 V IO PWR --- --- --- D15 A V CCCRT PWR --- - -- --- D16 VREF I/O WIRE A V C- CCRT --- D17 6, 2 PE I (PU 22.5 PD 22.5 ) IN T V IO PMR[23] 3 = 0 and (PMR[27] = 0 and FPCI_MON = 0) (PU/PD under software control.) TFTD14 O O 1/4 PMR[23] 3 = 1 and (PMR[27][...]

AMD Geode™ SC2200 Processor Data Book 33 Signal Definitions 32580B G29 V IO PWR --- - -- --- G30 V SS GND --- - -- --- G31 VPD7 I IN T V IO --- H1 SERR# I/O (PU 22.5 ) IN PCI , OD PCI V IO --- H2 PERR# I/O (PU 22.5 ) IN PCI , O PCI V IO --- H3 LOCK# I/O (PU 22.5 ) IN PCI , O PCI V IO --- H4 C/BE3# I/O (PU 22.5 ) IN PCI , O PCI V IO Cycle Multiple[...]

34 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B M4 AD8 I/O IN PCI , O PCI V IO Cycle Multiple xed A8 O O PCI M28 GPIO32 I/O (PU 22.5 ) IN PCI , O PCI V IO PMR[14] 4 = 0 and PMR[22] 4 = 0 LAD0 I/O (PU 22.5 ) IN PCI , O PCI PMR[14] 4 = 1 and PMR[22] 4 = 1 M29 GPIO13 I/O (PU 22.5 ) IN AB , O 8/8 V IO PMR[19] = 0 AB2D I/O (PU 22.5[...]

AMD Geode™ SC2200 Processor Data Book 35 Signal Definitions 32580B T30 V CORE PWR --- --- --- T31 V CORE PWR --- --- --- U1 AD0 I /O IN PCI , O PCI V IO Cycle Multiple xed A0 O O PCI U2 IDE_ADDR2 O O 1/4 V IO PMR[24] = 0 TFTD4 O O 1/4 PMR[24] = 1 U3 AD2 I /O IN PCI , O PCI V IO Cycle Multiple xed A2 O O PCI U4 V CORE PWR --- --- --- U13 V SS GND [...]

36 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B AA4 IDE_DA T A5 I/O IN TS1 , TS 1/4 V IO PMR[24] = 0 CLK27M O O 1/4 PMR[24] = 1 AA28 SDCLK 2 O O 2/5 V IO --- AA29 6 MD61 I/O IN T , TS 2/5 V IO --- AA30 6 MD62 I/O IN T , TS 2/5 V IO --- AA31 6 MD63 I/O IN T , TS 2/5 V IO --- AB1 IDE_DA T A4 I/O IN TS1 , TS 1/4 V IO PMR[24] = 0 [...]

AMD Geode™ SC2200 Processor Data Book 37 Signal Definitions 32580B AH16 6 MD34 I/O IN T , TS 2/5 V IO --- AH17 6 MD37 I/O IN T , TS 2/5 V IO --- AH18 V IO PWR --- - -- --- AH19 V SS GND --- - -- --- AH20 6 MD41 I/O IN T , TS 2/5 V IO --- AH21 MA9 O O 2/5 V IO --- AH22 MA8 O O 2/5 V IO --- AH23 DQM1 O O 2/ 5 V IO --- AH24 6 MD13 I/O IN T , TS 2/5 [...]

38 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B AL8 SDA T A_IN2 I IN TS V SB F3BAR0+Mem- ory Offset 08h[21] = 1 AL9 6 MD2 I/O IN T , TS 2/5 V IO --- AL10 6 MD4 I/O IN T , TS 2/5 V IO --- AL11 DQM0 O O 2/5 V IO --- AL12 CS0# O O 2/5 V IO --- AL13 V SS GND --- --- --- AL14 MA0 O O 2/ 5 V IO --- AL15 DQM4 O O 2/5 V IO --- AL16 V [...]

AMD Geode™ SC2200 Processor Data Book 41 Signal Definitions 32580B T able 3-3. BGU481 Ball Assignment - Sorted Alphabetical ly b y Signal Name Signal Name Ball No. A0 U1 A1 P3 A2 U3 A3 N1 A4 P1 A5 N3 A6 N2 A7 M2 A8 M4 A9 L2 A10 L3 A11 K1 A12 L4 A13 J1 A14 K4 A15 J3 A16 E1 A17 F4 A18 E3 A19 E2 A20 D3 A21 D1 A22 D2 A23 B6 AB1C N31 AB1D N30 AB2C N29[...]

42 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B F_C/BE3# C17 F_DEVSEL# V31 F_FRAME# A22 F_GNT0# U31 F_IRD Y# B20 F_ST OP# U29 F_TRD Y# U30 FP_VDD_ON V30, AB1 FPCI_MON A4 FPCICLK B18 FRAME# D8 GNT0# C5 GNT1# C6 GPIO0 D11 GPIO1 D10, N30 GPIO6 D28 GPIO7 C30 GPIO8 C31 GPIO9 C28 GPIO10 B29 GPIO11 AJ8 GPIO12 N29 GPIO13 M29 GPIO14 D9[...]

AMD Geode™ SC2200 Processor Data Book 43 Signal Definitions 32580B MD27 AC30 MD28 AE31 MD29 AD29 MD30 AD30 MD31 AD31 MD32 AJ15 MD33 AJ16 MD34 AH16 MD35 AK17 MD36 AJ17 MD37 AH17 MD38 AL17 MD39 AL18 MD40 AL21 MD41 AH20 MD42 AJ20 MD43 AK20 MD44 AL20 MD45 AJ19 MD46 AK18 MD47 AJ18 MD48 AH29 MD49 AF29 MD50 AF28 MD51 AH31 MD52 AD28 MD53 AF31 MD54 AF30 M[...]

44 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B V IO (T otal of 43) A2, A30, B2, B13, B16, B19, B31, C3, C7, C10, C22, C25, C29, D14, D18, D23, G3, G29, K2, K29, M3, M30, W1, W31, AB3, AB29, AE3, AE29, AH4, AH14, AH18, AJ7, AJ10, AJ22, AJ25, AJ29, AK1, AK13, AK16, AK19, AK31, AL2, AL30 VPCKIN F31 VPD0 J30 VPD1 J29 VPD2 J28 VPD[...]

AMD Geode™ SC2200 Processor Data Book 45 Signal Definitions 32580B 3.2 Strap Options Sev eral balls are read at powe r-up that set up the state of the SC2200. These balls are typical ly multiple x ed with other functions that are outputs after the power-up sequence is complete. The SC 2200 must read the state of the balls at power-up and the inte[...]

46 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B 3.3 Multiplexing Configuration The tables that follo w list multiplexing options and their configurations. Cer tain multiple xing options may be chosen per signal; others are av ailable only f or a group of signals . Where ev er a GPIO pin is mu ltiple xed with another func- tion[...]

AMD Geode™ SC2200 Processor Data Book 47 Signal Definitions 32580B GPIO A CCESS.bus N29 GPIO12 PMR[19] = 0 AB2C PMR[19] = 1 M29 GPIO13 AB2D GPIO U ART A G1 GPIO18 PMR[1 6] = 0 DTR1#/BOUT1 PMR[16] = 1 Infrared U AR T C11 IR TX PMR[6] = 0 SOUT3 PMR[6] = 1 AK8 IRRX1 SIN3 GPIO LPC M28 GPIO32 PMR[14] = 0 and PMR[22] = 0 LAD0 PMR[14] = 1 and PMR[22] = [...]

48 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B T able 3-6. Three-Signal/Group Multiplexing Ball No. Default Alternate1 Alternate2 Signal Configur ation Signal Configuration Signal Conf iguration Sub-ISA Sub-ISA 1 GPIO D9 IOR# PMR[21] = 0 and PMR[2] = 0 DOCR# PMR[21] = 0 and PMR[2] = 1 GPIO14 PMR[21] = 1 and PMR[2] = 1 A8 IO W[...]

AMD Geode™ SC2200 Processor Data Book 49 Signal Definitions 32580B Internal T est Internal T est TFT V30 GXCLK PMR[23] = 0 and PMR[29] = 0 TEST3 PMR[23] = 0 and PMR[29] = 1 FP_VDD_ON PMR[23] = 1 1. The combination of PMR[21] = 1 and PMR[2] = 0 is undefined and should not be used. 2. The combination of PMR[9] = 1 and PMR[4] = 0 is undefined and sh[...]

52 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B 3.4 Signal Descriptions Information in the tables that f ollow ma y ha ve duplicate inf or m ation in multiple tab les. Multiple references all contain identi - cal information. 3.4.1 Sys tem Interface Signal Name Ball No. T ype Description Mux CLKSEL1 AF3 I Fast- PCI Cloc k Sele[...]

AMD Geode™ SC2200 Processor Data Book 53 Signal Definitions 32580B X32I AJ2 I/O Crystal Connections. Connected directl y to a 32.768 KHz cr ystal. This clock input is required ev en if the inte r- nal RT C is not being used. Some of the inter nal clocks are derived from this clock. If an e xtern al clock is used, it should be connected to X32 I, [...]

54 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B 3.4.2 Memor y Interface Signals Signal Name Ball No. T ype Description Mux MD[63:0] See T ab le 3-3 on page 41. I/O Memory Data Bus. The data b us lines drive n to/from system me mor y . --- MA[12:0] See T ab le 3-3 on page 41. O Memory Address Bus. The multiplex ed row/column ad[...]

AMD Geode™ SC2200 Processor Data Book 55 Signal Definitions 32580B SDCLK_IN AJ27 I SDRAM Clock Input. The SC2200 samples the memory read data on this clock. W orks in conju nction with the SDCLK_OUT signal. --- SDCLK_OUT AK28 O SDRAM C lock Output. This output is routed back to SDCLK_IN. The board design er should vary the l ength of the board tr[...]

56 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B 3.4.4 C RT/TFT Interface Si gnals Signal Name Ball No. T ype Description Mux DDC_SCL Y1 O DDC Serial Clock. This is the serial clock f or the VESA Displa y Data Chan nel interf ace. It is used for monitor communications. The DDC2B standard is suppor ted by this interface. IDE_D A[...]

AMD Geode™ SC2200 Processor Data Book 57 Signal Definitions 32580B AB1D N30 I/O A CCESS.bus 1 Serial Data. This is the bidirectional serial data signal for the interface . Note: If AB1D function is selected but not used, tie AB1D high. GPIO1+IOCS1# AB2C N29 I/O A CCESS.bus 2 Serial Clock. This is the se rial clock for the interface . Note: If AB2[...]

58 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B PA R J 4 I / O Pa r i ty. P arity gene ration is required by all PCI age nts . The master drives P AR f or address- and write-data phases. The target drives P AR f or read-data phases. P ar- ity is e ven across AD[31:0] and C/BE[3:0]#. F or address phases, P AR is stab le and val[...]

AMD Geode™ SC2200 Processor Data Book 59 Signal Definitions 32580B ST OP# G1 I/O Ta r g e t S t o p . STOP# is asserted to indicate that the cur- rent target is requesti ng that the master stop the curren t transaction. This signal is used with DEVSEL# to indicate retr y , disco nnect, or target abor t. If ST OP# is sampled active b y the master [...]

60 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B PERR# H2 I/O Pa r it y E rr o r . PERR# is used f or repor ting data pari ty errors during all PCI transactions e xcept a Special Cycle. The PERR# line is driven two PCI clocks after the data in which the error was detected. This is one PCI clock after the P AR that is attached t[...]

AMD Geode™ SC2200 Processor Data Book 61 Signal Definitions 32580B 3.4.7 Sub-ISA Inte rface Signals Signal Name Ball No. T ype Description Mux A[23:0] See T ab le 3-3 on page 41. O Address Lines AD[23:0] D15 See T ab le 3-3 on page 41. I/O Data Bus ST OP# D14 IRD Y# D13 TRD Y# D12 PA R D11 C/BE3# D10 C/BE2# D9 C/BE1# D8 C/BE0# D[7:0] AD[31:24] BH[...]

62 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B 3.4.8 Low Pin Count (LPC) Bus Interface Sig nals Signal Name Ball No. T ype Description Mux LAD3 L29 I/O LPC Address-Data. Multiplex ed command, address, bidirectional data, an d cycle status. GPIO35 LAD2 L30 GPIO34 LAD1 L31 GPIO33 LAD0 M28 GPIO32 LDRQ# L28 I LPC DMA Request. Enc[...]

AMD Geode™ SC2200 Processor Data Book 63 Signal Definitions 32580B 3.4.9 I DE Interface Sign als Signal Name Ball No. T ype Description Mux IDE_RST# AA1 O IDE Reset. This signal resets all the devices that are attached to the IDE interf ace. TFTDCK IDE_ADDR2 U2 O IDE Address Bits. These addre ss bits are used to access a register or data por t in[...]

64 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B 3.4.10 Univ ersal Serial Bus (USB) Interface Signa ls Signal Name Ball No. T ype Description Mux PO WER_EN AH1 O Po wer Enable. This signal enables the pow er to a self- powered USB hub . --- O VER_CUR# AF4 I Overcurrent. This signal indicates that the USB hub has detected an ove[...]

AMD Geode™ SC2200 Processor Data Book 65 Signal Definitions 32580B RI2# AJ8 I Ring Indicator . When low , indicates to the modem that a telephone r ing signal has been received by the modem. They are monitored during pow er-off for w akeup e vent detection. Note: If selected as RI2# functi on b ut not used, tie RI2# high. GPIO11+IRQ15 DCD2# C28 I[...]

66 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B 3.4.12 Parallel Port Interfac e Signals Signal Name Ball No. T ype Description Mux ACK# B18 I Ackno wledg e. Pulsed low by the printer to indicate that it has received data from the P arallel Port. TFTDE+FPCICLK AFD#/DSTRB# D22 O Automatic Feed. When low , instructs the pr inter [...]

AMD Geode™ SC2200 Processor Data Book 67 Signal Definitions 32580B STB#/WRITE# A22 O Data Strobe. When low, indicates to the printer that valid data is available at the printer por t. This signal is in TRI- ST A TE after a 0 i s loaded into the co rresponding control register bit. An external 4.7 K Ω pull-up resistor should be employ ed. Write S[...]

68 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B 3.4.14 AC97 A udio In terface Signa ls Signal Name Ball No. T ype Description Mux BIT_CLK U30 I A udio Bit Clock. The serial bi t cloc k from the codec. Note: If selected as BIT_CLK function but not used, tie BIT_CLK low. F_TRD Y# SD A T A_OUT P29 O Serial Data Output. This outpu[...]

AMD Geode™ SC2200 Processor Data Book 69 Signal Definitions 32580B PWRBTN# A H5 I P ower Button. Input used by the power management logic to monitor e xter nal system e vents , most typically a system on/off button or s witch. The signal has a n internal pull-up of 100 K Ω , a Schmitt- trigger i nput buff er and debounce protection of at least 1[...]

70 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B 3.4.16 GPIO Inte rface Signals Signal Name Ball No. T ype Description Mux GPIO0 D11 I/O GPIO P ort 0. Each signal is configured independ ently as an input or I/O , with or without static pull-up, and with either open-drain or to tem-pole ou tput type . A debouncer and an interr u[...]

AMD Geode™ SC2200 Processor Data Book 71 Signal Definitions 32580B 3.4.17 Deb ug Monitoring Interface Signals Signal Name Ball No. T ype Description Mux FPCICLK B18 O Fast-PCI Bus Monitoring Signals. When enabled, this group of signals provides f or monitorin g of the internal F ast-PCI b us f or debug purpose s . T o enable , pull up FPCI_MON (b[...]

72 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B TRST# E29 I JT AG T est Reset. This signal has an internal weak pull- up resistor . F or nor mal JT A G operation, this signal should be active at power-up . If the JT AG interf ace is not being used, this signal can be tied low . --- 3.4.18 JT A G Interface Signal s (Continued) [...]

AMD Geode™ SC2200 Processor Data Book 73 Signal Definitions 32580B AV SSPLL3 AK3 GND PLL3 Analog Gr ound Connection. V PLL2 A17 PWR 3.3V PLL2 Analog P ower Conn ection. Low noise power f or PLL2 and PLL5. V PLL3 AJ4 PWR 3.3V PLL3 Analog Po wer Connection. Low noise pow er for PLL3, PLL4, and PLL6. AV CCUSB D27 PWR 3.3V Analog USB P ower Connectio[...]

74 AMD Geode™ SC2200 Processor Data Book Signal Definit ions 32580B[...]

AMD Geode™ SC2200 Processor Data Book 75 4 General Configuration Block 32580B 4.0 General Configur ation Bloc k The General Configuration bloc k includes registers for: • Pin Multiplexing and Miscellaneous Configuration • W A TCHDOG Timer • High-Resolution Ti mer • Clock Generators A selectable interrupt is shared by all these functions. [...]

76 AMD Geode™ SC2200 Processor Data Book General Configuration Block 32580B 4.2 Multiplexing, Inte rrupt Selection, and Base Ad dress Registers The registers described inT able 4-2 are used to dete rmine general configuration for the SC2200. These registers also indicate which multiplex ed signals are issued via balls from which more than one sig[...]

AMD Geode™ SC2200 Processor Data Book 77 General Configuration Block 32580B 25 A C97CKEN (Enable A C97_CLK Output). This bit e nab les the output drive of AC97_CLK (ball P31). 0: AC97_CLK output is HIZ. 1: AC97_CLK output is enabled. 24 TFTIDE (TFT/ IDE). Determines whether cer tain ball s are used for TFT signals or for ID E signals . Note that [...]

78 AMD Geode™ SC2200 Processor Data Book General Configuration Block 32580B 23 TFTPP (TFT/Parallel P ort). Determines w hether cer tain balls are used for TFT or PP/A CB1/FPCI. This bit is set to 1 at power-on if the TFT_PRSNT strap (ball P29) is pulled high. Ball # 0: PP/A CB1/FPCI 1: TFT Name Add’l Dependencies Name Add’l Dependencies H2 / [...]

AMD Geode™ SC2200 Processor Data Book 79 General Configuration Block 32580B 21 IOCSEL (Select I/O Commands ) . Selects ball functions. Ball # 0: I/O Command Signals 1: GPIO Signals Name Add’l Dependencies Name Add’l Dependencies F1 / D9 IOR# PMR[2] = 0 GPIO14 PMR[2] = 1 DOCR# PMR[2] = 1 Undefined PMR[2] = 0 G3 / A8 IOW# PMR[2] = 0 GPIO15 PMR[[...]

80 AMD Geode™ SC2200 Processor Data Book General Configuration Block 32580B 12 TRDESEL (Select TRDE#). Selects ball function. Ball # 0: Sub-ISA Signal 1: GPIO Signal Name Add’l Dependencies Name Add’l Dependencies H1 / D11 TRDE# None GPIO0 None 11 EIDE (Enable IDE Outputs). This bit enables IDE output signals . 0: IDE signals are HIZ . Other [...]

AMD Geode™ SC2200 Processor Data Book 81 General Configuration Block 32580B 16 Dela y HSYNC . HSYNC dela y by tw o TFT clock cyc les. 0: There is no delay on HSYNC. 1: HYSNC is delay ed twice by rising edge of TFT clock. Enab les delay betw een VSYNC and HSYNC suited for TFT dis- pla y . 15 Reserved. Write as read. 14 IBUS16 (In vert BUS16 ). Thi[...]

82 AMD Geode™ SC2200 Processor Data Book General Configuration Block 32580B 0 SDBE0 (Slave Disconnect Boundary Enable). Works in conjunction with the GX1 module’ s PCI Control Function 2 Regis- ter (Index 41h), bit 1 (SDBE1). Sets boundaries for when the GX1 module is a PCI sla ve . SDBE[1:0] 00: Read and Wr ite disconnect on boundar ies set b [...]

AMD Geode™ SC2200 Processor Data Book 83 General Configuration Block 32580B 4.3 W A TCHDOG The SC2200 includes a W A TCHDOG function to ser v e as a f ail-safe mechanism in case the system becomes hung. When tri ggered, the W A TCHDOG mechanism retur ns the system to a known state by generating an interrupt, a n SMI, or a system rese t (depending[...]

84 AMD Geode™ SC2200 Processor Data Book General Configuration Block 32580B W A TCHDOG Interrupt The W A TCHDOG interr upt (if configured and enabled) is routed to an IRQ signal. The IRQ signal is programmable via the INTSEL register (Offset 38h, d escribed in T able 4-2 "Multiplexing, Interrupt Selection, and Base Address Re gis- ters"[...]

AMD Geode™ SC2200 Processor Data Book 85 General Configuration Block 32580B 4.4 High-Resolution Timer The SC2200 p rovides an accurat e time v alue that can be used as a time stamp b y system software. This time is called the High-Resoluti on Timer . Th e length of the timer value can be e xtended via software. It is nor mally enabled while the s[...]

86 AMD Geode™ SC2200 Processor Data Book General Configuration Block 32580B T able 4-4. High-Resolutio n Timer Register s Bit Description Offset 08h-0Bh TIMER V alue Register - TMV ALUE (RO) Reset V alue: xxxxxxxxh This register contains the current value of the High-Resolution Timer . 31:0 Current Timer V alue. Offset 0Ch TIMER Status Register -[...]

AMD Geode™ SC2200 Processor Data Book 87 General Configuration Block 32580B 4.5 Cloc k Generators and PLLs This section describes the r egisters f or the clocks required by the GX1 module, Core Logic module, and the Video Processor , and how these clocks are generated. See Fig- ure 4-2 f or a clock generation diagram. The clock generators are bas[...]

88 AMD Geode™ SC2200 Processor Data Book General Configuration Block 32580B 4.5.1 27 MHz Cr ystal Oscilla tor The inter nal oscillator employs an e xter nal crystal co n- nected to the on-chip amplifie r . The on-chip amplifier is accessible on the X27I input and X27O output signals. See Figure 4-3 for the recommended e xter nal circuit and T abl[...]

AMD Geode™ SC2200 Processor Data Book 89 General Configuration Block 32580B 4.5.2 GX1 Module Core Cloc k The core clock is generated by an Analog Delay Loop (ADL) clock generator from the inter nal F ast-PCI clock. The clock can be any whole-n umber multiple of the input clock between 4 and 10. P ossible values are listed in T able 4-6. At pow er[...]

90 AMD Geode™ SC2200 Processor Data Book General Configuration Block 32580B 4.5.4 SuperI/ O Clocks The SuperI/O module requires a 48 MHz input for F ast infrared (FIR), U AR T , and other functions. This clock is sup- plied by PLL4 using a multiplier value of 576/(108x3) to generate 48 MHz. 4.5.5 Core L ogic Module Cloc ks The Core Logic mod ule [...]

AMD Geode™ SC2200 Processor Data Book 91 General Configuration Block 32580B 4.5.7 Clock Registe r s T a b le 4-9 describes the registers of the clock generator and PLL. T able 4-8. Clo ck Generator Configurat ion Bit Description Offset 10h Maximum Core Clock Multiplier Regist er - MCCM (R O) Reset V alue: Strapped V alue This register holds the m[...]

92 AMD Geode™ SC2200 Processor Data Book General Configuration Block 32580B 15:14 Reserved. 13 Reserved. Must be set to 0. 12 Reserved. Must be set to 0. 11:10 Reserved. 9:8 FPCICK (Internal Fast-PCI Clock). (Read Only) Reflects the internal F ast-PCI clock and is the input to the GX1 module that is used to generate the core clock. These bi ts re[...]

AMD Geode™ SC2200 Processor Data Book 95 5 SuperI/O Module 32580B 5.0 SuperI/O Module The SuperI/O (SIO) module is PC98 and ACPI compliant. It off ers a single-cell solution to the most commonly used ISA periphe rals . The SIO module in corporates: two Serial Ports, an Infrared Communication P ort that suppor ts FIR, MIR, HP-SIR, Shar p-IR, and C[...]

96 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 5.1 Features PC98 and A CPI Compliant • PnP Configuration Register str ucture • Flexib le resource allocation for all logical devices: — Relocatable base address — 9 parallel IRQ routing options — 3 optional 8-bit DMA channels (where ap plicab le) P arallel P ort • Softwa[...]

AMD Geode™ SC2200 Processor Data Book 97 SuperI/O Module 32580B 5.2 Module Ar chitecture The SIO module comprises a collection of generic func- tional blocks . Each functional block is described in detail later in this chapter. The beginning of this chapter describes the SIO str ucture and provides all device specific inf or mation, including spe[...]

98 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 5.3 Configuration Structure/Access This section descr ibes the st ructure of the config uration register file, and the method of ac cessing the configuration registers. 5.3.1 Index-Data Reg ister P air The SIO configuration access is performed via an Index- Data register pair , using[...]

AMD Geode™ SC2200 Processor Data Book 99 SuperI/O Module 32580B Write accesses to unimplemented registers (i.e., accessing the Data register while the I ndex register points to a non- ex isting register or the LDN is 07h or higher than 08h), are ignored and a re ad return s 00h on all addresses except f or 74h and 75h (DMA co nfiguration register[...]

100 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 5.4 Standard Configur ation Register s As illustrated in Figure 5-4, the Standard Configuration reg- isters are broadly divided i nto two categories: SIO Contro l and Configuration regi sters and Logical Device Control and Configuration registers (one per logical device, some are op[...]

AMD Geode™ SC2200 Processor Data Book 101 SuperI/O Module 32580B T a b le 5-3 provides the bit definitions for the Standard Con- figuration registers. • All reser ved bits return 0 o n reads, e xcept where noted otherwise. They must not be m odified as such modifica- tion may cause unpredictable results. Use rea d-modify- write to prevent the v[...]

102 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B Index 75h DMA Channel Select 1 (R/W) Indicates selected DMA channel for DMA 1 of the logical de vice (1 - the second DMA channel in case of using more than one D MA channel). 7:3 Reserved. 2:0 DMA 1 Channel Select: This bit field selects the DMA channel for DMA 1. The valid choices [...]

AMD Geode™ SC2200 Processor Data Book 103 SuperI/O Module 32580B 5.4.1 SIO Contr ol and Configuration Register s T a b le 5-4 lists the SIO Control and Configuration regi sters and T able 5-5 provides their bit f or mats. T able 5-4. SIO Control and C onf iguration Register Map Index T ype Name P ower Rail Reset V alue 20h RO SID . SIO ID V CORE [...]

104 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 5.4.2 Logica l Device Control and Configuration As described in Section 5.3.2 "Banked Logical Device Reg- isters" on page 98, each functio nal b lock is associated with a Logical Device Number (LDN). This section provides the register descriptions for each LDN. The registe[...]

AMD Geode™ SC2200 Processor Data Book 105 SuperI/O Module 32580B T able 5-7. RTC Configura tion Register s Bit Description Index F0h RAM Lock Register - RLR (R/W) When any non-reser v ed bit in this register is se t to 1, it c an be cleared only by hardw are reset. 7 Block Standard RAM. 0: No effect on Standard RAM access. (Def ault) 1: Read and [...]

106 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 5.4.2.2 LDN 01h - Sy stem Wakeup Contr ol T a b le 5-8 lists registers that are relev ant to the configura- tion of System W akeup Control (SWC). These regi sters are descri bed earlier in T able 5-3 "Standard Configuration Reg- isters" on page 101. T able 5 -8. Relev ant [...]

AMD Geode™ SC2200 Processor Data Book 107 SuperI/O Module 32580B 5.4.2.3 LDN 02h - Infrared Communication P ort or Serial P ort 3 T a b le 5-9 lists the configurati on registers which aff ect the Infrared Communication P or t or Ser ial P ort 3 (IRCP/SP3). Only the last register (F0h) is describ ed here (T able 5-10). See T able 5-3 "Standar[...]

108 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 5.4.2.4 LDN 03h and 08h - Serial P ort s 1 and 2 Serial P or ts 1 and 2 are iden tical, e xcept for their reset v al- ues. Serial Port 1 is designated as LDN 03h and Seri al P or t 2 as LDN 08h. T able 5-11 lists the configuration registers which aff ect Serial P or ts 1 and 2. Only[...]

AMD Geode™ SC2200 Processor Data Book 109 SuperI/O Module 32580B 5.4.2.5 LDN 05h and 06h - A CCESS.bus P or ts 1 and 2 A CCESS.b us por ts 1 and 2 (ACB1 and ACB2) are identi- cal. Each ACB is a tw o-wire synchronous ser ial interf ace compatible with the A CCESS.b us ph ysical la yer . ACB1 and A CB2 use a 24 MHz intern al cloc k. Six runtime reg[...]

110 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 5.4.2.6 LDN 07h - P arallel P ort The P arallel P or t suppor ts all IEEE 1284 standard commu- nication modes: Compatibility (known also as Standard or SPP), Bidirectional (known also as PS/2), FIFO , EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode). The P ara[...]

AMD Geode™ SC2200 Processor Data Book 111 SuperI/O Module 32580B 5.5 Real-Time Cloc k (RTC) The RTC pro vides timekeeping and calenda r management capabilities. The RTC uses a 32.768 KHz signal as th e basic clock f or timeke eping. It also includes 24 2 b ytes of batter y-back ed RAM f or general-pur pose use. The RTC pro vides the f ollowing fu[...]

112 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B External Elements Choose C 1 and C 2 capacitors (see Figure 5-5 on page 111) to match the cr ystal’ s load capacitance. The load capacitance C L “seen” b y cr ystal Y is comprised o f C 1 in series with C 2 and in parallel with the parasitic capacitance of the circuit. The par[...]

AMD Geode™ SC2200 Processor Data Book 113 SuperI/O Module 32580B 5.5.2.4 Timekeeping Data Format Time is kept in BCD or binar y format, as deter mined by bit 2 (DM) of Control Register B (CRB), and in either 12 or 24- hour f or mat, as determined by bit 1 of this register . Note: When changing the abov e f or mats, re-initialize all the time regi[...]

114 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 5.5.2.6 P ower Supply The device is supplied from two supply voltages , as shown in Figure 5-8: • System standby pow er supply voltage , V SB • Back up voltage , from low capacity Lithium batter y A standby v oltage, V SB , from the ext er nal A C/DC power supply powers the R TC[...]

AMD Geode™ SC2200 Processor Data Book 115 SuperI/O Module 32580B 5.5.2.7 System P ower States The system power state ma y be No P o wer , P ower On, P ower Off or P ower F a ilure . T able 5-18 indicates the pow er- source combinations for each state . No other power-source combinations are valid. In addition, th e pow er sources and di stributio[...]

116 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 5.5.2.9 Interrupt Handling The RTC has a single Interr upt Request line which hand les the following three interrupt condi tions: • P eriodic interr upt • Alar m interrupt • Update end interrupt The interrupts are generated if the respective enab le bits in the CRB register ar[...]

AMD Geode™ SC2200 Processor Data Book 117 SuperI/O Module 32580B 5.5.3 RTC Registers The RTC registers can be acce sse d (see Section 5.4.2.1 "LDN 00h - Real-Time Clock" on page 1 04) at any time dur- ing nor mal operation mode (i.e.,when V SB is within the rec- ommended operation range). This access is di sab led during ba ttery-b ac k[...]

118 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B Index 04h Hours Register - HOR (R/W) Reset T ype: V PP PUR 7:0 Hour s Data. For 12-hour mode , values can be 01 to 12 (AM) and 81 to 92 (PM) in BCD format, or 01 to 0C (AM) and 81 to 8C (PM) in binar y f or mat. F or 24-hour mode, values can be 0- to 23 in BCD format or 00 to 17 in [...]

AMD Geode™ SC2200 Processor Data Book 119 SuperI/O Module 32580B 1 Hour Mod e. This bit is reset at V PP power-up reset only . 0: Enable 12-hour format. 1: Enable 24-hour format. 0 Daylight Saving. This bit is reset at V PP power-up reset only . 0: Disab le. 1: Enab le: - In the spring, time advances from1:59:59 AM to 3:00:00 AM on the first Sund[...]

120 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B T able 5-21. Divider Chain Contr ol / T est Selection DV 2 DV 1 DV 0 Configuration CRA6 CRA 5 CRA4 0 0 X Oscilla tor Disabled 0 1 0 Nor mal Operation 01 1 T e s t 10 X 1 1 X Divider Cha in Reset T able 5-22. Perio dic Interrupt Rate Encoding Rate Select 3 2 1 0 Pe riodic Interrupt R[...]

AMD Geode™ SC2200 Processor Data Book 121 SuperI/O Module 32580B 5.5.3.1 Usage Hints 1) Read bit 7 of CRD at each system pow er-up to vali- date the contents of the R TC registers and the CMOS RAM. When this bit is 0, the contents of these re gis- ters and the CMOS RAM are questionable. This bit is reset when the backup batter y v oltage is too l[...]

122 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 5.6 System W akeup Contr ol (SWC) The SWC wak es up the system b y sending a power-up request to the ACPI controller in response to the f ollowing maskable system e vents: • Modem ring (RI2#) • A udio Codec ev ent (SD A T A_IN2) • Programmab le Consumer Electronics IR (CEIR) a[...]

AMD Geode™ SC2200 Processor Data Book 123 SuperI/O Module 32580B 5.6.2 SWC Regist ers The SWC registers are organized in two banks. The offsets are related to a base address that is deter mined by the SWC Base Address Register in the logical device configu- ration. The lo wer three registers are common to the two banks while the upper registers ([...]

124 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B T able 5-2 9. Banks 0 and 1 - Common Control and Status Register s Bit Description Offset 00h W akeup Events Statu s Regist er - WKSR (R/W1C) Reset V alu e: 00h This register is set to 00h on power-up of V PP or software reset. It indicates which wakeup e v ent and/or PME occurred. [...]

AMD Geode™ SC2200 Processor Data Book 125 SuperI/O Module 32580B T able 5-30. Bank 1 - CEIR W akeup Configuration and Contr ol Registers Bit Description Bank 1, Offset 03h CEIR Wakeup Control Register - IR WCR (R/W) Reset V alue: 00h This register is set to 00h on power-up of V PP or software reset. 7:6 Reserved. 5:4 CEIR Protocol Select. 00: RC5[...]

126 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B CEIR Wakeup Range 1 Registers These two registers (IR WTR1L and IRWTR1H) define the low and high limits of time range 1 (see T able 5-26 on page 123). The v alu es are represented in units of 0.1 ms. • RC-5 protocol: The pulse width defining a half-bit cell must fall within this r[...]

AMD Geode™ SC2200 Processor Data Book 127 SuperI/O Module 32580B 5.7 A CCESS.bus Interface The SC2200 has two ACCESS .b us (ACB) controllers. A CB is a two-wire synchronous ser ial interface compatib le with the ACCESS .bus ph ysical lay er , Intel's SMBus, and Phili ps’ I 2 C . The A CB can be configured as a bus master or sla ve , and ca[...]

128 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 5.7.3 Ac knowledge (A CK) Cyc le The ACK cycle consists of two signals: the A CK clock pulse sent by the master with each b yte transferred, and the ACK signal sent by the receiving device (see Figure 5-15). The master generates the ACK cloc k pulse on the ninth clock pulse of the b[...]

AMD Geode™ SC2200 Processor Data Book 129 SuperI/O Module 32580B 5.7.4 Acknowledge After Eve ry Byte Rule According to this rule, the master generates an acknowl- edge clock pulse after each byte transf er , and the receiver sends an acknowledge signal after e very byte receiv ed. There are two e xceptions to this r ule: • When the master is th[...]

130 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B Sending the Address Byte When the device is the active master of the A CCESS.bus (A CBST[1] is set), it can send the address on the bus. The address sent should not be the device’ s own address, as defined by A CBADDR[6:0] if AC BADDR[7] is set, nor should it be the globa l call a[...]

AMD Geode™ SC2200 Processor Data Book 131 SuperI/O Module 32580B Master Error Detection The ACB detects illegal Star t or Stop Conditions (i.e., a Star t or Stop Condition within the data transf er , or the ackno wledge cycle) and a conflict on the data lines o f the A CCESS.b us. If an illegal condition is detected, A CBST[5] is set, and master [...]

132 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 5.7.10 ACB Registers Each functional block is associated with a Logical Device Number (LDN) (see Section 5.3 .2 "Bank ed Logical Device Registers" on page 98). A CCESS.Bus P or t 1 is a ssigned as LDN 05h and ACCESS .b us P or t 2 as LDN 06h. In addi- tion to the registers[...]

AMD Geode™ SC2200 Processor Data Book 133 SuperI/O Module 32580B 1 MASTER. (RO) 0: Arbitration loss (BER, bit 5, is set) or recognition of a Stop Co ndition. 1: Bus master request succeeded and master mode active. 0 XMIT (T ransmit) . (RO) Direction bit. 0: Master/slave transmit mode not activ e. 1: Master/slave transmit mode activ e. Offset 02h [...]

134 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 2 INTEN (Interrupt Enable). 0: ACB interrupt disabled. 1: ACB interrupt enabled. An interrupt is generated in response to one of the follo wing ev ents: -Detection of an address match (ACBST[2] = 1) and A CBCTL1[6] = 1. -Receipt of Bus Error (ACBST[5] = 1). -Receipt of Negative Ac k[...]

AMD Geode™ SC2200 Processor Data Book 135 SuperI/O Module 32580B 5.8 Legacy Functional Blocks This section bri efly describes th e f ollowing bloc ks that pro- vide legacy device functions: • P arallel P ort . (Similar to P arallel P or t in the National Semiconductor PC87338.) • Serial P or t 1 and Serial Port 2 (SP1 and SP2), UAR T function[...]

136 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B T able 5-35. P arallel P or t Bit Map f or Firs t Level Offset Offset Name Bits 76543210 000h D A T AR Data Bits AFIFO Add ress Bits 001h DSR Printer Status ACK # Status PE Status SLCT Status ERR# Status RSVD EPP Timeout Status 002h DCR RSVD Direction Control Interrupt Enable PP Inp[...]

AMD Geode™ SC2200 Processor Data Book 137 SuperI/O Module 32580B 5.8.2 U ART Functionality ( SP1 and SP2) Both SP1 and SP2 provide U ART functionality . The gene ric SP1 and SP2 suppor t serial data communication with remote periphe ral de vice or modem using a wired inter- f ace. The functional blocks can function as a standard 16450, 16550, or [...]

138 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B T able 5-38. Bank Select ion Encoding BSR Bits Bank Selected 76543210 0xxxxxxx 0 1 0 xxxxxx 1 1 1 xxxx1 x 1 1 1 xxxxx1 1 11100000 2 11100100 3 T able 5-39. Bank 1 Register Map Offset T ype Name 00h R/W LBGD(L). Leg acy Baud Generator Divisor P or t (L ow Byte) 01h R/W LBGD(H). Legac[...]

AMD Geode™ SC2200 Processor Data Book 139 SuperI/O Module 32580B T able 5-41. Bank 3 Register Map Offset T ype Name 00h RO MRID. Module and Revision ID 01h RO SH_LCR. Shadow of LCR 02h RO SH_FCR. Shadow of FIFO Control 03h R/W BSR. Bank Select 04h-07h --- RSVD . Reser v ed T able 5-42. Bank 0 Bi t Map Register Bits O f f s e t N a m e 76543210 00[...]

140 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B T able 5-43. Bank 1 Bi t Map Register Bits O f f s e t N a m e 76543210 00h LBGD(L) LBGD[7:0] (Low Byte) 01h LBGD(H) LBGD[15:8] (High Byte) 02h RSVD Reser v ed 03h LCR 1 BKSE SBRK STKP EPS PEN STB WLS[1:0] BSR 1 BKSE BSR[6:0] (Bank Select) 04h-07h RSVD Reser ved 1. When bit 7 of thi[...]

AMD Geode™ SC2200 Processor Data Book 141 SuperI/O Module 32580B 5.8.3 IR Communications P ort (IRCP) / Serial P ort 3 (SP3) Funct ionality This section describes the IRCP/SP3 suppor t registers . The IRCP/SP3 functional block pro vides advanced, ve rsa- tile serial communications features with IR capabilities. The IRCP/SP3 also suppor ts two DMA[...]

142 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B T able 5-47. Bank Select ion Encoding BSR Bits Bank Selected Functionality 76543210 0 xxxxxxx 0 U A R T + I R 1 0xxxxxx 1 1 1xxxx 1 x 1 1 1xxxxx 1 1 11100000 2 11100100 3 11101000 4 I R O n l y 11101100 5 11110000 6 11110100 7 T able 5-48. Bank 1 Register Map Offset T ype Name 00h R[...]

AMD Geode™ SC2200 Processor Data Book 143 SuperI/O Module 32580B T able 5-50. Bank 3 Register Map Offset T ype Name 00h RO MID. Module and Re vision Identificatio n 01h RO SH_LCR. Link Control Shadow 02h RO SH_FCR. FIFO Control Shadow 03h R/W BSR. Bank Select 04h-07h --- RSVD . Reser v ed T able 5-51. Bank 4 Register Map Offset T ype Name 00h RO [...]

144 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B T able 5-53. Bank 6 Register Map Offset T ype Name 00h R/W IRCR3. IR Contro l 3 01h R/W MIR_PW . MIR Pulse Width 02h R/W SIR_PW . SIR Pulse Width 03h R/W BSR. Bank Select 04h R/W BFPL. Beginning Flags/Preamble Length 05h-07h --- RSVD . Reser v ed T able 5-54. Bank 7 Register Map Off[...]

AMD Geode™ SC2200 Processor Data Book 145 SuperI/O Module 32580B T able 5-56. Bank 1 Bi t Map Register Bits O f f s e t N a m e 76543210 00h LBGD(L) LBGD[7:0] (Low Byte Data) 01h LBGD(H) LBGD[15:8] (High Byte Data) 02h RSVD RSVD 03h LCR BKSE SBRK STKP EPS PEN STB WLS[1:0] BSR BKSE BSR[6:0] (Bank Select) 04h-07h RSVD RSVD T able 5-57. Bank 2 Bi t [...]

146 AMD Geode™ SC2200 Processor Data Book SuperI/O Module 32580B 06h RFRML(L)/ RFRCC(L) RFRML[7:0] / RFRCC[7:0] (Low Byte Data) 07h RFRML(H)/ RFRCC(H) RSVD RFRML[12:8] / RFRCC[12:8] (High Byte Data) T able 5-5 9. Bank 4 Bit Map (Continued) Register Bits O f f s e t N a m e 76543210 T able 5-60. Bank 5 Bi t Map Register Bits O f f s e t N a m e 76[...]

AMD Geode™ SC2200 Processor Data Book 149 6 Core Logic Mo dule 32580B 6.0 Core Logic Module The Core Logic module is an enh anced PCI-to-Sub-ISA bridge (South Br idge), this module is A CPI-compliant, and provides A T/Sub-ISA functio nality . The Core L ogic module also contains state-of-the-a r t power manageme nt. T wo bus mastering IDE control[...]

150 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B Integrated A udio • A C97 V ersion 2.0 compliant interface to audio codecs • Secondar y codec suppor t • AMC97 codec suppor t Video Processor Interface • Synchronous serial interface to the Video Processor • T ranslate s video and clock control register accesses from PC[...]

AMD Geode™ SC2200 Processor Data Book 151 Core Logic Mo dule 32580B 6.2.1 Fast-PCI Inter face to External PCI Bu s The Core Logic modu le provides a PCI bus interf ace that is both a slav e for PCI cycles init iated b y the GX1 module or other PCI master de vices, and a non-preemptive master f or DMA transf er cycles. It is also a standard PCI ma[...]

152 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B 6.2.2.1 Video Re trace Interrupt Bit 7 of the “Serial P ack et” can be used to generate an SMI whenev er a video retrace occurs within the GX1 module. This function is nor mally not used for po wer management but f or SoftV GA routines. Setting F0 Inde x 83h[2] = 1 enables th[...]

AMD Geode™ SC2200 Processor Data Book 153 Core Logic Mo dule 32580B value is listed because both data and command timings are the same mode. Howe v er , the actual timing value for the Mode 4 device would be constructed ou t of the Mode 4 data timing 16-bit value and the Mode 0 16-bit co mmand timing value. Both 16-bit values are shown in the reg[...]

154 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B 6.2.3.4 UltraDMA/33 Mode The IDE controller of the Core Logic mod ule suppor ts UltraDMA/33. It utilizes the standard IDE Bus Master func- tionality to interface , initiate and control the transfer . UltraDMA/33 definition also i ncorporates a Cyclic Redun- dancy Checking (CRC) e[...]

AMD Geode™ SC2200 Processor Data Book 155 Core Logic Mo dule 32580B 6.2.4 Universal Serial Bus The Core Logic mod ule provides three complete, indepen- dent USB por ts. Each por t has a Data "Nega tiv e" and a Data "P ositive" signal. The USB por ts are Open Host Controller Interface (Open- HCI) compliant. The OpenHCI specific[...]

156 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B 6.2.5.1 Sub-ISA Bus Cycles The ISA bus controller issues multiple ISA cycles to satisfy PCI transactions that are larger than 16 bits. A full 32-bit read or write resul ts in two 16-bit ISA transactions or f our 8- bit ISA transactions. The ISA controller gathers the data from mu[...]

AMD Geode™ SC2200 Processor Data Book 157 Core Logic Mo dule 32580B Figure 6-3. PCI to ISA Cycles wit h Delay ed T ransaction Enabled 6.2.5.3 Sub-ISA Bu s Data Steering The Core Logic mod ule performs all of the required data steerin g from SD[7:0] to SD[15:0] dur ing norma l 8-bit ISA cycles, as well as during DMA and ISA master cycles. It handl[...]

158 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B 6.2.5.5 ISA DMA DMA transf ers occur between ISA I/O per ipherals and sys- tem memory (i.e., not a v ailabl e e xter nally). The data width can be either 8 or 16 bits. Out of the sev en DMA channels av ailable , four are used f or 8-bit transf ers while the rema in- ing three are[...]

AMD Geode™ SC2200 Processor Data Book 159 Core Logic Mo dule 32580B 6.2.5.6 ROM Interface The Core Logic mo dule positively decodes memo ry addresses 000F0000h-000FFFFFh (64 KB) an d FFFC0000h-FFFFFFFFh (256 KB) at reset. These me mory cycles cause the Core Logic module to clai m the cycle, and generate an ISA b us memory cycle with ROMCS# asser [...]

160 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B Figure 6-6. PCI Change to Sub-ISA and Back 6.2.6 A T Compatibility Lo gic The Core Logic module integrates: • T wo 8237-eq uiv alent DMA controllers with full 32-bi t addressing • T wo 8259A-equ iv alent interrupt controll ers providing 13 individually programmable e xternal [...]

AMD Geode™ SC2200 Processor Data Book 161 Core Logic Mo dule 32580B DMA T ransfer Modes Each DMA channel can be programmed for single , blo ck , demand or cascade transf er modes. In the most commonly used mode, single transfer mode, one DMA cycle occurs per DRQ and the PCI bus is released after e v er y cycle . This allows the Core Logi c module[...]

162 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B DMA Addressing Capability DMA transf ers occu r o ver the entire 32-bit address range of the PCI bus. This is accomplished by using the DMA con- troller’ s 16-bit memor y address registers in conjunction with an 8-bit DMA Low P age register and an 8-bit DMA High P age register [...]

AMD Geode™ SC2200 Processor Data Book 163 Core Logic Mo dule 32580B 6.2.6.3 Programmable Interrupt Contr oller The Core Logic module con tains two 8259A-equiv alent programmab le interr upt controllers, with eight interrupt request lines each, for a total of 16 interr upts. The PCI device supports all x86 mod es of operation e xcept Special Fully[...]

164 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B PIC Interrupt Sequence A typical A T -compatible interrupt sequence is as follows . Any unmasked interrupt generates the inter nal INTR signa l to the CPU. The interrupt contro ller then responds to the interrupt acknowledge (INT A) cycles from the CPU . On the first INT A cycle [...]

AMD Geode™ SC2200 Processor Data Book 165 Core Logic Mo dule 32580B 6.2.7.1 I/O P ort 092h System Control I/O P or t 092h allows f or a fast k eyboard asser tion of an A20# SMI and a fast ke yboard CPU reset. Decoding for this register may be disabled via F0 Index 52h[3]. The asser tion of a f ast ke yboard A20# SMI is control led by either I/O P[...]

166 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B 6.2.9 Po wer Management Logic The Core Logic mo dule integrates advanced pow er man- agement features including idle timers for common system peripherals, address trap registers for programmab le address ranges for I/O or memor y accesses, f our program- mable general purpose ext[...]

AMD Geode™ SC2200 Processor Data Book 167 Core Logic Mo dule 32580B 6.2.9.2 Sleep States The SC2200 suppor ts four Sleep states (SL1-SL3) and the Soft Off state (G2 /S5). Thes e states are fully compliant with the ACPI specific ation, revision 1.0. When the SLP_EN bit (F1BAR1+I/O Offset 0Ch[13]) is set to 1, the SC2200 ente rs an SLx state accord[...]

168 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B 6.2.9.3 P ower Planes Control The SC2200 suppor ts up to three power planes. Three sig- nals are used to control these power planes. T able 6-6 describes th e signals and when each is asser ted. These signals allow control of the po wer of system de vices and the SC2200 itse lf .[...]

AMD Geode™ SC2200 Processor Data Book 169 Core Logic Mo dule 32580B P ower Button The power b utton (PWRBTN#) input provides two e vents: a wak e request, and a sleep request. For both these e v ents, the PWRBTN# signal is d ebounced (i.e., the signal state is transf erred only afte r 14 to 16 ms without transitions, to ensure that the signal is [...]

170 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B 6.2.10 P ower Mana gement Programming The power management resources provided by a com- bined GX1 module and Core Logic module base d system suppor ts a high efficiency power management implementa- tion. The follo wing explanations per tain to a full-featured “notebook” power[...]

AMD Geode™ SC2200 Processor Data Book 171 Core Logic Mo dule 32580B The automatic speedup events (video and IRQ) f or Sus- pend Modulation should be used together with software- controlled speedup register s f or major I/O ev ents such as any access to the FDC, HDD , or parallel/ser ial por ts, since these are indications of major system activiti[...]

172 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B 6.2.10.3 P eripheral Po wer Management The Core Logic module provides peripheral power man- agement using a combination of device idle timers, address traps, and general pur pose I/O pins. Idle timers are used in conjunction with traps to suppor t powering down peripheral devices[...]

AMD Geode™ SC2200 Processor Data Book 173 Core Logic Mo dule 32580B P ower Management SMI Status Repor ting Registers The Core Logic mod ule updates status registers to reflect the SMI sources. P o wer management SMI sources are the de vice idle timers, address traps, and general pur pose I/O pins. P o wer management ev ents are repor ted to the [...]

174 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B 6.2.10.4 P ower Manageme nt Pr ogramming Summary T a b le 6-9 provides a programming register summar y for the power management timers, tr aps, and functions. For com- plete bit inform ation regarding the registe rs listed in T able 6-9, ref er to Section 6.4.1 "Br idge, GPI[...]

AMD Geode™ SC2200 Processor Data Book 175 Core Logic Mo dule 32580B 6.2.11 GP IO Interface Up to 64 GPIOs in the in the Core Logi c module are pro- vided f or system control. F or fur ther inf ormation, see Sec- tion 4.2 "Multiplexing, Inte rr upt Selection, and Base Address Registers" on page 76 and T able 6-30 "F0BAR0+I/O Offset:[...]

176 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B Physical Region Descriptor T able Address Bef ore the bus master star ts a master transfer it must be pro- grammed with a pointer (PRD T able Address register) to a Ph ysical Region Descr iptor T able . This pointer sets the sta rt- ing memor y location of the Physical Region Des[...]

AMD Geode™ SC2200 Processor Data Book 177 Core Logic Mo dule 32580B 4) Read the SMI Status register to clear the Bus Master Error and End of P age bits (bits 1 and 0). Set the correct directi on to the Read or Write Contro l bit (Command register bit 3). Note that the direction of the data transfer of a par ticular bus master is fix ed and theref[...]

178 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B 6.2.12.2 A C97 Codec Interface The AC97 codec is the master of the serial interf ace and generates the clocks to Core Logic module. Figure 6-13 shows the signal connections between two codecs and the SC2200: • Codec1 can be AC97 Re v . 1.3 or higher compliant. • Codec2 is opt[...]

AMD Geode™ SC2200 Processor Data Book 179 Core Logic Mo dule 32580B 6.2.12.3 VSA T echnolo g y Suppor t Hardware The Core Logic mod ule incor porates the required hard- ware in order to suppor t the Vir tual System Architecture™ (VSA) technology f or capture and playback of audio using an external codec. This el iminates much of the hardware tr[...]

180 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B F ast P ath Wr ite captures t he data and address bit 1 (A1) of the first access, b ut does not generate an SMI. A1 is stored in F3BAR0+Memor y Offset 14h[15]. The second access causes an SMI, and the data and a ddress are captured as in a nor mal trapped I/O . In F ast P ath Wri[...]

AMD Geode™ SC2200 Processor Data Book 181 Core Logic Mo dule 32580B 6.2.12.4 IRQ Configuration Registers The Core Logic modul e provides the ability to set and cle ar IRQs inter nally through software control. If the IRQs are configured for softw are control, they do not respond to ex ter nal hardware . There are two registers provided for this f[...]

182 AMD Geode™ SC2200 Processor Data Book Core Logic Mo dule 32580B 6.2.12.6 LPC Interface Signal Definitions The LPC specification lists seven required and six optional signals for supporti ng the LPC interface . Many of the sig- nals are the same sign als f ound on the PCI interface and do not require any new pins on the host. Required signals [...]

AMD Geode™ SC2200 Processor Data Book 183 Core Logic Module - PCI Configuration Space an d Access Methods 32580B 6.3 Register Descriptions The Core Logic modul e is a multi-function module. Its reg- ister space can be broadly divided into three categories in which specific types of registers are located: 1) Chipset Register Space (F0-F5) (Note th[...]

184 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Re gister Summary 32580B 6.3.2 Register Su mmary The tables in this subsection summarize the registe rs of the Core Logic module. Included in the tables are the regis- ter’ s reset v alues and page references where the bit f or- mats are f ound. Note: Function 4 (F4) is f or Video Pr[...]

AMD Geode™ SC2200 Processor Data Book 185 Core Logic Mo dule - Registe r Summary 32580B 6Ch-6Fh 32 R/W R OM Mask Register 0000FF F0h P age 209 70h-71h 16 R/W IOCS1# Base Address Register 0000h P age 209 72h 8 R /W IOCS1# Control Register 00h Page 209 73h 8 --- Rese rved 00h P age 210 74h-75h 16 R /W IOCS0 Base Address Register 0000h Page 210 76h [...]

186 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Re gister Summary 32580B B8h 8 RO DMA Shadow Register xxh P age 225 B9h 8 RO PIC Shadow Register xxh P age 225 BAh 8 RO PIT Shadow Register xxh P age 226 BBh 8 RO RTC Index Shado w Register xxh Page 226 BCh 8 R/W Clock Stop Control Register 00h Page 226 BDh-BFh --- --- Reserved 00h Pag[...]

AMD Geode™ SC2200 Processor Data Book 187 Core Logic Mo dule - Registe r Summary 32580B T able 6-15. F0B AR0: GPIO Support Registers Summary F0BAR0+ I/O Offset Width (Bits) T ype Name Reset Va l u e Reference (T able 6-30) 00h-03h 32 R /W GPDO0 — GPIO Data Out 0 Register FFFFFFFFh P age 233 04h-07h 32 RO GPDI0 — GPIO Data In 0 Register F FFFF[...]

188 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Re gister Summary 32580B T able 6-17. F1: PCI He ader Registers for SMI Status and A CPI Suppor t Summary F1 Index Width (Bits) T ype Name Reset Va l u e Reference (T able 6-32) 00h-01h 16 RO V endor Identification Registe r 100Bh P age 245 02h-03h 16 RO Device Identification Register [...]

AMD Geode™ SC2200 Processor Data Book 189 Core Logic Mo dule - Registe r Summary 32580B T able 6-19. F1BAR1: A CPI Suppor t Registers Summar y F1BAR1+ I/O Offset Width (Bits) T ype Name Reset Va l u e Reference (T able 6-34) 00h-03h 32 R/W P_CNT — Processor Control Register 00000000h P age 255 04h 8 RO Reser ved, do not read 00h P age 255 05h 8[...]

190 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Re gister Summary 32580B T able 6-20. F2: PCI Header Register s f or IDE Controller Suppo r t Summary F2 Index Width (Bits) T ype Name Reset Va l u e Reference (T able 6-35) 00h-01h 16 RO V endor Identification Registe r 100Bh P age 266 02h-03h 16 RO Device Identification Register 0502[...]

AMD Geode™ SC2200 Processor Data Book 191 Core Logic Mo dule - Registe r Summary 32580B T able 6-21. F2BAR4: IDE Controlle r Support Registers Su mmary F2BAR4+ I/O Offset Width (Bits) T ype Name Reset Va l u e Reference (T able 6-36) 00h 8 R/W IDE Bus Master 0 Command Register — Primar y 00h P age 270 01h --- --- Not Used --- P age 270 02h 8 R/[...]

192 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Re gister Summary 32580B T able 6-23. F 3B AR0: Audio Support Re gisters Summary F3BAR0+ Memory Offset Width (Bits) T ype Name Reset Va l u e Reference (T able 6-38) 00h-03h 32 R /W Codec GPIO Status Register 00000000h Page 273 04h-07h 32 R /W Codec GPIO Control Register 00000000h Page[...]

AMD Geode™ SC2200 Processor Data Book 193 Core Logic Mo dule - Registe r Summary 32580B T able 6-24. F5: PCI He ader Registers for X-Bus Expansion Suppor t Summary F5 Index Width (Bits) T ype Name Reset Va l u e Reference (T able 6-39) 00h-01h 16 RO V endor Identification Registe r 100Bh P age 287 02h-03h 16 RO Device Identification Register 0505[...]

194 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Re gister Summary 32580B T able 6-26. PCIUSB: USB PCI Confi guration Registe r Summary PCIUSB Index Width (Bits) T ype Name Reset V alue Reference (T able 6-41) 00h-01h 16 RO V endor Identification 0E11h P age 292 02h-03h 16 RO Device Identification A0F8h Page 292 04h-05h 16 R/W Comman[...]

AMD Geode™ SC2200 Processor Data Book 195 Core Logic Mo dule - Registe r Summary 32580B T able 6-27. USB_BAR: USB Contr oller Register s Summary USB_BAR0 +Memory Offset Width (Bits) Type Name Reset Value Reference (T able 6-42) 00h-03h 32 R/W HcRe vision 00000110h Page 295 04h-07h 32 R/W HcControl 00000000h Page 295 08h-0Bh 32 R/W HcCommandStatus[...]

196 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Re gister Summary 32580B T able 6-28. ISA Legacy I/O Re gister Summary I/O P or t T ype Name Reference DMA Channel Control Registers (T able 6-43) 000h R/W DMA Channel 0 Address Register P age 305 001h R/W DMA Channel 0 T ransf er Count Register P age 305 002h R/W DMA Channel 1 Address[...]

AMD Geode™ SC2200 Processor Data Book 197 Core Logic Mo dule - Registe r Summary 32580B 487h R/W DMA Channel 0 High Page Register P age 310 489h R/W DMA Channel 6 High Page Register P age 310 48Ah R/W DMA Channel 7 High P age Register Page 310 48Bh R/W DMA Channel 5 High P age Register Page 310 Programmable Interval Timer Registers (T able 6-45) [...]

198 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B 6.4 Chipset Register Space The Chipset Register Space of the Core Logic module is comprised of six separate functions (F0-F5), ea ch with its own register space . Base Address Registers (BARs) in each PCI header register space set t[...]

AMD Geode™ SC2200 Processor Data Book 199 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B 4 Memory Write an d In validate. Allow the Core Logic module to do memory wr ite and in validate cycles , if the PCI Cache Line register (F0 Index 0Ch) is set to 32 bytes (08h). 0: Disable. (Def ault) 1: Enab le. 3 Special Cycles. Al[...]

200 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B Index 08h Device Revision ID Register (RO) Re set V alue: 00h Index 09h-0Bh PCI Class Co de Register (RO) Reset V alue: 060100h Index 0Ch PCI Cache Line Size Register (R/W) Re set V alue: 00h 7:0 PCI Cache Line Size Register . This [...]

AMD Geode™ SC2200 Processor Data Book 201 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B Index 40h PCI Function Co ntr ol Register 1 (R/W) Reset V alue: 39h 7:6 Reserved. Must be set to 0. 5 Reserved. Must be set to 0. 4 PC I Subtractiv e Decode. 0: Disable transf er of subtractiv e decode address to ex ternal PCI bus. E[...]

202 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B 0 Legac y Configur ation T rap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function 0 (F0), an SMI is generated. Reads and wr ites are snooped; access to the register is allowed. 0: Dis[...]

AMD Geode™ SC2200 Processor Data Book 203 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B 2 IDE Reset. Reset IDE bus . 0: Disab le. 1: Enab le (driv e IDE_R ST# lo w). Write 0 to clear. This bit is lev el-sensitiv e and must be cleared after the reset is enabled. Note: When X-Bus W arm Star t is enabled (bit 0 = 1) or dur[...]

204 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B Index 48h-4Bh Reserved Reset V alue: 00h Index 4Ch-4Fh T op of System Memor y (R/W) Reset Value: FFFFFFFFh 31:0 T op of Syste m Memory . Highest address in system used to deter mine acti ve decode for e x ternal PCI mastered memor y[...]

AMD Geode™ SC2200 Processor Data Book 205 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B Index 52h ROM/A T Logic Control Register (R/W) Reset V alue: 98h 7 Snoop Fast Keyboar d Gate A20 and Fast Reset. Enab les the snoop lo gic associat ed with k eyboard commands for A20 Mask and Reset. 0: Disable snooping. The ke yboard[...]

206 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B Index 5Ah Decode Control Register 1 (R/W) Reset V alue: 01h Indicates PCI positive or negativ e decodi ng for v arious I/O por ts on the ISA bus . Note: P ositive decoding by the Core Logic module speeds up I/O cycle time. The I/O p[...]

AMD Geode™ SC2200 Processor Data Book 207 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B 3 Primary IDE Controller P ositive Decode . Selects PCI positiv e or subtractive de coding f or accesses to I/O por ts 1F0h- 1F7h and 3F6h-3F7h (excluding writes to 3F7h). 0: Subtractive . Subtractively decoded IDE addresses are f or[...]

208 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B 5 SUSP_3 V Shut Down PL L3. Allow internal SUSP_3V to shut down PLL3. 0: Clock generator is stopped when internal SUSP_3V is activ e. 1: Clock generator continues working when internal SUSP_3V is active.. 4 SUSP_3 V Shut Down PL L2.[...]

AMD Geode™ SC2200 Processor Data Book 209 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B 4:0 IOCS1# I/O Address Rang e. This 5-bit field is used to select the range of IOCS1#. 00000: 1 Byte 01111: 16 Bytes 00001: 2 Bytes 11111: 32 Bytes 00011: 4 Bytes All other combinations are reser v ed. 00111: 8 Bytes Index 73h Reser [...]

210 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B Index 80h Po wer Management Enable Register 1 (R/W) Reset V alue: 00h 7:6 Reserved. Must be set to 0. 5 Codec SDA T A_IN SMI. When set to 1, this bit allows an SMI to be generated in response to an AC97 codec producing a positive ed[...]

AMD Geode™ SC2200 Processor Data Book 211 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B 6 User Defined Device 3 (UDEF3) Idle Timer Enable. T urn on UDEF3 Idle Timer Cou nt Register (F0 Inde x A4h) and gener- ate an SMI when the timer expires. 0: Disab le. 1: Enab le. If an access occurs in the programmed address range ,[...]

212 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B 1 Floppy Disk Idle Timer Enable. T ur n on Floppy Disk Idle Timer Count Register (F0 Inde x 9Ah) and generate an SMI when the timer expires. 0: Disab le. 1: Enab le. If an access occurs in the address ranges (listed bel ow , the tim[...]

AMD Geode™ SC2200 Processor Data Book 213 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B 2 Parallel/Serial Access T rap. 0: Disab le. 1: Enab le. If this bit is enabled and an access occurs in the address ranges listed below , an SMI is generated. — LPT1: I/O P or t 3BCh-3BEh. — LPT2: I/O P or t 378h-37Fh. — COM1: [...]

214 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B 3 VG A T im e r Ena ble. T u rn on VGA Timer Count Register (F0 Inde x 8Eh) and generate an SMI when the timer reaches 0. 0: Disab le. 1: Enab le. If an access occurs in the programmed address range , the time r is reloaded with the[...]

AMD Geode™ SC2200 Processor Data Book 215 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B Index 85h Secon d Level PME/SMI Status Mirr or Register 2 (RO) Reset V alue: 00h The bits in this register c ontain second lev el status repor ting. T op level st atus is reported in F1BAR0+I/O Offset 00h/02h[0]. This register is cal[...]

216 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B Index 86h Secon d Level PME/SMI Status Mirr or Register 3 (RO) Reset V alue: 00h The bits in this register c ontain second lev el status repor ting. T op level st atus is reported in F1BAR0+I/O Offset 00h/02h[0]. This register is ca[...]

AMD Geode™ SC2200 Processor Data Book 217 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B Index 87h Secon d Level PME/SMI Status Mirr or Register 4 (RO) Reset V alue: 00h The bits in this register cont ain second lev el status repor ting. T op level status is reported at F1BAR0+I/O Offset 00h/02h[0]. This register is call[...]

218 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B Index 89h General Purpose Timer 1 Control Register (R/W) Re set V alue: 00h 7 General Purpose Timer 1 TImebase . Selects timebase for General Purpose Timer 1 (F0 Index 88h). 0: 1 second. 1: 1 millisecond. 6 Re-trigger General Purpos[...]

AMD Geode™ SC2200 Processor Data Book 219 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B Index 8Ah General Purpose Timer 2 Count Register (R/W) Reset V alue: 00h 7:0 GPT2_COUNT . This field represents the load v alue for Gener al Pur pose Timer 2. This value can represent either an 8-bit or 16-bit counter (configured in [...]

220 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B Index 8Eh V GA Timer Count Register (R/W) Reset V alu e: 00h 7:0 V GA Timer Load V alue. This field represents the load value f or V GA Timer . It is loaded into the counter when the timer is enabled (F0 Inde x 83h[3] = 1). The coun[...]

AMD Geode™ SC2200 Processor Data Book 221 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B 2 Suspend Mode Conf iguration. Special 3V Suspend mode to suppor t powering down the GX1 module during Suspend. 0: Disab le. 1: Enab le. 1 SMI Speedup Configuration . Selects ho w the Suspend Modulation function should rea ct when an[...]

222 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B Index 9Eh-9Fh Keyboar d / Mouse Idle Timer Count Register (R /W) Reset V alue: 0000h 15:0 Keyboar d / Mouse Idle Timer C ount. This idle timer determines when the key board and mouse are not in use so that the LCD screen can be blan[...]

AMD Geode™ SC2200 Processor Data Book 223 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B Index A Ch-ADh Secondary Hard Disk Idle Timer Count Register (R /W) Reset Value: 0000h 15:0 Secondary Hard Disk Idle Timer Count. This idle timer is used to determine whe n the secondary hard disk is not in use so that it can be powe[...]

224 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B Index B8h DMA Shadow Register (RO) Reset V alu e: xxh 7:0 DMA Sha dow . This 8-bit por t sequences through the following list of shado wed DMA Controller registers. At power on, a pointer star ts at the first register in the list an[...]

AMD Geode™ SC2200 Processor Data Book 225 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B Index BBh R TC Index Shadow Register (RO) Reset V alue: xxh 7:0 RTC Index Shadow . The RTC Shadow register contains the last written v alue of the RTC Inde x register (I/O P ort 070h). Index BCh Clock Stop Control Register (R/W) Rese[...]

226 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B 6:0 Mask. If bit 7 = 0 (I/O): Bit 6 0: Disable write cycle tracking 1: Enable write cycle trac king Bit 5 0: Disable read cycle trac king 1: Enable read cycle trac king Bits [4:0] Mask for address bits A[4:0] If bit 7 = 1 (Memor y):[...]

AMD Geode™ SC2200 Processor Data Book 227 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B Index F4h Second Level PME/SMI Status Register 1 (RC) Reset V alue: 00h The bits in this register c ontain second lev el status repor ting. T op level st atus is reported in F1BAR0+I/O Offset 00h/02h[0]. Reading this register clears [...]

228 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B 3 Keyboar d/Mouse Idle Timer SMI Sta tus. Indicates whether or not an SMI was caused by e xpiration of K e yboard/ Mouse Idle Timer Count Register (F0 Index 9Eh). 0: No . 1: Y es. T o enable SMI generation, set F0 Index 81h[3] = 1. [...]

AMD Geode™ SC2200 Processor Data Book 229 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B 1 Floppy Disk Access T rap SMI Status. Indicates whether or not a n SMI w as caused by a trapped I/O access to the flopp y disk. 0: No . 1: Y es. T o enable SMI generation, set F0 Index 82h[1] = 1. 0 Primary Hard Disk Access T rap SM[...]

230 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B 0 A CPI Timer SMI Statu s. Indicates whether or not an SMI was caused by an A CPI Timer (F1BAR0+I/O Offset 1Ch or F1BAR1+I/O Offset 1Ch) MSB toggle. 0: No . 1: Y es. T o enable SMI generation, set F0 Index 83h[5] = 1. Index F8h-FFh [...]

AMD Geode™ SC2200 Processor Data Book 231 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B 6.4.1.1 GPIO Supp ort Registers F0 Inde x 10h, Base Address Register 0 (F0 BAR0) points to the base address of where the GPIO runtime an d configu- ration registers are located. T a b le 6-29 gives the bit f ormats of I/O mapped regi[...]

232 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B Offset 14h-17h GPDI1 — GPIO Data In 1 Register (RO) Reset V alue: FFFFFFFFh 31:0 GPIO Data In. Bits [31:0] of this reg ister correspond to GPIO63-GP IO32 signals, respectiv ely . R eading each bit returns the value of the correspo[...]

AMD Geode™ SC2200 Processor Data Book 233 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B 5:0 Signal Select. Selects the GPIO signal to be configured in the Bank se lected via bit 5 setting (i.e., Bank 0 or Bank 1). See T able 4-2 on page 76 for GPIO ball muxing options. GPIOs without an associated ball n umber are not av[...]

234 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B 4 PME Edge/Level Select. Selects the type (edge or lev el) of the signal that issues a PME from the selected GPIO signal. 0: Edge input. (Default) 1: Lev el input. For normal operation, alwa ys set this bit to 0 (edge input). Errati[...]

AMD Geode™ SC2200 Processor Data Book 235 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B 6.4.1.2 LPC Support Registers F0 Inde x 14h, Base Address Register 1 (F0 BAR1) points to the base address of the regist er space that contains the configuration registers for LPC suppor t. T able 6-31 gives the bit formats of the I/O[...]

236 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B 8 IRQ8# Source. Selects the interf ace source of the IRQ8# signal. 0: ISA - IRQ8# inter nal signal. (Connected to inter nal R TC.) 1: LPC - SERIRQ (ball J31). 7 IRQ7 S our ce. Selects the interface source of the IRQ7 signal. 0: ISA [...]

AMD Geode™ SC2200 Processor Data Book 237 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B 14 IRQ14 P olarity . If LPC is selected as the interface source for IRQ14 (F0BAR1+I/O Offset 00h[14] = 1), this bit allows signal polarity s election. 0: Active high. 1: Active lo w . 13 IRQ13 P olarity . If LPC is selected as the in[...]

238 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B 2 SMI# P olarity . This bit allows signal polar ity se lection of the SMI# generated from LPC . 0: Active high. 1: Active lo w . 1 IRQ1 Polarity . If LPC is selected as the interface source f or IRQ1 (F0BAR1+I/O Offset 00h[1] = 1), [...]

AMD Geode™ SC2200 Processor Data Book 239 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B 2 DRQ2 Source. Selects the interface source of the DRQ2 signal. 0: ISA - DRQ2 (unava ilable e xternally). 1: LPC - LDR Q# (ball L28). 1 DRQ1 Source. Selects the interface source of the DRQ1 signal. 0: ISA - DRQ1 (unava ilable e xtern[...]

240 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B 1 LPC Serial Port 0 Addressing. Serial P or t 0 addresses. See bit 16 f or decode. Address selection made via F0BAR1+I/O Offset 14h[4:2]. 0 LPC Parallel P ort Addressing. P arallel P ort addresses. See bit 16 for decode. Address sel[...]

AMD Geode™ SC2200 Processor Data Book 241 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32580B Offset 18h-1Bh LAD_D1 — LPC Address D ecode 1 Register (R/W) Reset Value: 00000000h 31:16 Reserved. Must be set to 0. 15:9 Wide Generic Base Address Select. Defines a 512 byte space. Can be mapped anywhere in the 64 KB I/O space. A[...]

242 AMD Geode™ SC2200 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32580B 3 LPC Timeout Err or Status. Indicates whether or not an error was generated by a timeout on LPC . 0: No . 1: Y es. Write 1 to clear. 2 LPC Error Write Status. Indicates whether or not an error was generated during a wr ite operatio[...]

AMD Geode™ SC2200 Processor Data Book 245 Core Logic Module - SMI Status and ACPI Registers - Function 1 32580B 6.4.2 SMI Status an d A CPI Registers - Function 1 The register space design ated as Function 1 (F1) is used to configure the PCI por tion of suppor t hardware for the SMI Status and ACPI Support registe rs . The bit formats for the PCI[...]

246 AMD Geode™ SC2200 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32580B 6.4.2.1 SMI Status Suppor t Registers F1 Index 10h, Base Address Register 0 (F1BAR0), p oints to the base address f or SMI Status register locations. T able 6-33 gives the bit f ormats of I/O mapped SMI Status regis- ters accessed thr[...]

AMD Geode™ SC2200 Processor Data Book 247 Core Logic Module - SMI Status and ACPI Registers - Function 1 32580B 5 SMI Source is Video Retrace. Indicates whether or not an SMI was caused b y a video retrace e vent as decoded from the internal ser ial connection (PSERIAL register , bit 7) from the GX1 module. 0: No . 1: Y es. T o enable SMI generat[...]

248 AMD Geode™ SC2200 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32580B 10 SMI Source is EXT_SMI[7:0]. (Read Only . Read Does Not Clear) Indicate s whether or not an SMI was caused b y a neg- ative-edge e v ent on EXT_SMI[7:0]. 0: No . 1: Y es. The next le v el (second lev el) of SMI status is at F1BAR0+I[...]

AMD Geode™ SC2200 Processor Data Book 249 Core Logic Module - SMI Status and ACPI Registers - Function 1 32580B Offset 04h-05h Second Level General T raps & Timers Reset V alue: 0000h PME/SMI Status Mirror Register (R O) The bits in this register cont ain second lev el status repor ting. T op level status is reported at F1BAR0+I/O Offset 00h/[...]

250 AMD Geode™ SC2200 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32580B Offset 06h-07h Se cond Level General T raps & Ti mers Status Register (RC) Reset V alue: 0000h The bits in this register contain second le vel of status repor ting. T op lev el status is repor ted in F1BAR0+I/O Offset 00h/02h[9 ].[...]

AMD Geode™ SC2200 Processor Data Book 251 Core Logic Module - SMI Status and ACPI Registers - Function 1 32580B Offset 20h-21h Second Level ACPI PME/SMI Reset V alue: 0000h Status Mirror Register (RO) The bits in this register c ontain second lev el SMI status repor ting. T op leve l status is reported in F1BAR0+I/O Offset 00h/02h[ 2]. Reading th[...]

252 AMD Geode™ SC2200 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32580B 1 THT_EN SMI Status. Indicates whether or not an SMI was caused by a write of 1 to the A CPI THT_EN bit (F1BAR1+I/O Offset 00h[4]). 0: No . 1: Y es. T o enable SMI generation, set F1BAR1+ I/O Offset 1 8h[8] to 1 (def ault). 0 SMI_CMD [...]

AMD Geode™ SC2200 Processor Data Book 253 Core Logic Module - SMI Status and ACPI Registers - Function 1 32580B 15 EXT_SMI7 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an asser tion of EXT_SMI7. 0: No . 1: Y es. T o enable SMI generation, set bit 7 to 1. 14 EXT_SMI6 SMI Status. (Read Only) Indicates whether or not an SMI[...]

254 AMD Geode™ SC2200 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32580B 4 EXT_SMI4 SMI Enable. When this bit is asser ted, allows EXT_SMI4 to generate an SMI on negative-edge e vents. 0: Disable . 1: Enable. T op lev el SMI status is repor ted at F1BAR0+00h/02h[10]. Second lev el SMI status is reported at[...]

AMD Geode™ SC2200 Processor Data Book 255 Core Logic Module - SMI Status and ACPI Registers - Function 1 32580B 6.4.2.2 A CPI Support Registers F1 Index 40h, Base Address Register 1 (F1BAR1), p oints to the base addre ss of wher e the A CPI Suppor t registers are located. T able 6-34 shows the I/O mapped ACPI Sup- por t registers accessed through[...]

256 AMD Geode™ SC2200 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32580B 0 PWRBTN_DBNC_DIS (Power Button Debounce). When enabled, a high-to-low or lo w- to-high transition of greater than 15.8 ms is required on PWRBTN# before it is recognized. 0: Enable. (Def ault) 1: Disable. (No debounce) Offset 08h-09h [...]

AMD Geode™ SC2200 Processor Data Book 257 Core Logic Module - SMI Status and ACPI Registers - Function 1 32580B 4 BM_STS (Bus Master Status). Indicates if PME was caused b y a system bus master requesting the system bus. 0: No . 1: Y es. For the PME to gener ate an SCI, set F1BAR1+I/O Offset 0Ch[1] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note [...]

258 AMD Geode™ SC2200 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32580B 12:10 SLP_TYPx (Sleep T ype). Defines the type of Sleep state the system enters when SLP_EN (bit 13) is set. 000: Sleep State S0 (Full on) 100: Sleep State SL4 001: Sleep State SL1 101: Sleep State SL5 (Soft off) 010: Sleep State SL2 [...]

AMD Geode™ SC2200 Processor Data Book 259 Core Logic Module - SMI Status and ACPI Registers - Function 1 32580B 10 GPWIO2_STS. Indicates if PME was caused b y activity on GPWIO2. 0: No . 1: Y es. Write 1 to clear. For the PME to generate an SCI: 1) Ensure that GPWIO2 is enabled as an input (F1BAR1+I/O Offset 15h[2] = 0). 2) Set F1BAR1+I/O Offset [...]

260 AMD Geode™ SC2200 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32580B 3 GPIO_STS. Indicates if PME was caused b y activity on any of t he GPIOs (GPIO47-GPIO 32 and GPIO15-GPIO0). 0: No . 1: Y es. Write 1 to clear. For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[3] = 1 and F1BAR1+I/O Offset 0Ch[...]

AMD Geode™ SC2200 Processor Data Book 261 Core Logic Module - SMI Status and ACPI Registers - Function 1 32580B 3 GPIO_EN. Allow GPIOs (GPIO47- GP IO32 and GPIO15-GPIO0) to generate an SCI. 0: Disab le. 1: Enab le. F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled for PME generation. This bit (GPIO_EN) globally enables those selected GPIO[...]

262 AMD Geode™ SC2200 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32580B 2 GPWIO2_DIR. Selects the direction of GPWIO2. 0: Input. 1: Output. 1 GPWIO1_DIR. Selects the direction of GPWIO1. 0: Input. 1: Output. 0 GPWIO0_DIR. Selects the direction of the GPWIO0. 0: Input. 1: Output. Offset 16h GPWIO Data Regi[...]

AMD Geode™ SC2200 Processor Data Book 263 Core Logic Module - SMI Status and ACPI Registers - Function 1 32580B 8 THT_SMIEN. Allow SMI generation when the THT_EN bit (F1BAR1+I/O Offset 00h[4]) is set. 0: Disab le. 1: Enable. (Def ault) T op lev el SMI status is repor ted at F1BAR0+I/O Offset 00h/02h[2]. Second lev el SMI status is repor ted at F1[...]

266 AMD Geode™ SC2200 Processor Data Book Core Logic Module - IDE C ontr oller Registers - Function 2 32580B 6.4.3 IDE Controller Register s - Function 2 The register space design ated as Function 2 (F2) is used to configure Channels 0 and 1 and the PCI portion of sup- por t hardware f or the IDE controllers. The bit formats for the PCI Header/Ch[...]

AMD Geode™ SC2200 Processor Data Book 267 Core Logic Module - IDE Controller Registers - Function 2 32580B Index 40h-43h Channel 0 Drive 0 PI O Register (R/W) Reset Value: 00009172h If Index 44h[31] = 0, F ormat 0. Bits [15:0] configure the same timing control for both command and data. Format 0 settings for a F ast-PCI clock frequency of 33.3 MH[...]

268 AMD Geode™ SC2200 Processor Data Book Core Logic Module - IDE C ontr oller Registers - Function 2 32580B Index 44h-47h Channel 0 Drive 0 DMA C ontrol Register (R /W) Reset V alue: 00077771h The structure of this register depends on the v alue of bit 20. If bit 20 = 0, Multiword DMA Settings for a F ast-PCI clock frequency of 33.3 MHz: — Mul[...]

AMD Geode™ SC2200 Processor Data Book 269 Core Logic Module - IDE Controller Registers - Function 2 32580B Index 50h-53h Channel 1 Drive 0 PI O Register (R/W) Reset Value: 00009172h Channel 1 Drive 0 Programmed I/O Control Register . See F2 Inde x 40h for bit descriptions. Index 54h-57h Channel 1 Drive 0 DMA C ontrol Register (R /W) Reset V alue:[...]

270 AMD Geode™ SC2200 Processor Data Book Core Logic Module - IDE C ontr oller Registers - Function 2 32580B 6.4.3.1 IDE Controller Support Registers F2 Index 20h, Base Address Register 4 (F2BAR4), p oints to the base address o f where the registers for IDE control- ler configuration are located. T able 6-36 gives the bit f or- mats of the I/O ma[...]

AMD Geode™ SC2200 Processor Data Book 271 Core Logic Module - IDE Controller Registers - Function 2 32580B Offset 08h ID E Bus Master 1 Command Register — Secondar y (R/W) Reset V alue: 00h 7:4 Reserved. Must be set to 0. Must retur n 0 on reads. 3 Read or Write Control. Sets the direction of bus master transf ers. 0: PCI reads are performed. 1[...]

272 AMD Geode™ SC2200 Processor Data Book Core Logic Module - A udio Registers - Function 3 32580B 6.4.4 Audio Register s - Function 3 The register designated as Func tion 3 (F3) is used to con- figure the PCI por tion of suppor t hardware f or the audio registers. The bit formats for the PCI Header regi sters are given in T able 6-37. A Base Add[...]

AMD Geode™ SC2200 Processor Data Book 273 Core Logic Module - Audio Registers - Function 3 32580B 6.4.4.1 A udio Support Re gisters F3 Index 10h, Base Address Register 0 (F3BAR0), p oints to the base address of where the registers for audio sup- por t are located. T able 6-38 gives the bit f ormats of the memor y mapped audio configuration regist[...]

274 AMD Geode™ SC2200 Processor Data Book Core Logic Module - A udio Registers - Function 3 32580B 16 Codec Status V alid. (Read Only) Indicates if the status in bits [15:0] of this r egister is valid. This bi t is high during slots 3 to 11 of the AC97 frame (i.e ., for appro ximately 14.5 µs), f or ev ery frame. 0: No . 1: Y es. 15:0 Codec Stat[...]

AMD Geode™ SC2200 Processor Data Book 275 Core Logic Module - Audio Registers - Function 3 32580B 4 Audio Bus Master 2 SMI Status. Indicates if an SMI was caused by an e vent occurring on A udio Bus Master 2. 0: No . 1: Y es. SMI generation is enabled when A udio Bus Master 2 is enabled (F3BAR0+Memory Offse t 30h[0] = 1). An SMI is then generated[...]

276 AMD Geode™ SC2200 Processor Data Book Core Logic Module - A udio Registers - Function 3 32580B 4 Audio Bus Master 2 SMI Status. Indicates if an SMI was caused by an e vent occurring on A udio Bus Master 2. 0: No . 1: Y es. SMI generation is enabled when A udio Bus Master 2 is enabl ed (F3BAR0+Memory Offse t 30h[0] = 1). An SMI is then gen- er[...]

AMD Geode™ SC2200 Processor Data Book 277 Core Logic Module - Audio Registers - Function 3 32580B 12 DMA T rap SMI Sta tus. (Read to Clear) Indicates if an SMI was caused by a trapped I/O access to the DMA I/O T rap. 0: No . 1: Y es. (See the note included in the general description of this register above.) This is the third lev el of SMI status [...]

278 AMD Geode™ SC2200 Processor Data Book Core Logic Module - A udio Registers - Function 3 32580B 5 Low MPU I/O T rap. If this bit is enabled and an access occurs at I/O P or t 300h-301h, an SMI is generated. 0: Disab le. 1: Enab le. T op lev el SMI status is repor ted at F1BAR0+I/O Offset 00h/02h[1]. Second lev el SMI status is repor ted at F3B[...]

AMD Geode™ SC2200 Processor Data Book 279 Core Logic Module - Audio Registers - Function 3 32580B 7 IRQ7 Intern al. Configures IRQ7 f or inter nal (so ftware) or e xternal (hardware) use. 0: Exter nal. 1: Internal. 6 Reserved. Must be set to 0. 5 IRQ5 Intern al. Configures IRQ5 f or inter nal (so ftware) or e xternal (hardware) use. 0: Exter nal.[...]

280 AMD Geode™ SC2200 Processor Data Book Core Logic Module - A udio Registers - Function 3 32580B 20 Mask Internal IRQ4. (Write Only) 0: Disab le. 1: Enab le. 19 Mask Internal IRQ3. (Write Only) 0: Disab le. 1: Enab le. 18 Reserved. (Write Only) Must be set to 0. 17 Mask Internal IRQ1. (Write Only) 0: Disab le. 1: Enab le. 16 Reserved. (Write On[...]

AMD Geode™ SC2200 Processor Data Book 281 Core Logic Module - Audio Registers - Function 3 32580B 1 Assert Masked Internal IRQ1. 0: Disab le. 1: Enab le. 0 Reserved. Must be set to 0. Offset 20h Audio Bus Master 0 Command Register (R/W) Reset Value: 00h Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4. 7:4 Reser[...]

282 AMD Geode™ SC2200 Processor Data Book Core Logic Module - A udio Registers - Function 3 32580B Offset 28h Audio Bus Master 1 Command Register (R/W) Reset Value: 00h Audio Bus Master 1: Input from codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 7:4 Reserved. Must be set to 0. Must retur n 0 on reads. 3 Read or Write Control. Set the tra[...]

AMD Geode™ SC2200 Processor Data Book 283 Core Logic Module - Audio Registers - Function 3 32580B Offset 30h Audio Bus Master 2 Command Register (R/W) Reset Value: 00h Audio Bus Master 2: Output to codec; 16-Bit; Slot 5. 7:4 Reserved. Must be set to 0. Must retur n 0 on reads. 3 Read or Write Control. Sets the transf er direction of Audio Bus Mas[...]

284 AMD Geode™ SC2200 Processor Data Book Core Logic Module - A udio Registers - Function 3 32580B Offset 38h Audio Bus Master 3 Command Register (R/W) Reset Value: 00h Audio Bus Master 3: Input from codec; 16-Bit; Slot 5. 7:4 Reserved. Must be set to 0. Must retur n 0 on reads. 3 Read or Write Control. Sets the transf er direction of Audio Bus M[...]

AMD Geode™ SC2200 Processor Data Book 285 Core Logic Module - Audio Registers - Function 3 32580B Offset 40h Audio Bus Master 4 Command Register (R/W) Reset Value: 00h Audio Bus Master 4: Output to codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memor y Offset 08h[19] selects slot). 7:4 Reserved. Must be set to 0. Must retur n 0 on reads. 3 Read or Write Con[...]

286 AMD Geode™ SC2200 Processor Data Book Core Logic Module - A udio Registers - Function 3 32580B Offset 48h Audio Bus Master 5 Command Register (R/W) Reset Value: 00h Audio Bus Master 5: Input from codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[20] sele cts slot). 7:4 Reserved. Must be set to 0. Must retur n 0 on reads. 3 Read or Write C[...]

AMD Geode™ SC2200 Processor Data Book 287 Core Logic Module - X-Bus Expansion Interface - Fu nction 5 32580B 6.4.5 X-Bus Expansion Interface - Function 5 The register space design ated as Function 5 (F5) is used to configure the PCI por tion of suppor t hardware for accessing the X-Bus Expansion suppor t registers. The bit f or mats f or the PCI [...]

288 AMD Geode™ SC2200 Processor Data Book Core Logic Module - X-Bus Expansi on Interface - Function 5 32580B Index 1Ch-1Fh Base Address Registe r 3 - F5B AR3 (R/W) Reset V alue: 00000000h Reserved. Reser ved f or possible future use by the Core Logic module. Configuration of this register is programmed th rough the F5BAR3 Mask Register (F5 Index [...]

AMD Geode™ SC2200 Processor Data Book 289 Core Logic Module - X-Bus Expansion Interface - Fu nction 5 32580B Index 44h-47h F5BAR1 Mask Address Register (R/W) Reset V alue: 00000000h T o use F5BAR1, the mask register sho uld be programmed first. The mask register def ines the size of F5BAR1 and whether the accessed offset registers are memor y or [...]

290 AMD Geode™ SC2200 Processor Data Book Core Logic Module - X-Bus Expansi on Interface - Function 5 32580B 6.4.5.1 X-Bus Expansio n Suppor t Registers F5 Index 10h, Base Address Register 0 (F5BAR0) set the base address that allows PCI access to addi tional I/O Con- trol suppor t registers. T able 6-40 shows the suppor t regis- ters accessed th [...]

AMD Geode™ SC2200 Processor Data Book 291 Core Logic Module - X-Bus Expansion Interface - Fu nction 5 32580B Offset 04h-07h I/O Control Regi ster 2 (R/W) Reset V alue: 00000002h 31:2 Reserved. Write as read. 1 Video Processor Access Enable. Allows access to video processor using F4BAR0. 0: Disab le. 1: Enable. (Def ault) Note: This bit is readabl[...]

292 AMD Geode™ SC2200 Processor Data Book Core Logic Module - USB Con tr oller Registers - PCIUSB 32580B 6.4.6 USB Controller Registers - PCIUSB The registers designated as PCIUSB are 32-bit registers decoded from the PCI address bits [7 :2] and C/BE[3:0]#, when IDSEL is high, AD[10:8] select the app ropriate func- tion, and AD[1:0] are 00. The P[...]

AMD Geode™ SC2200 Processor Data Book 293 Core Logic Module - USB Controller Registers - PCIUSB 32580B Index 06h-07h Status Register (R/W) Reset V alu e: 0280h The PCI specification defines this register to record status in f ormation for PCI rela ted ev ents. This is a read/write register. Ho we ver , writes can only reset bits. A bit is reset w[...]

294 AMD Geode™ SC2200 Processor Data Book Core Logic Module - USB Con tr oller Registers - PCIUSB 32580B Index 10h-13h Base Address Register - USB_BAR0 (R/W) Reset Value: 00000000h 31:12 Base Address. POST writes the value of the memor y base address to this register . 11:4 Alwa ys 0. Indicates that a 4 KB address range is requested. 3 Alwa ys 0.[...]

AMD Geode™ SC2200 Processor Data Book 295 Core Logic Module - USB Controller Registers - PCIUSB 32580B T able 6-42. USB_B AR+Memory Offset: USB Contr oller Registers Bit Description Offset 00h-03h Hc Revision Register (R O) Reset V alue = 0000011 0h 31:8 Reserved. Read/Wr ite 0s . 7:0 Revision (Read Only). Indicates the Open HCI Specification rev[...]

296 AMD Geode™ SC2200 Processor Data Book Core Logic Module - USB Con tr oller Registers - PCIUSB 32580B 6 RootHubStatusChang e. This bit is set when the conten t of HcRhStatus or the content of any HcRhP or tStatus register has changed. 5 FrameNumberOverflow . Set when bit 15 of Fr ameNumber changes value. 4 UnrecoverableErr or (Read Only). This[...]

AMD Geode™ SC2200 Processor Data Book 297 Core Logic Module - USB Controller Registers - PCIUSB 32580B 6 RootHubStatusChang eEnable. 0: Ignore. 1: Disable interrupt generation due to Root Hub Status Change. 5 FrameNumberOverflowEnable. 0: Ignore. 1: Disable interrupt generation due to Fr ame Number Overflo w . 4 UnrecoverableErr orEnable. This ev[...]

298 AMD Geode™ SC2200 Processor Data Book Core Logic Module - USB Con tr oller Registers - PCIUSB 32580B Offset 34h-37h HcFmInterval Register (R/W) Reset V alue = 00002EDFh 31 FrameIntervalT oggle (Read Only). This bit is toggled by HCD when it loads a new v alue into F rameInterval. 30:16 FSLargestDataP acket (Read Only ). This field specifies a[...]

AMD Geode™ SC2200 Processor Data Book 299 Core Logic Module - USB Controller Registers - PCIUSB 32580B 7:0 NumberDownstreamP orts (Read Only). USB suppor ts three downstream por ts. Note: This register is only reset b y a power-on reset (PCIRST#). It is wr itten during system initialization to configu re the Root Hub . These bit should not be wri[...]

300 AMD Geode™ SC2200 Processor Data Book Core Logic Module - USB Con tr oller Registers - PCIUSB 32580B Offset 54h-57h HcRhPortStatus[1] Register (R/W) Reset Value = 00000000h 31:21 Reserved. Read/Wr ite 0s . 20 P ortResetStatusCha nge. This bit indicates that the por t reset signal has comple ted. 0: P or t reset is not complete. 1: P or t rese[...]

AMD Geode™ SC2200 Processor Data Book 301 Core Logic Module - USB Controller Registers - PCIUSB 32580B 1 Read: PortEnableStatus. 0: P or t disabled. 1: P or t enabled. Write: SetP or tEnab le. Writin g a 1 sets P ortEna b leStatus. Writing a 0 has no effect. 0 Read: CurrentConnectStatu s. 0: No device connected. 1: Device connected. If DeviceRemo[...]

302 AMD Geode™ SC2200 Processor Data Book Core Logic Module - USB Con tr oller Registers - PCIUSB 32580B 3 Read: Po r tOverCurrentIndicator . This bit reflects the state of the O VRCUR pi n dedicated to this por t. This field is only valid if NoOverCurrentProtection is cleared and Ov erCurrentProtectionMode is set. 0: No over-current condition. 1[...]

AMD Geode™ SC2200 Processor Data Book 303 Core Logic Module - USB Controller Registers - PCIUSB 32580B 8 Read: Po r tP owerS tatus. This bit reflects the power state of the por t regardless of the pow er switching mode . 0: P or t power is off . 1: P or t power is on. If NoP owerSwitching is set, this bit is alwa ys read as 1. Write: SetP or tP o[...]

304 AMD Geode™ SC2200 Processor Data Book Core Logic Module - USB Con tr oller Registers - PCIUSB 32580B 1 EmulationInterrupt (Read Only). This bit is a static decode of the emulation interr upt condition. 0 EmulationEnable. When set to 1 the HC is enabled for legacy emul ation and will decode accesses to I/O registers 60h and 64h and generate IR[...]

AMD Geode™ SC2200 Processor Data Book 305 Core Logic Module - ISA Legacy Register Space 32580B 6.4.7 ISA Legacy Register Space The ISA Legacy registers reside in the ISA I/O address space in the address range from 000h to FFFh and are accessed through typical input/ output instructions (i.e., CPU direct R/W) with the designated I/O por t address [...]

306 AMD Geode™ SC2200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32580B 2 Channel 2 T erminal Count. Indicates if TC was reached. 0: No . 1: Y es. 1 Channel 1 T erminal Count. Indicates if TC was reached. 0: No . 1: Y es. 0 Channel 0 T erminal Count. Indicates if TC was reached. 0: No . 1: Y es. Write DMA Comm and Register[...]

AMD Geode™ SC2200 Processor Data Book 307 Core Logic Module - ISA Legacy Register Space 32580B I/O Port 00Bh DMA Chann el Mode Register , Channels 3:0 (WO) 7:6 T ransfer Mode. 00: Demand. 01: Single. 10: Bloc k. 11: Cascade. 5 Address Direction. 0: Increment. 1: Decrement. 4 Auto-initialize. 0: Disab le. 1: Enab le. 3:2 T ransfer T ype. 00: V eri[...]

308 AMD Geode™ SC2200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32580B I/O Port 0D0h (R/W) Read DMA Status Register , Channels 7:4 Note: Channels 5, 6, and 7 are not suppor ted. 7 Channel 7 Request. Indicates if a request is pending. 0: No . 1: Y es. 6 Channel 6 Request. Indicates if a request is pending. 0: No . 1: Y es.[...]

AMD Geode™ SC2200 Processor Data Book 309 Core Logic Module - ISA Legacy Register Space 32580B I/O Port 0D2h Software DMA Request Register , Channels 7:4 (W) Note: Channels 5, 6, and 7 are not suppor ted. 7:3 Reserved. Must be set to 0. 2 Request T ype. 0: Reset. 1: Set. 1:0 Channel Number Request Select. 00: Illegal. 01: Channel 5. 10: Channel 6[...]

310 AMD Geode™ SC2200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32580B I/O Port 0DEh DMA Write Mask Register Command, Channels 7:4 (W) Note: Channels 5, 6, and 7 are not suppor ted. T able 6-43. D MA Channel Cont r ol Registers (Cont inued) Bit Description T able 6 -44. DMA Pa ge Registers Bit Description I/O Port 081h DM[...]

AMD Geode™ SC2200 Processor Data Book 311 Core Logic Module - ISA Legacy Register Space 32580B T able 6-45. P r ogrammable Interval Timer Re gisters Bit Description I/O Port 040h Write PIT Timer 0 Counter 7:0 Counte r V alue. Read PIT Timer 0 Status 7 Counter Ou tput. State of counter output signal. 6 Counter Lo aded. Indicates if the last count [...]

312 AMD Geode™ SC2200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32580B I/O Port 042h Write PIT Timer 2 Counter (Speaker) 7:0 Counte r V alue. Read PIT Timer 2 Status (Spea ker) 7 Counter Ou tput. State of counter output signal. 6 Counter Lo aded. Indicates if the last count written is loaded. 0: Y es. 1: No . 5:4 Current [...]

AMD Geode™ SC2200 Processor Data Book 313 Core Logic Module - ISA Legacy Register Space 32580B T able 6-4 6. Programmab le Interrupt Contr oller Register s Bit Description I/O Po r t 020h / 0A0h Master / Slave PIC ICW1 (WO) 7:5 Reserved. Must be set to 0. 4 Reserved. Must be set to 1. 3 Tr i g g e r M o d e . 0: Edge . 1: Le ve l. 2 V ector Addre[...]

314 AMD Geode™ SC2200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32580B 2 IRQ2 / IRQ10 Mask. 0: Not Masked. 1: Mask. 1 IRQ1 / IRQ9 Mask. 0: Not Masked. 1: Mask. 0 IRQ0 / IRQ8 Mask. 0: Not Masked. 1: Mask. I/O Port 020h / 0A0h Master / Slave PIC OCW2 (WO) 7:5 Rotate/EOI Codes. 000: Clear rotate in Auto EOI mode 100: Set rot[...]

AMD Geode™ SC2200 Processor Data Book 315 Core Logic Module - ISA Legacy Register Space 32580B 3 IRQ3 / IRQ11 Pending. 0: Y es. 1: No . 2 IRQ2 / IRQ10 Pending. 0: Y es. 1: No . 1 IRQ1 / IRQ9 Pending. 0: Y es. 1: No . 0 IRQ0 / IRQ8 Pending. 0: Y es. 1: No . Interrupt Service Reg ister 7 IRQ7 / IRQ15 In-Service . 0: No . 1: Y es. 6 IRQ6 / IRQ14 In-[...]

316 AMD Geode™ SC2200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32580B T able 6 -47. Keyboa rd Contr oller Register s Bit Description I/O Port 060h External Ke yboard Controller Data Register (R/W) Keyboar d Controller Data Register . All accesses to this por t are passed to th e ISA b us. If the f ast keyboard gate A20 a[...]

AMD Geode™ SC2200 Processor Data Book 317 Core Logic Module - ISA Legacy Register Space 32580B T able 6- 48. Real-Time Cloc k Register s Bit Description I/O Po r t 070h RTC Address Register (WO) This register is shadowed within the Core Logic module and is read through the RTC Shadow Register (F0 Inde x BBh). 7 NMI Mask . 0: Enab le. 1: Mask. 6:0[...]

318 AMD Geode™ SC2200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32580B 3 IRQ3 Edge or L e vel Sensitive Select. Selects PIC IRQ3 sensitivity configuration. 0: Edge . 1: Le ve l. 2:0 Reserved . Must be set to 0. I/O Port 4D1h Interrupt Edg e/Level Select Register 2 (R/W) Reset V alue: 00h Notes: 1. If ICW1 - bit 3 in the P[...]

AMD Geode™ SC2200 Processor Data Book 319 7 Video Processor Module 32580B 7.0 Video Processor Module The Video Processor module co ntains a high perf or mance video back-end accelerator , a video/graphics Mix er/ Blender , and a Video Input P or t (VIP), suppor ting two out- put choices: CRT or TFT . The back-end accelerator func- tions include h[...]

320 AMD Geode™ SC2200 Processor Data Book Video Processor Module 32580B 7.1 Module Ar chitecture Figure 7-1 shows a top-lev el bloc k diagram of the Video Processor . F or information about the relation ship between the Video Processor an d the other modules of the SC22 00, see Section 2.2 on page 22. The Video Processor module includes the follo[...]

AMD Geode™ SC2200 Processor Data Book 321 Video Processor Module 32580B 7.2 Functional Description T o understand why the Video Processor functions as it does, it is first impor tant to understa nd the diff erence between video and graphics. Video is pictures in motion, which usua lly starts out in an encoded f ormat (i.e ., MPEG2, A VI, MPEG4) o[...]

322 AMD Geode™ SC2200 Processor Data Book Video Processor Module 32580B Figure 7-2. NTSC 525 Lines, 60 Hz, Odd Field Figure 7-3. NTSC 525 Lines, 60 Hz, Even Field V er tical Retrace - Logical Lines 4-9 — Scan Lines 4-9 V er tical Retrace - L ogical Lines 10-21 — Scan lines 10-21 V er tical Retrace - Logical Lines 22, 23 — Scan lines 22, 23 [...]

AMD Geode™ SC2200 Processor Data Book 323 Video Processor Module 32580B 7.2.1 Video Inp ut P ort (VIP) The VIP block is designed to interface the SC2200 with e xter nal video processors (e.g., Philips PNX1300 or Sigma Designs EM8400) or external TV decode rs (e .g., Philips SAA7114). It inputs CCIR-656 Vid eo and ra w VBI data sourced by those de[...]

324 AMD Geode™ SC2200 Processor Data Book Video Processor Module 32580B The GenLock control hardware is used to synch ronize the video input’ s field with the GX1 mod ule’ s g raphics frame. The graphics data is alwa ys sent full frame. F or the Ge n- Lock function to perf orm correctl y , the GX1 module’ s Dis- play Controller must be prog[...]

AMD Geode™ SC2200 Processor Data Book 325 Video Processor Module 32580B Figure 7-5. Capture Vid eo Mode Bob Example Using One Video Fra me Buffer We av e The Wea ve method assemb les the odd fie ld and ev en field together to form the complete frame, and then renders the “wea ved” frames to the displa y device . The Video da ta is conv er ted[...]

326 AMD Geode™ SC2200 Processor Data Book Video Processor Module 32580B 3) Field Interrupt. When the field interr upt occurs on the completion of an odd field, the interr upt must program the Video Data Odd Base Address with the other buffer’ s add ress. The odd field will pin g-pong between the two buff ers. When the interrupt is due to the co[...]

AMD Geode™ SC2200 Processor Data Book 327 Video Processor Module 32580B 7.2.2 Video Block The Video block receives video data from the VIP bloc k or the GX1 module’ s video frame buff er . Th e video data is f or- matted and scaled and then sent to the Mixer/Blender . The video data also changes clock domains while in the Video bloc k. It is cl[...]

328 AMD Geode™ SC2200 Processor Data Book Video Processor Module 32580B 7.2.2.2 Horizontal Downscal er with 4 -T ap Filtering The Video Processor implements up to 8:1 hor izontal downscaling with 4-tap filter ing for horizontal inter polation. Filter ing is performed on video da ta input to the Video Pro- cessor . This data is fed to the filter a[...]

AMD Geode™ SC2200 Processor Data Book 329 Video Processor Module 32580B 7.2.2.3 Line Buffer s After the data has been option ally horizontally downscaled the video data is stored in a 3- line b uffer . Each line is 36 0 D WORDs , which means a line width of up to 720 pix els can be stored. This buff er suppor ts two functions. First, the clock do[...]

330 AMD Geode™ SC2200 Processor Data Book Video Processor Module 32580B 7.2.3 Mixer/Blende r Block The Mixer/Blender bloc k of the Video Processor module perf or ms all the necessar y functions to proper ly mix/bl end the video data and the graphics data. These functions include Color Space Conv ersion (CSC), optional Gamma correction, color/chro[...]

AMD Geode™ SC2200 Processor Data Book 331 Video Processor Module 32580B 7.2.3.1 YUV to RGB CSC in Video Data Path This CSC must be enabled if the video data is in the YUV color space. The CSC_FOR_ VIDEO bit, F4BAR0+Memor y Offset 4Ch[10], controls this CSC . YUV video data is passed through this CSC to obtain 24-bit RGB data using th e f ollowing[...]

332 AMD Geode™ SC2200 Processor Data Book Video Processor Module 32580B 7.2.3.4 Color/Chroma K ey and Mixer/Blender The Mixer/Blender takes each pix el of the graphics and video data streams and mi x es or blends them together . Mixing is simply choosing the graphics pix el or the video pixel. Blending tak es a percentage of a graphics pix el (Al[...]

AMD Geode™ SC2200 Processor Data Book 333 Video Processor Module 32580B Mixing/Blendin g Operation T a b le 7-2 on page 333 sh ows the truth table used to create th e flow diagram, Figure 7-12 on page 3 34, that the Mix er/ Blender logic uses to deter mine each pix els disposition. T able 7-2 . T ruth T able f or Alpha Blending COLOR_ CHROMA_SEL [...]

334 AMD Geode™ SC2200 Processor Data Book Video Processor Module 32580B Figure 7-12. Color Ke y and Alpha Blending Logic Color register enabled f or this window “Graphics 2 inside Video” is enabled Cursor color ke y matches graphics value Pix el outside the video window No Ye s Use selected cur- sor color for pixel No No Pixel value 3 matches[...]

AMD Geode™ SC2200 Processor Data Book 335 Video Processor Module 32580B 7.2.4 VESA DDSC2B and DPMS Suppor t The Video Processor suppo r ts VESA, DDSC2B , and DPMS standards for enhanced monitor communicatio ns and power management suppor t. This suppor t is provided via signals DDC_SCL (mux ed with IDE_D A T A10) and DDC_SDA (m uxed with IDE_D A [...]

336 AMD Geode™ SC2200 Processor Data Book Video Processor Module 32580B 7.2.6 TFT I nterface The TFT interf ace can be programmed to one of two sets of balls: IDE balls or Par allel P or t balls. PMR[23] of the Gen- eral Co nfigura tion registers program w here the TFT inte r- f ace exists (see T able 4-2 on page 76). Note: If the TFT interface i[...]

AMD Geode™ SC2200 Processor Data Book 337 Video Processor Module 32580B 7.2.7 Integrated PL L The integrated (CR T) PLL can generate frequencies up to 135 MHz from a single 27 MHz source. The clock fre- quency is programmab le using two registers. Figure 7-15 shows the b lock diagr am of the Video Processor integrated PLL. F REF is 27 MHz, genera[...]

338 AMD Geode™ SC2200 Processor Data Book Video Processor Module - Register Summary 32580B 7.3 Register Descriptions The register space for accessing and configur ing the Video Processor is located in the Co re Logic Chipset Register Space (F0-F5). The Chipset Register Space is accesse d via the PCI interf ace using the PCI T ype One Configuratio[...]

AMD Geode™ SC2200 Processor Data Book 339 Video Processor Module - Register Summary 32580B 28h-2Bh 32 R/W Misce llaneous Register 00001400h Page 348 2Ch-2Fh 32 R /W PLL2 Clock Select Register 00000000h P age 348 30h-33h 32 --- Reser v ed 00000000h Page 349 34h-37h 32 RO Reser v ed 00000000h Page 349 38h-3Bh 32 RO Reserved 00000000h Page 349 3Ch-3[...]

340 AMD Geode™ SC2200 Processor Data Book Video Processor Module - Register Summary 32580B T able 7-5. F4BAR2: VIP Suppo rt Registers Summary F4BAR2+ Memory Offset Width (Bits) T ype Name Reset Va l u e Reference (T able 7-8) 00h-03h 32 R/W Video Interface P or t Configuration Register 00000000h P age 360 04h-07h 32 R/W Video Interface Control Re[...]

AMD Geode™ SC2200 Processor Data Book 341 Video Processor Module - Video Processor Registers - Function 4 32580B 7.3.2 Video Processor Registe rs - Function 4 The register space design ated as Function 4 (F4) is used to configure the PCI por tion of suppor t hardware for accessing the Video Processor support registers, including VIP (sepa rate BA[...]

342 AMD Geode™ SC2200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32580B Index 3Dh Interrupt Pin Register (R/W) Reset V alue: 03h This register selects which interrupt pin the device uses. VIP uses INTC# after reset. INT A#, INTB# or INTD# can be selected by writing 1, 2 or 4, respectively . Index 3Eh-FFh R[...]

AMD Geode™ SC2200 Processor Data Book 343 Video Processor Module - Video Processor Registers - Function 4 32580B 7.3.2.1 Video Proc essor Support Registe rs - F4B A R0 F4 Index 10h, Base Address Re gister 0 (F4BAR0) sets th e base address that allows PCI access to the Video Proces- sor suppor t registers, not including VIP . A separate base addre[...]

344 AMD Geode™ SC2200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32580B 0 VID_EN (Video Enable). Enables video acceleration hardware . 0: Disable (reset) video module. 1: Enab le. Offset 04h-07h Display Co nfiguration Register (R/W) Reset V alue: x0000000h General configuration register f or displa y contr[...]

AMD Geode™ SC2200 Processor Data Book 345 Video Processor Module - Video Processor Registers - Function 4 32580B 8 CRT_HSYNC_POL (CRT Horizontal Synchronization Polarity). Selects CRT horizontal sync polarity . 0: CR T horiz ontal sync is normally lo w , and is set hig h during sync interval. 1: CR T horiz ontal sy nc is normally hi gh, and is se[...]

346 AMD Geode™ SC2200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32580B 10:0 VID_Y_ST ART (Video Y Start Position). Represents the vertical star t position of the video window . This value is calculated according to the follo wing formula: V alue = Desired screen position + (V_TO T AL – V_SYNC_END) + 1. [...]

AMD Geode™ SC2200 Processor Data Book 347 Video Processor Module - Video Processor Registers - Function 4 32580B Offset 1Ch-1Fh Palette (Gamma Correction RA M) Address Register (R/W) Reset V alue: xxxxxxxxh 31:8 Reserved. 7:0 P AL_ADDR (Palette Address). Specifies the address to be used f or the next access to the P alette Data register (F4BAR0+M[...]

348 AMD Geode™ SC2200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32580B 19:16 CLK_SEL (Clock Select). Selects frequency (in MHz) of the display cloc k. 0000: 25.175 0100: 50 1000: 65 1100: 108 0001: 31.5 0101: 49.5 1001: 75 1101: 135 0010: 36 0110: 56.25 1010: 78.5 1110: 27 0011: 40 0111: 44.9 1011: 94.5 1[...]

AMD Geode™ SC2200 Processor Data Book 349 Video Processor Module - Video Processor Registers - Function 4 32580B Offset 44h-47h CRC Signature Register ( R/W) Reset V alue: xxxxx100h Signature values stored in this regi ster can be read b y the host. This register is used for test purposes. 31:8 SIG_V ALUE (Signa ture V alue). ( Read Only) A 24-bi[...]

350 AMD Geode™ SC2200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32580B 13 GV_SEL (GV Select). Selects input video f orm at. 0: YUV f ormat. 1: RGB f ormat. Note: Mixing and blending configurations are created using bits [13, 11:9] of this register . See T able 7-1 "V alid Mixing/ Blending Configurati[...]

AMD Geode™ SC2200 Processor Data Book 351 Video Processor Module - Video Processor Registers - Function 4 32580B 23:0 CUR_COLOR_KEY (Cursor Color Key). Specifies the 24-bit RGB v alue of the cu rsor color ke y . The incoming graphics stream is compared with this value. If a match is detected, the pix el is replaced by a 24-bi t v alue from one of[...]

352 AMD Geode™ SC2200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32580B 24 ALPHA1_COLOR_REG_EN (Alpha Win dow 1 Color Register Enable). Enab le bit for the color k ey matching in Alpha Window 1. 1: Enable. If this bit is enab led and the alpha window is enab led, then where there is a color key match. The [...]

AMD Geode™ SC2200 Processor Data Book 353 Video Processor Module - Video Processor Registers - Function 4 32580B 24 ALPHA2_COLOR_REG_EN (Alpha Win dow 2 Color Register Enable). Enab le bit for the color k ey matching in Alpha Window 2. 0: Disable. Where there is a color k ey match, gr aphics and video are alpha-blended. 1: Enable. If this bit is [...]

354 AMD Geode™ SC2200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32580B 24 ALPHA3_COLOR_REG_EN (Alpha Win dow 3 Color Register Enable). Enab le bit for the color k ey matching in Alpha Window 3. 0: Disable. Where there is a color k ey match, gr aphics and video are alpha-blended. 1: Enable. If this bit is [...]

AMD Geode™ SC2200 Processor Data Book 355 Video Processor Module - Video Processor Registers - Function 4 32580B 29 Reserved. Write as read. 28 Reserved. Write as read. 27:4 Reserved . Set to 0. 3 Reserved. Write as read. 2 Reserved. Write as read. 1:0 VID_SEL (Video Select). Selects the source of the video data. 00: GX1 modu le. 10: VIP block. 0[...]

356 AMD Geode™ SC2200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32580B Offset 43Ch-43Fh Continuous GenLock Timeout Register (R/W) Reset V alue: 1FF F1FFFh 31:16 CGENTO1 (Even Field Continuous GenLock Timeout). 15:0 CGENTO0 (Odd Field Continuous GenLock Timeout). T able 7-7. F4B AR0+Memory Offset: Vi deo P[...]

AMD Geode™ SC2200 Processor Data Book 357 Video Processor Module - Video Processor Registers - Function 4 32580B 7.3.2.2 VIP Support Registers - F4BAR2 F4 Inde x 18h, Base Address Register 2 (F4 BAR2) points to the base address of where the VIP Configuration registers are located. T able 7-8 shows the memory mappe d VIP sup- por t registers acces[...]

358 AMD Geode™ SC2200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32580B 10 Auto-Flip. Video port operation mo de. 0: The video por t automatically detects the e v en and odd fi elds based on the VP_HREF and VP_VSYNC_IN signals or the CCIR656 control codes. 1: The even/odd field detect logic is disab led an[...]

AMD Geode™ SC2200 Processor Data Book 359 Video Processor Module - Video Processor Registers - Function 4 32580B 8 Video Data Captur e Active. (Read Only) 0: Video data is not being stored to memor y . 1: Video data is now being stored to memor y . 7:1 Reserved. (Read Only) 0 Run Status. (Read Only) 0: Video por t capture is not active . 1: Video[...]

360 AMD Geode™ SC2200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32580B Offset 40h-43h VBI Data Odd Base Register (R/W) Reset V alue: 00000000h This register specifies the base address in graphics memor y where VBI data f or odd fields are stored. Changes to this registe r take effect at the beginning of t[...]

AMD Geode™ SC2200 Processor Data Book 365 8 Debu gging and Mo nitoring 32580B 8.0 Deb ugging and Monitori ng 8.1 T estability (JT A G) The T est Access P or t (T AP) allows board le ve l intercon- nection verification and chip production tests. An IEEE- 1149.1a compliant test interface, T AP suppor ts al l IEEE mandator y instructions as well as [...]

366 AMD Geode™ SC2200 Processor Data Book Debu gging and Mo nitoring 32580B[...]

AMD Geode™ SC2200 Processor Data Book 369 9 Electrical Specifications 32580B 9.0 Electr ical Specifications This chapter provides inf or mation about: • General electrical specificatio ns . • DC characteristics. • A C characteristics. • All voltage v alues in this chapter are with respect to V SS unless otherwise noted . 9.1 General Speci[...]

370 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.1.4 Operating Condit ions T a b le 9-3 lists the various power supplies of the SC2200 and provides the de vice operating conditions.- Notes: 1) All power sources except V BA T must be connected, even if the function is not used. 2) V SB and V SBL must be on if any other [...]

AMD Geode™ SC2200 Processor Data Book 371 Electrical Specifications 32580B T a b le 9-4 indicate s which power r ails are used for each signal of th e SC2200 e xter nal interface. P ower planes not listed in this table are interna l, and are not related to signals of the e xternal interface. 9.1.5 DC Current DC current is not a simple me asuremen[...]

372 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.1.5.3 Definition of Sy stem Conditions f or Measuring On P arameters The SC2200’ s current is highly dependent on two func- tional characteristics, DCLK (DOT clock) and SDRAM fre- quency . T ab le 9-5 on page 372 sh ows ho w these factors are controlled when measur ing[...]

AMD Geode™ SC2200 Processor Data Book 373 Electrical Specifications 32580B I CC3ONTFT I/O current contribution if TFT displa y is used 30 50 mA I CCCR T If CR T interface is used: CCCR T Current @ V CCCR T = 3.3 (Nominal); CPU state = On 60 80 mA Note 1. f CLK ratings refer to in ternal clock frequency. T able 9- 6. DC Characteristics f or On Sta[...]

374 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.1.6 Ball Capacitance and Inductance T a b le 9-8 gives ball capacitance and inductance values. T able 9-8. Ball Capacitance and Inductance Symbol P arameter Min T yp Max Unit Comment C IN Input Pin Capacitance 4 7 pF Note 1 C IN Clock Input Capacitance 5 8 12 pF Note 1 C[...]

AMD Geode™ SC2200 Processor Data Book 375 Electrical Specifications 32580B 9.1.7 Pull-Up and Pull- Down Resistors The follo wing table lists input balls that are inter nally con- nected to a pull-up (PU) or pull-d o wn (PD) resistor . If these balls are not used, they do not require connection to an e xternal PU or PD resistor . Note: The resisto[...]

376 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.2 DC Characteristics T a b le 9-15 descr ibes the signal buff er types of the SC2200. See T able 3-2 "BGD432 Ball Assignment - Sor ted by Ball Num- ber" on page 29 and T able 3-2 "BGU481 Ball Assignment - Sor ted by Ball Number" on page 29 for each si[...]

AMD Geode™ SC2200 Processor Data Book 377 Electrical Specifications 32580B 9.2.1 IN AB DC Characteristics 9.2.2 IN BTN DC Characteristics 9.2.3 IN PCI DC Characteristics Note that the b uffer type for PCICLK (ball A7) is IN T - not IN PCI . Symbol P arameter Min Max U nit Comments V IH Input Hi gh V oltage 1.4 V V IL Input Low V oltage -0.5 ( Not[...]

378 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.2.4 IN STRP DC Characteristics 9.2.5 IN T DC Characteristics 9.2.6 IN TS DC Characteristics 9.2.7 IN TS1 DC Characteristics Symbol P arameter Min Max U nit Comments V IH Input Hi gh V oltage 0.6V IO V IO +0 .3 (Note 1) V V IL Input Low V oltage 0.3V IO V I IL Input Leaka[...]

AMD Geode™ SC2200 Processor Data Book 379 Electrical Specifications 32580B 9.2.8 IN USB DC Characteristics Figure 9-1. Differential Input Sensitivity f or Common Mode Range 9.2.9 O AC9 7 DC Characterist ics 9.2.10 OD n DC Characteristics Symbol P arameter Min Max U nit Comments V IH Input Hi gh V oltage 2.0 V IO +0.3 (Note 1) V V IL Input Low V o[...]

380 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.2.11 OD PCI DC Characteristics 9.2.12 O p/n DC Characterist ics 9.2.13 O PCI DC Characteristics 9.2.14 O USB DC Characteristics 9.2.15 TS p/n DC Characteristics 9.2.15.1 Exceptions 1) I OH is valid f or a GPIO pin only when it is not configured as op en-drain. 2) Signals[...]

AMD Geode™ SC2200 Processor Data Book 381 Electrical Specifications 32580B 9.3 A C Characteristics The tables in this section list the following A C characteris- tics: • Output delays • Input setup requirements • Input hold requirements • Output float del a ys • P o wer-up sequencing requirements The default le vels f or measurement of [...]

382 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.3.1 Memor y Controller Interf ace The minimum input setup and hold ti mes described in Figure 9- 3 (legend C and D) define the sma llest acceptable sampling window during which a synchronous in put signal must be stable to ensure correct o peration. Figure 9-3. Drive Lev[...]

AMD Geode™ SC2200 Processor Data Book 383 Electrical Specifications 32580B T able 9-12. Memory C ontr oller Timing P arameters Symbol P arameter Min Max U nit Comments t 1 Control Output V alid from SDCLK[3:0] -3.0 + (x * y) 0.1 + (x * y) ns Note 1, Note 2 t 2 MA[12:0], BA [1.0] Output V alid from SDCLK[3:0] -3.2 + (x * y) 0.1 + (x * y) ns Note 2[...]

384 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-4. Memory Contr oller Output V alid Timing Diagra m Figure 9-5. Read Data In Setup and Hold Timing Dia gram SDCLK[3:0] Control Output, MA[12:0] BA[1:0], MD[63:0] t 1 , t 2 , t 3 t 6 t 7 t 7 V REF V OHD V OLD V REF t 10 t 11 SDCLK_IN Data V alid MD[63:0] Read Data [...]

AMD Geode™ SC2200 Processor Data Book 385 Electrical Specifications 32580B 9.3.2 Video Port Figure 9-6. Video Input P or t Timing Diagram T able 9-13 . Video Input P ort Timing Parameter s Symbol P arameter Min Max Unit Comments t VP_C VPCKIN cycle time 18 ns t VP_S Video P ort input setup time bef ore VPCKIN rising edge 6n s t VP_H Video P ort i[...]

386 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.3.3 CRT and TFT I nterface T a b le 9-19 and Figure 9-7 descr ibe the timing of the digital CRT interf ace of the SC2200. All measure ment points in this table are identical to the v oltage measurement le vels described in T able 9-16 on page 384. Note that signals DDC_S[...]

AMD Geode™ SC2200 Processor Data Book 387 Electrical Specifications 32580B T able 9-15. CRT VESA Compatible D AC (RED , GREEN, and BLUE Outputs) Symbol Parameter (Note 1) Min Max Unit Comments V FR Full range output voltage 0.6 0.72 V SETRES = 470 R L = 37.5 Digital input = FFh I FR Full range output current 16 1 9.2 mA SETR ES = 470 R L = 37.5 D[...]

388 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.3.4 A C CESS.b us Interface The f ollow ing tab les describe the timing f or the A CCESS .b us signals . Notes: 1) All A CCESS.bus timing is not 100% tested. 2) In this tab le t CLK = 1/24 MHz = 41.7 ns. T able 9-16. A CCESS.bu s Input Timing P arameter s Symbol P aramet[...]

AMD Geode™ SC2200 Processor Data Book 389 Electrical Specifications 32580B Figure 9-8. ACB Signals : Rising Time and Fa lling Timing Diagram Figure 9-9. ACB Start and Stop Cond ition Timing Diagram t SD Afo AB1D/AB2D signal f all time 300 ns t SD Aro AB1D/AB2D signal rise time 1 μ s t SD Aho AB1D/AB2D hold time 7 * t CLK - t SCL f o After AB1C/A[...]

390 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9 -10. A CB Star t Condit ion Timing Diagr am Figure 9-11. A CB Data Bit Timing Diagram t CSTRsi t DHCsi Star t Condition t CSTRhi AB1D AB1C t CSTRho t CSTRso t DHCso AB2D AB2C t SCLhigho t SCLlowo t SD Aho t SD A vo t SDAso AB1D AB1C t SDAsi t SCLlowi t SCLhighi t [...]

AMD Geode™ SC2200 Processor Data Book 391 Electrical Specifications 32580B 9.3.5 PCI Bus In terface The SC2200 is complian t with PCI bus v2.1 specification. Relev ant inf or mation from the PCI bus specification is pro- vided below . All parameters in T able 9-23 are not 100% tested. The parameters in this table are further descr ibed in Figure [...]

392 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-13. V/I Curves for PCI Output Signals Pull-Up Pull-Down T e st P oint V IO 0.9 V IO DC Drive P oint AC Drive P oint 0.3 V IO 0.6 V IO 0.1 A C Drive P oint DC Drive P oint T est P oint V IO Equation A fo r V IO >V OUT >0.7V IO I OL = (256/V IO )* V OUT *(V IO[...]

AMD Geode™ SC2200 Processor Data Book 393 Electrical Specifications 32580B Figure 9-14. PCICLK Timing and Measurement P oints T able 9-19. P CI Clock P arameters Symbol Parameter Min Max Unit Comments t CYC PCICLK cycle time 30 ns Note 1 t HIGH PCICLK high time 11 ns Note 2 t LO W PCICLK low time 11 ns No te 2 PCICLK sr PCICLK slew Rate 1 4 V/ns [...]

394 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-15. Load Circuits f or Maxim um Time Measurements T able 9-20. PCI Timing Parameters Symbol P arameter Min Max Unit Comments t VA L PCICLK to signal valid delay (on the bus) 2 11 ns Note 1, Note 2 t VA L (ptp) PCICLK to signal v alid delay (GNT#) 2 9 ns Note 1, No[...]

AMD Geode™ SC2200 Processor Data Book 395 Electrical Specifications 32580B 9.3.5.1 Measurement and T est Conditions Figure 9 -16. Outpu t Timing M easurement Conditions T able 9-21. Measurement Condition P arameter s Symbol V alue Unit Comments V TH 0.6 V IO V Note 1 V TL 0.2 V IO V Note 1 V TEST 0.4 V IO V V STEP (rising edge ) 0.285 V IO V V ST[...]

396 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-17. Input Timing Measuremen t Conditions Figure 9-18. PCI Reset Timing V TEST V TEST Input V alid t SU t H V TEST V MAX V TH V TL PCICLK Input V TH V TL ) ( 100 ms (typ) ) ( t RST t RST -CLK t RST -OFF TRI_ST A TE PCI Signals PCIRST# PCICLK PO WER POR# t FA I L V [...]

AMD Geode™ SC2200 Processor Data Book 397 Electrical Specifications 32580B 9.3.6 Sub-ISA Int erface All output timing is guaranteed for 50 pF load, unle ss other- wise specified. The ISA Clock divisor (defined in F0 Index 50h[2:0] of the Core Logic module) is 011. T able 9-22. S ub-ISA Timing Parameters Symbol Parameter Bus Width (Bits) T ype Min[...]

398 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B t RD Y A2 IOCHRD Y valid after IOR#/MEMR#/ RD#/DOCR# /IO W#/MEMW#/W R#/ DOCW# F E 8 M, I/O 366 9-19 9-20 t IOCSA IOCS[1:0]#/ DOCS#/R OMCS# driv en active from A[23:0] v alid 8, 16 M, I/O 34 9-19 9-20 t IOCSH IOCS[1:0]#/DOCS#/ROMCS# valid Hold after A[23:0] invalid 8, 16 M,[...]

AMD Geode™ SC2200 Processor Data Book 399 Electrical Specifications 32580B Figure 9-19. Sub-ISA Read Operation Timing Diagr am t RDx t ARx Valid Valid Valid Data t RCUx t RA t RVDS t RDH t HZ A[23:0]/BHE# D[15:0] t RDYAx t RDYH MEMW#/DOCW# ROMCS#/DOCCS# IOW#/WR# IOCS[1:0]# (Read) t IOCSA t IOCSH t WDAR D[15:0] (Write) IOR#/RD#/TRDE# MEMR#/DOCR# I[...]

400 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-20. Sub-ISA Writ e Operation Timing Diagram t WRx t AWx Valid Valid Valid Data t WCUx t WA t DH A[23:0]/BHE# TRDE# D[15:0] IOCHRDY t RDYAx t RDYH DOCCS#/ROMCS# t IOCSH IOCS[1:0]# t DF t DVx t IOCSA IO W#/WR# MEMW#/DOCW# IOR#/RD# MEMR#/DOCR# t WTR Note: x indicates[...]

AMD Geode™ SC2200 Processor Data Book 401 Electrical Specifications 32580B 9.3.7 LPC Interface Figure 9-21. LPC Output Timing Diagram Figure 9-22. LPC Input Timing Diagram T able 9-23. LPC and SERIRQ Timing Paramete rs Symbol P arameter Min Max Unit Comments t VA L Output V alid delay 0 17 ns After PCICLK r ising edge t ON Float to Activ e delay [...]

402 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.3.8 IDE Interfa ce Figure 9-23. IDE Reset Timing Dia gram T able 9-24. IDE Genera l Timing P arameters Symbol Parameter Min Max U nit Comments t IDE_F ALL IDE signals f all time (from 0.9V IO to 0.1V IO )5 n s C L = 40 pF t IDE_R ISE IDE signals rise time (from 0.1V IO t[...]

AMD Geode™ SC2200 Processor Data Book 403 Electrical Specifications 32580B T able 9-25. IDE Register T ransfer to/fr om Device Timing P arameter s Symbol P arameter Mode Unit Comments 01235 t 0 Cycle time (min) 600 383 24 0 180 120 ns Note 1 t 1 Address v alid to IDE_I OR[0:1]#/ IDE_IO W[0:1] # setup (min) 70 50 30 30 25 ns t 2 IDE_IOR[0:1]#/IDE_[...]

404 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-24. Register T ransf er to/fr om Device Timing Diag ram ADDR valid 1 WRITE READ t 0 t 1 t 2 t 9 t 2i t 3 t 5 t 6z t 6 t A t 4 t C t RD t B t C IDE_IOR0# IDE_IOW0# IDE_IORD Y0 2,3 IDE_IORD Y0 2,4 IDE_IORD Y0 2,5 Notes: 1) De vice address con sists of signals IDE_CS[...]

AMD Geode™ SC2200 Processor Data Book 405 Electrical Specifications 32580B T able 9-26. IDE PIO Data T ran sfer to/fr om Device Timing Parameters Symbol P arameter Mode Unit Comments 01234 t 0 Cycle time (min) 600 383 24 0 180 120 ns Note 1 t 1 Address v alid to IDE_IO R[0:1]#/ IDE_IO W[0:1] # setup (min) 70 50 30 30 25 ns t 2 IDE_IOR[0:1]#/IDE_I[...]

406 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9- 25. PIO Data T ran sfer to/from De vice Timin g Diagram ADDR valid 1 WRITE IDE_DATA[15:0] READ IDE_DATA[15:0] t 0 t 1 t 2 t 9 t 2i t 3 t 5 t 6z t 6 t A t 4 t C t RD t B t C IDE_IOR0# IDE_IOW0# IDE_IORD Y0 2,3 IDE_IORD Y0 2,4 IDE_IORD Y0 2,5 Notes: 1) De vice addr[...]

AMD Geode™ SC2200 Processor Data Book 407 Electrical Specifications 32580B T able 9-27. IDE Multiw or d DMA Data T ransfer Timing P arameter s Symbol P arameter Mode Unit Comments 012 t 0 Cycle time (min) 480 150 120 ns Note 1 t D IDE_IOR[0:1]#/IDE_IOW[0:1]# (min) 215 80 70 ns t E IDE_IOR[0:1]# data a ccess (max) 150 60 50 ns t F IDE_IOR[0:1]# da[...]

408 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-26. Multiwor d DMA Data T ransfer Timing Diagr am t M t N t L t j t K t D t I t E t Z t F t G t G t H t 0 IDE_CS[1:0]# IDE_DATA[15:0] IDE_DATA[15:0] IDE_DREQ0 IDE_DA CK0# IDE_IOR0# IDE_IOW0# Notes: 1) F or Multiword DMA transf ers, the De vice may negate IDE_ DREQ[...]

AMD Geode™ SC2200 Processor Data Book 409 Electrical Specifications 32580B T able 9-28. IDE UltraDMA Data Bur st Timing P arameters Symbol P arameter Mode 0 Mode 1 Mode 2 Unit Comments Min Max Min Max Min Max t 2CYC T ypical sustained av erage two cycle time 240 160 120 ns T wo cycle time allowing for cloc k variations (from rising edge to next r[...]

410 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B All timing parameters are measured at the connector of the d e vice to which the parameter ap plies. F or e xample, the sender stops generating STROBE edges t RFS after the negation of DMARD Y . Both STROBE and DMARD Y timing measurements are taken at the connector of the [...]

AMD Geode™ SC2200 Processor Data Book 411 Electrical Specifications 32580B Figure 9-28. Sustained UltraDMA Data In Burst Timing Diagram t DS t DH t DS t DH t DH t DVH t DVS t DVH t DVS t DVH t 2CYC t CYC t CYC t 2CYC IDE_D A T A[15:0] at device IDE_D A T A[15:0] at host IDE_IRD Y0 (DSTROBE0) at de vice IDE_IRD Y0 (DSTROBE0) at host Note: IDE_DA T[...]

412 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-29. Host P ausing an UltraDMA Data In Burst Timing Dia gram t RP IDE_D A T A[15:0] (de vice) t RFS t SR IDE_IRD Y0 (DSTROBE0) (device) IDE_IOR0#(HDMAR D Y0#) (host) IDE_IOW0#(ST OP0) (host) IDE_D A CK0# (host) IDE_DREQ0 (device) Notes: 1) The host can asser t IDE_[...]

AMD Geode™ SC2200 Processor Data Book 413 Electrical Specifications 32580B Figure 9-30. Device T erminating an Ultr aDMA Da ta In Burst Timing Diagr am IDE_D A T A[15:0] (de vice) IDE_CS[0:1]# IDE_ADDR[2:0] CR t ACK t DV H t DV S t ZAH t AZ t SS t LI t AC K t IORDZ t ACK t MLI t LI t LI IDE_IRD Y0 (DSTROBE0) (device) IDE_IOR0# (HDMARD Y0#) (host)[...]

414 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-31. Host T erminat ing an UltraDMA Data In Bur st Timing Diag ram IDE_D A T A[15:0] (de vice) IDE_CS[0:1]# IDE_ADDR[2:0] CR t ACK t DV H t DV S t AC K t IORD YZ t ACK t MLI t LI t RP t MLI t LI t RFS t AZ t ZAH IDE_IRD Y0 (DSTROBE0) (device) IDE_IOR0# (HDMARD Y0#)[...]

AMD Geode™ SC2200 Processor Data Book 415 Electrical Specifications 32580B Figure 9-32. Initiating an UltraDMA Data Out Bur st Timing Diagram IDE_D A T A[15:0] (de vice) IDE_CS[0:1]# IDE_ADDR[2:0] t UI t AC K t ENV t LI t UI t ZIORD Y t ACK t DV S t DV H t AC K IDE_D A CK0# (host) IDE_DREQ0 (device) IDE_IO W0# (ST OP0#) (host) IDE_IORD Y0 (DDMARD[...]

416 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-33. Sustained UltraDMA Data Out Burst Timing Dia gram t DS t DH t DS t DH t DH t DVH t DVS t DVH t DVS t DVH t 2CYC t CYC t CYC t 2CYC IDE_D A T A[15:0] at host IDE_D A T A[15:0] at de vice IDE_IOR0# (HSTRO BE0#) at host IDE_IOR0# (HSTRO BE0#) at de vice Note: IDE[...]

AMD Geode™ SC2200 Processor Data Book 417 Electrical Specifications 32580B Figure 9 -34. Device Pausing an Ult raDMA Data O ut Burst Timing D iagram t RP IDE_D A T A[15:0] (host) t RFS t SR IDE_IOR0# (HSTROBE0#) (host) IDE_DA CK0# (host) IDE_DREQ0 (device) IDE_IOW0# (ST OP0#) (host) IDE_IORD Y0# (DDMARD Y0#) (device) Notes: 1) The de vice can de-[...]

418 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-35. Host T erminating an UltraDMA Data Out Bur st Timing Diagram IDE_D A T A[15:0] (host) IDE_CS[0:1]# IDE_ADDR[2:0] CR t LI t MLI t AC K t LI t SS t LI t ACK t DV H t DV S t AC K t IORD YZ IDE_IOR0# (HSTROBE0#) (host) IDE_IORD Y0# (DDMARD Y0)# (device) IDE_IO W0#[...]

AMD Geode™ SC2200 Processor Data Book 419 Electrical Specifications 32580B Figure 9-3 6. Device T ermin ating an UltraDMA Data Out Burst Timing Diagram IDE_D A T A[15:0] (host) IDE_CS[0:1]# IDE_ADDR[2:0] CR t ACK t DV H t DV S t RFS t ACK t IORDZ t ACK t MLI t LI t RP t MLI t LI IDE_IOR0# (HSTROBE0#) (host) IDE_IORD Y0# (DDMARD Y0#) (device) IDE_[...]

420 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.3.9 Universal Serial Bus (USB) Interf ace T able 9-29. USB Timing Parameters Symbol P arameter Min Ma x Unit Figur e Comments Full Speed Source (Note 1, Note 2) t USB_R1 DPOS_P or t1,2,3, DNEG_P or t1,2,3 Driver Rise Time 4 20 ns 9-37 (Monotonic) from 10% to 90% of the D[...]

AMD Geode™ SC2200 Processor Data Book 421 Electrical Specifications 32580B t USB_DJU22 Source diff erential dr iv er jitter for paired transactions –150 150 ns 9-38 Function (downstream), Note 4 t USB_SE2 Source EOP width 1.25 1.5 μ s 9-39 Note 4, Note 5 t USB_DE2 Diff erential to EOP transiti on sk ew –40 100 ns 9-3 9 Note 5 t USB_RJD21 Rec[...]

422 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-37. Data Signal Rise an d Fall Timing Diagram Figure 9-38. Source Diff erential Data Ji tter Timing Diagra m Rise Time F all Time t USB_R1,2 t USB_F1,2 90% 90% 10% 10% Differential Data Lines C L C L Full Speed: 4 to 20 ns at C L = 50 pF Low Speed: 75 ns at C L = [...]

AMD Geode™ SC2200 Processor Data Book 423 Electrical Specifications 32580B Figure 9-39. EOP Width Timing Diagra m Figure 9-40 . Receiver J itter T olerance Timin g Diagram EOP Width Data Crossov er Lev el Diff erential Data Lines t period_F tperiod_L Differential Data to SE0 Skew N*t period_F + t USB_DE1 N*t period_L + t USB_DE2 t USB_SE1, t USB_[...]

424 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.3.10 Se rial P ort (U A R T) Figure 9-41. U ART , Sharp-IR, SIR, and C onsu mer Remote Contr ol Timing Diagram T able 9-3 0. U AR T , Sharp-IR, SIR, and Consumer Remote Control Timing P arameters Symbol Parameter Min Max Unit Comments t BT Single bit time in U ART and Sh[...]

AMD Geode™ SC2200 Processor Data Book 425 Electrical Specifications 32580B 9.3.11 Fast IR Port Figure 9-42. Fast IR ( MIR and FIR) Timing Diagram T able 9-31. Fast IR P ort Timing P arameters Symbol P arameter Min Max Unit Comments t MPW MIR signal pulse width t MWN -25 (Note 1) t MWN +25 ns T ransmitter 60 ns Receiver M DRT MIR tr ansmitter data[...]

426 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.3.12 Parallel Port Interfa ce Figure 9-43. Standard P arallel Port T ypical Data Exchange Timing Diagram T able 9-32. Standar d P arallel P or t Timing P arameter s Symbol P arameter Min T yp Max Unit Comments t PDH P o rt data hold 500 ns Note 1 t PDS P o rt data setup [...]

AMD Geode™ SC2200 Processor Data Book 427 Electrical Specifications 32580B Figure 9-44. Enhanced Parallel P ort Timing Diagram T able 9-33. Enhanced P arall el P ort Timing P arameter s Symbol P arameter Min Max EPP 1.7 EPP 1.9 Unit Comments t WW19a WRITE# active from W AIT# low 45 x ns t WW19i a WRITE# inactive from W AIT# low 45 x ns t WST19a D[...]

428 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.3.12.1 Extended Capab ilities P ort (ECP) Figure 9-45. ECP Forward Mode Timing Dia gram T able 9-3 4. ECP Forward Mode Timing P arameter s Symbol P arameter Min Max Unit Comments t ECDSF Data setup bef ore STB# active 0 ns t ECDHF Data hold after BUSY inactive 0 ns t ECL[...]

AMD Geode™ SC2200 Processor Data Book 429 Electrical Specifications 32580B Figure 9-46. ECP Rever se Mode Timing Dia gram T able 9 -35. ECP Reverse Mod e Timing P arameter s Symbol P arameter Min Max Unit Comments t ECDSR Data setup bef ore ACK# activ e 0 ns t ECDHR Data hold after AFD# active 0 ns t ECLHR AFD# inactive after A CK# activ e 75 ns [...]

430 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.3.13 Audio Interface (A C97) Figure 9-47. A C97 Reset Timing Dia gram Figure 9-48. A C97 Sync Timing Diagram T able 9-36. AC Reset Timing Parameters Symbol P arameter Min T yp Max Unit Comments t RST_LO W A C97_RST# active lo w pulse width 1.0 µs t RST2CLK A C97_RST# in[...]

AMD Geode™ SC2200 Processor Data Book 431 Electrical Specifications 32580B Figure 9-49. A C97 Cloc ks Diagram T able 9-38. A C97 Clocks P arameters Symbol P arameter Min T yp Max Unit Comments F BIT_CLK BIT_CLK frequency 12.288 MHz t CLK_PD BIT_CLK period 81.4 ns t CLK_J BIT_CLK output jitter 750 ps t CLK_H BIT_CLK high pulse width 32.56 40.7 48.[...]

432 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-50. A C97 Data TIming Diagr am T able 9-39. A C97 I/O Timin g P arameters Symbol Parameter Min T yp Max Unit Comments t AC 97_S Input setup to falling edge of BIT_CLK 15.0 ns t AC 97_H Hold from f alling edge of BIT_CLK 10.0 n s t AC 97_O V SD A T A_OUT or SYNC va[...]

AMD Geode™ SC2200 Processor Data Book 433 Electrical Specifications 32580B Figure 9-51. A C97 Rise and F all Timing Dia gram T able 9-40. A C97 Signal Rise and F all Timing P arameter s Symbol Parameter Min T yp Max Unit Comments trise CL K BIT_CLK rise time 2 6 ns tfall CLK BIT_CLK f all time 2 6 ns trise SYNC SYNC r ise time 2 6 ns C L = 50 pF [...]

434 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Figure 9-52. AC97 L ow P o wer Mode Timing Dia gram T able 9-41. A C97 Lo w P ower Mode Timing P arameters Symbol Parameter Min T yp Max Unit Comments t s2_pdow n End of Slot 2 to BIT_CLK, SD A T A_IN low 1.0 µs SYNC BIT_CLK SD A T A_OUT SD A T A_IN Slot 1 Slot 2 Note: BI[...]

AMD Geode™ SC2200 Processor Data Book 435 Electrical Specifications 32580B 9.3.14 Po wer Managemen t LED# Cycle time: 1 s ± 0.1 s, 40%-60% duty cycle . Figure 9-53. PWRBTN# T rigger and ONCTL# Timing Diagram Figure 9-54. GP WIO and ONCTL# Timing Diagram T able 9-42. PWRBTN# Timin g P arameters Symbol Parameter Min Max Unit Comments t PBTNP PWRBT[...]

436 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.3.15 Po wer-Up Sequencing Figure 9-55. P ower -Up Sequenci ng With PWRBTN# Timing Dia gram T able 9-4 4. P ower -Up Sequence Using the P ower Button Timing P arameter s Symbol Parameter Min Max Unit Comments t 1 V oltage sequence -10 0 100 ms Optimum power-up results wit[...]

AMD Geode™ SC2200 Processor Data Book 437 Electrical Specifications 32580B Figure 9-56. P ower -Up Sequencing Wit hout PWRBTN# Timing Diagram A CPI is non-functional and a ll A CPI outputs are unde fined when the power-up sequence does not include us ing the pow er button. SUSP# is an internal signal gen erated from the A C PI b lock. Without an [...]

438 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B 9.3.16 JT A G Interface Figure 9-57. TCK Measurement P oints and Timing Diagram T able 9-46. JT A G Timing P arameter s Symbol Parameter Min Max Unit Comments TCK frequency 25 MHz t 1 TCK per iod 40 ns t 2 TCK high time 10 ns t 3 TCK low time 10 ns t 4 TCK rise time 4 ns t[...]

AMD Geode™ SC2200 Processor Data Book 439 Electrical Specifications 32580B Figure 9-58. JT A G T est Timing Diagram TCK t 8 Input Output TDO TDI, t 11 t 13 t 9 t 7 t 6 t 12 t 10 TMS Signals Signals[...]

440 AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B[...]

AMD Geode™ SC2200 Processor Data Book 443 10 Pac kage Specifications 32580B 10.0 P ac kage Specifications 10.1 Thermal Characteristics The junction-to-case ther mal resistance ( θ JC ) of th e pack- ages shown in T able 10-1 can be us ed to calcul ate the junction (die) temperature under any given circumstance. Note that there is no specificatio[...]

444 AMD Geode™ SC2200 Processor Data Book Pac kage Specifications 32580B 10.1.1 Heatsi nk Considerations T a b le 10-2 on page 443 shows the maximum allow ed ther- mal resistance of a heatsink for par ticular operating envi- ronments. The calculated values, defined as θ CA , represent the required ability of a par ticular heatsink to transf er h[...]

AMD Geode™ SC2200 Processor Data Book 445 Pac kage Specifications 32580B 10.2 Ph ysical Dimensions The figures in this section provide the mechanical package ou tlines for the BGU481 (Thermally Enhanced Ball Grid Arra y) package. Figure 10-2. BGU481 P acka ge - T op View[...]

446 AMD Geode™ SC2200 Processor Data Book Pac kage Specifications 32580B Figure 10-3. BGU481 Pac kage - Bottom Vie w[...]

AMD Geode™ SC2200 Processor Data Book 447 Appendix A: Suppor t Documentation 32580B Appendix A Suppor t Documentation A.1 Order Inf ormation Ordering P ar t Number (AMD OPN) 1 1. The “F” suffix denotes the Pb-free (lea d-free) package. See Section 10.0 on page 443 for the BGU481 (481-terminal Ball Grid Array Cavity Up) package specificati on.[...]

448 AMD Geode™ SC2200 Processor Data Book Appendix A: Data Bo ok Revision History 32580B A.2 Data Book Revision History This document is a repo rt of the re vi sion/creation pro cess of the data book f o r th e AMD Geode™ SC2200 processor . Any re visions (i.e., additions, deletions, parameter co rrections, etc.) are recorded in the table below[...]

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