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Cypress CY7C65113C manuel d'utilisation

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Table des matières du manuel d’utilisation

  • Page 1

    USB Hub with Microcontrolle r CY7C651 13C Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-08002 Rev . *D Revised March 6, 2006 USB Hub with Microcontroller [+] Feedback[...]

  • Page 2

    CY7C651 13C Document #: 38-08002 Rev . *D Page 2 of 49 TABLE OF CONTENTS 1.0 FEATURES .................................................... ........................................... .................. .....................5 2.0 FUNCTIONAL OVERVIEW ................................................ ................................ ...................[...]

  • Page 3

    CY7C651 13C Document #: 38-08002 Rev . *D Page 3 of 49 16.0 USB HUB ................................................................................................ ................. ....................29 16.1 Connecting/Disconnecting a USB Device ................................................... ...........................29 16.2 Enabling/Disab[...]

  • Page 4

    CY7C651 13C Document #: 38-08002 Rev . *D Page 4 of 49 Figure 16-5. Hub Ports Force Low Register .................... .......................................... ...................... ..... 31 Figure 16-6. Hub Ports SE0 Status Register ............................ ..................................................... .. .... 31 Figure 16-7. Hub Por[...]

  • Page 5

    CY7C651 13C Document #: 38-08002 Rev . *D Page 5 of 49 1.0 Features • Full Speed USB hub with an integrated microcontroller • 8-bit USB optimized microcontroller — Harvard architecture — 6-MHz external clock so urce — 1 2-MHz internal CPU clock — 4 8-MHz intern al hub c lock • Internal memory — 256 bytes of RAM — 8 KB of PROM • [...]

  • Page 6

    CY7C651 13C Document #: 38-08002 Rev . *D Page 6 of 49 2.0 Functional Overview The CY7C651 13C device is a one-time programmable 8-bit microc o ntroller with a buil t-in 12-Mbps USB hub tha t supports up to four downstream ports. The microcontroll er instruction set has been optimize d spec ifically for USB operations, although the microcontrollers[...]

  • Page 7

    CY7C651 13C Document #: 38-08002 Rev . *D Page 7 of 49 Logic Block Diagram Interrupt Controller PROM 12-bit Timer Reset W atchdog Tim er Repeater Power-on SCLK I 2 C comp. USB Transceiver USB Transceiver USB Transceiver GPIO PORT 1 GPIO PORT 0 P0[0] P0[7] P1[0] P1[2] SDATA D+[3] D–[3] D+[2] D–[2] 8-bit Bus 6-MHz crystal RAM USB SIE USB Transcei[...]

  • Page 8

    CY7C651 13C Document #: 38-08002 Rev . *D Page 8 of 49 4.0 Product Summary T ables 4.1 Pin Assign ments 3.0 Pin Configurations T able 4-1. Pin Assignmen t s Name I/O 28-pin Description D+[0], D–[0] I/O 5, 6 Upstream port, USB differential dat a. D+[1], D–[1] I/O 7, 8 Downstream Port 1, USB differential data. D+[2], D–[2] I/O 9, 10 Downstream [...]

  • Page 9

    CY7C651 13C Document #: 38-08002 Rev . *D Page 9 of 49 4.2 I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instruct ions. IORD reads da ta from the selected port into the accu mulator . IOWR performs the revers e; it writes data from the accumulator to the selected p ort. Indexed I/O Wri te (IOWX) [...]

  • Page 10

    CY7C651 13C Document #: 38-08002 Rev . *D Page 10 of 49 4.3 Instructi on Set Summary Refer to the CY ASM Assembler User ’s Guide for more details. Note that conditional ju mp instructions (i.e., JC, JNC, JZ, JNZ) take five cycles if jump is t aken, four cycles if no jump. Hub Port Control (Ports [4:1]) 0x4B R/W Hub Downstream Ports Cont rol (Port[...]

  • Page 11

    CY7C651 13C Document #: 38-08002 Rev . *D Page 1 1 of 49 5.0 Programming Model 5.1 14-bit Program Counter The 14-bit Program Counter (PC) allows ac ce ss to up to 8 KB o f PROM available with the CY7C651 1 3C architecture. The top 32 bytes of the ROM in the 8K part are reserved for testing purpo ses. The pro gram counter is cleared durin g reset, s[...]

  • Page 12

    CY7C651 13C Document #: 38-08002 Rev . *D Page 12 of 49 5.1.1 Progra m Memory Organization Note tha t the upper 32 bytes of the 8K PR OM are reserved . Ther efore, user ’s program must not overwrite this space. after reset Address 14-bit PC 0x0000 Program execution begins here after a reset 0x0002 USB Bus Reset interrupt vector 0x0004 128- µ s t[...]

  • Page 13

    CY7C651 13C Document #: 38-08002 Rev . *D Page 13 of 49 5.2 8-bit Accumula tor (A) The accumulator is the general-purpose register for the microcontroller . 5.3 8-bit T emporary Register (X) The “X” register is available to the firmware for temporary st orage of intermediate results. The microcontroller can perfo rm in dexed operations based on[...]

  • Page 14

    CY7C651 13C Document #: 38-08002 Rev . *D Page 14 of 49 5.5 8-bit Dat a St ack Pointer (DSP) The Data S tack Pointer (DSP) supports PUSH and POP instruct ions that use the data st a ck for temporary storage. A PUSH instruction pre-decrements the DSP , then writes da ta to the memory location addressed by the DSP . A POP i nstruction reads data from[...]

  • Page 15

    CY7C651 13C Document #: 38-08002 Rev . *D Page 15 of 49 6.0 Clocking The XT ALIN and XT ALOUT are the cl ock pins to the microcontroller . The user can connect an external oscillator or a crystal to these pins. When using an externa l crystal, keep PCB traces betw een the chip l eads and crystal as short as possible (less than 2 cm). A 6-MHz fundam[...]

  • Page 16

    CY7C651 13C Document #: 38-08002 Rev . *D Page 16 of 49 7.2 W atchdog Reset The WDR occurs when the internal W atchdo g T imer rolls over. W rit ing any value to the write-on ly W atchdog Reset Clear Register ( Figure 7-1 ) clears the timer . The timer rolls over and WDR occurs if it is not cleared within t WATC H of the last clear (se e Section 23[...]

  • Page 17

    CY7C651 13C Document #: 38-08002 Rev . *D Page 17 of 49 9.0 General-purpose I/O Port s There are 1 1 GPIO pi ns (P0[7:0] and P1[2 :0]) for the hardware interface. Each po rt can be configured as in puts with internal pull-ups, open drain outputs, or tr aditional CMOS outputs. The data for each GPIO port is accessible through the data registers . Po[...]

  • Page 18

    CY7C651 13C Document #: 38-08002 Rev . *D Page 18 of 49 9.1 GPIO Configurat ion Port Every GPIO port can be programmed as input s with internal pull-ups, outp uts LOW or HI GH, or Hi-Z (floating, the pin i s not driv en internally). In addition, the in terrupt polarity for each port can be programmed. The Port Configuration bits ( Figure 9-4 ) and [...]

  • Page 19

    CY7C651 13C Document #: 38-08002 Rev . *D Page 19 of 49 Q1, Q2, and Q3 discussed below are the transistors referenced in Figu re 9-1 . The available GPIO drive strength are: • Output LOW Mode : The pin’s Data Register is set to ‘0.’ Writing ‘0’ to the pin’s Data Register puts the pin in output LOW mode, regardless of the conten ts of [...]

  • Page 20

    CY7C651 13C Document #: 38-08002 Rev . *D Page 20 of 49 Bit [7:0]: T imer lower eight bits. Bit [3:0]: Timer higher nibble Bit [7:4]: Reserved . 1 1.0 I 2 C Configuration Regis ter Internal hardware suppo rts communication with extern al devices through an I 2 C-compatible interfa ce. I 2 C-compa tible function is discussed in detail in Section 12.[...]

  • Page 21

    CY7C651 13C Document #: 38-08002 Rev . *D Page 21 of 49 12.0 I2C-compatible Controll er The I2C-compatible block provides a versatile two-wire comm unication with external devices , supp orting master , slave, and multi-master modes of operation. The I2C-compatible block functi ons b y handling the l ow-level signaling in hardware, and issuin g int[...]

  • Page 22

    CY7C651 13C Document #: 38-08002 Rev . *D Page 22 of 49 Bit 7 : MSTR Mode Setting this bit to 1 ca uses the I 2 C-compatible block to initiate a master mode transaction by sendi ng a start bit and transmitting the first data byte from the data register (this typ i cally holds the target address and R/W bit). Subsequent bytes are initiated by settin[...]

  • Page 23

    CY7C651 13C Document #: 38-08002 Rev . *D Page 23 of 49 13.0 Processor St atus and Control Register Bit 0: Run This bit is manipulated by the HAL T inst ructio n. When Halt is executed, all the bi ts of the Processo r S tatus and Control Register are cleared to 0. Since the run b it is cleared, the proc essor stops at the end of the cu rrent instru[...]

  • Page 24

    CY7C651 13C Document #: 38-08002 Rev . *D Page 24 of 49 14.0 Interrupts Interrupts are generated by GPIO pins, internal timers, I 2 C-comp atib le operation, internal USB hub and USB traffic conditions. All interrupts are maskable by the Global Interrupt Enable R egi ster and the USB End Poin t Interrupt Enable Register . Writing a ‘1’ to a bit[...]

  • Page 25

    CY7C651 13C Document #: 38-08002 Rev . *D Page 25 of 49 During a reset, the contents of the Global Interrupt Enable Regi ster and USB End Point Interrupt Enable Register are cleare d, effectively disabling all interrupts, The interrupt controller contains a separate flip-fl op for each interrupt. See Figure 14-3 for the logic block diagram of the i[...]

  • Page 26

    CY7C651 13C Document #: 38-08002 Rev . *D Page 26 of 49 Although Reset is not an in terrupt, the first instructi on executed after a rese t is at PROM address 0x0000h—wh ich corresponds to the first entry in the Interrupt V ector T abl e. Because the JMP instruction is two bytes long, the interrupt vectors occupy t wo bytes. 14.2 Interrupt Lat en[...]

  • Page 27

    CY7C651 13C Document #: 38-08002 Rev . *D Page 27 of 49 14.5 USB End point Interrupts There are five USB endpoint interrupts, one per endpoint. A USB endpoint interrupt is generated after the USB host writes to a USB endpoint FIFO or after the USB controller sends a packet to the USB host. The interrupt is generated on the last packet of the transa[...]

  • Page 28

    CY7C651 13C Document #: 38-08002 Rev . *D Page 28 of 49 3. In sl ave transmit mode, after the slave transmits a byte of data: The ACK bit indicates i f the master that requeste d the byte acknowledged the byte. If more bytes are to be sent, firmware writes the next byte into the Data Register and then sets the Xmit MODE and Co ntinue/Busy bits as r[...]

  • Page 29

    CY7C651 13C Document #: 38-08002 Rev . *D Page 29 of 49 6. The host sends a request for the Device descrip tor using the new USB address. 7. Firmware decodes the request and retrieves the Device descriptor fro m program memory tables. 8. The host performs a control read sequence and Firmware resp onds by sending its Device descriptor over the USB b[...]

  • Page 30

    CY7C651 13C Document #: 38-08002 Rev . *D Page 30 of 49 Bit [0..3] : Port x S peed (where x = 1..4). Set to 1 if the device plugged in to Port x is Low S p eed; Set to 0 if the device plugged in to Port x is Full S peed. Bit [4..7] : Rese rved. Set to 0. The Hub Ports S peed register is cleared to zero by reset or bu s reset. This must be set by th[...]

  • Page 31

    CY7C651 13C Document #: 38-08002 Rev . *D Page 31 of 49 The downstream USB ports are designed for connection of USB devices, but can also serve as output ports under firmware control. This all ows unused USB ports to be used for functions su ch as driving LEDs or providin g add itional input signals. Pull ing up these pins to voltages above V REF m[...]

  • Page 32

    CY7C651 13C Document #: 38-08002 Rev . *D Page 32 of 49 . Bit [0..3] : Port x Diff Data (where x = 1..4). Set to 1 if D+ > D- (forced differential 1, if signal is differential, i.e. not a SE0 or SE1). Set to 0 i f D- > D+ (forced diff erential 0, if signal is differential, i.e. not a SE0 or SE1). Bit [4..7] : Rese rved. Set to 0. 16.4 Downstr[...]

  • Page 33

    CY7C651 13C Document #: 38-08002 Rev . *D Page 33 of 49 Bit [0..3] : Resume x (where x = 1..4). When set to 1 Port x requesting to be resumed (set by hardware); default state is 0. Bit [4..7] : Rese rved. Set to 0. Resume from a selectively suspended port, with the hu b not in suspend, typically involves the following actions: 1. Hardware detects t[...]

  • Page 34

    CY7C651 13C Document #: 38-08002 Rev . *D Page 34 of 49 Bit 3: Bus Activity . This is a “sticky” bit that in dicates if any non-idle USB event has occurr ed on the upstream USB port. Firmware s h ould check and clear this bit periodi cally to detect any loss of bus activity . Writing a ‘0’ to the Bus Activity bit clears it, whil e writing a[...]

  • Page 35

    CY7C651 13C Document #: 38-08002 Rev . *D Page 35 of 49 When the SIE writes data to a FIFO, the inte rnal data bus is driven by the SIE; not the CPU. This causes a sh ort delay in the CPU operation. The delay is thre e clock cycles per byte. For example, an 8-byte data write by the SIE to the FIFO generates a delay of 2 µ s (3 cycles/byte * 83.33 [...]

  • Page 36

    CY7C651 13C Document #: 38-08002 Rev . *D Page 36 of 49 Bits[6:0] of the endpoint 0 mode register are locked from CPU write o perations whenever the SI E has updated o ne of these bits, which the SIE does only at the end of the token phase of a tran saction (SETUP ... Data... ACK, OU T ... Data.. . ACK, or IN... Data ... ACK). The CPU can unl ock t[...]

  • Page 37

    CY7C651 13C Document #: 38-08002 Rev . *D Page 37 of 49 Bit 6: Data V alid. This bit is set on receiving a pro per CRC when the endpoint FIFO buffer is loaded with data during transactions. Thi s bit is used OUT and SETUP tokens only . If the CRC is not co rrect, the endpoint interrupt occurs, but Data V alid is cleared to a zero. Bit 7: Data 0/1 T[...]

  • Page 38

    CY7C651 13C Document #: 38-08002 Rev . *D Page 38 of 49 A C K 1. IN T ok e n H O S T D E V I C E S Y N C IN A D D R C R C 5 E N D P S Y N C D A T A 1/0 C R C 16 S Y N C Dat a Token Packet Data Packet Hand Shake Packe t UPDATE Host To Device Device To Hos t Host To De vice S Y N C IN A D D R C R C 5 E N D P Token Packet Host To Device S Y N C Da ta [...]

  • Page 39

    CY7C651 13C Document #: 38-08002 Rev . *D Page 39 of 49 18.0 USB Mode T ables Mode This lists the mnemonic given to the different modes that can be set in the Endpoint Mode Register by writing to the lower ni bb le (bits 0..3). The bit settings for different modes are covered in the column ma rked “Mode Bits”. The S tatus IN and S tatus OUT rep[...]

  • Page 40

    CY7C651 13C Document #: 38-08002 Rev . *D Page 40 of 49 Comments Some Mode Bits are automatically chan ged by the SIE in respons e to certain USB transactions. For example, if the Mode Bits [ 3 : 0 ] a r e s e t t o ' 1111 ' w h i c h i s A C K I N - St a t u s O U T m ode as shown i n T able 18-1 , the SIE will ch ange the endpoint Mode [...]

  • Page 41

    CY7C651 13C Document #: 38-08002 Rev . *D Page 41 of 49 . T able 18 -3. Details of Modes for Differing T raffic Conditions (see T able 18-2 for the decod e legend) SETUP (if accepting S ETUPs) Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bit s Mode Bits token count bu ffer dval DTOG DV AL COUNT Setup In Out ACK M[...]

  • Page 42

    CY7C651 13C Document #: 38-08002 Rev . *D Page 42 of 49 0 0 1 0 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 S tall yes 0 0 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no 0 0 1 0 Out x UC invalid UC UC UC UC 1 UC UC NoChange ignore no 0 0 1 0 In x UC x UC UC UC UC 1 UC UC 0 0 1 1 S tall yes OUT ENDPOINT Properties of Incoming[...]

  • Page 43

    CY7C651 13C Document #: 38-08002 Rev . *D Page 43 of 49 19.0 Register Summary Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Write/B oth/–[7] Default/ Reset GPIO CONFIGURA TION PORTS 0 AND 1 0x00 Port 0 Data P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 BBBBB BBB 11111111 0x01 Port 1 Data P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P[...]

  • Page 44

    CY7C651 13C Document #: 38-08002 Rev . *D Page 44 of 49 HUB PORT CONTROL, STA TUS, SUSPEN D RESUME, SE0, FORCE LOW 0x48 Hub Port Connect S tatus Reserved Reserved Reserved Reserved Port 4 Connect Sta t u s Port 3 Connect St a t u s Port 2 Connect Sta t u s Port 1 Connect Sta t u s BBBBBBBB 00000000 HUB PORT CONTROL, ST A TUS, SUS PEND RESUME, SE0, [...]

  • Page 45

    CY7C651 13C Document #: 38-08002 Rev . *D Page 45 of 49 20.0 Sample Schematic 21.0 Absolute Maximum Ratings S torage T emperature ...................... ......................... ......................... ......................... .......... ............. .............. .... –65°C to +15 0°C Ambient T emperature with Power Applied .............[...]

  • Page 46

    CY7C651 13C Document #: 38-08002 Rev . *D Page 46 of 49 22.0 Electrical Characteristics f OSC = 6 MHz; Operating T emperature = 0 to 70°C, V CC = 4.0V to 5.25V Parameter Description Conditions Min. Max. Unit General V REF Reference V oltage 3.3V ±5% 3.15 3.45 V V pp Programming V oltage (disabled) –0.4 0.4 V I CC V CC Operating Current No GPIO [...]

  • Page 47

    CY7C651 13C Document #: 38-08002 Rev . *D Page 47 of 49 23.0 Switching Characteristics (f OSC = 6.0 MHz) Parameter Description Min. Ma x. Unit Clock Source f OSC Clock Rate 6 ±0.25% MHz t cyc Clock Period 166.25 167.08 ns t CH Clock HIGH time 0.45 t CYC ns t CL Clock LOW time 0.45 t CYC ns USB Full-speed Si gnaling [10] t rfs T ransition Rise Time[...]

  • Page 48

    CY7C651 13C Document #: 38-08002 Rev . *D Page 48 of 49 © Cypress Semi conductor Corpora tion, 2006. The i n formation con tained herein is subject to change without notice. Cy press Semic onductor Corpo r ation assumes no responsib il ity for the use of any circuitry o ther than circuitry embodied in a Cypress prod uct. Nor does it convey or imp [...]

  • Page 49

    CY7C651 13C Document #: 38-08002 Rev . *D Page 49 of 49 Document History Page Document Title: CY7C651 13C USB Hub with Microcontroller Document Number: 38 -08002 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 1 09965 02/22/02 SZV Change from S pe c number: 38-00590 to 38-08002 *A 1 20372 12/17/02 MON Added register bit d efinitio[...]