Freescale Semiconductor DSP56366 manuel d'utilisation

Document Number: DSP56366UM Rev. 4 08/2006 DSP56366 24-Bit Digital Signal Pr ocessor User Manual[...]

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DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor TOC-1 1 DSP56366 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 DSP5[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 TOC-2 Freescale Semiconductor 3.1 Data and Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 Reserved Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.1.2 [...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor TOC-3 6.5.1 Host Receive Data Register (HORX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.5.2 Host Transmit Data Register (HOTX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.5.3 Host Contr[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 TOC-4 Freescale Semiconductor 6.6.1.4 ICR Host Flag 0 (HF0) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6.6.1.5 ICR Host Flag 1 (HF1) Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6.6.1.6 ICR[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor TOC-5 7.4.6.2 HCSR I 2 C/SPI Selection (HI2C)—Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2 . . . . . . . . . . . . . . . . . . . . . . 7-11 7.4.6.4 HCSR I 2 C Clock Freeze (H[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 TOC-6 Freescale Semiconductor 8.2.10 Frame Sync for Transmitter (FST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 -7 8.2.11 High Frequency Clock for Transmitter (HCKT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.2.12 High Frequ[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor TOC-7 8.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23 . . . . . . . . . . . . 8-26 8.3.4 ESAI Receive Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26 8.3.4.1 RCR ESAI Receiver 0 Enable (RE0) - B[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 TOC-8 Freescale Semiconductor 8.3.11 ESAI Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40 8.3.12 Transmit Slot Mask Registers (TSMA, TSMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40 8.3.13 Receive Slot M[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor TOC-9 9.3.4.3 RCCR_1 Rx High Freq. Clock Direction (RHCKD) - Bi t 23 . . . . . . . . . . . . . . . . . . . . 9-9 9.3.5 ESAI_1 Receive Control Register (RCR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.3.6 ESAI_1 Common Control Register (SAI[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 TOC-10 Freescale Semiconductor 10.5.7.2 DAX Transmit Underrun Error Flag (XAUR)—Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.5.7.3 DAX Block Transfer Flag (XBLK)—Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.5.7.4 XSTR Reserved Bits—Bits 3?[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor TOC-11 11.3.4.12 TCSR Timer Compare Flag (TCF) Bit 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.3.4.13 TCSR Reserved Bits (Bits 3, 10, 14, 16-19, 22, 23) . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.3.5 Timer Load Register (TLR)[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 TOC-12 Freescale Semiconductor B.4 Interrupt Source Priorities (within an IPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B -10 B.5 Host Interface—Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12 B.[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor LOF-1 Figure 1-1 DSP56366 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Figure 2-1 Signals Identified by Functional Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Figure 3-[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 LOF-2 Freescale Semiconductor Figure 7-4 SHI Programming Mode l—DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Figure 7-5 SHI I/O Shift Register (IOSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Figure 7-6 [...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor LOF-3 Figure 9-11 TSMA_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 Figure 9-12 TSMB_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 LOF-4 Freescale Semiconductor Figure D-20 ESAI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-35 Figure D-21 ESAI_1 Multiplex Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-36 Figu[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor LOT-1 Table 2-1 DSP56364 Functional Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Table 2-2 Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Table[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 LOT-2 Freescale Semiconductor Table 6-12 Host Mode Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Table 6-13 INIT Command Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 Ta[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor i Preface This manual describes the DSP56366 24-bit digital sign al processor (DSP), its memory , operating modes, and peripheral modules. The DSP56366 is a member of the DSP56300 family of programmable CMOS DSPs. Changes in core functionality specific to the DSP[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 ii F reescale Semico nductor SECTION 6— HOST INTERFACE (HDI08) • Describes the HDI08 pa rallel host interface. SECTION 7—SERIAL HOST INTERFACE (SHI) • Describes the serial input/output interf ace providing a path for communication and program/coefficient data transfers between th[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor iii • The word “assert” means that a high true (active high) signal is pulled high to V CC or that a low true (active low) signal is pulled low to ground. Th e word “deassert” means that a high true signal is pulled low to ground or that a low true sign[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 iv F reescale Semico nductor NO TES[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 1-1 1 DSP56366 Over view 1.1 Intr oduction This manual describes the DSP56366 24-bit digital sign al processor (DSP), its memory , operating modes, and peripheral modules. The DSP56366 is a member of the DSP56300 family of programmable CMOS DSPs. The DSP56366 is [...]

DSP56300 Core Description DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 1-2 F reescale Semico nductor 1.2 DSP56300 Core Description The DSP56366 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides up to twice the performan ce of Freescale's popular DSP56000 core family while retai[...]

DSP56366 Audio Processor Arc hitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 1-3 — Off-chip expansion up to two 16M × 24-bit word of Data memory . — Off-chip expansion up to 16M × 24-bit word of Program memory . — Simultaneous glueless interface to SRAM and DRAM. • Peripheral modules — Se[...]

DSP56300 Core Functional Blocks DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 1-4 F reescale Semico nductor • Instruction cache controller • PLL-based clock oscillator • OnCE module • JT AG T AP • Memory In addition, the DSP56366 provides a set of on-chip peripherals, described in Section 1.5, "Peripheral Overview&quo[...]

DSP56300 Core Functional Blocks DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 1-5 the A or B accumulator . A 56-bit resu lt can be stored as a 24-bit operand. The LSP can either be truncated or rounded into the MSP . Rounding is performed if specified. 1.4.2 Address Generation Unit (A GU) The AGU performs th[...]

DSP56300 Core Functional Blocks DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 1-6 F reescale Semico nductor • Nested hardware DO loops • Fast auto-return interrupts The PCU implements its functions using the following registers: • PC—program counter register • SR—Status register • LA—loop address register • LC—lo[...]

DSP56300 Core Functional Blocks DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 1-7 • End-of-block-transfer interrupts • T riggering from interrupt lines and all peripherals 1.4.6 PLL-based Cloc k Oscillator The clock generator in the DSP56300 core is compos ed of two main blocks: the PLL, which performs c[...]

P eripher al Overvi ew DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 1-8 F reescale Semico nductor ALU. Memory space includes internal RAM and ROM and can be expanded of f-chip under software control. There is an instruction cache, made using program RA M. The patch mode (which uses instruction cache space) is used to patch program [...]

P eripheral Overview DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 1-9 1.5.1 Host Interface (HDI08) The host interface (HDI08) is a byt e-wide, full-duplex, double-buf fered, pa rallel port that can be connected directly to the data bus of a host processor . The HDI08 supports a vari ety of buses and provide[...]

P eripher al Overvi ew DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 1-10 F reescale Semico nductor 1.5.4 Enhanced Serial A udio Interface (ESAI) The ESAI provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, ot her DSPs, microprocessors, and peri[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-1 2 Signal/Connection Descriptions 2.1 S ignal Gr oupings The input and output signals of th e DSP56364 are organized into functi onal groups, which are listed in Ta b l e 2 - 1 and illustrated in Figure 2-1 . The DSP56364 is operated from a 3.3 V supply; howev[...]

Signal Groupings DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-2 F reescale Semico nductor Figure 2-1 Signals Identified b y Functional Group PORT A ADDRESS BUS A0-A17 VCCA (3) GNDA (4) D0-D23 VCCD (4) GNDD (4) AA0-AA2/RAS0 -RAS2 PORT A BUS CONTROL PORT A DATA BUS OnCE ‰ ON-CHIP EMULATION/ TCK TDO VCCH GNDH VCCQL (4) Port B Port[...]

Pow e r DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-3 2.2 P ower 2.3 Gr ound T able 2-2 P ower Inputs P ower Name Description V CCP PLL P ower — V CCP is V CC de dicated for PLL use. The v oltage should be well-regulated and the input should be provided with an e xtremely low impedance path to the V CC[...]

Cloc k and PLL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-4 F reescale Semico nductor 2.4 Clock and PLL GND A (4) Address Bus Ground — GND A is an isolated ground f or sections of the addre ss bus I/O drivers . This connection must be tied e xter nally to all other chip ground connecti ons. The user must pro vide adequate ext[...]

External Memory Expansion P ort (Port A) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-5 2.5 E xternal Memory Expansion P o r t (P or t A) When the DSP56364 enters a low-power standby mode (s top or wait), it releas es bus mastership and tri-states the relevant port A signals: A0 – A17, D0 – D23, AA0/R[...]

External Memory Expansion P ort (P ort A) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-6 F reescale Semico nductor WR Output T r i-stated Write Enable — When the DSP is the bus master , WR is an active-low output that is asser ted to wr ite external memor y on the data bus (D0-D23). Otherwise, WR is tri-stated. TA Input Ignored[...]

Interrupt and Mode Cont rol DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-7 2.6 Interrupt and Mode Control The interrupt and mode control signals select the chip’ s operating m ode as it comes out of hardware reset. After RESET is deasserted, thes e inputs are hardware interrupt request lines. BG Input I[...]

Interrupt and Mode Control DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-8 F reescale Semico nductor T ab le 2-8 Interrupt and Mode Control Signal Name T ype State during Reset Signal Description MOD A/IRQA Input Input Mode Sele ct A/External Interrupt Request A — MOD A/IRQA is an active-lo w Schmitt-trigger input, inter nal ly [...]

P ARALLEL HOST INTERF A CE (HDI08) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-9 2.7 P ARALLEL HOST INTERF A CE (HDI08) The HDI08 provides a fast, 8-bit, para llel data port that may be connect ed directly to the host bus. The HDI08 supports a variety of standard buses and can be directly connected to a [...]

P ARALLEL HOST INTERF A CE (HDI08) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-10 F reescale Semico nductor HA2 Input GPIO disconnected Host Address Input 2 — When the HDI08 is programmed to interface a non-multiple xed host bus and the HI func tion is selected, this si gnal is line 2 of the host address (HA2) input bus. HA9 I[...]

P ARALLEL HOST INTERF A CE (HDI08) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-11 HCS Input GPIO disconnected Host Chip Select — When HD I08 is programmed to interface a nonmultiplex ed host bus and the HI function is selecte d, this signal is th e host chip select (HCS) input. The polar ity of the chi[...]

Serial Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-12 F reescale Semico nductor 2.8 S erial Host Interface The SHI has five I/O signals that can be configured to allow the SH I to operate in eith er SPI or I 2 C mode. HACK / HACK Input GPIO disconnected Host Ackno wledge — When HD I08 is programmed to interface [...]

Serial Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-13 MISO Input or output T r i-stated SPI Master-In-Sla ve-Out — When the SPI is configur ed as a master , MISO is the master data input line. The MISO signal is used in conjuncti on with the MOSI signal f or transmitting and receiving se[...]

Serial Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-14 F reescale Semico nductor SS Input T ri-stated SPI Slave Select — This signal is an activ e low Schmitt-trigger input when configured for the SPI mode . When conf igured for the SPI Sla ve mode , this signal is used to enable the SPI slave f or transf er . Wh[...]

Enhanced Serial Au d i o I n t e rf a c e DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-15 2.9 E nhanced Serial A udio Interface T ab le 2-11 Enhanced Serial Au dio Interface Signal s Signal Name Signal T ype State during Reset Signal Description HCKR Input or output GPIO disconnected High Frequency Clock [...]

Enhanced Serial A udio Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-16 F reescale Semico nductor FST Input or output GPIO disconnected Frame Sync for T ransmitter — This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the fr ame sync f or both transmitters and receivers. F or as[...]

Enhanced Serial Au d i o I n t e rf a c e DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-17 SDO5 Output GPIO disconnected Serial Data Output 5 — When progr ammed as a transmitter , SDO5 is used to transmit data from the TX 5 serial tr ansmit shift register . SDI0 Input Serial Data Input 0 — When program[...]

Enhanced Serial A udio Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-18 F reescale Semico nductor SDO2/ SDO2_1 Output GPIO disconnected Serial Data Output 2 — When progr ammed as a transmitter , SDO2 is used to transmit data from the TX 2 serial tr ansmit shift register When enabled f or ESAI_1 op eration, this is the [...]

Enhanced Serial Audio Interface_1 DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-19 2.10 Enhanced Serial A udio Interface_1 T able 2-12 Enhanced Serial A udio Interface_1 Signals Signal Name Signal T ype State during Reset Signal Description FSR_1 Input or output GPIO disconnected Frame Sync for Receiver_1 [...]

Enhanced Serial A udio Interface_1 DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-20 F reescale Semico nductor SCKR_1 Input or output GPIO disconnected Receiver Serial Clock_1 — SCKR provides the receiv er serial bit clock f or the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchr[...]

SPDIF T ransmitter Digi tal A udio Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-21 2.11 SPDIF T ransmitter Digital A udio Interface SDO4_1 Output GPIO disconnected Serial Data Output 4_1 — When programmed as a transmitter , SDO4 is used to transmit data from the TX4 serial transmit shift regis[...]

Timer DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-22 F reescale Semico nductor 2.12 Timer 2.13 JT A G/OnCE Interface T a ble 2-14 Timer Signal Signal Name Ty p e State during Reset Signal Description TIO0 Input or Output Input Timer 0 Schmitt-T rig ger Input/Output — When timer 0 fu nctions as an external ev ent counter or in [...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-1 3 Memory Configuration 3.1 Data and Program Memory Maps The on-chip memory configuration of the DSP56366 is af fected by the state of the CE (Cache Enable), MSW0, MSW1, and MS (Memory Switch) control bits in the OMR register , and by the SC bit in the S tatus[...]

Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-2 F reescale Semico nductor T ab le 3-2 On-chip RAM Memory Locations Bit Settings RAM Me mory Locations MSW1 MSW0 CE MS SC Prog. RAM Prog. Cache X Data RAM Y Data RAM X X 0 0 X $0000 - $0BFF n.a. $0000 - $33FF $0000-$1BFF X X 1 0 X $0000 - $07FF enabled $00[...]

Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-3 Figure 3-1 Memor y Maps for MSW=(X,X), CE=0, MS=0, SC=0 Figure 3-2 Memor y Maps for MSW=(X,X), CE=1, MS=0, SC=0 PROGRAM $FFFFFF $000000 $000C00 3K INTERNAL RAM X DATA $FFFFFF $000000 $003400 13K INTERNAL RAM INTERNAL I/O Y DATA $F[...]

Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-4 F reescale Semico nductor Figure 3-3 Memory Maps f or MSW=(0,0), CE=0 MS=1, SC=0 Figure 3-4 Memory Maps f or MSW=(0,1), CE=0, MS=1, SC=0 PROGRAM $FFFFFF $000000 $002800 10K INTERNAL RAM X DATA $FFFFFF $000000 $002000 8K INTERNAL RAM INTERNAL I/O Y DATA $F[...]

Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-5 Figure 3-5 Memory Maps f or MSW=(1,0), CE=0, MS=1, SC=0 Figure 3-6 Memory Maps f or MSW=(0,0), CE=1, MS=1, SC=0 PROGRAM $FFFFFF $000000 $001000 4K INTERNAL RAM X DATA $FFFFFF $000000 $002C00 11K INTERNAL RAM INTERNAL I/O Y DATA $F[...]

Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-6 F reescale Semico nductor Figure 3-7 Memory Maps f or MSW=(0,1), CE=1, MS=1, SC=0 Figure 3-8 Memory Maps f or MSW=(1,0), CE=1, MS=1, SC=0 PROGRAM $FFFFFF $000000 $001C00 7K INTERNAL RAM X DATA $FFFFFF $000000 $002000 8K INT ERNAL RAM INTERNAL I/O Y DATA $[...]

Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-7 Figure 3-9 Memor y Maps for MSW=(X,X), CE=0, MS=0, SC=1 Figure 3-10 Memory Maps fo r MSW=(X,X), CE=1, MS=0, SC=1 PROGRAM $FFFF $0000 $0C00 3K INTERNAL RAM X DATA $FFFF $0000 $3400 13K INTERNAL RAM INTERNAL I/O Y DATA $FF80 (128 wo[...]

Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-8 F reescale Semico nductor Figure 3-11 Memory Maps f or MSW=(0,0), CE=0, MS=1, SC=1 Figure 3-12 Memory Maps f or MSW=(0,1), CE=0, MS=1, SC=1 PROGRAM $FFFF $0000 $2800 10K INTERNAL RAM X DATA $FFFF $0000 $2000 8K INTERNAL RAM INTERNAL I/O Y DATA $FF80 (128 [...]

Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-9 Figure 3-13 Memory Maps f or MSW=(1,0), CE=0, MS=1, SC=1 Figure 3-14 Memory Maps f or MSW=(0,0), CE=1, MS=1, SC=1 PROGRAM $FFFF $0000 4K INTERNAL RAM X DATA $FFFF $0000 $2C00 11K INTERNAL RAM INTERNAL I/O Y DATA $FF80 (128 words) [...]

Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-10 F reescale Semico nductor Figure 3-15 Memory Maps f or MSW=(0,1), CE=1, MS=1, SC=1 Figure 3-16 Memory Maps f or MSW=(1,0), CE=1, MS=1, SC=1 PROGRAM $FFFF $0000 $1C00 7K INTERNAL RAM X DATA $FFFF $0000 $2000 8K INTERNAL RAM INTERNAL I/O Y DATA $FF80 (128 [...]

Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-11 3.1.1 Reserved Memory Spaces The reserved memory spaces should not be accessed by the user . They are reserved for future expansion. 3.1.2 Pr ogram R OM Area Reserved for Freescale Use The last 128 words ($FF AF80-$FF AFFF) of th[...]

Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-12 F reescale Semico nductor while the DSP is in Debug mode. As a result, subseque nt instructions might be fetched according to the new memory configuration (after the swit ch), and thus might execute improperly . 3.1.5 External Memory Support The DSP56366 does[...]

Internal I/O Memor y Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-13 DMA1 X:$FFFFEB DMA SOURCE ADDRESS REGISTER (DSR1) X:$FFFFEA DMA DESTINA TION ADDRESS REGISTER (DDR1) X:$FFFFE9 DMA COUNTER (DCO1) X:$FFFFE8 DMA CONTR OL REGISTER (DCR1) DMA2 X:$FFFFE7 DMA SOURCE ADDRESS REGISTER (DSR2) X:$FFFFE6 DMA [...]

Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-14 F reescale Semico nductor HDI08 X:$FFFFC7 HOST TRANSMIT REGISTER (HO TX) X:$FFFFC6 HOST RECEIVE RE GISTER (HORX) X:$FFFFC5 HOST BASE ADDR ESS REGISTER (HBAR) X:$FFFFC4 HOST PORT CONTR OL REGISTER (HPCR) X:$FFFFC3 HOST ST A TUS REGISTER (HSR) X:$FFFFC2 HOST CO[...]

Internal I/O Memor y Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-15 ESAI X:$FFFFBC ESAI RECEIVE SL O T MASK REGISTER B (RSMB) X:$FFFFBB ESAI RECEIVE SLO T MASK REGISTER A (RSMA) X:$FFFFBA ESAI TRANSMIT SLO T MASK REGISTER B (TSMB) X:$FFFFB9 ESAI TRANSMIT SL O T MASK REGISTER A (TSMA) X:$FFFFB8 ESAI R[...]

Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-16 F reescale Semico nductor X:$FFFF97 Reser ved X:$FFFF96 Reser ved X:$FFFF95 Reser ved SHI X:$FFFF94 SHI RECEIVE FIFO (HRX) X:$FFFF93 SHI TRANSMIT REGISTER (HTX) X:$FFFF92 SHI I 2 C SLA VE ADDRESS REGISTER (HSAR) X:$FFFF91 SHI CONTROL/ST A TUS REGISTER (HCSR) [...]

Internal I/O Memor y Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-17 Y :$FFFF A C Reser ved Y: $ F F F FA B Reser ved Y: $ F F F FA A Reser ved Y: $ F F F FA 9 Reser ved Y: $ F F F FA 8 Reser ved Y: $ F F F FA 7 Reser ved Y: $ F F F FA 6 Reser ved Y: $ F F F FA 5 Reser ved Y: $ F F F FA 4 Reser ved Y:[...]

Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-18 F reescale Semico nductor ESAI_1 Y :$FFFF9C ESAI_1 RECEIVE SLO T MASK REGISTER B (RSMB_1) Y :$FFFF9B ESAI_1 RECEIVE SLOT MASK REGIS TER A (RSMA_1) Y :$FFFF9A ESAI_1 TRAN SMIT SLO T MASK REGISTER B (TSMB_1) Y :$FFFF99 ESAI_1 TRANSMIT SLO T MASK REGISTER A (TSM[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-1 4 Core Configuration 4.1 Intr oduction This chapter contains DSP56300 core configuration information deta ils specific to the DSP56366. These include the following: • Operating modes • Bootstrap program • Interrupt sources and priorities • DMA request[...]

Operating Mode Regist er (OMR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-2 F reescale Semico nductor 4.2.1 Asynchr onous Bus Arbitr ation Enable (ABE) - Bit 13 The asynchronous bus arbitration mode is activated by setting the ABE b it in the OMR register . Hardware reset clears the ABE bit. 4.2.2 Address Attrib ute Priori ty D[...]

Operating Mode Register (OMR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-3 The Instruction Cache should be initialized with the new instructions according to the following procedure: These steps should be executed from external memory or by downl oad via host interface: 1. Set Cache Enable = 1 2. Set Pa[...]

Operating Mod es DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-4 F reescale Semico nductor ; do #(PATCH_DATA_END-PATCH_DATA_START+1),PATCH_LOOP movem p:(r1)+,x0 movem x0,p:(r2)+ nop ; Do-loop restriction PATCH_LOOP jsr #M_PROMS ; start ROM code execution ENDTEST jmp ENDTEST nop nop nop nop ; ; patch data ; PATCH_DATA_START move #5[...]

Operating Modes DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-5 6 0110 $ F F 0 0 0 0 B o o t s t r a p f r o m S H I ( s l a v e I 2 C mode) (HCKFR=1, 100ns filter enabled) 7 0111 $ F F 0 0 0 0 B o o t s t r a p f r o m S H I ( s l a v e I 2 C mode)(HCKR=0) 8 1000 $ 0 0 8000 Expanded mod e 9 1001 $ F F 0 0[...]

Interrupt Priori ty Registers DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-6 F reescale Semico nductor 4.4 Interrupt Priority Registers There are two interrupt priority registers in the DSP56366: 1. IPR-C is dedicated for DSP56300 Core interrupt sources. 2. IPR-P is dedicated for DSP56366 peripheral interrupt sources. The interru[...]

Interrupt Priori ty Register s DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-7 Figure 4-1 Interrupt Priority Regi ster P Figure 4-2 Interrupt Prior ity Register C ESL0 ESL1 SHL0 SHL1 HDL0 HDL1 23 22 21 20 19 18 17 16 15 14 13 12 0 1 2 3 4 5 6 7 8 9 10 11 ESAI IPL SHI IPL HDI08 IPL DAX IPL ESAI_1 IPL ESL11 [...]

Interrupt Priori ty Registers DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-8 F reescale Semico nductor T ab le 4-5 Interrupt Sour c es Priorit ies Within an IPL Priority Interrupt Source Lev el 3 (Nonma skable) Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interr upt Tr a p Low est Non-Maskable Interrupt Le[...]

Interrupt Priori ty Register s DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-9 SHI Receive FIFO Full SHI T ransmit Data SHI Receive F IFO Not Empty HOST Command Interr upt HOST Receive Data Interrupt HOST T ransmit Data Interrupt D AX T ransmit Underr un Error D AX Bloc k T ransf erred D AX T ransmit Regis[...]

Interrupt Priori ty Registers DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-10 F reescale Semico nductor T ab le 4-6 DSP56366 Inte rrupt V ectors Interrupt Starting Address Interrupt Priority Level Range Interrupt Source VBA:$00 3 Hardware RESET VBA:$02 3 Stack Error VBA:$04 3 Illegal Instruction VBA:$06 3 Debug Request Interrupt [...]

Interrupt Priori ty Register s DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-11 VBA:$44 0 - 2 SHI Receive FIFO Not Empty VBA:$46 0 - 2 Reserved VBA:$48 0 - 2 SHI Receive FIFO Full VBA:$4A 0 - 2 SHI Receiv e Ov errun Error VBA:$4C 0 - 2 SHI Bus Error VBA:$4E 0 - 2 Reserved VBA:$50 0 - 2 Reserved VBA:$52 0 -[...]

DMA Request Sources DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-12 F reescale Semico nductor 4.5 DMA Request Sources The DMA Request Source bits (DRS0-DR S4 bits in the DMA Control/S tatus registers) encode the source of DMA requests used to trigger the DMA transfer s. The DMA request sources may be the internal peripherals or e[...]

PLL Initialization DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-13 4.6 P LL Initialization 4.6.1 PLL Multiplication F actor (MF0-MF11) The DSP56366 PLL multiplication factor is set to 6 during hardware re set, i.e. the Multiplication Factor Bits MF0-MF1 1 in the PLL Contro l Register (PCTL) are set to $00[...]

JT A G Boundary Scan Register (BSR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-14 F reescale Semico nductor 4.9 JT A G Boundary Scan Register (BSR) The boundary scan register (BSR) in the DSP56366 JT AG implementation contains bits for all device signal and clock pins and asso ciated control signals. All bidirectional pins have[...]

JT A G Boundary Sc an Register (BSR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-15 17 D13 Input/Output Data 93 HAD6 — Control 18 D12 Input/Output Data 94 HAD6 Input/Output Data 19 D11 Input/Output Data 95 HAD7 — Control 20 D10 Input/Output Data 96 HAD7 Input/Output Data 21 D9 Input/Output Data 97 HA[...]

JT A G Boundary Scan Register (BSR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-16 F reescale Semico nductor 43 A7 Output3 Data 119 HSCKR — Control 44 A6 Output3 Data 120 HSCKR Input/Output Data 45 A[8:0] — Control 121 HSCKT — Con trol 46 A5 Output3 Data 122 HSCKT Input/Output Data 47 A4 Output3 Data 123 SCKR — Control 4[...]

JT A G Boundary Sc an Register (BSR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-17 69 EXT AL Input Data 145 SS I nput Data 70 SCKT_1 — Control 146 SCK/SCL — Control 71 SCKT_1 Input/Output Data 147 SCK/SCL Input/Output Da ta 72 CAS — Control 148 MISO/SD A — Control 73 CAS Output3 Data 149 MISO/SD[...]

JT A G Boundary Scan Register (BSR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-18 F reescale Semico nductor NO TES[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 5-1 5 General Purpose Input/Output 5.1 Intr oduction The DSP56362 provides up to 37 bidirectional signals that can be confi gured as GPIO signals or as peripheral dedicated signals. No dedicated GPIO signals are provided. All of these signals are GPIO by default [...]

Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 5-2 F reescale Semico nductor 5.2.4 P or t E Signals and Registers Port E has 10 signals, shared with the ESAI_1. Six of the ESAI_1 signals have their own pin, so each of the six signals, if not used as an ESAI_1 signal, can be configured indi vidually as a GPIO signal.[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-1 6 Host Interface (HDI08) 6.1 Intr oduction The host interface (HDI08) is a byt e-wide, full-duplex, double-buf fered, pa rallel port that can be connected directly to the data bus of a host processor . The HDI08 supports a vari ety of buses and provides gluel[...]

HDI08 Features DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-2 F reescale Semico nductor — Bit addressing instructions (e.g. BCHG , BCLR, BSET , BTST , JCLR, JSCLR, JSET , JSSET) simplify I/O service routines. 6.2.2 Interface - Host Side • Sixteen signals are provide d to support non-multiplex ed or multiplexed buses: — H0-H[...]

HDI08 Host Port Signals DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-3 — Cycle-stealing DMA with initialization • Dedicated Interrupts: — Separate interrupt lines for each interrupt source — Special host commands force DSP core inte rrupts under host processor control, which are useful for the fol[...]

HDI08 Block Diagram DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-4 F reescale Semico nductor 6.4 HDI08 Block Diag ram Figure 6-1 shows the HDI08 registers. The top row of registers (HCR, HSR, HDDR, HDR, HBAR, HPCR, HOTX, HORX) can be accessed the DSP core. The bottom row of registers (ISR, ICR, CVR, IVR, RXH:RXM:RXL and TXH:TXM:T[...]

HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-5 Figure 6-1 HDI08 Bl ock Dia gram 6.5 HDI08 – DSP-Side Programmer’ s Model The DSP core threats the HDI08 as a memory-mapped peripheral occupyi ng eight 24-bit words in X data memory space. The DSP may use the HDI0[...]

HDI08 – DSP-Side Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-6 F reescale Semico nductor The eight host processor registers cons ists of two data re gist ers and six control regist ers. All registers can be accessed by the DSP core but not by the external processor . Data registers are 24-bit registers us[...]

HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-7 NO TE When writing data to a pe ripheral device, there is a two-cycle pipeline delay until any status bits affected by th e operation are updated. If the programmer reads any of those status bits within the next two c[...]

HDI08 – DSP-Side Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-8 F reescale Semico nductor 6.5.3.4 HCR Host Flags 2,3 (HF2,HF3) Bits 3-4 HF2 and HF3 bits are used as a general-purpose flags for DSP to host communicati on. HF2 and HF3 may be set or cleared by the DSP core. HF2 and HF3 are refl ected in the i[...]

HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-9 If HDM1 or HDM0 are set, the DMA mode is enabled, and the HOREQ signal is used to request DMA transfers (the value of the HM1, HM0, HLEND and HDREQ bi ts in the ICR have no affect). When the DMA mode is enabled, the H[...]

HDI08 – DSP-Side Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-10 F reescale Semico nductor for the DMA controller to supply the HA2, HA1, and HA 0 signals. For 16- or 24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, resp ectively , from the host request rate – i.e., for[...]

HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-11 by the HDI08 hardware when the interrupt request is serviced by the DSP core. The host can clear HC, which also clears HCP . 6.5.4.4 HSR Host Flags 0,1 (HF0,HF1) B its 3-4 HF0 and HF1 bits are used as a general-purpo[...]

HDI08 – DSP-Side Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-12 F reescale Semico nductor 6.5.5.2 HB AR Reserved Bits 8-15 These bits are reserved. They read as zero and shou ld be written with zero for future compatibility . Figure 6-5 Self Chip Select logic 6.5.6 Host P or t Control Register (HPCR) The [...]

HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-13 6.5.6.2 HPCR Host Address Line 8 Enable (HA8EN) Bit 1 If the HA8EN bit is set and the HDI08 is used in multiplexed bus mode, then HA8/HA1 is used as host address line 8 (HA8). If this bit is cleared and the HDI08 is [...]

HDI08 – DSP-Side Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-14 F reescale Semico nductor 6.5.6.9 HPCR Host Request Open Drain (HROD) Bit 8 The HROD bit controls the output drive of the hos t request signals. In the single host request mode (HDRQ=0 in ICR), if HROD is cleared and host re quests are enable[...]

HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-15 Figure 6-8 Dual str obes bus 6.5.6.14 HPC R Host Chip Select P olarity (HCSP) Bit 13 If the HCSP bit is clea red, the chip sele ct (HCS ) signal is configured as an active low input and the HDI08 is selected when the[...]

HDI08 – DSP-Side Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-16 F reescale Semico nductor 6.5.8 Host Data Register (HDR) The HDR register holds the data va lue of the corresponding bits of the HDI08 pins which are configured as GPIO pins. The functionality of the Dxx bi t depends on the corresponding HDDR[...]

HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-17 6.5.10 Host Interface DSP Core Interrupts The HDI08 may request interrupt service from either the DSP core or the host processor . The DSP core interrupts are internal and do not require the use of an external interr[...]

HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-18 F reescale Semico nductor Figure 6-11 HSR-HCR Ope ration 6.6 HDI08 – External Host Programmer’ s Model The HDI08 has been designed to provide a simple, hi gh speed interface to a host processor . T o the host bus, the HDI08 appears t[...]

HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-19 One of the most innovative features of the host interfac e is the host command feature. W ith this feature, the host processor can issue vectored interrupt reque sts to the DSP core. The host may select any of 12[...]

HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-20 F reescale Semico nductor 6.6.1.1 ICR Receive Request Enable (RREQ) Bit 0 In interrupt mode (HDM[2:0]=000 or HM[1:0]=00), RREQ is used to enable host receive data requests via the host request (HOREQ or HRRQ) signal when the receive data[...]

HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-21 6.6.1.3 ICR Double Host Request (HDRQ) Bit 2 The HDRQ bit determines the functions of the HOREQ/HTRQ and HACK/HRRQ signals as shown in T a ble 6-1 1 . 6.6.1.4 ICR Host Flag 0 (HF0) Bit 3 The HF0 bit is used as a [...]

HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-22 F reescale Semico nductor 6.6.1.6 ICR Host Little Endian (HLEND) Bit 5 If the HLEND bit is cleared, the HDI08 can be accessed by the host in big endian byte order . If set, the HDI08 can be accessed by the host in little endian byte orde[...]

HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-23 from the host request rate – i.e., for every two or thre e host processor data transfers of one byte each, there is only one 24-bit DSP CPU interrupt. If either HDM1 or HDM0 in the HCR register are set, bits 6 [...]

HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-24 F reescale Semico nductor The host processor can select the starting address of a ny of the 128 possible interr upt routines in the DSP by writing the interrupt routine address divided by 2 in to the HV bits. The host processor can thus [...]

HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-25 written by the host processor . TXDE can be set by the host processor using the initialize feature. TXDE may be used to assert the external HOREQ signal if the TREQ bit is set. Rega rdless of whether the TXDE int[...]

HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-26 F reescale Semico nductor 6.6.4 Interrupt V ector Register (IVR) The IVR is an 8-bit read/write register which typically contains the interrupt vector number used with MC68000 Family processor vectored interrupts. Only the host processor[...]

HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-27 6.6.7 Host Side Register s After Reset T a ble 6-15 shows the result of the four kinds of reset on bits in each of the HDI08 registers seen by the host processor . The hardware reset (H W) is caused by asserting [...]

Servicing The Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-28 F reescale Semico nductor 6.7 S ervicing The Host Interface The HDI08 can be serviced by using one of the following protocols: • Polling • Interrupts 6.7.1 HDI08 Host Pr ocessor Data T ransfer T o the host processor , the HDI08 appears as a contiguou[...]

Servicing The Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-29 Figure 6-16 HDI08 Host Request Structur e 6.7.3 Servicing Interrupts If either the HOREQ/HTRQ or the HRRQ signal or both are connected to the host processor interrupt inputs, the HDI08 can request servi ce from the host processor[...]

Servicing The Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-30 F reescale Semico nductor[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-1 7 Serial Host Interface 7.1 Intr oduction The Serial Host Interface (SHI) is a serial I/O interface that provides a path for commu nication and program/coefficient data transfers between the DSP and an external host processor . The SHI can also communicate wi[...]

Serial Host Interface Internal Arch itecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-2 F reescale Semico nductor 7.2 S erial Host Interface Internal Ar chitecture The DSP views the SHI as a memory-mapped peripheral in the X data memory space. The DSP uses the SHI as a normal memory-m apped peripheral using standard polling o[...]

Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-3 user ’ s responsibility to select the proper clock rate within the range as defined in the I 2 C and SPI bus specifications. Figure 7-2 SHI Clock Generator 7.4 S erial Host Interface Pr ogramming Model The Serial Hos[...]

Serial Host Interface Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-4 F reescale Semico nductor Figure 7-4 SHI Programming Mod el—DSP Side HCKFR 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 0 23 SHI Receive Data FIFO (HRX) (read only, X: $FFFF94) HRX SHI Transmit Data Register (HTX) (write only, X: $FFFF93) Re[...]

Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-5 The SHI interrupt vector table is shown in Ta b l e 7 - 1 and the exception prioritie s generated by the SHI are shown in Ta b l e 7 - 2 . 7.4.1 SHI Input/Output Shi ft Register (IOSR)—Host Side The variable length I[...]

Serial Host Interface Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-6 F reescale Semico nductor Figure 7-5 SHI I /O Shift Register ( IOSR) 7.4.2 SHI Host T ransmit Da ta Register (H TX)—DSP Side The host transmit data register (HTX) is used for DSP- to-Host data transfers. The HTX register is 24 bits wide. W ri[...]

Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-7 7.4.4.1 HSAR Reserved Bits—Bits 19, 17–0 These bits are reserved. They read as zero and shou ld be written with zero for future compatibility . 7.4.4.2 HSAR I 2 C Slave Address (HA[6:3], HA1)—Bits 23–20,18 Part[...]

Serial Host Interface Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-8 F reescale Semico nductor Figure 7-6 SPI Data-T o-Clock T iming Diagram If CPOL is cleared, it pr oduces a steady-state low valu e at the SCK pin of the ma ster device whenever data is not being transferred. If the CPOL bit is set, it produces [...]

Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-9 When the SHI is in master mode and CPHA = 1, the DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. The HT X data is transferred to the shif t register for transmission as soon as the shift r[...]

Serial Host Interface Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-10 F reescale Semico nductor When HFM[1:0] = 00, the filter is bypassed (spikes are not filtered out). This mode is useful when higher bit-rate transfers are required and the SHI operates in a noise-free environment. When HFM[1:0] = 10, the narro[...]

Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-11 7.4.6.1.1 SHI Individual Reset While the SHI is in the individual reset state, SHI i nput pins are inhibited, output and bidirectional pins are disabled (high impedance), the HC SR status bits and the transmit/r eceiv[...]

Serial Host Interface Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-12 F reescale Semico nductor It is recommended that an SHI individual reset be generated (HEN cleared) before changing HCKFR. HCKFR is cleared during hardwa re reset and software reset. 7.4.6.5 HCSR FIFO-Enable Contr ol (HFIFO)—Bit 5 The read/w[...]

Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-13 7.4.6.8 HCSR Idle (HIDLE)—Bit 9 The read/write control/status bi t HIDLE is used only in the I 2 C master mode; it is i gnored otherwise. It is only possible to set the HIDLE bit dur ing writes to the HCSR. HIDLE is[...]

Serial Host Interface Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-14 F reescale Semico nductor transmit-underrun-error interrupt serv ice from the interrupt controller . HTIE is cleared by hardware reset and software reset. NO TE Clearing HTIE masks a pending transmit interrupt only after a one instruction cycl[...]

Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-15 If a transmit interrupt occurs with HTUE set, the transmit-underrun interrupt v ector is generated. If a transmit interrupt occurs with HTUE cleared, the re gular transmit-data interrupt vector is generated. HTUE is c[...]

Characteristics Of The SPI Bus DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-16 F reescale Semico nductor 7.4.6.18 Host Bus Error (HBER)—Bit 21 The read-only status bit HBER indicates, when set, that an SHI bus error occurred when operating as a master (HMST set). In I 2 C mode, HBER is set if the transmitter does not receive an[...]

Characteristics Of The I 2 C Bus DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-17 7.6.1 Overview The I 2 C bus protocol must conform to the following rules: • Data transfer may be initiate d only when the bus is not busy . • During data transfer , the data lin e must remain stable whenever th e clock l[...]

Characteristics Of The I 2 C Bus DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-18 F reescale Semico nductor Figure 7-9 Ac knowledgmen t on the I 2 C Bus A device generating a signal is called a transmitter , and a device receiv ing a signal is called a receiver . A device controlling a signal is called a master and devices control[...]

SHI Prog ramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-19 Figure 7-11 I 2 C Bus Pr otocol For Host Read Cyc le NO TE The first data byte in a write-bus cycl e can be used as a user -predefined control byte (e.g., to determine the locat ion to which the forthcoming data bytes should b[...]

SHI Pr ogramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-20 F reescale Semico nductor If a write to HTX occurs, its contents are transferred to IOSR between da ta word transfers. The IOSR data is shifted out (via MISO) and received data is shifte d in (via MOSI). The DSP may write HTX with either DSP instructi[...]

SHI Prog ramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-21 It is recommended that an SHI individual reset (H EN cleared) be generated before beginning data reception in order to reset the receive FIFO to its initial (empty) state (e.g., wh en switchi ng from transmit to receive data).[...]

SHI Pr ogramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-22 F reescale Semico nductor In a receive session, only the receive path is enabled and HTX to IOSR transfers are inhibited. The HRX FIFO contains valid data, which may be read by the DSP with either DSP instru ctions or DMA transfers (if the HRNE status[...]

SHI Prog ramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-23 may be used to inte rrupt the external I 2 C master device. Connecting the HREQ line between two SHI-equipped DSPs, one operating as an I 2 C master device and the other as an I 2 C slave device, enables full hardware handshak[...]

SHI Pr ogramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-24 F reescale Semico nductor the HREQ line between two SHI-equippe d DSPs, one opera ting as an I 2 C master device and the other as an I 2 C slave device, enables full hardware handshaking. 7.7.4.1 Receive Data in I 2 C Master Mode A receive session is [...]

SHI Prog ramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-25 7.7.5 SHI Operation During DSP Stop The SHI operation cannot continue when the DSP is in the stop state, because no DSP clocks are active. While the DSP is in the sto p state, the SHI remains in the individual reset state. Whi[...]

SHI Pr ogramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-26 F reescale Semico nductor NO TES[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-1 8 Enhanced Serial A UDIO Interface (ESAI) 8.1 Intr oduction The Enhanced Serial Audio Interfac e (ESAI) provides a full-duplex se rial port for seri al communication with a variety of serial devi ces including one or more industry-standard codecs, other DSPs,[...]

Introd uction DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-2 F reescale Semico nductor Figure 8-1 ESAI Block Diagram SDO1 [PC10] SDO0 [PC11] Shift Register RX0 TX5 SDO5/SDI0 [PC6] Shift Register RX1 TX4 SDO4/SDI1 [PC7] Shift Register RX2 TX3 SDO3/SDI2 [PC8] Shift Register RX3 TX2 SDO2/SDI3 [PC9] Shift Register TX1 Shift Register [...]

ESAI Data and Contr ol Pins DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-3 8.2 E SAI Data and Contr ol Pins Three to twelve pins are require d for operation, depending on the opera ting mode selected and the number of transmitters and receivers enable d. The SDO0 and SDO1 pins are used by transmitters 0 a[...]

ESAI Data and Control Pins DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-4 F reescale Semico nductor 8.2.4 Serial T ransmit 3/Receive 2 Data Pin (SDO3/SDI2) SDO3/SDI2 is used as the SDO3 sign al for transmitting data from the TX3 serial transmit s hift register when programmed as a transmitter pin, or as the SDI2 signal for receiv[...]

ESAI Data and Contr ol Pins DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-5 When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register . When configured as the output flag OF0, this pin reflects the value of the OF0 bit in the SAICR register , and the d[...]

ESAI Data and Control Pins DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-6 F reescale Semico nductor SCKT may be programmed as a general-purpose I/O pi n (PC3) when the ESAI SC KT function is not being used. NO TE Although the external ESAI serial clock can be independent of and asynchronous to the DSP system clock, the DSP clock [...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-7 8.2.10 Frame Sync f or T ransmitter (FST) FST is a bidirectional pin providing the frame sync for both the transmitters and receivers in the synchronous mode (SYN=1) and fo r the transmitters only in as ynchronous mode (SYN=0) (see Ta b[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-8 F reescale Semico nductor special-purpose time slot register . The following paragraphs give detail ed descriptions and operations of each bit in the ESAI registers. The ESAI pins can also function as GPIO pins (Port C), described in Section 8.5, "GPIO - P[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-9 Figure 8-3 ESAI Cloc k Generator Functiona l Block Diagram 8.3.1.2 TCCR T ransmit Prescaler Rang e (TPSR) - Bit 8 The TPSR bit controls a fixed divide -by-eight prescaler in series with the variable prescaler . This bit is used to exten[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-10 F reescale Semico nductor operational (see Figure 8-3 ). The maximum internally generated bit clock frequency is Fosc/4; the minimum internally generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096. NO TE Do not use the combination TPSR=1 and TPM7-TPM0[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-11 Figure 8-4 ESAI Frame Sync Gener ator Functional Bloc k Diagram 8.3.1.4 TCCR Tx High Frequency Cloc k D ivider (TFP3-TFP0) - Bits 14–17 The TFP3–TFP0 bits control the divide ratio of the transmitter high frequency clock to the tran[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-12 F reescale Semico nductor 8.3.1.5 TCCR T ransmit Clock P olarity (TCKP) - Bit 18 The T ransmitter Clock Polarity (TCK P) bit controls on which bit cloc k edge data and frame sync are clocked out and latched in. If TCKP is cleared the data and the frame sync ar[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-13 . Hardware and software reset clear all the bits in the TCR register . The TCR bits are described in the following paragraphs. 8.3.2.1 TCR ESAI T ransmit 0 Enable (TE0) - Bit 0 TE0 enables the transfer of data from TX0 to the tr ansmit[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-14 F reescale Semico nductor 8.3.2.3 TCR ESAI T ransmit 2 Enable (TE2) - Bit 2 TE2 enables the transfer of data from TX2 to the tr ansmit shift register #2. When TE2 is set and a frame sync is detected, the tran smit #2 portion of the ESAI is enabled fo r that fr[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-15 The SDO4/SDI1 pin is the data input pin for RX1 if TE4 is cl eared and RE1 in the RCR register is set. If both RE1 and TE4 are cleared the trans mitter and receiver are disabled, and the pin is tri- stated. Both RE1 and TE4 should not [...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-16 F reescale Semico nductor 2. If the data word is right-aligne d (TW A=1), and zero padding is disabled (P ADC=0), then the first data bit is repeated before the transmission of the data word. If zero padding is enabled (P ADC=1), zeroes are transmitted before [...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-17 Figure 8-6 Normal and Netw ork Operation Normal Mode SERIAL CLOCK FRAME SYNC SERIAL DA T A DA T A DA T A TRANSMITTER INTERR UPT (OR DMA REQUEST) AND FLA GS SET RECEIVER INTERR UPT (OR DMA REQUEST) AND FLAGS SET NOTE: Interrupts occur a[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-18 F reescale Semico nductor 8.3.2.10 TCR Tx Slot and W or d Length Select (TSWS4-TSWS0) - Bits 10-14 The TSWS4-TSWS0 bits are used to select the length of the slot and the length of the data words being transferred via the ESAI. The word length must be equa l to[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-19 8.3.2.11 TCR T ransmit Frame Sy nc Length (TFSL) - Bit 15 The TFSL bit selects the length of frame sync to be generated or recognized. If TFSL is cleared, a word-length frame sync is selected. If TFSL is se t, a 1-bit clock period fram[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-20 F reescale Semico nductor Figure 8-7 Frame Length Selection DA T A DA T A SERIAL CLOC K RX, TX FRAME SYNC WORD LENGTH: TFSL=0, RFSL=0 RX, TX SERIAL D A T A NO TE: F rame sync occurs while data is v alid. DA T A DA T A SERIAL CLOC K RX, TX FRAME SYNC ONE BIT LE[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-21 8.3.2.12 TCR T ransmit Frame Sync Relative Timing (TFSR) - Bit 16 TFSR determines the relative timing of the tr ansmit frame sync signal as referred to the serial data lines, for a word length frame sync only (TFSL=0). When T FSR is cl[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-22 F reescale Semico nductor 8.3.2.17 TCR T ransmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21 The TEDIE control bit is used to enable the transmit even slot data in terr upts. If TEDIE is set, the transmit even slot data interrupts are enab led. If TEDIE i[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-23 Hardware and software reset clear all the bits of the RCCR register . 8.3.3.1 RCCR Receiver Prescale Modulus Select (RPM 7–RPM0) - Bits 7–0 The RPM7–RPM0 bits specify the divide ratio of the prescale divider in the ESAI receiver [...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-24 F reescale Semico nductor 8.3.3.5 RCCR Receiver Cloc k P olarity (RCKP) - Bit 18 The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in. If RCKP is cleared the data and th e frame sync are clo[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-25 In the synchronous mode when RCKD is set, the SCKR pin becomes the OF0 out put flag. If RCKD is cleared, then the SCKR pin becomes the IF0 input flag. See Ta b l e 8 - 1 and Ta b l e 8 - 7 . 8.3.3.9 RCCR Receiver Frame Sync Signal Dire[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-26 F reescale Semico nductor 8.3.3.10 RCC R Receiver High Frequency Clock Direction (RHCKD) - Bit 23 The Receiver High Frequency Clock Direction (RHC KD) bit selects the sour ce of the receiver high frequency clock when in the asynchronous mode (S YN=0), and the [...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-27 8.3.4.1 RCR ESAI Receiver 0 Enable (RE0) - Bit 0 When RE0 is set and TE5 is cleared, the ESAI receiv er 0 is enabled and samples data at the SDO5/SDI0 pin. TX5 and RX0 should not be enabled at the same time (RE0=1 and TE5=1). When RE0 [...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-28 F reescale Semico nductor 8.3.4.7 RCR Receiver W or d Al ignment Control (R W A) - Bit 7 The Receiver W ord Alignment Control (R W A) bit defines the alignment of the data word in relation to the slot. This is relevant for the cases where the word le ngth is s[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-29 T a ble 8-11 ESAI Receive Slot and W ord Lengt h Selection RSWS4 RSWS3 RSWS2 RSWS1 RSWS 0 S LO T LENGTH W ORD LENGTH 00000 8 8 00100 1 2 8 00001 1 2 01000 1 6 8 00101 1 2 00010 1 6 01100 2 0 8 01001 1 2 00110 1 6 00011 2 0 10000 2 4 8 [...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-30 F reescale Semico nductor 8.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 15 The RFSL bit selects the lengt h of the receive frame sync to be generated or recogn ized. If RFSL is cleared, a word-length frame sync is selecte d. If RFSL is set, a 1-bit cloc[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-31 8.3.4.13 RCR Receive Exception Inte rrupt Enable (REIE) - Bit 20 When REIE is set, the DSP is interrupted when both RDF and ROE in the SAISR status register are set. When REIE is cleared, this interrupt is disabled. Re ading the SAISR [...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-32 F reescale Semico nductor Hardware and software re set clear all the bits in the SAICR regis ter . 8.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0 The Serial Output Flag 0 (OF0) is a data bit used to hold data to be send to the OF0 pin. When the ESAI is in th[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-33 the transmit and receive s ections. When SYN is set, the synchronous mode is chosen an d the transmit and receive sections use common cl ock and frame sync signals. When in the synchronous mode (SYN=1), the transmit and receive section[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-34 F reescale Semico nductor Figure 8-11 SAICR SYN Bit Op eration 8.3.6 ESAI Status Register (SAISR) The S tatus Register (SAISR) is a read-only status regi ster used by the DSP to read the status and serial input flags of the ESAI. See Figure 8-12 . The status b[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-35 8.3.6.1 SAISR Serial Input Flag 0 (IF0) - Bit 0 The IF0 bit is enabled only when the SCKR pin is defined as ESAI in the Port Control Register , SYN=1 and RCKD=0, indicating that SCKR is an input flag and the s ynchronous mode is select[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-36 F reescale Semico nductor a word is received, it indicates (only in the netw ork mode) that the frame sync did not occur during reception of that word. RFS is cleare d by hardware, software, ESAI individua l, or ST OP reset. RFS is valid only if at least one o[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-37 during the second time slot in the frame. TFS is useful in network mode to identify the start of a frame. TFS is cleared by hardware, software , ESAI individual, or ST OP reset. TFS is valid only if at least one transmitter is enabled [...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-38 F reescale Semico nductor TSR disabled time slot period in network mode (as if data were be ing transmitted after the TSR was written). When set, TODE indicates that data should be written to all the TX registers of the enabled transmitters or to the time slot[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-39 Figure 8-14 ESAI Data P ath Pr ogramming Model ([R/T]SHFD=1) SDI 23 16 15 87 0 7 0 7070 RECEIVE HIGH BYTE RECEIVE MIDDLE B YTERECEIVE LO W BYTE ESAI RECEIVE DA T A REGISTER (READ ONL Y) ESAI RECEIVE SHIFT REGISTER 23 16 1587 0 7 0 7070[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-40 F reescale Semico nductor 8.3.7 ESAI Receive Shift Register s The receive shift registers (see Figure 8-13 and Figure 8-14 ) receive the incoming data from the serial receive data pins. Data is shifted in by the selected (i nternal/external) bit clock wh en th[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-41 transmitter empty condition (TDE=1), or to tri-stat e the transmitter data pi ns. TSMA and TSMB should each be considered as containing half a 32-bit register TSM. See Figure 8-15 and Figure 8-16 . Bit number N in TSM (TS**) is the ena[...]

ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-42 F reescale Semico nductor NO TE When operating in normal mode, bit 0 of the mask register must be set, otherwise no output is generated. 8.3.13 Receive Slot Mask Registers (RSMA, RSMB) The Receive Slot Mask Registers (R SMA and RSMB) are two read/write registe[...]

Operating Modes DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-43 NO TE When operating in normal mode, bit 0 of the mask register must be set to one, otherwise no input is received. 8.4 Operating Modes ESAI operating mode are selected by the ESAI control registers (TC CR, TCR, RCCR, RCR and SAICR). The main[...]

Operating Mod es DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-44 F reescale Semico nductor 8.4.3 ESAI Interrupt Requests The ESAI can generate eight differen t interrupt requests (ordered from th e highest to the lowest priority) : 1. ESAI Receive Data with Exception Status . Occurs when the receive exception interrupt is enab le[...]

Operating Modes DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-45 8. ESAI T r ansmit Data Occurs when the transmit interrupt is enabled (TIE =1), at least one of th e enabled transmit data registers is empty (TDE=1), no exception has occurred (TUE=0 or TEIE=0), and no even slot interrupt has occurred (TEDE=[...]

Operating Mod es DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-46 F reescale Semico nductor Data clock and frame sync signals can be generated internally by the DSP or may be obtained from external sources. If internally genera ted, the ESAI clock gene rator is used to derive high frequency clock, bit clock and frame sync signals [...]

GPIO - Pins and Regi sters DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-47 RCCR and SAICR registers.Th e output data bits (OF2, OF1 and OF0) and the input data bits (IF2, IF1 and IF0) are double buffered to/from th e HCKR, FSR and SCKR pins. Doubl e buf fering the fl ags keeps them in sync with the TX and[...]

GPIO - Pins and Regi sters DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-48 F reescale Semico nductor 8.5.3 P or t C Data register (PDRC) The read/write 24-bit Port C Data Register (see Figure 8-21 ) is used to read or write data to/from ESAI GPIO pins. Bits PD(1 1:0) are used to read or write data from/to the corresponding port p[...]

ESAI Initialization Examples DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-49 8.6 E SAI Initialization Examples 8.6.1 Initializing the ESAI Using Individual Reset • The ESAI should be in its individual reset state (PCRC = $000 and PRRC = $000). In the individual reset state, both the transmitter and rece[...]

ESAI Initialization Examples DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-50 F reescale Semico nductor • Configure the control registers TCCR and TCR according to the operating mode, making sure to clear the transmitter enable bits (TE0 - TE5). TPR must remain set. • T ake the transmitter section out of the personal reset sta[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-1 9 Enhanced Serial A udio Interface 1 (ESAI_1) 9.1 Intr oduction The Enhanced Serial Audio Interface I (ESAI_1) is the second ESAI periphe ral in the DSP56366. It is functionally identical to the ESAI peripheral described in Section 8, "Enhanced Serial AU[...]

Introd uction DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-2 F reescale Semico nductor Figure 9-1 ESAI_1 Block Dia gram Clock / Frame Sync Generators and Control Logic SDO1_1 [PE10] SDO0_1 [PE11] Shift Register RX0_1 TX5_1 SDO5_1/SDI0_1 [PE6] Shift Register RX1_1 TX4_1 SDO4_1/SDI1_1 [PE7] Shift Register RX2_1 TX3_1 SDO3_1/SDI2_1 [...]

ESAI_1 Data and Contr ol Pins DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-3 9.2 E SAI_1 Data and Contr ol Pins The ESAI_1 has 6 dedicated pi ns and shares 4 pins with the ESAI. The pins are de scribed in the following sections. 9.2.1 Serial T ransmit 0 Data Pin (SDO0_1) SDO0_1 transmits data from the TX0[...]

ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-4 F reescale Semico nductor 9.2.6 Serial T ransmit 5/Receiv e 0 Data Pin (SDO5_1/SDI0_1) SDO5_1/SDI0_1 transmits data from the TX5_1 serial transmit shift register when programmed as transmitter pin, or receives serial da ta to the RX0_1 serial shift register w[...]

ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-5 The ESAI_1 also contains the GPIO Port E functionality , described in Section 9.5, "GPIO - Pins and Registers" . The following paragraphs give de tailed descriptions of bits in the ESAI_1 registers that dif fer in functional[...]

ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-6 F reescale Semico nductor 9.3.2.1 TCCR_1 Tx High Freq. Clock Divider (TFP3-TF P0) - Bits 14–17 Since the ESAI_1 does not have the transmitter high frequency cl ock pin, the TFP3–TFP0 bits simply specify an additional division rati o in the clock divider c[...]

ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-7 Figure 9-4 ESAI_1 Clock Generator Functional Bloc k Diagram FLAG0 OUT (SYNC MODE) FLA G0 IN (SYNC MODE) SCKR_1 SCKT_1 RCKD TCKD SYN=1 SYN=0 RCLOCK TCLOCK INTERNAL BIT CLOCK SYN=1 RSWS4-RSWS0 TSWS4-TSWS0 RX WORD LENGTH DIVIDER TX W ORD[...]

ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-8 F reescale Semico nductor Figure 9-5 ESAI_1 Frame Sync Generator Function al Block Diag ram 9.3.3 ESAI_1 T ransmit Control Register (TCR_1) The read/write T r ansmit Control Re gister (TCR_1) controls the ESAI _1 transmitter sec tion. Interrupt enable bits fo[...]

ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-9 9.3.4 ESAI_1 Receive Cloc k Contr ol Register (RCCR_1) The read/write Receive Clock Cont rol Register (RCCR_1) controls the ESAI_1 receiver clock generator bit and frame sync rates, word length, and number of words per frame for the s[...]

ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-10 F reescale Semico nductor 9.3.5 ESAI_1 Receive Contr ol Register (RCR_1) The read/write Receive Control Register (R CR_1) controls the ESAI_1 receiver section. Hardware and software re set clear all the bits in the RCR_1 register . 9.3.6 ESAI_1 Common Contr [...]

ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-11 9.3.8 ESAI_1 Receive Shift Register s The receive shift registers receive the incoming data from the serial receive data pins. Data is shifted in by the selected (internal/external) bit clock when the associated frame sync I/O is ass[...]

ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-12 F reescale Semico nductor 9.3.12 ESAI_1 Time Sl ot Register (TSR_1) The write-only T ime Slot Register (TSR _1) is ef fectively a null data register that is used when the data is not to be transmitted in the available transmit time slot. The transmit data pi[...]

Operating Modes DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-13 9.4 Operating Modes 9.4.1 ESAI_1 After Reset Hardware or software reset clears the EMUXR re gist er , the port E control regi ster bits and the port E direction control register bits, which configur e all 6 ESAI_1 dedicated I/O pi ns as disco[...]

GPIO - Pins and Regi sters DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-14 F reescale Semico nductor 9.5.2 P ort E Direction Register (PRRE) The read/write 24-bit Port E Direct ion Register (PRRE) in conjunction with the Port E Control Register (PCRE) controls the functionali ty of the ESAI_1 GPIO pins. Ta b l e 9 - 4 describes t[...]

GPIO - Pins and Regi sters DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-15 1 1 1 0 9876543210 Y :$FFFF9D PD11 PD10 PD9 PD8 PD7 PD6 PD4 PD3 PD1 PD0 23 22 21 20 19 18 17 16 15 14 13 12 Reser ved bit - read as z ero; should be written with zero for future compatibility . Figure 9-17 PDRE Register[...]

GPIO - Pins and Regi sters DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-16 F reescale Semico nductor NO TES[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-1 10 Digital A udio T ransmitter 10.1 Intr oduction The Digital Audio T ransmitter (DAX) is a serial audio interface module that outputs digital audio data in the AES/EBU, CP-340 and IEC958 formats. Some of the key features of the DAX are listed below . • Op[...]

D AX Signals DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-2 F reescale Semico nductor Figure 10-1 Digital A udio T ransmitter (D AX) Bloc k Diagram 10.2 D AX Signals The DAX has two signal lines: • D AX Digital A udio Output (ADO/PD1) —The ADO pin sends audio and non-audio data in the AES/EBU, CP340, and IEC958 formats in a [...]

D AX Pr ogramming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-3 • Parity generator (PR TYG) • Preamble generator • Biphase encoder • Clock multiplexer • Control state machine XADR, XADBUF A, XADBUFB and XADS R creates a FIFO-like data pa th. Channel A is written to XADR and moves to XADB[...]

D AX Internal Ar chitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-4 F reescale Semico nductor 10.5 D AX Internal Ar chitecture Hardware components shown in Figure 10-1 are described in the following sections. The DAX programming model is illustrated in Figure 10-2 . Figure 10-2 D AX Programming Model T ab le 10-1 D AX Int[...]

D AX Internal Ar chitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-5 10.5.1 D AX A udio Data Register (XADR) XADR is a 24-bit write-only re gister . One frame of audio data, which is to be tran smitted in the next fr ame slot, is transferred to this register . Successive write accesses to this regi[...]

D AX Internal Ar chitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-6 F reescale Semico nductor 10.5.4.2 D AX Channel A Us er Data (XU A)—Bit 11 The value of the XUA bit is transmitte d as the thirtieth bit (B it 29) of the channel A subframe in the next frame. 10.5.4.3 D AX Channel A Channel Status (XCA)—Bit 12 The val[...]

D AX Internal Ar chitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-7 10.5.6.1 Audio Data Register Empty Interrupt Enable (XDIE)—Bit 0 When the XDIE bit is set, the audio data register empty inte rrupt is enabled and send s an interrupt request signal to the DSP if the XADE status bit is set. Wh e[...]

D AX Internal Ar chitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-8 F reescale Semico nductor 10.5.7.1 D AX A udio Data Register Empty (XADE)—Bit 0 The XADE status flag indicates th at the DAX audio data register XADR and the audio data buf fer XADBUF A are empty (and ready to rece ive the next frame’ s audio data). T[...]

D AX Internal Ar chitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-9 10.5.8 D AX P a rity Generator (PR TYG) The PR TYG generates the parity bit for the subframe being transmitted. The gene rated parity bit ensures that subframe bits four to thirty-one w ill carry an even number of ones and zeroes.[...]

D AX Programming Consideratio ns DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-10 F r eescale Semiconductor • The internal DSP core clock—assumes 1024 × Fs • DAX clock input pin (ACI)—512 × Fs • DAX clock input pin (ACI)—384 × Fs • DAX clock input pin (ACI)—256 × Fs Figure 10-5 shows how each clock is divided [...]

D AX Pr ogramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-11 non-audio data bits of the next frame are stored in XNADR a nd one frame of audio data to be transmitted in the next frame is stored in th e FIFO by two consecutive MOVEP inst ructions to XADR. If the non-audio bits are not [...]

GPIO (PORT D) - Pins and Register s DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-12 F r eescale Semiconductor Figure 10-6 Examples of data or ganization in memory 10.6.5 D AX Operation During Stop The DAX operation cannot continue when the DSP is in the stop state since no DSP clocks are active. While the DSP is in the sto p sta[...]

GPIO (POR T D) - Pi ns and Register s DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-13 10.7.2 P ort D Direction Register (PRRD) The read/write 24-bit Port D Direct ion Register controls the direction of the DAX GPIO pins. When port pin[i] is configured as GPIO, PDC[ i] controls the port pin direction. Wh [...]

GPIO (PORT D) - Pins and Register s DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-14 F r eescale Semiconductor 10.7.3 P o r t D Data Register (PDRD) The read/write 24-bit Port D Data Register is used to read or write data to/fro m the DAX GPIO pins. Bits PD[1:0] are used to read or write data from/to the corresponding port pins i[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-1 11 Timer/ Event Counter 11.1 Intr oduction This section describes the internal timer/event counter in the DSP56366. Each of the thr ee timers (timer 0, 1 and 2) can use internal clocking to interrupt the DSP56366 or trigger DMA transfers after a specified nu[...]

Timer/Event Counter Architecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-2 F reescale Semico nductor 11.2.2 Individual Timer Bloc k Diagram Figure 1 1-2 shows the structure of an indi vidual timer module. The three timer s are identical in structure, but only timer 0 is externally accessible. Each timer includes a 24-bit co[...]

Timer/Event Counter Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-3 11.3 Timer/Event Counter Pr ogramming Model The DSP56366 views each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory space. Either standard polled or interrupt prog[...]

Timer/Event Counte r Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-4 F reescale Semico nductor Figure 11-3 Timer Module Pr ogrammer’ s Model DO DI DIR 15 14 13 12 11 10 9 8 TC1 TC0 INV TCIE TE 76543210 Timer Control/St atus Registe r (TCSR) - reserved, read as 0, should be written with 0 for future compatibili[...]

Timer/Event Counter Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-5 11.3.1 Prescaler Counter The prescaler counter is a 21-bit counter that is decr emented on the rising edge of the prescaler input clock. The counter is enabled when at least one of the three timers is enabled (i.e., one [...]

Timer/Event Counte r Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-6 F reescale Semico nductor 11.3.2.3 TPL R Reserved Bit 23 This reserved bit is read as zero and should be written with zero for future compatibility . 11.3.3 Timer Prescaler Count Register (TPCR) The TPCR is a 24-bit read-only re gister that ref[...]

Timer/Event Counter Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-7 Clearing the TE bit disables th e timer . The TE bit is cl eared by the hardware RESET signal or the software RESET instruction. NO TE When timer 0 is disabled a nd TIO0 is not in GPIO m ode, the pin is tri-stated. T o p[...]

Timer/Event Counte r Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-8 F reescale Semico nductor T a ble 11-2 Timer Contr ol Bits f or Timer 0 Bit Settings Mode Characteristics TC3 TC2 TC 1 TC0 Mode Number Mode Function TIO0 Cloc k 0 0 0 0 0 Timer and GPIO GPI O 1 1 The GPIO function is enabled only if all of the [...]

Timer/Event Counter Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-9 11.3.4.5 TCSR In vert er (INV) Bit 8 The INV bit affects the polarity of the incoming signal on the TIO0 input signal and the polarity of the output pulse generated on the TIO0 output signal. The effects of the INV bit a[...]

Timer/Event Counte r Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-10 F r eescale Semiconductor NO TE The INV bit affects both th e timer and GPIO modes of operation. T o ensure correct operation, this bit should be ch anged only when one or both of the following conditio ns is true: • The timer has been disab[...]

Timer/Event Counter Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-11 The DO bit is cleared by the hardware RESET signal or the softwa re RESET instruction. This bit is not in use for timers 1 and 2. It should be left cleared. 11.3.4.10 TCSR Prescaler Cl o c k Enable (PCE) Bit 15 The PCE [...]

Timer Modes of Operation DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-12 F r eescale Semiconductor 11.3.5 Timer Load Register (TLR) The TLR is a 24-bit write-only register . In all modes, the counter is prel oaded with the TLR value after the TE bit in the TCSR is set and a first event occurs. The programmer must initialize the [...]

Timer Modes of Operatio n DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-13 — Event counter , mode 3: Internal timer interrupt generated by an external clock •M e a s u r e m e n t — Input width, mode 4: Input pulse width measurement — Input pulse, mode 5: Input signal period measurement — Captur[...]

Timer Modes of Operation DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-14 F r eescale Semiconductor 11.4.1.2 Timer Pulse (Mo de 1) In this mode, the timer generates a compare interrupt when the timer count reaches a preset value. In addition, timer 0 provides an exte rnal pulse on its TIO0 signal. Set the TE bit to clear the coun[...]

Timer Modes of Operatio n DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-15 When the counter value matches the value in the TCPR, the polarity of the TIO0 output signal is inverted. The TCF bit in the TCSR is set and a compare in terrupt is generated if the TCIE bit is set. If the TRM bit is set, the count[...]

Timer Modes of Operation DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-16 F r eescale Semiconductor 11.4.2 Signal Measurement Modes The following signal measurement modes are provided: • Measurement input width • Measurement input period • Measurement capture These functions are av ailable only on timer 0. 11.4.2.1 Measurem[...]

Timer Modes of Operatio n DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-17 11.4.2.3 Measurement In put P eriod (Mode 5) In this mode, the timer counts the period between the reception of signal edges of the same polarity across the TIO0 signal. Set the TE bit to clear the counter a nd enable the timer . T[...]

Timer Modes of Operation DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-18 F r eescale Semiconductor clock signal can be taken from either the DSP56366 clock divided by two (CLK/2) or fr om the prescaler clock output. Each subsequent cloc k signal increments the counter . At the first appropriate tr ansition of the external clock [...]

Timer Modes of Operatio n DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-19 The duty cycle of the TIO0 signal is determined by the value in the TC PR. When the value in the TLR is incremented to a value equal to the value in the TCPR, the TIO0 signal is toggled. The duty cycle is equal to ($FFFFFF – TCPR[...]

Timer Modes of Operation DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-20 F r eescale Semiconductor 11.4.4.2 W atchdog T oggle (Mode 10) In this mode, the timer generates an interrupt at a preset rate. T ime r 0 also toggles the output on TIO0. Set the TE bit to clear the counter a nd enable the timer . The value the time r is to[...]

Timer Modes of Operatio n DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-21 11.4.6.2 Timer B ehavior during Stop During the execution of the ST OP inst ruction, the timer clocks are disabled, timer ac tivity is stopped, and the TIO0 signal is disconnect ed. Any external changes that happen to the TIO0 sign[...]

Timer Modes of Operation DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-22 F r eescale Semiconductor NO TES[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-1 Appendix A Bootstrap R OM Contents A.1 DSP56366 Bootstrap Pr ogram ; BOOTSTRAP CODE FOR DSP56366 Rev. 0 silicon - (C) Copyright 1999 Motorola Inc. ; ; ; Revision 0.0 1999/JAN/26 - Modified from 56362_RevA_regular_boot_rev01.asm: ; - Change the length of xram [...]

DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-2 F reescale Semico nductor ; Program ROM, without loading the Program RAM. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Operation mode MD:MC:MB:MA=0011 is reserved. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;[...]

DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-3 ; The HOST 8051 bootstrap code expects to read 3 bytes forming a 24-bit word ; specifying the number of program words, 3 bytes forming a 24-bit word ; specifying the address to start loading the program words and then 3 bytes ; form[...]

DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-4 F reescale Semico nductor ;; ;;;;;;;;;;;;;;;;;;;; DSP I/O REGISTERS ;;;;;;;;;;;;;;;;;;;;;;;; ;; M_AAR1 EQU $FFFFF8 ; Address Attribute Register 1 M_OGDB EQU $FFFFFC ; OnCE GDB Register M_HPCR EQU $FFFFC4 ; Host Polarity Control Register M_HSR EQU $FFFFC3 ; [...]

DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-5 SHILD ; This is the routine which loads a program through the SHI port. ; The SHI operates in the slave ; mode, with the 10-word FIFO enabled, and with the HREQ pin enabled for ; receive operation. The word size for transfer is 24 b[...]

DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-6 F reescale Semico nductor ; MD:MC:MB:MA=0001 EPROMLD move #BOOT,r2 ; r2 = address of external EPROM movep #AARV,X:M_AAR1 ; aar1 configured for SRAM types of access do #6,_LOOP9 ; read number of words and starting address movem p:(r2)+,a2 ; Get the 8 LSB fro[...]

DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-7 ; E - i8051 - Dual strobes multiplexed bus with negative strobe pulses ; dual negative request. ; F - MC68302 - Single strobe non-multiplexed bus with negative strobe ; pulse single negative request. ;===============================[...]

DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-8 F reescale Semico nductor ; future compatability ; HEN = 0 When the HPCR register is modified ; HEN should be cleared ; HAEN = 0 Host acknowledge is disabled ; HREN = 1 Host requests are enabled ; HCSEN = 1 Host chip select input enabled ; HA9EN = 0 (addres[...]

DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-9 ; HROD = 0 Host request is active when enabled ; spare = 0 This bit should be set to 0 for ; future compatability ; HEN = 0 When the HPCR register is modified ; HEN should be cleared ; HAEN = 0 Host acknowledge is disabled ; HREN = [...]

DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-10 F reescale Semico nductor ;======================================================================== ; MD:MC:MB:MA=1001 is used for Burn-in code BURN_RESER jclr #MB,omr,BURN ; IF MD:MC:MB:MA=1001, go to BURN ;================================================[...]

DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-11 ;; r5 = test fail flag = $000000 lua (r5)-,r7 ;; r7 = test pass flag = $FFFFFF burnin_loop do #9,burn1 ;;---------------------------- ;; test RAM ;; each pass checks 1 pattern ;;---------------------------- move p:(r6)+,x1 ;; patte[...]

DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-12 F reescale Semico nductor move y:(r0)+,a1 ;; a0=a2=0 eor x0,a add a,b ;; accumulate error in b _loopd else ;; x/y ram not symmetrical ;; check xram clr a #start_xram,r0 ;; restore pointer, clear a do n0,_loopx move x:(r0)+,a1 ;; a0=a2=0 eor x1,a add a,b ;;[...]

DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-13 BURN_END ORG PL:,PL: PATTERNS dsm 4 ;; align for correct modulo addressing ORG PL:BURN_END,PL:BURN_END dup PATTERNS-* ; write address in unused Boot ROM location dc * endm ORG PL:PATTERNS,PL:PATTERNS ;; Each value is written to all[...]

DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-14 F reescale Semico nductor move x0,x:(r0)+ move #$1,x0 move x0,x:(r0)+ move #$2,x0 move x0,x:(r0)+ move #$3,x0 move x0,x:(r0)+ move #$4,x0 move x0,x:(r0)+ move #$5,x0 move x0,x:(r0)+ move #$6,x0 move x0,x:(r0)+ move #$7,x0 move x0,x:(r0)+ move #$8,x0 move x[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-1 Appendix B Equates ;********************************************************************************* ; EQUATES for DSP56366 interrupts ; Last update: April 24, 2000 ; ;********************************************************************************* page 132[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-2 F reescale Semico nductor ;------------------------------------------------------------------------ ; Interrupt Request Pins ;------------------------------------------------------------------------ I_IRQA EQU I_VEC+$10 ; IRQA I_IRQB EQU I_VEC+$12 ; IRQB I_IRQC EQU I_VEC+$14 [...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-3 I_ESAIRLS EQU I_VEC+$36 ; ESAI Receive Last Slot I_ESAITD EQU I_VEC+$38 ; ESAI Transmit Data I_ESAITED EQU I_VEC+$3A ; ESAI Transmit Even Data I_ESAITDE EQU I_VEC+$3C ; ESAI Transmit Data With Exception Status I_ESAITLS EQU I_VEC+$3E ; ESAI Transmit L[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-4 F reescale Semico nductor I_HI08TX EQU I_VEC+$62 ; Host Transmit Data Empty I_HI08CM EQU I_VEC+$64 ; Host Command (Default) ;------------------------------------------------------------------------ ; ESAI_1 Interrupts ;---------------------------------------------------------[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-5 ; ; EQUATES for I/O Port Programming ; ;------------------------------------------------------------------------ ; Register Addresses M_HDR EQU $FFFFC9 ; Host port GPIO data Register M_HDDR EQU $FFFFC8 ; Host port GPIO direction Register M_PCRC EQU $F[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-6 F reescale Semico nductor M_IAL1 EQU 1 ; IRQA Mode Interrupt Priority Level (high) M_IAL2 EQU 2 ; IRQA Mode Trigger Mode M_IBL EQU $38 ; IRQB Mode Mask M_IBL0 EQU 3 ; IRQB Mode Interrupt Priority Level (low) M_IBL1 EQU 4 ; IRQB Mode Interrupt Priority Level (high) M_IBL2 EQU [...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-7 M_D4L0 EQU 20 ; DMA4 Interrupt Priority Level (low) M_D4L1 EQU 21 ; DMA4 Interrupt Priority Level (high) M_D5L EQU $C00000 ; DMA5 Interrupt priority Level Mask M_D5L0 EQU 22 ; DMA5 Interrupt Priority Level (low) M_D5L1 EQU 23 ; DMA5 Interrupt Priority[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-8 F reescale Semico nductor ;------------------------------------------------------------------------ ; Register Addresses Of DMA M_DSTR EQU $FFFFF4 ; DMA Status Register M_DOR0 EQU $FFFFF3 ; DMA Offset Register 0 M_DOR1 EQU $FFFFF2 ; DMA Offset Register 1 M_DOR2 EQU $FFFFF1 ; [...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-9 M_DCR3 EQU $FFFFE0 ; DMA3 Control Register ; Register Addresses Of DMA4 M_DSR4 EQU $FFFFDF ; DMA4 Source Address Register M_DDR4 EQU $FFFFDE ; DMA4 Destination Address Register M_DCO4 EQU $FFFFDD ; DMA4 Counter M_DCR4 EQU $FFFFDC ; DMA4 Control Regist[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-10 F reescale Semico nductor M_DRS1 EQU 12 ;DMA Request Source bit 1 M_DRS2 EQU 13 ;DMA Request Source bit 2 M_DRS3 EQU 14 ;DMA Request Source bit 3 M_DRS4 EQU 15 ;DMA Request Source bit 4 M_DCON EQU 16 ; DMA Continuous Mode M_DPR EQU $60000 ; DMA Channel Priority M_DPR0 EQU 17[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-11 ;------------------------------------------------------------------------ ; ; EQUATES for Phase Locked Loop (PLL) ; ;------------------------------------------------------------------------ ; Register Addresses Of PLL M_PCTL EQU $FFFFFD ; PLL Control[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-12 F reescale Semico nductor M_PEN EQU 18 ; PLL Enable Bit M_COD EQU 19 ; PLL Clock Output Disable Bit M_PD EQU $F00000 ; PreDivider Factor Bits Mask (PD0-PD3) M_PD0 EQU 20 ;PreDivider Factor bit 0 M_PD1 EQU 21 ;PreDivider Factor bit 1 M_PD2 EQU 22 ;PreDivider Factor bit 2 M_PD[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-13 M_BA1W EQU $3E0 ; Area 1 Wait Control Mask (BA1W0-BA14) M_BA1W0 EQU 5 ;Area 1 Wait Control Bit 0 M_BA1W1 EQU 6 ;Area 1 Wait Control Bit 1 M_BA1W2 EQU 7 ;Area 1 Wait Control Bit 2 M_BA1W3 EQU 8 ;Area 1 Wait Control Bit 3 M_BA1W4 EQU 9 ;Area 1 Wait Con[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-14 F reescale Semico nductor M_BRW0 EQU 2 ;Out of Page Wait States bit 0 M_BRW1 EQU 3 ; Out of Page Wait States bit 1 M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1) M_BPS0 EQU 4 ; DRAM Page Size Bits 0 M_BPS1 EQU 5 ; DRAM Page Size Bits 1 M_BPLE EQU 11 ; Page Logic Enabl[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-15 M_BAM EQU 6 ; Address Muxing M_BPAC EQU 7 ; Packing Enable M_BNC EQU $F00 ; Number of Address Bits to Compare Mask (BNC0-BNC3) M_BNC0 EQU 8 ; Number of Address Bits to Compare 0 M_BNC1 EQU 9 ; Number of Address Bits to Compare 1 M_BNC2 EQU 10 ; Numbe[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-16 F reescale Semico nductor M_S EQU 7 ; Scaling Bit M_I0 EQU 8 ; Interupt Mask Bit 0 M_I1 EQU 9 ; Interupt Mask Bit 1 M_S0 EQU 10 ; Scaling Mode Bit 0 M_S1 EQU 11 ; Scaling Mode Bit 1 M_SC EQU 13 ; Sixteen_Bit Compatibility M_DM EQU 14 ; Double Precision Multiply M_LF EQU 15 ;[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-17 M_BE EQU 10 ; Burst Enable M_TAS EQU 11 ; TA Synchronize Select M_BRT EQU 12 ; Bus Release Timing M_ABE EQU 13 ;Async. Bus Arbitration Enable M_APD EQU 14 ;Addess Priority Disable M_ATE EQU 15 ;Address Tracing Enable M_XYS EQU 16 ; Stack Extension sp[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-18 F reescale Semico nductor M_XBLK EQU 2 ; DAX Block Transferred (XBLK) ; non-audio bits in XNADR M_XVA EQU 10 ; DAX Channel A Validity (XVA) M_XUA EQU 11 ; DAX Channel A User Data (XUA) M_XCA EQU 12 ; DAX Channel A Channel Status (XCA) M_XVB EQU 13 ; DAX Channel B Validity (X[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-19 ; HSAR bits M_HA6 EQU 23 ; SHI I2C Slave Address (HA6) M_HA5 EQU 22 ; SHI I2C Slave Address (HA5) M_HA4 EQU 21 ; SHI I2C Slave Address (HA4) M_HA3 EQU 20 ; SHI I2C Slave Address (HA3) M_HA1 EQU 18 ; SHI I2C Slave Address (HA1) ; control and status bi[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-20 F reescale Semico nductor ; control bits in HCKR M_HFM1 EQU 13 ; SHI Filter Model (HFM1) M_HFM0 EQU 12 ; SHI Filter Model (HFM0) M_HDM7 EQU 10 ; SHI Divider Modulus Select (HDM7) M_HDM6 EQU 9 ; SHI Divider Modulus Select (HDM6) M_HDM5 EQU 8 ; SHI Divider Modulus Select (HDM5[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-21 M_RCR_1 EQU $FFFF97 ; ESAI_1 Receive Control Register (RCR_1) M_TCCR_1 EQU $FFFF96 ; ESAI_1 Transmit Clock Control Register (TCCR_1) M_TCR_1 EQU $FFFF95 ; ESAI_1 Transmit Control Register (TCR_1) M_SAICR_1 EQU $FFFF94 ; ESAI_1 Control Register (SAICR[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-22 F reescale Semico nductor M_RCR EQU $FFFFB7 ; ESAI Receive Control Register (RCR) M_TCCR EQU $FFFFB6 ; ESAI Transmit Clock Control Register (TCCR) M_TCR EQU $FFFFB5 ; ESAI Transmit Control Register (TCR) M_SAICR EQU $FFFFB4 ; ESAI Control Register (SAICR) M_SAISR EQU $FFFFB3[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-23 M_RS21 EQU 5 ; ESAI M_RS20 EQU 4 ; ESAI M_RS19 EQU 3 ; ESAI M_RS18 EQU 2 ; ESAI M_RS17 EQU 1 ; ESAI M_RS16 EQU 0 ; ESAI ; RSMA Register bits M_RS15 EQU 15 ; ESAI M_RS14 EQU 14 ; ESAI M_RS13 EQU 13 ; ESAI M_RS12 EQU 12 ; ESAI M_RS11 EQU 11 ; ESAI M_RS[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-24 F reescale Semico nductor M_TS27 EQU 11 ; ESAI M_TS26 EQU 10 ; ESAI M_TS25 EQU 9 ; ESAI M_TS24 EQU 8 ; ESAI M_TS23 EQU 7 ; ESAI M_TS22 EQU 6 ; ESAI M_TS21 EQU 5 ; ESAI M_TS20 EQU 4 ; ESAI M_TS19 EQU 3 ; ESAI M_TS18 EQU 2 ; ESAI M_TS17 EQU 1 ; ESAI M_TS16 EQU 0 ; ESAI ; TSMA [...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-25 M_TS1 EQU 1 ; ESAI M_TS0 EQU 0 ; ESAI ; RCCR Register bits M_RHCKD EQU 23 ; ESAI M_RFSD EQU 22 ; ESAI M_RCKD EQU 21 ; ESAI M_RHCKP EQU 20 ;ESAI M_RFSP EQU 19 ; ESAI M_RCKP EQU 18 ;ESAI M_RFP EQU $3C000 ;ESAI MASK M_RFP3 EQU 17 ; ESAI M_RFP2 EQU 16 ; [...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-26 F reescale Semico nductor M_RPM1 EQU 1 ; ESAI M_RPM0 EQU 0 ; ESAI ; RCR Register bits M_RLIE EQU 23 ; ESAI M_RIE EQU 22 ; ESAI M_REDIE EQU 21 ; ESAI M_REIE EQU 20 ; ESAI M_RPR EQU 19 ; ESAI M_RFSR EQU 16 ; ESAI M_RFSL EQU 15 ; ESAI M_RSWS EQU $7C00 ;ESAI MASK M_RSWS4 EQU 14 [...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-27 M_THCKD EQU 23 ; ESAI M_TFSD EQU 22 ; ESAI M_TCKD EQU 21 ; ESAI M_THCKP EQU 20 ;ESAI M_TFSP EQU 19 ; ESAI M_TCKP EQU 18 ; ESAI M_TFP EQU $3C000 M_TFP3 EQU 17 ; ESAI M_TFP2 EQU 16 ; ESAI M_TFP1 EQU 15 ; ESAI M_TFP0 EQU 14 ; ESAI M_TDC EQU $3E00 ; M_TD[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-28 F reescale Semico nductor M_TLIE EQU 23 ; ESAI M_TIE EQU 22 ; ESAI M_TEDIE EQU 21 ; ESAI M_TEIE EQU 20 ; ESAI M_TPR EQU 19 ; ESAI M_PADC EQU 17 ; ESAI M_TFSR EQU 16 ; ESAI M_TFSL EQU 15 ; ESAI M_TSWS EQU $7C00 M_TSWS4 EQU 14 ; ESAI M_TSWS3 EQU 13 ; ESAI M_TSWS2 EQU 12 ; ESAI[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-29 M_ALC EQU 8 ;ESAI M_TEBE EQU 7 ; ESAI M_SYN EQU 6 ; ESAI M_OF2 EQU 2 ; ESAI M_OF1 EQU 1 ; ESAI M_OF0 EQU 0 ; ESAI ; status bits of SAISR M_TODE EQU 17 ; ESAI M_TEDE EQU 16 ; ESAI M_TDE EQU 15 ; ESAI M_TUE EQU 14 ; ESAI M_TFS EQU 13 ; ESAI M_RODF EQU [...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-30 F reescale Semico nductor M_HORX EQU $FFFFC6 ; HOST Receive Register (HORX) M_HBAR EQU $FFFFC5 ; HOST Base Address Register (HBAR) M_HPCR EQU $FFFFC4 ; HOST Port Control Register (HPCR) M_HSR EQU $FFFFC3 ; HOST Status Register (HSR) M_HCR EQU $FFFFC2 ; HOST Control Register [...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-31 M_HCSEN EQU $3 ; HOST Chip Select Enable M_HREN EQU $4 ; HOST Request Enable M_HAEN EQU $5 ; HOST Acknowledge Enable M_HOEN EQU $6 ; HOST Enable M_HROD EQU $8 ; HOST Request Open Dranin mode M_HDSP EQU $9 ; HOST Data Strobe Polarity M_HASP EQU $a ; H[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-32 F reescale Semico nductor M_TCSR0 EQU $FFFF8F ; TIMER0 Control/Status Register M_TLR0 EQU $FFFF8E ; TIMER0 Load Reg M_TCPR0 EQU $FFFF8D ; TIMER0 Compare Register M_TCR0 EQU $FFFF8C ; TIMER0 Count Register ; Register Addresses Of TIMER1 M_TCSR1 EQU $FFFF8B ; TIMER1 Control/St[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-33 M_TOF EQU 20 ; Timer Overflow Flag M_TCF EQU 21 ; Timer Compare Flag ; Timer Prescaler Register Bit Flags M_PS EQU $600000 ; Prescaler Source Mask M_PS0 EQU 21 M_PS1 EQU 22 ; Timer Control Bits M_TC0 EQU 4 ; Timer Control 0 M_TC1 EQU 5 ; Timer Contro[...]

Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-34 F reescale Semico nductor NO TES[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor C-1 Appendix C JT A G BSDL -- FILENAME : 56366TQFP_revA.bsdl -- -- M O T O R O L A S S D T J T A G S O F T W A R E -- BSDL File Generated: Mon Jan 18 10:13:53 1999 -- -- Revision History: -- entity DSP56366 is generic (PHYSICAL_PIN_MAP : string := "TQFP144&q[...]

JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 C-2 F reescale Semico nductor CAS_: out bit; EXTAL: in bit; CVCC: linkage bit_vector(0 to 1); CGND: linkage bit_vector(0 to 1); TA_: in bit; BR_: buffer bit; BB_: inout bit; WR_: out bit; RD_: out bit; BG_: in bit; A: out bit_vector(0 to 17); AVCC: linkage bit_vector(0 to 2);[...]

JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor C-3 "QVCCH: (20, 49, 95), " & "HP: (43, 42, 41, 40, 37, 36, 35, 34, 33, 32, 31, 22, 21, 30, 24, 23), " & "ADO: 27, " & "ACI: 28, " & "TIO: 29, " & "HVCC: 38, " & "[...]

JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 C-4 F reescale Semico nductor attribute INSTRUCTION_OPCODE of DSP56366 : entity is "EXTEST (0000)," & "SAMPLE (0001)," & "IDCODE (0010)," & "CLAMP (0101)," & "HIGHZ (0100)," & "ENABLE_ONCE (0110),"[...]

JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor C-5 "28 (BC_1, *, control, 1)," & "29 (BC_6, D(2), bidir, X, 28, 1, Z)," & "30 (BC_6, D(1), bidir, X, 28, 1, Z)," & "31 (BC_6, D(0), bidir, X, 28, 1, Z)," & "32 (BC_1, A(17), output3, X, 35,[...]

JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 C-6 F reescale Semico nductor "80 (BC_1, RESET_, input, X)," & "81 (BC_1, *, control, 1)," & "82 (BC_6, HP(0), bidir, X, 81, 1, Z)," & "83 (BC_1, *, control, 1)," & "84 (BC_6, HP(1), bidir, X, 83, 1, Z)," &[...]

JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor C-7 "133 (BC_1, *, control, 1)," & "134 (BC_6, SDOI41, bidir, X, 133, 1, Z)," & "135 (BC_1, *, control, 1)," & "136 (BC_6, SDOI32, bidir, X, 135, 1, Z)," & "137 (BC_1, *, control, 1)," [...]

JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 C-8 F reescale Semico nductor NO TES[...]

DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-1 Appendix D Pr ogrammer’ s Reference D .1 Introduction This section has been compiled as a reference for programmers. It cont ains a table show ing th e addresses of all the DSPs memory-mapped peripherals, an interr upt address table, an inte rrupt exception[...]

Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-2 F reescale Semico nductor T ab le D-1. Inter nal I/O Memory Map Peripheral Address Register Name IPR X:$FFFFFF INTERR UPT PRIOR ITY REGISTER CORE (IPR-C) X:$FFFFFE INTERR UPT PRIORITY REGISTER PERIPHERAL (IPR-P) PLL X :$FFFFFD PLL CONT ROL REGISTER (PCTL) ONCE[...]

Internal I/O Memor y Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-3 DMA4 X:$FFFFDF DMA SOURCE ADDRESS REGISTER (DSR4) X:$FFFFDE DMA DESTINA TION ADDRESS REGISTER (DDR4) X:$FFFFDD DMA COUNTER (DCO4) X:$FFFFDC DMA CONTR OL REGISTER (DCR4) DMA5 X:$FFFFDB DMA SOURCE ADDRESS REGISTER (DSR5) X:$FFFFD A DMA [...]

Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-4 F reescale Semico nductor ESAI X:$FFFFBC ESAI RECEIVE SL O T MASK REGISTER B (RSMB) X:$FFFFBB ESAI RECEIVE SLO T MASK REGISTER A (RSMA) X:$FFFFBA ESAI TRANSMIT SLO T MASK REGISTER B (TSMB) X:$FFFFB9 ESAI TRANSMIT SL O T MASK REGISTER A (TSMA) X:$FFFFB8 ESAI RE[...]

Internal I/O Memor y Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-5 X:$FFFF99 Reser ved X:$FFFF98 Reser ved X:$FFFF97 Reser ved X:$FFFF96 Reser ved X:$FFFF95 Reser ved SHI X:$FFFF94 SHI RECEIVE FIFO (HRX) X:$FFFF93 SHI TRANSMIT REGISTER (HTX) X:$FFFF92 SHI I 2 C SLA VE ADDRESS REGISTER (HSAR) X:$FFFF9[...]

Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-6 F reescale Semico nductor Y: $ F F F FA 7 Reser ved Y: $ F F F FA 6 Reser ved Y: $ F F F FA 5 Reser ved Y: $ F F F FA 4 Reser ved Y: $ F F F FA 3 Reser ved Y: $ F F F FA 2 Reser ved Y: $ F F F FA 1 Reser ved Y: $ F F F FA 0 Reser ved POR T E Y :$FFFF9F POR T E[...]

Internal I/O Memor y Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-7 ESAI_1 Y :$FFFF9C ESAI_1 RECEIVE SLO T MASK REGISTER B (RSMB_1) Y :$FFFF9B ESAI_1 RECEIVE SLOT MASK REGIS TER A (RSMA_1) Y :$FFFF9A ESAI_1 TRAN SMIT SLO T MASK REGISTER B (TSMB_1) Y :$FFFF99 ESAI_1 TRANSMIT SLO T MASK REGISTER A (TSMA[...]

Interrupt V ector Addresses DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-8 F reescale Semico nductor D .3 Interrupt V ector Ad dresses T able D-2. DSP56366 Inte rrupt V ectors Interrupt Starting Address Interrupt Priority Level Range Interrupt Source VBA:$00 3 Hardware RESET VBA:$02 3 Stack Error VBA:$04 3 Illegal Instruction VBA[...]

Interrupt V ector Addresses DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-9 VBA:$42 0 - 2 SHI T ransmit Underrun Error VBA:$44 0 - 2 SHI Rece ive FIFO Not Empty VBA:$46 0 - 2 Reser ved VBA:$48 0 - 2 SHI Receive FIFO Full VBA:$4A 0 - 2 SHI Receive Overrun Error VBA:$4C 0 - 2 SHI Bus Error VBA:$4E 0 - 2 Rese[...]

Interrupt Source Priori ties (within an IPL) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-10 F reescale Semico nductor D .4 Interrupt Source Prio rities (within an IPL) T abl e D-3. Interrupt Sources Priorities Within an IPL Priority Interrupt Source Lev el 3 (Nonma skable) Highest Hardware RESET Stack Error Illegal Instruction D[...]

Interrupt Sou rce Priorities (within an IPL) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-11 HOST T ransmit Data Interrupt D AX T ransmit Underr un Error D AX Bloc k T ransf erred D AX T ransmit Register Empty TIMER0 Ov erflow Interrupt TIMER0 Compare Interr upt TIMER1 Ov erflow Interrupt TIMER1 Compare I[...]

Host Interface—Quick Reference DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-12 F reescale Semico nductor D .5 Host Interface—Quick Ref erence T abl e D-4. HDI08 Pr ogramming Model Reg Bit Comments Reset T ype Num Mnemonic Name V al Funct ion HW / SW IR ST DSP SIDE HCR 0 HRIE Receive Interrupt Enable 0 1 HRRQ interrupt disable[...]

Host Interface—Quick Reference DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-13 HPCR 0 HGEN Host GPIO Enable 0 1 GPIO pin disconnected GPIO pins active 0 - - 1 HA8EN Host Address Line 8 Enable 0 HA8/HA1 = GPIO this bit is treated as 1 if HMUX=0 this bit is treated as 0 if HEN=0 0 - - 1 HA8/HA1 = HA8/HA1 [...]

Host Interface—Quick Reference DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-14 F reescale Semico nductor HSR 0 HRDF Host Receive Data Full 0 1 no receive data to be read receive data register is full 00 0 1 H TDE Host T ransmit Data Empty 1 0 transmit data register empty transmit data reg. not empty 11 1 2 HCP Host Command Pend[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-15 D .6 Programming Sheets The worksheets shown on the following pages contain li stings of major programmable registers for the DSP56366. The programming sheets are gr ouped into the following order: • Central Processor • Host Interface [...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-16 F reescale Semico nductor Figure D- 1. Status R egister ( SR) Application: Dat e: Programmer : Sheet 1 of 5 Central Processor 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UZ V C 19 18 17 16 23 22 21 2 0 L LF S1 SM I1 I0 CE SA FV S0 N Scaling Mode S(1:0) Scaling Mode 00 0[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-17 Figure D-2. Operating Mode Register (OMR) Chip Operating Modes MOD(D:A) Reset Vector Description See Core Configuration Section. Application : Date: Programmer: Sheet 2 of 5 1 5 1 4 1 3 1 2 1 1 1 0 98 7 654321 0 EBD MC MB MA 19 18 17 16 23[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-18 F reescale Semico nductor Figure D-3. Interrupt Priority Register–Core (IPR–C) Application: Date: Programmer: Sheet 3 of 5 CENTRAL PROCESSOR 15 14 13 12 11 10 9 876543210 D1L0 IDL2 IDL1 IBL2 IBL1 IBL0 IA L2 IAL1 IAL0 Interrupt Priority X:$FFFFFF R/ W D0L1 D0L0[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-19 Figure D-4. Interrupt Priority Regist er – P eripherals (IPR–P) Application: Date: Programmer: Sheet 4 of 5 CENTRAL PROCESSOR * = Reserved, Pro gram as 0 Interrupt Priority X:$FFFFFE R/W Reset = $000000 Register (IPR –P) ESL1 ESL0 En[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-20 F reescale Semico nductor Figure D-5. Phase Loc k Loop Contr ol Register (PCTL) Application: Date: Programmer: Sheet 5 of 5 PLL 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 MF7 MF5 MF4 MF3 MF2 MF1 MF0 19 18 17 16 23 22 21 20 PEN COD PD1 PD3 MF6 PD2 XTLD XTLR DF2 DF1 DF0 MF1[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-21 Figure D-6. Ho st Receive and Host T ransmit Data Register s Application: Date: Programmer: Sheet 1 of 6 HOST (HDI08) 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 19 18 17 16 23 22 21 20 Receive High Byte Receive Middle Byte Receive Low Byte Host R[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-22 F reescale Semico nductor Figure D-7. Host Control a nd Status Register s Application: Date: Programmer: Sheet 2 of 6 HOST 76 5 4 3 2 1 0 15 * = Reserved, Program as 0 * 0 * 0 * 0 DSP Side Host Receive Data Full 1 = Read 0 = Wait HCP HRDF HF1 HTDE HF0 Host Flags R[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-23 Figure D-8. Host Base Ad dress and Host P or t Contr ol Application: Date: Programmer: Sheet 3 of 6 HOST (HDI08) 76 5 4 3 21 0 15 BA5 BA3 BA7 BA4 BA6 * 0 Host Base Address Register (HBAR) X:$FFFFC5 Reset = $80 8 BA8 BA9 BA10 * 0 1 5 1 4 1 [...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-24 F reescale Semico nductor Figure D-9. Host Interrupt Contr ol and Interrupt Status Application: Date: Programm er: Sheet 4 of 6 HOST (HDI08) 76 5 4 3 2 1 0 Processor Side RREQ HF1 TREQ HF0 INIT HLEND Transmit Request Enable DMA Off 0 = Interrupts Disabled 1 = Inte[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-25 Figure D-10. Host Inte rrupt V ector and Command V ector Application: Date: Programmer : Sheet 5 of 6 HOST (HDI08) 76 5 4 3 2 1 0 IV0 IV4 IV1 IV3 IV7 IV5 Interrupt Vector Register (IVR) IV2 Contains the interrupt vector or number IV6 76 5 [...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-26 F reescale Semico nductor Figure D-11. Host Re ceive and T ransmit Byte Register s Application: Date: Programmer: Sheet 6 of 6 HOST (HDI08) 70 7 0 0 7 Host Receive Data (HLEND = 1) Receive Byte Re gisters $7, $6, $5, $4 Read Only Reset = Empty Transmit By te Regis[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-27 Figure D-12. SHI Sla ve Address and Clock Contr ol Registers 10 Application: Date: Programme r: Sheet 1 of 3 SHI 15 14 13 12 1 1 9876543210 HDM4 HDM2 HDM1HDM0 HRS CPOL C PHA SHI Clock Control X:$FFFF90 Reset = $000 001 Register (HCKR) 19 1[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-28 F reescale Semico nductor Figure D-13. SHI T ransmit and Receive Data Register s Application: Date: Programmer: Sheet 2 of 3 SHI 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 SHI Host Transmit X:$FFFF93 Write Only Reset = $xxxxxx Data Register (HTX) 19 18 17 16 23 22 21 20 H[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-29 Figure D-14. SHI Host Control/Status Register HBUSY I 2 C SPI Mode 0 Stop event Not Busy 1 SHI detects Start SS detected (Slave) -OR- HTX/IOSR not empty (master) SHI * * = Reserved, write as 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HRQE0 HF[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-30 F reescale Semico nductor Figure D-15. ESAI T ransmit Clock Control Register Application: Date: Programmer : 15 6 5 4 19 18 17 16 10 9 8 7 14 13 12 11 TPM0 3210 TPM2 23 22 21 20 TPM1 TPM3 TPM4 TPM5 TPM6 TPM7 TPSR TDC0 TDC1 TDC2 TDC3 TDC4 TF P0 TFP1 TFP2 TFP3 TCKP [...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-31 Figure D-16. ESAI T ransmit Contr ol Register 15 6 5 4 19 18 17 16 10 9 8 7 14 13 12 11 TE0 3210 TE2 23 22 21 20 TE1 TE3 TE4 TE5 TSHFD TMOD0 TFSL TFSR TEI E TEDIE TIE TLIE TFSR Description 0 1 Word-length frame sync synchronous to beginnin[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-32 F reescale Semico nductor Figure D-17. ESAI Receive Cloc k Control Regist er 15 6 5 4 19 18 17 16 10 9 8 7 14 13 12 11 RPM0 3210 RPM2 23 22 21 20 RPM1 RPM3 RPM4 RPM5 RPM6 RPM7 RPSR RDC0 RDC1 RDC2 RDC3 RDC4 RFP0 RFP1 RFP2 RFP3 RCKP RFSP RHCKP RCKD RFSD RHCKD RCKP D[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-33 Figure D-18. ESAI Receive Contr o l Register 15 6 5 4 19 18 17 16 10 9 8 7 14 1 2 13 1 1 RE0 3210 RE2 23 22 21 20 RE1 RE3 Rsvd Rsvd RS HFD RWA RFSL RFSR REIE REDI E RIE RLIE RSWS [0:4] Description Defines slot and data word length ESAI RCR[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-34 F reescale Semico nductor Figure D-19. ESAI Common Contr ol Register 1 5 654 19 18 17 16 10 9 8 7 14 12 13 11 OF0 3210 OF2 23 22 21 20 OF1 SYN TEBE Description SYN ESAI SAICR - ESAI Common Control Register X: $FFFFB4 Rese t: $000000 ALC Description 0 1 Data left a[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-35 Figure D-20. ESAI Status Register 1 5 654 19 18 17 16 10 9 8 7 14 13 12 11 IF0 3210 IF2 23 22 21 20 IF1 RFS RDF Description Description 0 1 Holds data sent fr om SCKR pin. ESAI SAISR - ESAI Status Register X: $FFFFB3 Reset $000000 RFS Desc[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-36 F reescale Semico nductor Figure D-21. ESAI_1 Multiple x Control Regis ter 1 5 654 19 18 17 16 10 9 8 7 14 12 13 11 EMUX0 3210 EMUX2 23 22 21 20 EMUX1 Description EMUXR - ESAI_1 Mu ltiplex Control Register Y: $FFFFAF Rese t: $000000 Reserved Applicat ion: Date: Pr[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-37 Figure D-22. ESAI_1 T ransmit Clock Contr ol Register Application: Date: Programmer : 15 6 5 4 19 18 17 16 10 9 8 7 14 13 12 11 TPM0 3210 TPM2 23 22 21 20 TPM1 TPM3 TPM4 TPM5 TPM6 TPM7 TPSR TDC0 TDC1 TDC2 TDC3 TDC4 TF P0 TFP1 TFP2 TFP3 TCK[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-38 F reescale Semico nductor Figure D-23. ESAI_1 T ransmit Control Register 15 6 5 4 19 18 17 16 10 9 8 7 14 13 12 11 TE0 3210 TE2 23 22 21 20 TE1 TE3 TE4 TE5 TSHFD TMOD0 TFSL TFSR TEI E TEDIE TIE TLIE TFSR Description 0 1 Word-length frame sync synchronous to beginn[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-39 Figure D-24. ESAI_1 Receive Cloc k Contr ol Register 15 6 5 4 19 1 8 17 16 10 9 8 7 14 13 12 11 RPM0 3210 RPM2 23 22 21 20 RPM1 RPM3 RPM4 RPM5 RPM6 RPM7 RPSR RDC0 RDC1 RDC2 RDC3 RDC4 RFP0 RFP1 RFP2 RFP3 RCKP RFSP RHCKP RCKD RFSD RHCKD RCKP[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-40 F reescale Semico nductor Figure D-25. ESAI_1 Receive Contr ol Register 15 6 5 4 19 18 17 16 10 9 8 7 14 1 2 13 1 1 RE0 3210 RE2 23 22 21 20 RE1 RE3 Rsvd Rsvd RS HFD RWA RFSL RFSR REIE REDI E RIE RLIE RSWS [0:4] Description Defines slot and data word length RCR_1 [...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-41 Figure D-26. ESAI_1 Common Contr ol Register 1 5 654 19 18 17 16 10 9 8 7 14 12 13 11 OF0 3210 OF2 23 22 21 20 OF1 SYN TEBE Description SYN SAICR_1 - ESAI_1 Common Control Register Y: $FFFF94 Res et: $000000 ALC Description 0 1 Data left a[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-42 F reescale Semico nductor Figure D-27. ESAI_1 Status Register 1 5 654 19 18 17 16 10 9 8 7 14 13 12 11 IF0 3210 IF2 23 22 21 20 IF1 RFS RDF Description Description 0 1 Holds da ta sent from SCK R_1 pin . SAISR_1 - ESAI_1 Status Register Y: $FFFF93 Reset $000000 RF[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-43 Figure D-28. D AX Non-Audio Data Register DAX 15 14 13 12 1 1 1 0 9876543210 DAX Non-Audio Data X:$FFFFD1 Reset = $00XX 00 Register (XNADR) * 0 * 0 * 0 * 0 * 0 * 0 16 17 18 19 20 21 22 23 * 0 * 0 * 0 * 0 * 0 * 0 * 0 XCB XUB XVB XCA XUA XVA[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-44 F reescale Semico nductor Figure D-29. D AX Control and Status Re gisters XBLK DAX Block transfer 0 not last frame 1 191st frame transmission DAX 15 14 13 12 1 1 1 0 987654321 0 DAX Control X:$FFFFD0 Reset = $000000 Register (XCTR) * 0 * 0 * 0 * 0 * 0 * = Reserved[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-45 Figure D-30. Timer Prescaler Lo ad and Prescaler Count Register s (TPLR, TPCR) Application: D a t e: Programmer: Sheet 1 of 3 TEC 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 19 18 17 16 23 22 21 20 PS0 PS1 * 0 Prescaler Preload Value ( PL [0:20]) *[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-46 F reescale Semico nductor Figure D-31. Timer Contr ol/Status Register Note that for Timers 1 and 2, TC (3:0 ) = 0000 is the on ly valid combination. Application: Date: Programmer: Sheet 2 of 3 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 TC3 TC1 TC0 T CIE TOIE TE 19 18 17 1[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-47 Figure D-32. Timer Load, Compare and Count Register s Application: Date: Programmer: Sheet 3 of 3 TEC 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 19 18 17 16 23 22 21 20 Timer Reload Value Timer Load Register TLR0:$FFFF8E Write Only Reset = $XXXXXX[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-48 F reescale Semico nductor Figure D-33. GPIO P ort B Application: Date: Programmer: Sheet 1 of 4 GPIO 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 DR5 DR4 DR3 DR2 DR1 DR0 DR6 DR15 DR14 DR13 DR1 2 DR8 DR11 DR9 DR10 Direction Reg ister X:$FFFFC8 Reset = $0 (HDDR) Read/Write Ho[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-49 Figure D-34. GPIO P ort C Application: Date: Programmer: Sheet 2 of 4 GPIO 2 3 1 1 987654 PC9 PC8 PC7 PC6 PC5 PC4 Port C Control Register X:$FFFFBF Reset = $0 (PCRC) Read/Write * = Reserved, Progr am as 0 * 0 Port C (ESAI) 2 3 1 0 987654 P[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-50 F reescale Semico nductor Figure D-35. GPIO P ort D Application: Date: Programmer: Sheet 3 of 4 GPIO 2 3 6543210 PC1 PC0 Port D Control Register X:$FFFFD7 Reset = $0 (PCRD) Read/Write * 0 * = Reserved, Program as 0 * 0 Port D (DAX) Port D Direction Register X:$FFF[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-51 Figure D-36. GPIO P o rt E Application: Date: Programmer: Sheet 4 of 4 GPIO 2 3 1 1 987654 PC4 Port E Control Register Y:$FFFF9F Reset = $0 (PCRE) Read/Write * = Reserved, Progr am as 0 * 0 Port E (ESAI_1) 23 1 0 987654 PDC4 Port E Directi[...]

Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-52 F reescale Semico nductor NO TES[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor Index-1 Inde x Numerics 5 V tolerance 1 A adder modulo 5 offset 5 reverse-carry 5 address bus 1 Address Generation Unit 5 addressing modes 5 AES/EBU 10, 1 AGU 5 B barrel shifter 4 bus external address 5 external data 5 bus control 1 buses internal 6 C Central Processing Unit[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Index-2 Freescale Semiconductor triggered by timer 21 DO bit 10 DO loop 6 DRAM 8 DSP56300 core 2 DSP56300 Family Manual i, 2 DSP56303 Technical Data i E Enhanced Serial Audio Interface 15, 19 Enhanced Synchronous Audio Interface 1 ESAI 1, 15, 19 ESAI block diagram 1 ESSI0 (GPIO) 1, 2 ESSI1 (GPIO) 1[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor Index-3 Transmit Data In Master Mode 24 Transmit Data In Slave Mode 22 I 2 C Bus Acknowledgment 18 I 2 C Mode 1 IEC958 10, 1 Inter Integrated Circuit Bus 10, 1 internal buses 6 Internal Exception Priorities SHI 5 interrupt 6 interrupt and mode control 1, 7, 8 interrupt contr[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Index-4 Freescale Semiconductor R reserved bits in TCSR register bits 3, 10, 14, 16–19, 22, 23 11 in TPCR 6 in TPLR 6 RESET 8 reverse-carry adder 5 S SC register 6 Serial Host Interface 1, 12 Serial Host Interface (SHI) 10, 1 Serial Peripheral Interface Bus 10, 1 SHI 10, 1, 12, 1 Block Diagram 2 [...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor Index-5 TC0–TC3 bits 7 TCF 11 TCIE bit 7 TCPR 12 TCR 12 TCSR register 6 bit 0—Timer Enable bit (TE) 6 bit 2—Timer Compare In terrupt Enable bit (TCIE) 7 bits 4–7—Timer Control bits (TC0–TC3) 7 bit 13—Data Output bit (DO) 10 reserved bits—bits 3, 10, 14, 16–[...]

DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Index-6 Freescale Semiconductor[...]