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Fujitsu Intel Pentium Dual Core E2160 manuel d'utilisation

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Table des matières du manuel d’utilisation

  • Page 1

    Document Number: 316981 -005 Intel ® Pentium ® Dual-Core Desktop Processor E2000 Δ Series Datasheet March 2008[...]

  • Page 2

    2 Datasheet INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH IN TEL PRODUCTS . NO LICENSE, EXPRES S OR IMPLIED , BY EST OPPEL OR OTH ERW IS E , TO AN Y I NT EL LE CT UA L P RO PE RTY RI GH TS IS GR AN TE D B Y T H IS DOCUMENT . EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY [...]

  • Page 3

    Datasheet 3 Contents 1I n t r o d u c t i o n ......... ......... .......... ........... ........ ........... .......... ......... .......... ......... .......... .... 9 1.1 Terminology ........... .......... ......... .......... ........... .......... ........... ........ ........... .......... .. 9 1.1.1 Processor Terminology ........... ........[...]

  • Page 4

    4 Datasheet 5.2.2 Thermal Monito r 2 ................. .......... ........... ........ ........... .......... ........... .... 78 5.2.3 On-Demand M ode ..... ......... .......... ........... .......... ......... .......... ........... ........79 5.2.4 PROCHOT# Sig nal ............. .......... ........... .......... ......... .......... ........... [...]

  • Page 5

    Datasheet 5 Figures 1V CC Static and Transient Tolerance for Processors..... .... ........ ........... .......... ......... .......... 21 2V CC Overshoot Examp le Waveform .............. ........... .......... ........... .......... ........... .......... 22 3 Differential Clock Waveform .......... ........... .......... ........... ........... ...[...]

  • Page 6

    6 Datasheet Tables 1 References ............... ......... .......... ........... ........ ........... .......... ......... .......... ........... ......11 2 Voltage Identification Definition .... ........... .......... ......... .......... ........... ........ ........... ........15 3 Market Segment Selection Truth Table for MSID[1: 0], , , .......[...]

  • Page 7

    Datasheet 7 Intel ® Pentium ® Dual-Core Desktop Processor E2000 Δ Series The Intel Pentium ® Dual-Core desktop processor E2000 serie s deliver Intel's advanced, powerful processors for desktop PCs. The processor is design ed to deliver performance across applications and usages where end-users can truly appreciate and experience the perfor[...]

  • Page 8

    8 Datasheet Revision History § § Revision Number Description Date -001 • Initial release June 2007 -002 • Added specifications for Intel ® Pen tiu m ® Dual-Core Desktop processor E2180 August 2007 -003 • Added specifications for Intel ® Pen tiu m ® Dual-Core Desktop processor E2160 and E2140 for a second thermal profile (See T able 26) [...]

  • Page 9

    Datasheet 9 Introduction 1 Introduction The Intel ® Pen t i um ® Dual-Core Desktop processor E2000 series combines the performance of the current gener ation of de sktop products with the power efficiencies of a low-power microarchitecture to enable smaller , quieter systems. These dual-core processors are based on 65 nm process technology . They[...]

  • Page 10

    Introduction 10 Datasheet 1.1.1 Processor Terminology Commonly used terms are expl ained here for clarification: • Intel ® Pentium ® Dual-Core Desktop pr ocessor E2000 series — Dual core processor in the FC -LGA6 package with a 1 MB L2 cache. • Processor — F or this document, the term processor is the generic form of the Intel ® Pen t i [...]

  • Page 11

    Datasheet 11 Introduction 1.2 References Material and concepts available in the fo llowing documents may be beneficial when reading this document. § § Table 1. References Document Location Intel ® Pentium ® Dual-Core Desktop Proce ssor E2000 Series Specification Update http://www.intel.com// design/processor/ specupdt/31698 2.htm Intel ® Core?[...]

  • Page 12

    Introduction 12 Datasheet[...]

  • Page 13

    Datasheet 13 Electrical Specifications 2 Electrical Specifications This chapter describes the electrical charac teristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VT T and VSS (ground) inputs for on-chip power distribution. All power lands must be [...]

  • Page 14

    Electrical Specifications 14 Datasheet 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, so me of the high frequency capacitance required for the FSB is included on the processor package. However , additional high frequency capacita nce must be added to the motherboard to properly decouple the return currents[...]

  • Page 15

    Datasheet 15 Electrical Specifications Table 2. Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 V CC_MAX VID6 VID5 VID4 VID3 VID2 VI D1 V CC_MAX 1 1 11 01 0 . 8 5 0 0 0 11110 1 . 2 3 7 5 1 1 11 00 0 . 8 6 2 5 0 11101 1 . 2 5 0 0 1 1 10 11 0 . 8 7 5 0 0 11100 1 . 2 6 2 5 1 1 10 10 0 . 8 8 7 5 0 11011 1 . 2 7 5 0 1 1 10 01 0 . 9 0 0 0[...]

  • Page 16

    Electrical Specifications 16 Datasheet 2.4 Market Segment Identification (MSID) The MSID[1:0] signals may be used as outp uts to determine the Market Segmen t of the processor . Ta b l e 3 provides details regarding the state of MSID[1:0]. A circuit can be used to preven t 130 W TDP processors from booting on boards optimized for 65 W TDP . 2.5 Res[...]

  • Page 17

    Datasheet 17 Electrical Specifications The TESTHI signals ma y use individual pull-u p resistors or be grouped together as detailed below. A matched resistor must be used for each group: • TESTHI[1:0] • TESTHI[7:2] • TESTHI8/FC42 – cannot be grouped with o ther TESTHI signals • TESTHI9/FC43 – cannot be grouped with o ther TESTHI signals[...]

  • Page 18

    Electrical Specifications 18 Datasheet NOTES: 1. For functional oper ation, all processor electrical, signal qu ality , mechanical and thermal specificati ons must be sat isfied. 2. Excessive overshoot or un dersh oot on any signal wi ll likely result in permanent damage to the processor . 3. Storage temper ature is applicable to stor age co nditio[...]

  • Page 19

    Datasheet 19 Electrical Specifications 2.6.2 DC Voltage and Cu rrent Sp ecification Table 5. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 1, 2 NOTES: 1. Unless oth erwise note d, all specific ations in thi s table are based on estimates and si mulations or empirical data. These specifications will be updated with chara[...]

  • Page 20

    Electrical Specifications 20 Datasheet Table 6. V CC Static and Transient Tolerance for Pr ocessors I CC (A) Voltage Deviation from VID Setting (V) 1, 2, 3, 4 NOTES: 1. The loadline specification incl udes both static and tr ansient limits exc ept for overshoot allowe d as shown in Section 2.6.3 . 2. This table is in tended to aid in reading discre[...]

  • Page 21

    Datasheet 21 Electrical Specifications NOTES: 1. The loadline specification includes bot h static and transient li mits except for overshoo t allowed as shown in Section 2.6 .3 . 2. This loadlin e specificati on shows the de viation from th e VID set point. 3. The loadlines s pecify vo ltage limits at the die measur ed at the VCC_SENSE an d VSS_SEN[...]

  • Page 22

    Electrical Specifications 22 Datasheet NOTES: 1. V OS is measured overshoot voltage. 2. T OS is measured time dur ation above VID. 2.6.4 Die Voltage Validation Overshoot events on processor mu st meet the specifications in Ta b l e 7 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be igno[...]

  • Page 23

    Datasheet 23 Electrical Specifications 2.7.1 FSB Signal Groups The front side bus sign als have be en combined into groups b y buffer type. GTL+ input signals have differential input buffers, whic h use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input gr oup as well as the GTL+ I/O group when re[...]

  • Page 24

    Electrical Specifications 24 Datasheet 3. The value of these signals during the acti ve-to- inactive e dge of RESET# defines the processor configuratio n options. See Section 6.1 for details. 4. PROCHOT# signal type is open dr ain output and CMOS input. . . 2.7.2 CMOS and Open Drain Signals Legacy input signals such as A20M#, IG NNE#, INIT#, SMI#, [...]

  • Page 25

    Datasheet 25 Electrical Specifications 2.7.3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. . Table 11. G TL+ Signal Group DC Specifications Symbol Parameter Min Max Unit[...]

  • Page 26

    Electrical Specifications 26 Datasheet . 2.7.3.1 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integr ated into the processor silicon. See Ta b l e 9 for details on which GTL+ signals do not include on-die termination. V alid high and low levels are determined by the input buffers by comparing[...]

  • Page 27

    Datasheet 27 Electrical Specifications Table 14. G TL+ Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes 1 NOTES: 1. Unless otherwise not ed, all specifications in this table apply to all proce ssor frequencies. GTLREF_PU GTLREF pull up resistor on Intel 975X and 96x Ex press Chipset family boards 124 * 0.99 124 124 * 1.01 Ω 2 2. GT[...]

  • Page 28

    Electrical Specifications 28 Datasheet 2.8 Clock Specifications 2.8.1 Front Side Bus Clock (BCL K[1:0]) and Processor Clocking BCLK[1:0] directly controls the FS B interface speed as well as the core frequency of the processor . As in previous generation processors, the processor’ s core frequency is a multiple of the BCLK[1:0] frequency . The pr[...]

  • Page 29

    Datasheet 29 Electrical Specifications 2.8.3 Phase Lock Loop (PLL) and Filter An on-die PLL filter solution will be implemented on the processor . The VCCPLL input is used for the PLL. R efer to Ta b l e 5 for DC speci fications. 2.8.4 BCLK[1:0] Specifications (CK505 based Platforms) Table 16. BSEL[2:0] Fre quency Table fo r BCLK[1:0] BSEL2 BSEL1 B[...]

  • Page 30

    Electrical Specifications 30 Datasheet Figure 3. D ifferential Clock Waveform Figure 4. D ifferential Clock Crosspoint Specification High Time Period V CROSS CLK 1 CLK 0 Low Time V CROSS Min 300 mV V CROSS Max 550 mV median V CROSS median V CROSS Median + 75 mV Median - 75 mV V CROSS 660 670 680 690 700 71 0 720 730 740 750 7 60 770 780 790 800 810[...]

  • Page 31

    Datasheet 31 Electrical Specifications 2.8.5 BCLK[1:0] Specifications (CK410 based Platforms) Table 18. Front Side Bus Differential BCLK Specifica tions Symbol Parameter Min Typ Max Unit Figure Notes 1 NOTES: 1. Unless otherwise no ted, all specifi cations in this table apply to al l processor frequencies. V L Input Low V oltage -0.150 0.00 0 N/A V[...]

  • Page 32

    Electrical Specifications 32 Datasheet 2.9 PECI DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication ch annel between Intel processors (may also include chipset components in the futu re) and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DT S) distributed throughout d[...]

  • Page 33

    Datasheet 33 Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-L GA6) package that interfaces with the motherboar d via an LG A775 sock et. The package consists of a processor core mounted on a substrate land-carrier . An integrated heat spreader (IHS) is attached to t[...]

  • Page 34

    Package Mechanical Specifications 34 Datasheet Figure 8. Processor Package Drawing Sheet 1 of 3[...]

  • Page 35

    Datasheet 35 Package Mechanical Specifications Figure 9. Processor Package Drawing Sheet 2 of 3[...]

  • Page 36

    Package Mechanical Specifications 36 Datasheet Figure 10. Processor Package Drawing Sheet 3 of 3[...]

  • Page 37

    Datasheet 37 Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep- out zone requirements. A thermal and mechanical solution design must n ot intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside [...]

  • Page 38

    Package Mechanical Specifications 38 Datasheet 3.5 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide . 3.6 Processor Mass Specificat ion The typical mass of the processor is 2 1.5 g [0.76 [...]

  • Page 39

    Datasheet 39 Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 12 shows the top view of the processor land coordinates. The coordinates are referred to throughout the docume nt to identify processor lands. . § § Figure 12. Processor La nd Coordinates and Quadrants, Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 [...]

  • Page 40

    Package Mechanical Specifications 40 Datasheet[...]

  • Page 41

    Datasheet 41 Land Listi ng and Sign al Description s 4 Land Listing and Signal Descriptions This chapter provides the processor la nd assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for th e processor . The land-out footprint is shown in Figure 13 and Figure 14 . These figures represent the[...]

  • Page 42

    Land Listing and Signal Descriptions 42 Datasheet Figure 13. land-out Diagram (Top View – Lef t Side) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN VCC VCC VSS VSS VCC VC C VSS VSS VCC VCC VSS VCC VCC VSS VS S VCC AM VCC VCC VSS VSS VCC VC C VSS VSS VCC VCC VSS VCC VCC VSS VS S VCC AL VCC VCC VSS VSS VCC VC C VSS VSS VCC VCC VSS VCC VCC VSS [...]

  • Page 43

    Datasheet 43 Land Listi ng and Sign al Description s Figure 14. land-out Diagram (Top View – Right Side) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VCC VSS VCC VCC VS S VCC VCC VID_SELE CT VSS_MB_ REGULA TION VCC_MB_ REGULA TION VSS_ SENSE VCC_ SENSE VSS VSS AN VCC VSS VCC VCC VS S VCC VCC VID7 FC40 VID6 VSS VID2 VID0 VSS AM VCC VSS VCC VCC VS S VCC VCC VS[...]

  • Page 44

    Land Listing and Signal Descriptions 44 Datasheet Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type Direction A3# L5 S ource Synch Input/Output A4# P6 Source Synch Input/Output A5# M5 Source Synch Input/Output A6# L4 S ource Synch Input/Output A7# M4 Source Synch Input/Output A8# R4 Source Synch Input/Output A9# T5 Source [...]

  • Page 45

    Land Listi ng and Sign al Description s Datasheet 45 D22# D10 Source Synch Input/Output D23# F11 Source Sync h Input/Output D24# F12 Source Sync h Input/Output D25# D13 Source Synch Input/Output D26# E13 Source Synch Input/Output D27# G13 Source Sync h Input/Output D28# F14 Source Sync h Input/Output D29# G14 Source Sync h Input/Output D30# F15 Sou[...]

  • Page 46

    Land Listing and Signal Descriptions 46 Datasheet FC33 H16 Power/Other FC34 J17 P ower/Other FC35 H4 P ower/Other FC36 AD3 Power/Other FC37 AB3 Power/Other FC38 G10 Power/Other FC38 C9 Power/Ot her FC39 AA2 Power/Other FC40 AM6 Power/Other FERR#/PBE# R3 Asynch CMOS Output GTLREF0 H1 Power/Other Input GTLREF1 H2 Power/Other Input HIT# D4 Common Cloc[...]

  • Page 47

    Land Listi ng and Sign al Description s Datasheet 47 TRDY# E3 Com mon Cloc k Inp ut TRST# AG1 T AP Input VCC AA8 Power/Oth er VCC AB8 Power/O ther VCC AC23 Power/Other VCC AC24 Power/Other VCC AC25 Power/Other VCC AC26 Power/Other VCC AC27 Power/Other VCC AC28 Power/Other VCC AC29 Power/Other VCC AC30 Power/Other VCC AC8 Power/Other VCC AD23 Power/[...]

  • Page 48

    Land Listing and Signal Descriptions 48 Datasheet VCC AJ18 Power/Other VCC AJ19 Power/Other VCC AJ21 Power/Other VCC AJ22 Power/Other VCC AJ25 Power/Other VCC AJ26 Power/Other VCC AJ8 Power/Other VCC AJ9 Power/Other VCC AK11 Power/Other VCC AK12 Power/Other VCC AK14 Power/Other VCC AK15 Power/Other VCC AK18 Power/Other VCC AK19 Power/Other VCC AK21[...]

  • Page 49

    Land Listi ng and Sign al Description s Datasheet 49 VCC J28 Power/Othe r VCC J29 Power/Othe r VCC J30 Power/Othe r VCC J8 Power/Other VCC J9 Power/Other VCC K23 Power/Othe r VCC K24 Power/Othe r VCC K25 Power/Othe r VCC K26 Power/Othe r VCC K27 Power/Othe r VCC K28 Power/Othe r VCC K29 Power/Othe r VCC K30 Power/Othe r VCC K8 Power/Other VCC L8 Po[...]

  • Page 50

    Land Listing and Signal Descriptions 50 Datasheet VID0 AM2 Power/Other Output VID1 AL5 Power/O ther Output VID2 AM3 Power/Other Output VID3 AL6 Power/O ther Output VID4 AK4 Power/O ther Output VID5 AL4 Power/O ther Output VID6 AM5 Power/Other Output VID7 AM7 Power/Other Output VRDSEL AL3 Pow er/Other VSS A12 P ower/Other VSS A15 P ower/Other VSS A1[...]

  • Page 51

    Land Listi ng and Sign al Description s Datasheet 51 VSS AG2 3 Power/Other VSS AG2 4 Power/Other VSS AG7 Powe r/Other VSS AH1 Power/Other VSS AH10 Power/Other VSS AH13 Power/Other VSS AH16 Power/Other VSS AH17 Power/Other VSS AH20 Power/Other VSS AH23 Power/Other VSS AH24 Power/Other VSS AH3 Power/Other VSS AH6 Power/Other VSS AH7 Power/Other VSS A[...]

  • Page 52

    Land Listing and Signal Descriptions 52 Datasheet VSS B24 Power/Other VSS B5 Powe r/Other VSS B8 Powe r/Other VSS C10 Power/Ot her VSS C13 Power/Ot her VSS C16 Power/Ot her VSS C19 Power/Ot her VSS C22 Power/Ot her VSS C24 Power/Ot her VSS C4 P ower/Other VSS C7 P ower/Other VSS D12 Power/Other VSS D15 Power/Other VSS D18 Power/Other VSS D21 Power/[...]

  • Page 53

    Land Listi ng and Sign al Description s Datasheet 53 VSS N6 Power/Oth er VSS N7 Power/Oth er VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other VSS P26 Power/Other VSS P27 Power/Other VSS P28 Power/Other VSS P29 Power/Other VSS P30 Power/Other VSS P4 Power/Other VSS P7 Power/Other VSS R2 P ower/Other VSS R23 Power/Other VSS R24 Power/Other[...]

  • Page 54

    Land Listing and Signal Descriptions 54 Datasheet Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction A2 V SS Power/Other A3 RS2# Common Clo ck Input A4 D02# Source Synch Input/Output A5 D04# Source Synch Input/Output A6 V SS Power/Other A7 D07# Source Synch Input/Output A8 DBI0# Source Synch Input/Output A9 V SS Power[...]

  • Page 55

    Land Listi ng and Sign al Description s Datasheet 55 C20 D BI3# Source Synch Input/Output C21 D58# Source Synch Input/Output C22 VSS Power/Ot her C23 VCCIOPLL Power/Other C24 VSS Power/Ot her C25 VTT Power/ Other C26 VTT Power/ Other C27 VTT Power/ Other C28 VTT Power/ Other C29 VTT Power/ Other C30 VTT Power/ Other D1 RESERVED D2 ADS# Commo n Cloc[...]

  • Page 56

    Land Listing and Signal Descriptions 56 Datasheet F11 D23# Source Synch Input/Output F12 D24# Source Synch Input/Output F13 VSS Power/Other F14 D28# Source Synch Input/Output F15 D30# Source Synch Input/Output F16 VSS Power/Other F17 D37# Source Synch Input/Output F18 D38# Source Synch Input/Output F19 VSS Power/Other F20 D41# Source Synch Input/Ou[...]

  • Page 57

    Land Listi ng and Sign al Description s Datasheet 57 H30 BSEL1 Power/Other Output J1 VT T_OUT_LEF T Power/Other Output J2 FC3 Power/Other J3 FC22 Power/Other J4 VSS Power/Other J5 REQ1# Source Synch Input/Output J6 REQ4# Source Synch Input/Output J7 VSS Power/Other J8 VCC Power/Other J9 VCC Power/Other J10 VCC Power/Other J11 VCC Power/Other J12 VC[...]

  • Page 58

    Land Listing and Signal Descriptions 58 Datasheet M30 VCC Power/O ther N1 PWRGO OD Power/Other Input N2 IGNNE# Asynch CMOS Input N3 VSS Power/Other N4 RESERVED N5 RESERVED N6 VSS Power/Other N7 VSS Power/Other N8 V CC Power/Other N23 VCC Power/Other N24 VCC Power/Other N25 VCC Power/Other N26 VCC Power/Other N27 VCC Power/Other N28 VCC Power/Other [...]

  • Page 59

    Land Listi ng and Sign al Description s Datasheet 59 U28 VCC P ower/Other U29 VCC P ower/Other U30 VCC P ower/Other V1 MSID1 Power/Other Output V2 RESERVED V3 VSS Power/ Other V4 A15# Source Synch Input/Output V5 A14# Source Synch Input/Output V6 VSS Power/ Other V7 VSS Power/ Other V8 VCC Power/Other V23 VSS Power/Other V24 VSS Power/Other V25 VSS[...]

  • Page 60

    Land Listing and Signal Descriptions 60 Datasheet AB26 VSS Power/Other AB27 VSS Power/Other AB28 VSS Power/Other AB29 VSS Power/Other AB30 VSS Power/Other AC1 TMS T AP Input AC2 DBR# Power/Other Output AC3 VSS Power/Other AC4 RESERVED AC5 A25# Source Synch Input/Output AC6 VSS Power/Other AC7 VSS Power/Other AC8 VCC Powe r/Other AC23 VCC Power/Othe[...]

  • Page 61

    Land Listi ng and Sign al Description s Datasheet 61 AF12 VC C Power/Other AF13 VSS Power/Ot her AF14 VC C Power/Other AF15 VC C Power/Other AF16 VSS Power/Ot her AF17 VSS Power/Ot her AF18 VC C Power/Other AF19 VC C Power/Other AF20 VSS Power/Ot her AF21 VC C Power/Other AF22 VC C Power/Other AF23 VSS Power/Ot her AF24 VSS Power/Ot her AF25 VSS Po[...]

  • Page 62

    Land Listing and Signal Descriptions 62 Datasheet AH30 VCC Power/Other AJ1 BPM1# Common Clock Input/Output AJ2 BPM0# Common Clock Input/Output AJ3 ITP_CLK1 T AP Input AJ4 VSS Power/Ot her AJ5 A34# Source Synch Input/Output AJ6 A35# Source Synch Input/Output AJ7 VSS Power/Ot her AJ8 VCC Power/O ther AJ9 VCC Power/O ther AJ10 VSS Power/Other AJ11 VCC[...]

  • Page 63

    Land Listi ng and Sign al Description s Datasheet 63 AL18 VCC Power/Other AL19 VCC Power/Other AL20 VSS Power/Other AL21 VCC Power/Other AL22 VCC Power/Other AL23 VSS Power/Other AL24 VSS Power/Other AL25 VCC Power/Other AL26 VCC Power/Other AL27 VSS Power/Other AL28 VSS Power/Other AL29 VCC Power/Other AL30 VCC Power/Other AM1 VSS Power/Other AM2 [...]

  • Page 64

    Land Listing and Signal Descriptions 64 Datasheet 4.2 Alphabetical Signals Reference Table 25. Signal Descript ion (Sheet 1 of 9) Name Type Description A[35:3]# Input/ Output A[35:3]# (Address) define a 2 36 -byte physical memory address space. In sub-phase 1 of the addr ess phas e, these si gnals tran smit the address of a transaction. In sub-phas[...]

  • Page 65

    Land Listi ng and Sign al Description s Datasheet 65 BPM[5:0]# Input/ Output BPM[5:0]# (Breakpoint Moni tor) are breakpoint and performance monitor signal s. They are outpu ts from the processor whi ch indicate the status of breakpoints and progr ammable counters used for monitoring processor performance . BPM[5:0]# sh ould connect th e appropriate[...]

  • Page 66

    Land Listing and Signal Descriptions 66 Datasheet D[63:0]# Input/ Output D[63:0]# (Data) are the data signal s. These signal s provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer . D[63:0]# are quad-pumpe d signal[...]

  • Page 67

    Land Listi ng and Sign al Description s Datasheet 67 DEFER# Input DEFER# is asserted by an agent to indicate that a tr ansact ion cannot be ensured in-order completion. As sertion of DEFER# is normall y the responsibil ity of the addresse d me mory or input/output ag ent. This signal must connec t the approp riate pins/lands of all processor FSB ag[...]

  • Page 68

    Land Listing and Signal Descriptions 68 Datasheet HIT# HITM# Input/ Output Input/ Output HIT# (Snoop Hit) and HITM# (Hit Modif ied) conve y transact ion snoop operation results. Any FSB agen t may assert both HIT# and HITM# together to indicat e that it requires a snoop stall, which can be continued by reassertin g HIT# and HITM# together . IERR# O[...]

  • Page 69

    Land Listi ng and Sign al Description s Datasheet 69 LOC K# Input/ Output LOCK# indicates to the sy stem that a transaction mu st occur atomically . This signal must connect th e appropri ate pins/lands of all processor FSB agents . For a locked sequence of transactions, LOCK# is asserted from the be ginning of the f irst tran saction to the end o [...]

  • Page 70

    Land Listing and Signal Descriptions 70 Datasheet RS[2:0]# Input RS[2:0]# (Response Status ) are driven by the response agen t (the agent responsible for comple tion of the current transaction), and must connect the appropriate pins/l ands of all proc essor FSB agents. SKTOCC# Output SKTOCC# (Socket O ccupied) will be pulled to ground by the proces[...]

  • Page 71

    Datasheet 71 Land Listi ng and Sign al Description s THERMTRIP# Output In the event of a catastrophic c ooling failure, the processor will automatically s hut down when the sili con has reached a tempe rature approximately 20 °C above the m aximum T C . Assertion of THERMTRI P# (Thermal T rip) indi cates the processor jun ction temperature has rea[...]

  • Page 72

    Land Listing and Signal Descriptions 72 Datasheet § § VRDSEL Input This input should be left as a no connect in order for the processor to boot. The processor will no t boot on legacy platforms where this land is connec ted to V SS . VSS Inp ut VSS are the ground pins for the pr ocessor and should be connected to the system ground plane. VSSA Inp[...]

  • Page 73

    Datasheet 73 Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temper atures within the operating limits as described in Section 5 .1.1 . Any attem pt to operate the processor outside these operating limits ma[...]

  • Page 74

    Thermal Specifications and Design Considerations 74 Datasheet The case temperature is defined at the geometric top center of the processor . Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the[...]

  • Page 75

    Datasheet 75 Thermal Specifications and Design Considerations Table 27. Thermal Profile (Intel ® Pentium ® Dual-Core Processors with CPUID = 06F2h) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 43.2 24 49.9 48 56.6 2 43.8 26 50.5 50 57.2 4 44.3 28 51.0 52 57.8 6 44.9 30 51.6 54 58.3 8 45.4 32 52.2 56 58.9 10 4[...]

  • Page 76

    Thermal Specifications and Design Considerations 76 Datasheet Table 28. Thermal Profi le (Intel ® Pentium ® Dual-Core Processors with CPUID = 06FDh ) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 45.3 2 4 55.6 48 65.9 2 46.2 2 6 56.5 50 66.8 4 47.0 2 8 57.3 52 67.7 6 47.9 3 0 58.2 54 68.5 8 48.7 3 2 59.1 56 69[...]

  • Page 77

    Datasheet 77 Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temper atures (T C ) for the processor is specified in Ta b l e 2 6 . This temperature specification is meant to help ensure proper operation of the processor . Figure 17 illustr ates where Intel recommends T C thermal measurements sho[...]

  • Page 78

    Thermal Specifications and Design Considerations 78 Datasheet under-designed thermal solution that is not ab le to prev ent excessive activ ation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a T C that exceeds the specified maximum temperature and may affect the long-term[...]

  • Page 79

    Datasheet 79 Thermal Specifications and Design Considerations The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Therma l Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 T CC cannot be activated via the on demand mode. The Thermal Monitor TCC, howev er , can be[...]

  • Page 80

    Thermal Specifications and Design Considerations 80 Datasheet 5.2.4 PROCHOT# Signal An external signal, PROCHO T# (processor hot), is asserted when the processor core temperature has reached its maximum oper ating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for th e processor to be operating within [...]

  • Page 81

    Datasheet 81 Thermal Specifications and Design Considerations 5.3 Thermal Diode The processor incorporates an on-die PNP transistor where the base emitter junction is used as a thermal "diode", with its colle ctor shorted to grou nd. A thermal sensor located on the system board may monitor the die temperature of th e processor for thermal[...]

  • Page 82

    Thermal Specifications and Design Considerations 82 Datasheet NOTES: 1. Intel does not support or re commend operation of the thermal diode under revers e bias. 2. Same as I FW in Ta b l e 2 9 . 3. Preliminar y data. Will be char acterized ac ross a temper ature ra nge of 50–80 °C. 4. Not 100% tested. Spe cified by design char acterization. 5. T[...]

  • Page 83

    Datasheet 83 Thermal Specifications and Design Considerations 5.4 Platform Environment Control Interface (PECI) 5.4.1 Introduction PECI offers an interface for thermal m o nitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. Figure 19 shows an example of the PECI topology in a system[...]

  • Page 84

    Thermal Specifications and Design Considerations 84 Datasheet . . Figure 20. C onceptual Fan Cont rol on PECI-Based Platforms Mi n Max Fan Sp eed (R PM ) T CONTROL Set t i ng TCC Ac t i v at i on Tem perat ur e PECI = 0 PECI = -10 PECI = -20 Tem perat ur e N ot e: N ot inte nd e d to de pic t a ctu al im p lem en tat ion Figure 21. Conce ptual Fan [...]

  • Page 85

    Datasheet 85 Thermal Specifications and Design Considerations 5.4.2 PECI Specifications 5.4.2.1 PECI Device Address The PECI device address for the socket is 30h. For more information on PECI domains, refer to the Platform Environment Control Interface Specification . 5.4.2.2 PECI Command Support PECI command support is cov ered in detail in the Pl[...]

  • Page 86

    Thermal Specifications and Design Considerations 86 Datasheet[...]

  • Page 87

    Datasheet 87 Features 6 Features 6.1 Power-On Configuration Options Several configur ation options can be config ured by hardw are. The processor samples the hardware configur ation at reset, on the active-to-inactiv e transition of RESET#. For specifications on these options, refer to Ta b l e 3 3 . The sampled information configures the processor[...]

  • Page 88

    Feature s 88 Datasheet 6.2 Clock Control and Low Power States The processor allows the use of AutoHAL T and Stop-Grant states to reduce power consumption by stopping the clock to internal sections of th e processor , depending on each particular state. See Fig ure 2 2 for a visual represen tation of the processor low power states. 6.2.1 Normal Stat[...]

  • Page 89

    Datasheet 89 Features 6.2.2.1 HALT Powerdown Stat e HAL T is a low power state entered when all the process or cores have executed the HAL T or MWAIT instructions. When one of the processor cores executes the HAL T instruction, that processor core is halted, however , the other processor continues normal operation. The processor will transition to [...]

  • Page 90

    Feature s 90 Datasheet 6.2.3.1 Stop-Grant State When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor -issued Stop Grant Acknowledge special bus cycle. Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing the level to r[...]

  • Page 91

    Datasheet 91 Features 6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State The processor will remain in the lower bus ratio and VID oper ating point of the Extended HAL T state or Extended Stop Grant state. While in th e Extended HAL T Snoop State or Extended Stop Grant Snoop State, snoops are handled the same way as in the HAL T Snoo[...]

  • Page 92

    Feature s 92 Datasheet[...]

  • Page 93

    Datasheet 93 Boxed Processor Specifications 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor . Intel boxed processors are intended for system integr ators who build systems from baseboards and standard components. The box ed processor will be supplied with a cooling solution. This chapter documents bas[...]

  • Page 94

    Boxed Processor Specifications 94 Datasheet 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical spec ifications of the boxed processor . The boxed processor will be shipped with an unattached fan heatsink. Figure 23 shows a mechanical representation of the box ed processor . Clear an[...]

  • Page 95

    Datasheet 95 Boxed Processor Specifications NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 25. Space Requir ements for the Boxed P rocessor (Top View) Figure 26. Space Requirements for the Boxed Pr ocessor (Overall View) Bo x e d Proc Ov era ll View[...]

  • Page 96

    Boxed Processor Specifications 96 Datasheet 7.1.2 Boxed Processor Fan Heatsink Weight The boxed pro cessor fan heatsink will not weigh more than 550 grams. See Chapter 5 and the appropriate Thermal and Mech anical Design Guidelines (see Section 1.2 ) for details on the processor weight and heatsink requirements. 7.1.3 Boxed Processor Retention Mech[...]

  • Page 97

    Datasheet 97 Boxed Processor Specifications Figure 27. Boxed Processo r Fan Heatsink Power Cable Conn ector Description Table 34. Fan Heatsink Powe r and Signal Specifications Description Min Typ Max Unit Notes +12 V : 12 v olt fan power supply 11.4 12 12.6 V - IC: - Maximum fan steady-state current dr aw - Aver age fan steady-state current draw - [...]

  • Page 98

    Boxed Processor Specifications 98 Datasheet 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor . 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cool ed with a fan heatsink. However , meeting the processor's temperature specification[...]

  • Page 99

    Datasheet 99 Boxed Processor Specifications Figure 29. Boxed Processor Fa n Heatsink Airspace Keepo ut Requirements (side 1 view) Figure 30. Boxed Processor Fan He atsink Airspace Keepout Requir ements (Side 2 V iew)[...]

  • Page 100

    Boxed Processor Specifications 100 Datasheet 7.3.2 Fan Speed Control Operation (Intel ® Pentium ® Dual-Core Desktop Processor E2000 Series) If the boxed processor f an heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will oper ate at different speeds over a short range of inte[...]

  • Page 101

    Datasheet 101 Boxed Processor Specifications If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designe d with a fan speed controller with PWM output (CONTROL see Ta b l e 3 4 ) and remote thermal diode measu rement capability the boxed processor will oper ate as follows: As process[...]

  • Page 102

    Boxed Processor Specifications 102 Datasheet[...]

  • Page 103

    Datasheet 103 Debug Tools Specifications 8 Debug Tools Specifications 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer ve ndors to provide logic analyzer interfaces (LAIs) for use in debugging systems. T ektronix and Agilent should be contacte d to get specific information about their logic analyzer interfaces. The follow[...]

  • Page 104

    Debug Tools Specifications 104 Datasheet[...]