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HP X5670 manuel d'utilisation

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Table des matières du manuel d’utilisation

  • Page 1

    Reference Number:323372-001 Intel® Xeon® Processor 5600 Series Specification Update March 2010[...]

  • Page 2

    2 Intel® Xeon® Processor 5600 Series Specification Update, March 2010 Legal Lines and Disclaime rs INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNE CTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRE SS OR IMPLIED, BY ESTOPPEL OR O THERWISE, TO ANY INTELLECTUAL PROPER TY RIGHTS IS GRANTED BY THIS DOCUMENT . EXCEPT AS PROVIDED IN INTEL 'S TERMS [...]

  • Page 3

    Intel® Xeon® Processor 5600 Series 3 Specification Update, March 2010 Contents Revision History ................ ............ ................. ............. ................ ............. ................ ........ 5 Preface .............. ............. ................ ............. ................. ............ ................. ............ .[...]

  • Page 4

    Intel® Xeon® Processor 5600 Series 4 Specification Update, March 2010[...]

  • Page 5

    Intel® Xeon® Processor 5600 Series 5 Specification Update, March 2010 Revision History Doc ID Revision Description Date 323372 -001 • Initial R elease March 2010[...]

  • Page 6

    Intel® Xeon® Processor 5600 Series 6 Specification Update, March 2010 Preface This document is an update to th e specifications contained in the Affected Documents able below . This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware systemmanufacturers and software d[...]

  • Page 7

    Intel® Xeon® Processor 5600 Series 7 Specification Update, March 2010 Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics, e.g. , core speed, L2 cache size, package type, etc. as described in the processor iden tification information ta ble. Read all notes associat[...]

  • Page 8

    Intel® Xeon® Processor 5600 Series 8 Specification Update, March 2010 Identification Information Component Identification The Intel® X eon® Processor 5600 Series stepping can be ide ntified by the following register contents. Notes: 1. The Extended Fami ly, bits [27:20] are used in conjunction with the Family Code, specific in bit s [11:8], to [...]

  • Page 9

    Intel® Xeon® Processor 5600 Series 9 Specification Update, March 2010 Component Marking The Intel® X eon® Processor 5600 Series can be identified by the following component markings: Figure 1. Processor Top-si de Markings (Examp le) Table 2. Intel® Xeon® Processor 5600 Series Identification (Sheet 1 of 2) S-Spec Number Steppin g CPUID 1 Core [...]

  • Page 10

    Intel® Xeon® Processor 5600 Series 10 Specification Update, March 2010 Notes: 1. CPUID is 0000206Csh, where ‘s’ is the stepping number . 2. This is an Intel® Xe on Processor X5680. 3. This is an Intel® Xe on Processor X5677. 4. This is an Intel® Xe on Processor X5670. 5. This is an Intel® Xe on Processor X5660. 6. This is an Intel® Xe on[...]

  • Page 11

    Intel® Xeon® Processor 5600 Series 11 Specification Update, March 2010 Summary Table of Changes The table included in this section indi cate the err ata, Specification Changes, Specification Clarifications, or Document Changes which apply to the Intel® X eon® Processor 5600 Series. Intel may fix some of the errata in a future stepping of the co[...]

  • Page 12

    Intel® Xeon® Processor 5600 Series 12 Specification Update, March 2010 T = Mobile Intel® Pentium® 4 processor-M U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA package W= Intel® Celeron® M processor X = Intel® P entium® M processor on 90nm process wit[...]

  • Page 13

    Intel® Xeon® Processor 5600 Series 13 Specification Update, March 2010 AAB= Intel® X eon® E3110 processor AAC= Intel® Celeron® dual-core processor E1000 series AAD = Intel ® Core™2 Extreme processor QX9775 AAE = Intel® Atom™ processor Z5xx series AAF = Intel® Atom™ processor 200 series AAG = Intel® Atom™ processor N series AAH = I[...]

  • Page 14

    Intel® Xeon® Processor 5600 Series 14 Specification Update, March 2010 Errata Summary Table 3. Errata Summary Table (Sheet 1 of 4) Errata Number Steppings Status ERRATA B-1 BD1 X No Fix The Processor may R eport a #TS Instead of a #GP Fa ult BD2 X No Fix REP MOVS/STOS Executing with F ast Strings Enabled and Crossing Page Boundaries with Inconsis[...]

  • Page 15

    Intel® Xeon® Processor 5600 Series 15 Specification Update, March 2010 BD25 X No Fix Intel® QuickPath Memory Controller May Hang Due to Uncorrectable ECC Erro rs Occurring on Both Channels in Mirror Channel Mode BD26 X No Fix Simultaneous Correctable ECC Errors on Different Memory Channels With Patrol Scrubbing Enabled May Result in Incorrect In[...]

  • Page 16

    Intel® Xeon® Processor 5600 Series 16 Specification Update, March 2010 BD52 X No Fix Memory Aliasing of Code Pages May Cause Unpredictable System Behavior BD53 X No Fix Performance Monitor Counters May Count Incorrectly BD54 X No Fix Memory Thermal Throttling May Not Work as Expected in Lockstep Channel Mode BD55 X No Fix Simultaneous Accesses to[...]

  • Page 17

    Intel® Xeon® Processor 5600 Series 17 Specification Update, March 2010 BD79 X No Fix APIC T imer CCR May Report 0 in Periodic Mode BD80 X No Fix LBR, BTM or BTS Records May have In correct Branch From Information After an Intel Enhanced S peedS tep T echnology T ransition, T -states, C1E, or Adaptive Thermal Throttling BD81 X No Fix PEBS Records [...]

  • Page 18

    Intel® Xeon® Processor 5600 Series 18 Specification Update, March 2010 Errata BD1. The Processor may Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (T ask -State Segment) may cause a #TS (invalid T SS exception) instead of a #GP f ault (general p rotection exception). Implication: Oper ation systems that access a busy TSS may g[...]

  • Page 19

    Intel® Xeon® Processor 5600 Series 19 Specification Update, March 2010 W orkaround: None identified. Status: For the steppin gs affected, see the Summary Table of Changes . BD4. Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: P erformance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track retired [...]

  • Page 20

    Intel® Xeon® Processor 5600 Series 20 Specification Update, March 2010 did occur in V86 mode, the exception may be directed to the gener al-protection exception handler . Status: For the steppin gs affected, see the Summary Table of Changes . BD7. Incorrec t Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update Pro[...]

  • Page 21

    Intel® Xeon® Processor 5600 Series 21 Specification Update, March 2010 Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture , for information on the usage of the ENTER instructions. This erratum is not expected to occur in ring 3. F aults ar e usually processed in ring 0 and stack switch occurs when tr[...]

  • Page 22

    Intel® Xeon® Processor 5600 Series 22 Specification Update, March 2010 during a specific boundary condition where the exception/interrupt occurs right after the execution of an instruction at th e lower canonical boundary (0x00007 FFFFFFFFFFF) in 64-bit mode, the LBR return registe rs will save a wrong return address with bits 63 to 48 incorrectl[...]

  • Page 23

    Intel® Xeon® Processor 5600 Series 23 Specification Update, March 2010 Management Mode) may cause the lower two bits of CS segment register to be corrupted. Implication: The corruption of the bottom two bits of the CS segment register will have no impact unless software explicitly examines th e CS segment register between enabling protected mode [...]

  • Page 24

    Intel® Xeon® Processor 5600 Series 24 Specification Update, March 2010 BD22. Improper Parity Error Signaled in the IQ Follo wing Reset When a Code Breakpoint is Set on a #GP Instruction Problem: While coming out of cold reset or exiting from C6, if the processor encounters an instruction longer than 15 bytes (which causes a #GP) and a code breakp[...]

  • Page 25

    Intel® Xeon® Processor 5600 Series 25 Specification Update, March 2010 BD25. Intel® QuickPath Memory Contro ller May Hang Due to Uncorrectable ECC Errors Occurring on B oth Ch annels in Mirror Channel Mode Problem: If an uncorrectable ECC error or parity e rror o ccurs on the mirrored channel before an uncorrectable ECC error or parity error on [...]

  • Page 26

    Intel® Xeon® Processor 5600 Series 26 Specification Update, March 2010 BD29. Disabling Thermal Monitor While Pr ocessor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio Problem: If a processor is at its TCC (Thermal Control Circuit) activ ation temperature and then Thermal Monitor is disabled by a write to IA 32_MISC_ENABLES MSR[...]

  • Page 27

    Intel® Xeon® Processor 5600 Series 27 Specification Update, March 2010 BD32. xAPIC Timer May Decremen t To o Quickly Following an Automatic Reload While in Periodic Mode Problem: When the xAPIC Timer is automat ically reload ed by counting down to zero in periodic mode, the xAPIC Timer may slip in its sync hronization with the external clock. The[...]

  • Page 28

    Intel® Xeon® Processor 5600 Series 28 Specification Update, March 2010 W orkaround: As long as machine check exceptions are enabled, the machine check exception handler can log the TLB error prior to core C6 entry . This will ensure the error is logged before it is cleared. Status: For the steppin gs affected, see the Summary Table of Changes . B[...]

  • Page 29

    Intel® Xeon® Processor 5600 Series 29 Specification Update, March 2010 be processed after C6 wakeup and after interrupts are re-enabled (EFLAGS.IF=1). However , the pending interrupt event will not be cleared. Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the external interrupt. Intel has not [...]

  • Page 30

    Intel® Xeon® Processor 5600 Series 30 Specification Update, March 2010 Status: For the steppin gs affected, see the Summary Table of Changes . BD42. APIC Error “Received Illegal Vector” May be Lost Problem: APIC (Advanced Pro grammable Interrupt Controller) may not update the ESR (Error Status Register) flag R eceived Illegal V ector bit [6] [...]

  • Page 31

    Intel® Xeon® Processor 5600 Series 31 Specification Update, March 2010 BD46. ECC Errors Can Not be Injected on Back-to-Back Writes Problem: E C C e r r o r s s h o u l d b e i n j e c t e d o n e v e r y write that matches the address set in the MC_CHANNEL_{0,1,2}_AD DR_MA TCH CSRs. Due to this err atum if there are two back - to-back writes that[...]

  • Page 32

    Intel® Xeon® Processor 5600 Series 32 Specification Update, March 2010 BD50. Failing DIMM ID May be Incorrect in the 2DPC Configuration When Mirroring is Enabled Problem: When redundancy is lost in the 2DPC (2 DIMMs Per Channel) configuration, MC_SMI_SPARE_DIMM_ERROR_ST A T US CSR bits [13: 12] (REDUNDANCY_LOSS_F AILING_DIMM) may indi cate the in[...]

  • Page 33

    Intel® Xeon® Processor 5600 Series 33 Specification Update, March 2010 registers, then programming three event v alues 0x4300D2, 0 x4300B1 and 0x4300B5 into the IA32_PERFEVTSELx MSRs, and fina lly continuing with new event programming and restoring previous programming if necessary . Each performance counter , IA32_PMCx, must have its correspondi[...]

  • Page 34

    Intel® Xeon® Processor 5600 Series 34 Specification Update, March 2010 EFLAGS Discrepancy on Page Faults an d on EPT-Induced VM Ex its after a Translation Change Problem: This err atum is regardin g the case where pag ing structures ar e modified to change a linear address from writable to non-writable without software performing an appropriate T[...]

  • Page 35

    Intel® Xeon® Processor 5600 Series 35 Specification Update, March 2010 ASR_PRESENT was intended to allow low power self refresh with DRAM that does not support automatic self refresh. W orkaround: It is possible for Intel prov ided BIOS reference code to contain a workaround for this erratum. Please refer to the latest v ersio n of the BIOS memor[...]

  • Page 36

    Intel® Xeon® Processor 5600 Series 36 Specification Update, March 2010 of load or store instructions retired. However , due to this erratum, they may underco unt. Implication: The performance monitor event INSTR_RETI RED and MEM_INST_RET IRED may reflect a count lower than the actual number of events. W orkaround: None identified. Status: For the[...]

  • Page 37

    Intel® Xeon® Processor 5600 Series 37 Specification Update, March 2010 BD66. Pending x8 7 FPU Exceptions (# MF) May be Signaled Earlier Than Expected Problem: x87 instructions that trigger #MF normally service interrupts before the #MF . Due to this erratum, if an instruction that tri ggers #MF is executed while Enhanced Intel SpeedStep® T echno[...]

  • Page 38

    Intel® Xeon® Processor 5600 Series 38 Specification Update, March 2010 overly aggressive in demoting OS C -sate re quests to a C-sate with higher power and lower exit latency . Implication: This aggressive demotion can result in higher platform power under idle conditions. W orkaround: None identified Status: For the steppin gs affected, see the [...]

  • Page 39

    Intel® Xeon® Processor 5600 Series 39 Specification Update, March 2010 BD73. Performance Moni toring Events STORE_BLOCKS.NOT_STA an d STORE_BLOCKS.STA May No t Count Events Correctly Problem: P erformance Monitor Events STORE_BL OCKS.NO T_ST A and ST ORE_BLOCKS.ST A should only increment the coun t when a load is blocked by a store. Due to this e[...]

  • Page 40

    Intel® Xeon® Processor 5600 Series 40 Specification Update, March 2010 determines this asserted state as another PECI host initiating a transaction, it ma y release control of the bus resulting in a permanent tri-state condition. Implication: Due to this erratum, the PECI host may incorrectly determine that it is not the bus master and consequent[...]

  • Page 41

    Intel® Xeon® Processor 5600 Series 41 Specification Update, March 2010 BD80. PEBS Records Not Crea ted For FP-Assists Events Problem: When a performance monitor counter is configured to count FP_ASSIST S (Event: F7H) and to trigger PEBS (Precise Ev ent Based Sa mpling), the processor does not create a PEBS record when the counter ov erflows. Impl[...]

  • Page 42

    Intel® Xeon® Processor 5600 Series 42 Specification Update, March 2010 BD84. PECI Reads of Machine Ch eck MS Rs in the Processor Core May Not Function Correctly Problem: PECI reads which target machine check MSRs in the processor core may either be directed to a different core than intended or report that the data is not a vailable. Implication: [...]

  • Page 43

    Intel® Xeon® Processor 5600 Series 43 Specification Update, March 2010 BD88. FP Data Operand Poin ter May Be Incorrectly Calculated After an FP Access Which Wraps a 64-Kbyte Boundary in 16-bit Code Problem: The FP (Floating P oint) Data Operand Pointe r is the effectiv e address of the operand associated with the last non-control FP instruction e[...]

  • Page 44

    Intel® Xeon® Processor 5600 Series 44 Specification Update, March 2010 Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Xeon® Processor 5600 Series Datasheet V olumes 1 & 2 • Intel® 64 and IA-32 Architectures Software Developer’s Manual, V olume 1: Basic Architecture ?[...]

  • Page 45

    Intel® Xeon® Processor 5600 Series 45 Specification Update, March 2010 Specification Clarifications The Specification Changes listed in this section apply to the following documents: • Intel® Xeon® Processor 5600 Series Datasheet V olume 1 & 2 • Intel® 64 and IA-32 Architectures Software Developer’s Manual, V olume 1: Basic Architect[...]

  • Page 46

    Intel® Xeon® Processor 5600 Series 46 Specification Update, March 2010 Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® Xeon® Processor 5600 Series Datasheet V olume 1 & 2 • Intel® 64 and IA-32 Architectures Software Developer’s Manual, V olume 1: Basic Architecture •[...]