Intel 307017-001 manuel d'utilisation

Intel ® I/O Controller Hub 7 (ICH7)/ Intel ® High Definition Audio/ AC’97 Programmer’s Reference Manual (PRM) For the Intel ® 82801GB ICH7 and 82801GR ICH7R I/O Controller Hubs April 2005 Document Number: 307017-001[...]

2 Programmer’s Refe rence Manual Contents[...]

3 Programmer’s Reference Manual INFORMA TION IN THIS DOCUMENT IS PROVID ED IN CONNECTION W ITH INTEL ® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER WISE, TO ANY INTELLECTUAL PROPER TY RIGH TS IS GRANTED BY THIS DOCUMENT . EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, IN TEL ASSUMES NO LIABIL[...]

4 Programmer’s Refe rence Manual Contents Contents 1I n t e l ® High Defi nition Audi o Controller Re gisters (D2 7:F0) ................ ............. ................ ....... 13 1.1 Intel ® High Definition Audio PCI Configuration Space (Intel ® High Definition Audio— D27:F0) ............ ................. ................ ................ .[...]

Programmer’s Reference Manual 5 Contents 1.1.24 PCS— Power Manag ement Contro l and Status Re gister (Intel ® High Definit ion Audio Controller—D27: F0) . ............. ................ ................ ... 25 1.1.25 MID—MSI Capability ID Register (Intel ® High Definit ion Audio Controller—D27: F0) . ............. ................ .....[...]

6 Programmer’s Refe rence Manual Contents 1.1.50 L1ADDU—Link 1 Upper Address Register (Intel ® High Definition Audio Controller—D2 7:F0) ............. ................. ................ ... 35 1.2 Intel ® High Definition Audio Memory Map ped Configuration Registers (Intel ® High Definition Audio— D27:F0) ............ ................. ..[...]

Programmer’s Reference Manual 7 Contents 1.2.25 RIRBWP—RIRB Write Pointer Register (Intel ® High Definit ion Audio Controller—D27: F0) . ............. ................ ................ ... 51 1.2.26 RIN TCNT—Res ponse Inte rrupt Count Register (Intel ® High Definit ion Audio Controller—D27: F0) . ............. ................ .........[...]

8 Programmer’s Refe rence Manual Contents 2.1.8 BCC—Base Class C ode Register (Audio —D30:F2) ...... ................ .................... ... 67 2.1.9 HEADTYP—Header Type Register (Audio— D30:F2) . ................... .................... ... 68 2.1.10 NAMBAR—Native Audio Mi xer Base Address Register (Audio—D30:F2) ... ..............[...]

Programmer’s Reference Manual 9 Contents (Modem—D30:F3) ............................. ................. ................ ................ ................ ... 93 3.1.11 MBAR—Modem B ase Address Register (Modem— D30:F3) .......... ................... ... 94 3.1.12 SVID —Subsystem Vendor Identification R egister (Modem—D30:F3) ...........[...]

10 Programmer’s Refe rence Manual Contents Figures 4-1 Intel ® ICH7 High Definition Audio/AC’ 97 Share Signals to Codecs ...... ................... ..... 109 4-2 Intel ® High Definition Audio Codec Node S tructur e and Addressing ............. ... ... ... ... .... . 113 Tables 1-1 Intel® High Definition Aud io PCI Regist er Address M ap (Int[...]

Programmer’s Reference Manual 11 Contents Revision History § Revision Description Date -001 • Initial release April 2005[...]

12 Programmer’s Refe rence Manual Contents[...]

Programmer’s Reference Manual 13 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1 Intel ® High Definition Audio Controller Registers (D27:F0) The Intel® HD Audio controller resides in PCI Device 27, Functio n 0 on bus 0. This function contains a set of DMA engines that are used to mo ve sam ples of digitally encoded data between [...]

14 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 14h–17h HDBARU Intel® High Definition Audio Upper Base Address (Memory) 00000000h R/W 2Ch–2Dh SVID Subsystem V endor Identification 0000h R/WO 2Eh–2Fh SID Subsystem Identification 0000h R/WO 34h CAPPTR Capability List Pointer 50h RO 3Ch INTLN Int[...]

Programmer’s Reference Manual 15 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.1.1 VID—V endor Iden tification Register (Intel ® High Definition Audio Controll er—D27: F0) Offset: 00h-01h Attribute: RO Default Value: 8086h Size: 16 bits 1.1.2 DID—Device Identification Register (Intel ® High Definition Audio Controll er?[...]

16 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.1.3 PCICMD—PCI Command Register (Intel ® High Definition Audi o Controller—D27:F0) Offset Address: 04h – 05h Attribute: R/W, RO Default Value: 0000h Size: 16 bits Bit Description 15:1 1 Rese rved 10 Interrupt Disable (ID) — R/W. 0= The INTx# [...]

Programmer’s Reference Manual 17 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.1.4 PCISTS—PCI S t atus Register (Intel ® High Definition Audio Controll er—D27:F0) Offset Address: 0 6h – 07 h Attribute: RO, R/WC Default Value: 0010h Size: 16 bits 1.1.5 RID—Revision Identification Regi ster (Intel ® High Definition Audio[...]

18 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.1.6 PI—Programming Interface Register (Intel ® High Definition Audio Controller—D27:F0) Offset: 09h Attribute: RO Default Value: 00h Size: 8 bits 1.1.7 SCC—Sub Class Code Register (Intel ® High Definition Audi o Controller—D27:F0) Address Of[...]

Programmer’s Reference Manual 19 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.1.10 L T—Latency Timer Register (Intel ® High Definition Audio Controll er—D27: F0) Address Offset: 0 Dh Attribute: RO Default Value: 00h Size: 8 bits 1.1.1 1 HEADTYP—Header T ype Register (Intel ® High Definition Audio Controll er—D27: F0) [...]

20 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.1.14 SVID—Subsystem V endor Identification Register (Intel ® High Definition Audi o Controller—D27:F0) Address Offset: 2Ch–2Dh Attribute: R/WO Default Value: 0000h Size: 16 bits The SVID register, in combination with the Subsystem ID register ([...]

Programmer’s Reference Manual 21 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.1.16 CAPPTR—Cap abilities Poin ter Register (Audio—D30:F2) Address Offset: 3 4h Attribute: RO Default Value: 50h Size: 8 bits This register indicates the of fset for the capability pointer . 1.1.17 INTLN—Interrupt Line Register (Intel ® High De[...]

22 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.1.19 HDCTL—Intel ® High Definition Audi o Control Register (Intel ® High Definition Audi o Controller—D27:F0) Address Offset: 40h Attribute: R/W, RO Default Value: 00h Size: 8 bits Bit Description 7:4 Reserved. 3 BITCLK Detect Clear (CLKDETCLR) [...]

Programmer’s Reference Manual 23 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.1.20 TCSEL—T raffic Cl ass Select Register (Intel ® High Definition Audio Controll er—D27: F0) Address Offset: 4 4h Attribute: R/W Default Va lue: 00h Size: 8 bits This register assigned the value to be placed in the TC field. CORB and RIRB data [...]

24 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.1.21 DCKSTS—Docking St atus Register (Intel ® High Definition Audio Controller—D27:F0) Address Offset: 4Dh Attribute: R/WO, RO Default V alue: 80h Size: 8 bits 1.1.22 PID—PCI Power Manageme nt Capability ID Register (Intel ® High Definition Au[...]

Programmer’s Reference Manual 25 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.1.23 PC—Power Management Cap abilities Register (Intel ® High Definition Audio Controll er—D27: F0) Address Offset: 5 2h–53h Attribute: RO Default Value: C842h Size: 16 bits 1.1.24 PCS—Power Management Control and S t atus Register (Intel ® [...]

26 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.1.25 MID—MSI Cap ability ID Register (Intel ® High Definition Audi o Controller—D27:F0) Address Offset: 60h–61 h Attribute: RO Default Value: 7005h Size: 16 bi ts 1.1.26 MMC—MSI Message Control Register (Intel ® High Definition Audi o Contro[...]

Programmer’s Reference Manual 27 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.1.27 MMLA—MSI Message Lo wer Address Register (Intel ® High Definition Audio Controll er—D27: F0) Address Offset: 6 4h–6 7h Attribute: RO, R/W Default Value: 00000000h Size: 32 bits 1.1.28 MMUA—MSI Message Upper Address Register (Intel ® Hig[...]

28 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.1.31 PXC—PCI Express* Cap abilities Register (Intel ® High Definition Audi o Controller—D27:F0) Address Offset: 72h–73 h Attribute: RO Default Value: 0091h Size: 16 bi ts 1.1.32 DEVCAP—Device Cap abilities Register (Intel ® High Definition A[...]

Programmer’s Reference Manual 29 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.1.33 DEVC—Device Control Register (Intel ® High Definition Audio Controll er—D27: F0) Address Offset: 7 8h–7 9h Attribute: R/W, RO Default Value: 0800h Size: 16 bits 1.1.34 DEVS—Device St atus Register (Intel ® High Definition Audio Controll[...]

30 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.1.35 VCCAP—V irtual Channel Enhanced Capability Header (Intel ® High Definition Audi o Controller—D27:F0) Address Offset: 100 h–103h Attribute: RO Default Value: 13010002h Size: 32 bits 1.1.36 PVCCAP1—Port VC Cap ability Register 1 (Intel ® [...]

Programmer’s Reference Manual 31 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.1.37 P VCCAP2 — Port VC Cap ability Register 2 (Intel ® High Definition Audio Controll er—D27: F0) Address Offset: 1 08h–10Bh Attribute: RO Default Value: 00000000h Size: 32 bits 1.1.38 P VCCTL — Port VC Control Register (Intel ® High Defini[...]

32 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.1.40 VC0CAP—VC0 Reso urce Capability Register (Intel ® High Definition Audi o Controller—D27:F0) Address Offset: 110 h–113h Attribute: RO Default Value: 00000000h Size: 32 bits 1.1.41 VC0CTL—VC0 Reso urce Control Re gister (Intel ® High Defi[...]

Programmer’s Reference Manual 33 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.1.43 VCiCAP—VCi Resource Cap ability Register (Intel ® High Definition Audio Controll er—D27: F0) Address Offset: 1 1Ch–11Fh Attribute: RO Default Value: 00000000h Size: 32 bits 1.1.44 VCiCTL—VCi Resource Control Register (Intel ® High Defin[...]

34 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.1.45 VCiSTS—VCi Resource St atus Register (Intel ® High Definition Audi o Controller—D27:F0) Address Offset: 126 h–127h Attribute: RO Default Value: 0000h Size: 16 bi ts 1.1.46 RCCAP—Root Com plex Link Declaration Enha nced Cap ability Header[...]

Programmer’s Reference Manual 35 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.1.48 L1DESC—Link 1 Description Register (Intel ® High Definition Audio Controll er—D27: F0) Address Offset: 1 40h–143h Attribute: RO Default Value: 00000001h Size: 32 bits 1.1.49 L1ADDL—Link 1 Lower Address Register (Intel ® High Definition [...]

36 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.2 Intel ® High Definition Audio Memory Mapped Configuration Registers ( Intel ® High Definition Audio — D27:F0) The base memory location for these memory mapp ed configuration registers is specified in the HDBAR register (D27:F0:offset 10h and D27[...]

Programmer’s Reference Manual 37 Intel ® High Definition Audio Cont roller Registers (D27:F0) 5Ch RIRBCTL RIRB Control 00h R/W 5Dh RIR BSTS RIRB St atus 00h R/WC 5Eh RIRBSIZE RIRB Size 42h RO 60h–63h IC Immediate Command 00000000h R/W 64h–67h IR Immediate Response 00000000h RO 68h–69h IRS Immediate Command S tatus 0000h R/W , R/WC 70h–73[...]

38 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) D0h–D1h ISD2FIFOS ISD2 FIFO Size 0077h RO D2h–D3h ISD2FMT ISD2 Format 0000h R/W D8h–DBh ISD2BDPL ISD2 Buffer Descriptor List Pointer-Lower Base Address 00000000h R/W , RO DCh–DFh ISD2BDPU ISD2 Buffer Description List Pointer-Upper Base Address 0[...]

Programmer’s Reference Manual 39 Intel ® High Definition Audio Cont roller Registers (D27:F0) 138h–13Bh OSD1BDPL OSD1 Buffer Descriptor List Pointer-Lower Base Address 00000000h R/W, RO 13Ch–13Fh OSD1BDPU OSD1 Buffer Description List Pointer-Upper Base Address 00000000h R/W 140h–142h OSD2CTL Output S tream Descriptor 2 (OSD2) Control 04000[...]

40 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.2.1 GCAP—Global Cap abilities Register (Intel ® High Definition Audi o Controller—D27:F0) Memory Address: HDBAR + 00h Attribute: RO Default Value: 4401h Size: 16 bi ts 1.2.2 VMIN—Minor V ersion Register (Intel ® High Definition Audi o Controll[...]

Programmer’s Reference Manual 41 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.2.4 OUTP A Y—Output Payload Cap ability Register (Intel ® High Definition Audio Controll er—D27: F0) Memory Addr ess: HDBAR + 04h Attribute: RO Default Value: 003Ch Size: 16 bits 1.2.5 INP A Y—Input Payload Cap ability Register (Intel ® High D[...]

42 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.2.6 GCTL—Global Control Register (Intel ® High Definition Audi o Controller—D27:F0) Memory Address: HDBAR + 08h Attribute: R/W Default Value: 00000000h Size: 32 bits Bit Description 31:9 Reserved. 8 Accept Unsolicited Respon se Enable — R/W . 0[...]

Programmer’s Reference Manual 43 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.2.7 W AKEEN—W ake Enable R egister (Intel ® High Definition Audio Controll er—D27: F0) Memory Addr ess: HDBAR + 0Ch Attribute: R/W Default Value: 0000h Size: 16 bits 1.2.8 ST A TESTS—St ate Change S tatus Register (Intel ® High Definition Audi[...]

44 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.2.9 GSTS—Global St atus Register (Intel ® High Definition Audi o Controller—D27:F0) Memory Address: HDBAR + 10h Attribute: R/WC Default Value: 0000h Size: 16 bi ts 1.2.10 OUTSTRMP A Y—Output Stream Payload Cap a bility (Intel ® High Definition[...]

Programmer’s Reference Manual 45 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.2.1 1 INSTRMP A Y—Input S tream Payload Cap ability (Intel ® High Definition Audio Controll er—D27: F0) Memory Addr ess: HDBAR + 1Ah Attribute: RO Default Value: 0018h Size: 16 bits Bit Description 15:14 Input FIFO Padding T ype (IP ADTYPE) — R[...]

46 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.2.12 INTCTL—Interrupt Control Regi ster (Intel ® High Definition Audi o Controller—D27:F0) Memory Address: HDBAR + 20h Attribute: R/W Default Value: 00000000h Size: 32 bits Bit Description 31 Global Interrupt Enable (GIE) — R/W . Global bit to [...]

Programmer’s Reference Manual 47 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.2.13 INTSTS—Interrupt S tatus Register (Intel ® High Definition Audio Controll er—D27: F0) Memory Addr ess: HDBAR + 24h Attribute: RO Default Value: 00000000h Size: 32 bits 1.2.14 W ALCLK—W all Clock Counter Register (Intel ® High Definition A[...]

48 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.2.15 SSYNC—S tream Sync hronization Register (Intel ® High Definition Audi o Controller—D27:F0) Memory Address: HDBAR + 34h Attribute: R/W Default Value: 00000000h Size: 32 bits 1.2.16 CORBLBASE—CORB Lower Base Address Register (Intel ® High D[...]

Programmer’s Reference Manual 49 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.2.17 CORBUBASE—CORB Uppe r Base Address Register (Intel ® High Definition Audio Controll er—D27: F0) Memory Addr ess: HDBAR + 44h Attribute: R/W Default Value: 00000000h Size: 32 bits 1.2.18 CORBWP—CORB W rit e Pointer Register (Intel ® High D[...]

50 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.2.20 CORBCTL—CORB Control Register (Intel ® High Definition Audi o Controller—D27:F0) Memory Address: HDBAR + 4Ch Attribute: R/W Default Value: 00h Size: 8 bits 1.2.21 CORBST—CORB St atus Register (Intel ® High Definition Audi o Controller—D[...]

Programmer’s Reference Manual 51 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.2.23 RIRBLBASE—RIRB Lower Base Address Register (Intel ® High Definition Audio Controll er—D27: F0) Memory Address: HDBAR + 50h Attribute: R/W, RO Default Value: 00000000h Size: 32 bits 1.2.24 RIRBUBASE—RIRB Uppe r Base Address Register (Intel [...]

52 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.2.26 RINTCNT—Response Interrupt Count Register (Intel ® High Definition Audi o Controller—D27:F0) Memory Address: HDBAR + 5Ah Attribute: R/W Default Value: 0000h Size: 16 bi ts 1.2.27 RIRBCTL—RIRB Control Regist er (Intel ® High Definition Aud[...]

Programmer’s Reference Manual 53 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.2.28 RIRBSTS—RIRB St atus Register (Intel ® High Definition Audio Controll er—D27: F0) Memory Addr ess: HDBAR + 5Dh Attribute : R/WC Default Va lue: 00h Size: 8 bits 1.2.29 RIRBSIZE—RIRB Size Register (Intel ® High Definition Audio Controll er[...]

54 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.2.31 IR—Immediate Response Register (Intel ® High Definition Audi o Controller—D27:F0) Memory Address: HDBAR + 64h Attribute: RO Default Value: 00000000h Size: 32 bits 1.2.32 IRS—Immediate Co mmand St atus Register (Intel ® High Definition Aud[...]

Programmer’s Reference Manual 55 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.2.33 DPLBASE—DMA Position Lower Base Address Register (Intel ® High Definition Audio Controll er—D27:F0) Memory Address: HDBAR + 70h Attribute: R/W, RO Default Value: 00000000h Size: 32 bits 1.2.34 DPUBASE—DMA Position Upper Base Addr ess Regis[...]

56 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) Bit Description 23:20 Str ea m Nu mb e r — R/W. This value reflects the T ag as sociated with the data being transferred on the link. When data controlled by this descriptor is sent ou t over the link, it will have its stream number encoded on the SYN[...]

Programmer’s Reference Manual 57 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.2.36 SDSTS—Stream Descriptor S t atus Register (Intel ® High Definition Audio Controll er—D27: F0) Memory Add ress: Inpu t Stream[0 ]: HDBAR + 83h Attribute: R/WC, RO Input Stream[1 ]: HDBAR + A3h Input Stream[2 ]: HDBAR + C3h Input Stream[3 ]: H[...]

58 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.2.37 SDLPIB—S tream Descriptor Link Position in Buffer Register (Intel ® High Definition Audio Controller—D27:F0) Memory Address: Input Stream [0]: HDBAR + 84h Attribute: RO Input Stream[1]: HDBAR + A4h Input Stream[2]: HDBAR + C4h Input Stream[3[...]

Programmer’s Reference Manual 59 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.2.39 SDL VI—Stream Descriptor Last V alid Index Register (Intel ® High Definition Audio Controll er—D27: F0) Memory Address: Inpu t Stream[0]: HDBAR + 8Ch Attribute: R/W Input Stream[1 ]: HDBAR + ACh Input Stream[2 ]: HDBAR + CCh Input Stream[3 ][...]

60 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.2.41 SDFIFOS—Stream Descriptor FIFO Size Register (Intel ® High Definition Audi o Controller—D27:F0) Memory Address: Input Stream[0 ]: HDBAR + 90h Attribute: Input: RO Input Stream[1]: HDBAR + B0h Output: R/W Input Stream[2]: HDBAR + D0h Input St[...]

Programmer’s Reference Manual 61 Intel ® High Definition Audio Cont roller Registers (D27:F0) 1.2.42 SDFMT—St ream Descr iptor Format Register (Intel ® High Definition Audio Controll er—D27: F0) Memory Add ress: Inpu t Stream[0 ]: HDBAR + 92h Attribute: R /W Input Stream[1 ]: HDBAR + B2h Input Stream[2 ]: HDBAR + D2h Input Stream[3 ]: HDBAR[...]

62 Programmer’s Reference Manual Intel ® High Definition Audio C ontroller Registers (D27:F0) 1.2.43 SDBDPL—Stream Descriptor Buffer Descript or List Pointer Lower Base Address Register (Intel ® High Definition Audi o Controller—D27:F0) Memory Address: Input Stream[0 ]: HDBAR + 98h Attribute: R/W,RO Input Stream[1]: HDBAR + B8h Input Stream[...]

Programmer’s Reference Manual 63 AC ’97 Audio Controller Registers (D30: F2) 2 AC ’97 Audio Controller Registers (D30:F2) 2.1 AC ’97 Audio PCI Configuration Sp ace (Audio—D3 0:F2) Note: Registers that are not shown s hould be treated as Reserved. Note: Internal reset as a result of D3 HOT to D0 transition will reset all the core well regi[...]

64 Programmer’s Reference Manual AC ’97 Audio Controller Registers (D30:F2) Core well registers not reset by the D3 HOT t o D0 transition: • offset 2Ch – 2Dh – Subsystem V end or ID (SVID) • offset 2Eh – 2Fh – Su bs ystem ID (SID) • offset 40h – Programmable Codec ID (PCID) • offset 41h – Configuration (CFG) Resume well regi[...]

Programmer’s Reference Manual 65 AC ’97 Audio Controller Registers (D30: F2) 2.1.3 PCICMD—PCI Command Register (Audio—D30:F2) Address Offset: 0 4h – 05h Attribute: R/W, RO Default Value: 0000h Size: 16 bits Lockable: No Power Well: Core PCICMD is a 16-bit control register . Refer to th e PCI 2.3 specification for complete details on each [...]

66 Programmer’s Reference Manual AC ’97 Audio Controller Registers (D30:F2) 2.1.4 PCISTS—PCI St atus Register (A udio—D30:F2) Offset: 06h – 07h Attribute: RO, R/WC Default Value 0280h Size: 16 bi ts Lockable: No Power Well: Core PCIST A is a 16-bit status register . Refer to th e PCI 2.3 specification for complete details on each bit. Bit[...]

Programmer’s Reference Manual 67 AC ’97 Audio Controller Registers (D30: F2) 2.1.5 RID—Revision Identific ation Register (Audio—D30:F2) Offset: 08h Attribute: RO Default Va lue: See bit description Size: 8 Bits Lockable: No Power Well: Core 2.1.6 PI—Programming Interfac e Register (Audio—D30:F2) Offset: 09h Attribute: RO Default Value: [...]

68 Programmer’s Reference Manual AC ’97 Audio Controller Registers (D30:F2) 2.1.9 HEADTYP—Header T ype Register (Audio—D30:F2) Address Offset: 0Eh Attribute: RO Default Value: 00h Size: 8 bits Lockable: No Power Well: Core 2.1.10 NAMBAR—Native Aud io Mi xer Base Address Register (Audio—D30:F2) Address Offset: 10 – 13h Attribute: R/W, [...]

Programmer’s Reference Manual 69 AC ’97 Audio Controller Registers (D30: F2) 2.1.1 1 NABMBAR—Native Audio Bus Mastering Base Address Register (Audio—D30:F2) Address Offset: 1 4h – 17h Attribute: R/W, RO Default Value: 00000001h Size: 32 bits Lockable: No Power Well: Core The Native PCI Mode Audio function uses PCI Base Address register #1[...]

70 Programmer’s Reference Manual AC ’97 Audio Controller Registers (D30:F2) 2.1.13 MBBAR—Bus Master B ase Address Register (Audio—D30:F2) Address Offset: 1Ch – 1Fh Attribute: R/W, RO Default Value: 00000000h Size: 32 bits Lockable: No Power Well: Core This BAR creates 256-bytes of memory space to signify the base addre ss of the bus maste[...]

Programmer’s Reference Manual 71 AC ’97 Audio Controller Registers (D30: F2) 2.1.15 SID—Subsystem Identifica tion Register (Audio—D30:F2) Address Offset: 2Eh – 2Fh Attri bute: R/WO Default Value: 0000h Size: 16 bits Lockable: No Power Well: Core The SID register , in combination with the Subsystem V endor ID register (D30:F2 :2Ch) make it[...]

72 Programmer’s Reference Manual AC ’97 Audio Controller Registers (D30:F2) 2.1.18 INT_PN—Interrupt Pi n Register (Audio—D30:F2) Address Offset: 3Dh Attribute: RO Default Value: See Descrip ti on Size: 8 bits Lockable: No Power Well: Core This register indicates which PCI interrupt pin is used for the AC '97 module interrup t. The AC &[...]

Programmer’s Reference Manual 73 AC ’97 Audio Controller Registers (D30: F2) 2.1.21 PID—PCI Power Manageme nt Cap ability Identification Register (Audio—D30:F2) Address Offset: 5 0h – 51h Attribute: RO Default Value: 0001h Size: 16 bits Lockable: No Power Well: Core 2.1.22 PC—Power Management Cap abilities Register (Audio—D30:F2) Addr[...]

74 Programmer’s Reference Manual AC ’97 Audio Controller Registers (D30:F2) 2.1.23 PCS—Power Management Control and St atus Register (Audio—D30:F2) Address Offset: 54h – 55h Attribute: R/W, R/WC Default Value: 0000h Size: 16 bits Lockable: No Power Well: Resume Bit Description 15 PME Status (PMES) — R/WC. Th is bit resides in the resume[...]

Programmer’s Reference Manual 75 AC ’97 Audio Controller Registers (D30: F2) 2.2 AC ’97 Audio I/O Sp ace (D30:F2) The AC ’97 I/O space includes Native Audio Bus M aster registers and Native Mixer registers. For the ICH7, the offsets are importan t as they will determine bits 1:0 of the T AG field (codec ID). Audio Mixer I/O space can be acc[...]

76 Programmer’s Reference Manual AC ’97 Audio Controller Registers (D30:F2) NOTE: 1. Software should not try to access reserved registers 2. Primary Codec ID cannot be changed. Secondar y codec ID can be changed via bits 1:0 of configuration register 40h. T ertiary codec ID can be changed via bits 3:2 of configuration register 40h. 3. The terti[...]

Programmer’s Reference Manual 77 AC ’97 Audio Controller Registers (D30: F2) T able 2-3. Native Audio Bus Master Control Registe rs (Sheet 1 of 2) Offset Mnemonic Name Default Access 00h PI_BDBAR PCM In Buffer Descriptor list Base Address 00000000h R/W 04h PI_CIV PCM In Current Index V alue 00h RO 05h PI_L VI PCM In Last V alid Index 00h R/W 06[...]

78 Programmer’s Reference Manual AC ’97 Audio Controller Registers (D30:F2) Note: Internal reset as a result of D3 HOT to D0 transition will reset all the core well registers except the registers shared with the AC ’97 Modem (GCR, GSR, CASR). All resume well regi sters will not be reset by the D3 HOT to D0 transition. Core well registers and [...]

Programmer’s Reference Manual 79 AC ’97 Audio Controller Registers (D30: F2) 2.2.2 x _CIV—Current Index V alu e Register (Audio—D30:F2) I/O Address: NABMBAR + 04h (PICIV), Attribute: RO NABMBAR + 14h (POCIV), NABMBAR + 24h (MCCIV) MBBAR + 44h (MC2CIV) MBBAR + 54h (PI2CIV) MBBAR + 64h (SPCIV) Default Va lue: 00h Size: 8 bits Lockable: No Pow[...]

80 Programmer’s Reference Manual AC ’97 Audio Controller Registers (D30:F2) 2.2.4 x _SR—S tatus Register (Audio—D30:F2) I/O Address: NABMBAR + 06h (PISR), Attribute: R/WC, RO NABMBAR + 16h (POSR), NABMBAR + 26h (MCSR) MBBAR + 46h (MC2SR) MBBAR + 56h (PI2SR) MBBAR + 66h (SPSR) Default Value: 000 1h Size: 16 bits Lockable: No Power Well: Core[...]

Programmer’s Reference Manual 81 AC ’97 Audio Controller Registers (D30: F2) 2.2.5 x _PICB—Position In Curre nt Buffer Register (Audio—D30:F2) I/O Address: NABMBAR + 08h (PIPICB), Attribute: RO NABMBAR + 18h (POPICB), NABMBAR + 28h (MCPICB) MBBAR + 48h (MC2PICB) MBBAR + 58h (PI2PICB) MBBAR + 68h (SPPICB) Default Value: 0000h Size: 1 6 bits [...]

82 Programmer’s Reference Manual AC ’97 Audio Controller Registers (D30:F2) 2.2.7 x _CR—Control Regis ter (Audio—D30:F2) I/O Address: NABMBAR + 0Bh (PICR) , Attribute: R/W, R/W (special) NABMBAR + 1Bh (POCR), NABMBAR + 2Bh (MCCR) MBBAR + 4Bh (MC2CR) MBBAR + 5Bh (PI2CR) MBBAR + 6Bh (SPCR) Default Value: 00h Size: 8 bits Lockable: No Power We[...]

Programmer’s Reference Manual 83 AC ’97 Audio Controller Registers (D30: F2) 2.2.8 GLOB_CNT—Global Cont rol Register (Audio—D30:F2) I/O Address: NABMBAR + 2Ch Attr ibute: R/W, R/W (special) Default Value: 00000000h Size: 32 bits Lockable: No Power Well: Core Bit Description 31:30 S/PDIF Slot Map (SSM) — R/W . If the run/pause bus master b[...]

84 Programmer’s Reference Manual AC ’97 Audio Controller Registers (D30:F2) NOTE: Reads across DWord boundaries are not supported. 2 AC ’97 Warm Reset — R/W (special). 0 = Normal operation. 1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset will awaken a suspended codec without clearing its internal r eg[...]

Programmer’s Reference Manual 85 AC ’97 Audio Controller Registers (D30: F2) 2.2.9 GLOB_ST A—Global St atus Register (Audio—D30:F2) I/O Address: NABMBAR + 30h Attribute: RO, R/W, R/WC Default Value: 00x0xxx01110000000000 xxxxx00xxxb Size: 32 bits Lockable: No Power Well: Core Bit Description 31:30 Reserved. 29 ACZ_SDIN2 Resume Interrupt ( S[...]

86 Programmer’s Reference Manual AC ’97 Audio Controller Registers (D30:F2) NOTE: Reads across DWord boundaries are not supported. 14 Bit 3 of Slot 12 — RO. Displa y bit 3 of the most recent slot 12. 13 Bit 2 of Slot 12 — RO. Displa y bit 2 of the most recent slot 12. 12 Bit 1 of slot 12 — RO. Display bit 1 of the most recent slot 12. 11 [...]

Programmer’s Reference Manual 87 AC ’97 Audio Controller Registers (D30: F2) 2.2.10 CAS—Codec Access Semaph ore Register (Audio—D30:F2) I/O Address: NABMBAR + 34h Attribute: R/W (special) Default Value: 00h Size: 8 bits Lockable: No Power Well: Core NOTE: Reads across DWord boundaries are not supported. 2.2.1 1 SDM—SDA T A_IN Map Register[...]

88 Programmer’s Reference Manual AC ’97 Audio Controller Registers (D30:F2)[...]

Programmer’s Reference Manual 89 AC ’97 Mode m Controller Reg isters (D30 :F3) 3 AC ’97 Modem Controller Registers (D30:F3) 3.1 AC ’97 Modem PCI Configuration Sp ace (D30:F3) Note: Registers that are not shown s hould be treated as Reserved. Note: Internal reset as a result of D3 HOT to D0 transition will reset all the core well registers e[...]

90 Programmer’s Reference Manual AC ’97 Modem Controller Registers (D30:F3) 3.1.1 VID—V endor Identificati on Register (Modem—D30:F3) Address Offset: 00h – 01h Attribute: RO Default Value: 8086 Size: 16 Bits Lockable: No Power Well: Core 3.1.2 DID—Device Identificat ion Register (Modem—D30:F3) Address Offset: 02h – 03h Attribute: RO[...]

Programmer’s Reference Manual 91 AC ’97 Mode m Controller Reg isters (D30 :F3) 3.1.4 PCISTS—PCI S t atus Register (Modem—D30:F3) Address Offset: 0 6h – 07h Attribute: R/WC, RO Default Value: 0290h Size: 16 bits Lockable: No Power Well: Core PCISTS is a 16-bit status register . Refer to the PCI Local Bus Specification for complete d etails[...]

92 Programmer’s Reference Manual AC ’97 Modem Controller Registers (D30:F3) 3.1.5 RID—Revision Identification Register (Modem—D30:F3) Address Offset: 08h Attribute: RO Default Value: See bi t descrip tion Size: 8 Bits Lockable: No Power Well: Core 3.1.6 PI—Programming Interface Register (Modem—D30:F3) Address Offset: 09h Attribute: RO D[...]

Programmer’s Reference Manual 93 AC ’97 Mode m Controller Reg isters (D30 :F3) 3.1.9 HEADTYP—Header T ype Register (Modem—D30:F3) Address Offset: 0 Eh Attribute: RO Default Va lue: 00h Size: 8 bits Lockable: No Power Well: Core 3.1.10 MMBAR—Modem M ixer Base Address Register (Modem—D30:F3) Address Offset: 10 – 13h Attri bute: R/W, RO [...]

94 Programmer’s Reference Manual AC ’97 Modem Controller Registers (D30:F3) 3.1.1 1 MBAR—Modem Base Addr ess Register (Modem—D30:F3) Address Offset: 14h – 17h Attribute: R/W, RO Default Value: 00000001h Size: 32 bits The Modem function uses PCI Base Address register #1 to request a contiguous block of I/O space that is to be used for the [...]

Programmer’s Reference Manual 95 AC ’97 Mode m Controller Reg isters (D30 :F3) 3.1.13 SID—Subsystem Identifica tion Register (Modem—D30:F3) Address Offset: 2Eh – 2Fh Attri bute: R/WO Default Value: 0000h Size: 16 bits Lockable: No Power Well: Core The SID register , in combination with the Subsystem V e ndor ID reg ister make it po ssib l[...]

96 Programmer’s Reference Manual AC ’97 Modem Controller Registers (D30:F3) 3.1.16 INT_PIN—Interrupt Pi n Register (M odem—D30:F3) Address Offset: 3Dh Attribute: RO Default Value: See de scri ption Size: 8 bits Lockable: No Power Well: Core This register indicates which PCI interrupt pin is used for the AC ’97 modem interrupt . The AC ’[...]

Programmer’s Reference Manual 97 AC ’97 Mode m Controller Reg isters (D30 :F3) 3.1.19 PCS—Power Management Control and S t atus Register (Modem—D30:F3) Address Offset: 5 4h Attribute: R/W, R/WC Default Value: 0000h Size: 16 bits Lockable: No Power Well: Resume This register is not af fected by the D3 HOT to D0 transition. Bit Description 15[...]

98 Programmer’s Reference Manual AC ’97 Modem Controller Registers (D30:F3) 3.2 AC ’97 Modem I/O Sp ace (D30:F3) In the case of the split codec implementation accesses to the mode m mixer registers in different codecs are dif ferentiated by the c ontroller by using address offsets 00h – 7Fh for the primary codec and address offsets 80h – [...]

Programmer’s Reference Manual 99 AC ’97 Mode m Controller Reg isters (D30 :F3) These registers exist in I/O space and reside in the AC ’97 controller . The two channels, Modem in and Modem out, each have their own set of Bus Mastering registers. Th e following register descriptions apply to both channels. The na m ing prefix convention used i[...]

100 Programmer’s Reference Manual AC ’97 Modem Controller Registers (D30:F3) 3.2.1 x _BDBAR—Buffer Descriptor Li st Base Address Register (Modem—D30:F3) I/O Address: MBAR + 0 0h (MIBDBAR), Attribute: R/W MBAR + 10h (MOBDBAR) Default Value: 000000 00h Size: 32bits Lockable: No Power Well: Core Software can read the register at offset 00h by [...]

Programmer’s Reference Manual 101 AC ’97 Mode m Controller Reg isters (D30 :F3) 3.2.4 x _SR—St atus Register (Modem—D30:F3) I/O Address: MBAR + 06h (MI SR), Attri bute: R/WC, RO MBAR + 16h (MOSR) Default Value: 0001h Size: 1 6 bits Lockable: No Power Well: Core Software can read the regist ers at offsets 04h, 05h and 06h simultaneously b y [...]

102 Programmer’s Reference Manual AC ’97 Modem Controller Registers (D30:F3) 3.2.5 x _PICB—Position in Curr ent Buffer Register (Modem—D30:F3) I/O Address: MBAR + 0 8h (MIPICB), Attribute: RO MBAR + 18h (MOPICB), Default Value: 000 0h Size: 16 bits Lockable: No Power Well: Core Software can read the registers at the offsets 08h, 0Ah, and 0B[...]

Programmer’s Reference Manual 103 AC ’97 Mode m Controller Reg isters (D30 :F3) 3.2.7 x _CR—Control Register (Modem—D30:F3) I/O Address: MBAR + 0Bh (MICR), Attribute: R/W, R/W (special ) MBAR + 1Bh (MOCR) Default Value: 00h Size: 8 bits Lockable: No Power Well: Core Software can read the registers at the of fsets 08h, 0Ah, and 0Bh by perfor[...]

104 Programmer’s Reference Manual AC ’97 Modem Controller Registers (D30:F3) 3.2.8 GLOB_CNT—Global Control Register (Modem—D30:F3) I/O Address: MBAR + 3Ch Att ribute: R/W, R/W (special) Default Value: 000 00000h Size: 32 bits Lockable: No Power Well: Core Note: Reads across DW ord bou ndaries are not supported. Bit Description 31:6 Reserved[...]

Programmer’s Reference Manual 105 AC ’97 Mode m Controller Reg isters (D30 :F3) 3.2.9 GLOB_ST A—G lobal St at us Register (Modem—D30:F3) I/O Address: MBAR + 40h A ttribute: RO, R/W, R/WC Default Value: 00300000h Size: 32 bits Lockable: No Power Well: Core Bit Description 31:30 Reserved. 29 ACZ_SDIN2 Resume Interrupt ( S2RI) — R/WC. This b[...]

106 Programmer’s Reference Manual AC ’97 Modem Controller Registers (D30:F3) Note: On reads from a codec, the controller will give the codec a maximum of four frames to respond, after which if no re sponse is received, it will return a dummy read completio n to the processor (with all F’ s on the data) and also set the Read Completion Status [...]

Programmer’s Reference Manual 107 AC ’97 Mode m Controller Reg isters (D30 :F3) 3.2.10 CAS—Codec Access Semaphore Register (Modem—D30:F3) I/O Address: NABMBAR + 44h Attribute: R/W (special) Default Value: 00h Size: 8 bits Lockable: No Power Well: Core Note: Reads across DW o rd boundaries are not supported. § Bit Description 7:1 Reserved 0[...]

108 Programmer’s Reference Manual AC ’97 Modem Controller Registers (D30:F3)[...]

Programmer’s Reference Manual 109 Intel® High Definition A udio BIOS Considerations 4 Intel ® High Definition Audio BIOS Considerations The Intel ® HD Audio control ler (Bus #0, Device #27, Function #0) is an ICH7 internal PCI Express Endpoint device. Softw are may access the Intel® HD Audio control ler registers (including the memory mapped [...]

110 Programmer’s Reference Manual Intel® High Definition Audio BIOS Conside rations 4.1.1 Intel ® High Definition Audi o/AC’ 97 Codec Detection Before PCI device enumeration during POST , BIOS must d etermine the t ype of codec present on the platform, then program the AZ/AC97# bit to select either Intel® HD Audio or AC’ 97 signal mode, an[...]

Programmer’s Reference Manual 111 Intel® High Definition A udio BIOS Considerations 4. De-assert AC_RESET# bit to take th e link out of RESET# (NABMBAR at D30 :F2:Reg14h + offset 2Ch[1]=1). 5. W ait ~20ms for AC'97 codec driven BIT_CLK startup. 6. W rite a 0 to the Intel® HD Audi o/A C97# bit (D27:F0:Reg40 h[0 ]=0) to ensure that AC’97 m[...]

112 Programmer’s Reference Manual Intel® High Definition Audio BIOS Conside rations 4.1.2 Intel ® High Definition Audio Codec Initialization This section involves the programming interf ace on Intel® HD Audio codec link. Readers are encouraged to read the relevant chapters of Intel® HD Audi o Specification for information regarding architectu[...]

Programmer’s Reference Manual 113 Intel® High Definition A udio BIOS Considerations A codec verb is a 32-bit DW ord command sent to a cod ec by software that contains the following information: • Codec address and Node ID of the target node in the codec • Command to be p erformed by the t arget node • Data payload (if any) Below is the for[...]

114 Programmer’s Reference Manual Intel® High Definition Audio BIOS Conside rations Below is a sample Intel® HD Audi o Codec V erb T abl e, defined in Intel x86 Assembly Language, for a platform with 1 codec at codec address 01h. ;Sample Intel® HD Audio Co dec Verb Table ;Codec Address (CAd) = 01h ;Codec Vendor: XYZ Company ;VenID DevID: dd 12[...]

Programmer’s Reference Manual 115 Intel® High Definition A udio BIOS Considerations ;Pin Complex 5 (NID 15h) dd 11571C11h dd 11571D01h dd 11571E00h dd 11571F00h ;Pin Complex 6 (NID 31h) dd 13171C11h dd 13171D01h dd 13171E00h dd 13171F00h ;Pin Complex 9 (NID 19h) dd 11971C11h dd 11971DC4h dd 11971E00h dd 11971F00h ;Pin Complex 10 (NID 18h) dd 118[...]

116 Programmer’s Reference Manual Intel® High Definition Audio BIOS Conside rations 4.1.2.3 Codec Initializa tion Programming Sequence After BIOS has determined the presence of In tel® HD Audio cod ec(s), it mu st follow the programming sequence giv e n in thi s section to up date the codec with co rrect jack information specific to the platfor[...]

Programmer’s Reference Manual 117 Intel® High Definition A udio BIOS Considerations 4.1.2.4 Codec Initiali zation Sample Code This section shows an example of code implementation of the Int el® HD Audio co dec initialization sequence. ;---------- --------- ---------- ----------- ----------- ---------- --------- ------ ; ; Procedure:Initializ eI[...]

118 Programmer’s Reference Manual Intel® High Definition Audio BIOS Conside rations ; dx is the map of SDI pi ns, and the bits will be cleared as the ; associated codecs are serviced mov dx, word ptr es:[ebx+HDAudio_MMIO_STATESTS] InitCurrentCodec: dec cx btr dx, cx ; Test for 'cx'th codec jnc NextSDI ;--------- -------- ----------- --[...]

Programmer’s Reference Manual 119 Intel® High Definition A udio BIOS Considerations ; (bits 31:28) respre sents the codec addre ss (CAd). ; c. Set bits 1:0 of the IRS register at AZBAR+68h[1:0] ; d. Poll ICS register bits at AZBAR+68h[1:0] until they return 10b indicating ; the ver b has been sent to the cod ec and response data from codec is no[...]

120 Programmer’s Reference Manual Intel® High Definition Audio BIOS Conside rations ; the verb has b een sent to the codec and response da ta from codec is now valid. PollDataValid: mov al, byte ptr es:[ebx+HDAudio_MMIO_ICS] cmp al, 10b jne P ollDataValid ; e. Read IR register at AZBAR+ 64h, the dword d ata is the VendorID/ Device ; ID value ret[...]

Programmer’s Reference Manual 121 Intel® High Definition A udio BIOS Considerations t e s t w o r d ptr es:[ebx+HDAudio_MMIO_ICS], HDAudio_MMIO_ICS_ICB j z I C BB i t 2 ; Po l l IC B bi t u n ti l i t re t ur ns 0 (n e e d t o change”HDAudio” in this command to HDAudio? loop PollICBB it2 ; Add er ror handling code here ICBBit2: pop cx ; b. W[...]

122 Programmer’s Reference Manual Intel® High Definition Audio BIOS Conside rations ; ; Description:Detects whether the ven dor and device ID of the current codec ; is supported bas ed on whether the value is found at the start ; of any of the codec verb tables. ; ; Input:EAX - Vendor and de vice ID of th e current codec ; ECX - Current codec ad[...]

Programmer’s Reference Manual 123 Intel® High Definition A udio BIOS Considerations jmp CodecC heckDone FoundValidCodec: mov edx , dword ptr cs:[si+ VerbHeaderSize] ; Get firs t verb shr edx, 28 cmp edx, ecx ; Is the c odec address correct? jne CodecNotV alid add si, 6 call GetVerbTab leSize ; Codec has valid DID/VID and addr CodecCheckDone: pop[...]

124 Programmer’s Reference Manual Intel® High Definition Audio BIOS Conside rations ;--------- -------- ----------- ----------- ---------- --------- ---------- -------- GetverbTableSize PROC NEAR PUBLIC push ebx mov cl, byte ptr cs:[si] ; al = Front panel support bit inc si or cl, cl mov cx, word ptr cs:[si] ; cx = length of rear panel table jz [...]

Programmer’s Reference Manual 125 Intel® High Definition A udio BIOS Considerations 4.1.3 Intel ® High Definition Audio Co dec Initialization on S3 Resume According to Microso ft, the SSID response from the Intel ® HD Audio codec mu st be consistent at any point the OS may read the value. Similarly ot her codec confi guration information must [...]

126 Programmer’s Reference Manual Intel® High Definition Audio BIOS Conside rations 4.3 Intel ® High Definition Audio PME Event Although it is a PCI Express Root Complex Integrated endpoint, the Int el® HD Audio co ntroller in the ICH7 is not capable of supporting the native PME software mod el. Its PME is supported in the same manner as a PCI[...]

Programmer’s Reference Manual 127 Intel® High Definition A udio BIOS Considerations } // End AZAL } // End Device PCI0 } // End _SB scope Scope (_GPE) // GPE event handlers { Method (_L05, 0) // Intel® HD Audio/ AC97 PME event handler { // If Intel® HD Audio is the enabled controller // Notify ( _SB.PCI0.A ZAL, 0x02)// notify wake event // [...]