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Intel 41210 manuel d'utilisation

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Table des matières du manuel d’utilisation

  • Page 1

    Intel® 41210 Serial to Parallel PCI Bridge Design Guid e May 2005 Order Num ber: 27880 1-004[...]

  • Page 2

    ii Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide INFORMA TION IN THIS DOCUM ENT IS PROVIDE D IN CONNECTION WIT H INTEL ® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTO PPEL OR OTHERWISE, T O ANY INTELLECTUAL PROPERTY RIG H TS IS GRANTED BY THIS DOCUMENT . EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITI ONS OF SALE FOR SUCH PR[...]

  • Page 3

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide iii Contents Contents 1 About This Document ................... ............. ................... ............. ................... ............. ................... 7 1.1 Terminology and Defin itions . ................... ............. ................... ............. ...................[...]

  • Page 4

    iv Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide Contents 8.6.1 Embedde d PCI-X 133 MHz ..... ............. ................... ............. ................... ............. . 39 8.6.2 Embedde d PCI-X 100 MHz ..... ............. ................... ............. ................... ............. . 40 8.6.3 PCI-X 66 MHz Embedded To p[...]

  • Page 5

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide v Contents 22 PCI 33 MHz Embedded M ode Rou ting Topolo gy ......... ............. ................... ............. ................. 4 3 23 PCI Ana log Voltage Fi lter Circui t ............... ............. ................... ................... ............. ............. .... 50 24 PC[...]

  • Page 6

    vi Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide Contents This page intentionally left blank .[...]

  • Page 7

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 7 About This Document 1 Thi s d ocu m ent provi des l a you t inf orma tion a nd gu idel ines for de sign ing p latf orm o r add- in bo ard applications with the Intel ® 41210 Serial to Paralle l PCI Bri dge (also c alled the 41210 Bridge). I t is recommended th at this do cumen t be used[...]

  • Page 8

    8 Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide About This Document PCB Printed circuit board. Example manufacturing process consists of the following steps: • Consists of alt ernating layers of core and prepreg stacked • The finished PCB is heated and cured. • The via hol es are drilled • Plating covers holes and outer surfac[...]

  • Page 9

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 9 Introduction 2 The Intel ® 41210 Serial to Parallel PCI Bridge integrates tw o PCI Exp ress-to -PCI bridges. Each bridge f ollows the P CI-to-PCI Bridge progr amming mod el. The PCI Ex press por t is complia nt to the PCI Expr ess Specification , Revision 1.0. The two PCI bus interfaces[...]

  • Page 10

    10 Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide Introduction • T unable i nbound read prefetch algo rithm for PCI MRM/MRL commands • Local initialization v ia SMBu s • Secondary side initializat ion via T ype 0 configuration cycles. 2.3 Powe r Managemen t • Support for PCI Expr ess Acti ve State P ower Manageme nt (ASPM) L0s [...]

  • Page 11

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 11 Introduction 2.4.2 Micro control ler Connections to the 41210 Bridge The following diagr am shows the SMB interface f r om the 4121 0 Bridge to the micr ocontroller . Figure 1. 41210 Bridge Microcontroller Block Diagram B2707-01 Configuration Register Address Space Intel fi 41210 Bridg[...]

  • Page 12

    12 Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide Introduction 2.5 JT AG • Compliant with IEEE S tandar d T est Access Port and Bo undary Sca n Ar chitectur e 1 149.1a 2.6 Related Documents • Intel® 41210 Serial to Parallel PCI Bridge Design Specifi cati on (EDS) , Revision 1.0. • PCI Expr ess Specification , Revi sion 1.0, from[...]

  • Page 13

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 13 Introduction 2.7 Int el ® 41210 Serial to Parallel PCI Bridge Applications This sectio n provide s a block di agram for a t ypical the 41 210 Bridge application. This app lication shows a PCI-E adapter card with two Dual 2Gb Fi bre Channel controllers. Each of the PCI-X bus segments is[...]

  • Page 14

    14 Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide Introduction This page intentionally le ft blank .[...]

  • Page 15

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 15 Package Information 3 3.1 Package Specification The 41210 B ridge is in a 567-b all FCBGA p ackage, 31m m X 31mm in size, with a 1.27mm ball pitch. Figure 5. T op View - 41210 Bri dge 567-B all FCBGA Pac kage Dimen sions Pkg_567- Bal l _Top 0. 550 i n . H a n d lin g E xcl usi on Ar e a[...]

  • Page 16

    16 Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide Package Information Figure 6. B ottom V iew - 41210 Bridge 567-Ball FCBGA Package Dimensions B2711-01 31.00 – 0.100 31.00 – 0.100 29.2100 8X 14.605 23X 1.270 23X 1.270 4X 15.500 4X 0.635 (0.895) 0.200 -B- -A- A + + A B C D E F G H J K L M N P R T U V W Y AA AB AC AD 3 5 7 9 11 13 15[...]

  • Page 17

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 17 Package Informatio n Figure 7. Side View - 4121 0 Bridge 5 67-Ball FCBG A Package Dim ensions B2712-01 1.170 – 0.085 H 1.940 – 0.150 J Die FC BGA Substrate 0.100 – 0.025 Die Solder Bumps Underfill Epoxy 0.74 – 0.025 Detail H Scale 5:1 Detail J Scale 5:1 0.600 – 0.100 BGA Solde[...]

  • Page 18

    18 Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide Package Information This page intentionally left blank.[...]

  • Page 19

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 19 Power Plane Layout 4 This chapter provides deta ils on the decoupl ing and volt age planes needed t o bias the 4121 0 Bridge package. 4.1 41210 Bridge Deco upling Guidelin es Ta b l e 2 li sts the decoupling guidelines for the 412 10 Brid ge. Figur e 8 and Figur e 9 provide the decoupli[...]

  • Page 20

    20 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Power P lane Layout Figure 9 . D ecoupling Placement for PCI/P CI-X 1.5V an d 3.3V V oltage Planes B2714-01 Capacitor Legend 0603-0.1 F 0603-1 F 1206-10 F[...]

  • Page 21

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 21 Power Plan e La yout T abl e 2. 41210 Bri dge Decoup ling Guidel ines 4.2 S plit V olt age Planes There are two 1.5V v oltage pl anes that supp ly power to th e 41210 Bridge: • VCC15:1 .5V ±5% (1.5V core vol tage) • VCCPE:1.5V ±3% (1.5 V PCI Expres s voltag e) The 41210 B ridge co[...]

  • Page 22

    22 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Power P lane Layout Note: Linear volt age regulator s are reco mmended when us ing 1.5 V olt power supplie s. Figure 1 0. 4121 0 Bridge S ingle-Laye r Split V oltage Plan e B2715-01 re Core PCI Express[...]

  • Page 23

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 23 41210 Bridge Reset and Power Timing Considerations 5 This chapter describes the 41210 Bridge reset tim in g considerations. 5.1 A_RST#,B_RST# an d PERST# Timing Requirement s The PCI-X Specification requires that ther e is a 100ms delay fro m valid power ( PE RST# ) to reset deassertion[...]

  • Page 24

    24 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide 41210 B ridge Reset a nd Pow er Timing Consid erations This page intentionally le ft blank.[...]

  • Page 25

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 25 General Routing Guidelines 6 This chapter pr ovides some basi c routing gu idelines for layou t and design of a print ed circuit board using th e 41210 Br idge. The high-s peed clockin g required when designing w ith the 4121 0 Bridge requires special attention to si gnal integrity . In[...]

  • Page 26

    26 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide General Routing Guidelines • A void slots in the gro und plane. S lots increas es mutual inductance th us increas ing crosstalk. • Make sure th at ground pl ane surro unding connect or pin fields are n ot completely cleared out. When this area is completely cleared out, aroun d the c[...]

  • Page 27

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 27 General Routing Guidelines 6.4 Power Distribution and Decoup ling Have ample deco upling to g round, for the power p l anes, to minimize the ef fects of the switching currents. Thr ee types of decoupling are: th e bulk, the high- frequency ceramic, and th e inter-plan e capacitors. • [...]

  • Page 28

    28 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide General Routing Guidelines Note: Using stripline transmiss ion lines may give better results than microst rip. This is due to th e difficulty o f precisely contro lling the dielectric cons tant o f the solder mask, and the difficulty in limiting the plated thick ness o f microstrip condu[...]

  • Page 29

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 29 Board Layout Guidelines 7 This chapter pr ovides details on adap ter card stack up suggestions. It is highly r ecommended that signal integrity simulations be run to v erify each 4 121 0 Bridge PCB lay out especially if it deviates from the recommendations listed in these desi gn guidel[...]

  • Page 30

    30 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Board Layout Guide lines NOT E: Each interface will set the trace spacing bas ed on its signal integrity of differential impedance requirements. For the pur poses of the building the trans mission line m odels, it is assumed the art work is very accurate and therefore a constant. Thus, a[...]

  • Page 31

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 31 PCI-X Layout Guidelines 8 This chapt er describes s everal factors to be consid ered with a 412 10 Brid ge PCI/PCI-X des ign. These include the PCI IDSEL, PC I RCOMP , PCI Interrupts and PCI arbitration. 8.1 Int errupt s PCI Express provides interrupt messages that emul ate the legacy w[...]

  • Page 32

    32 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI-X Layo ut Guidelines Note: PCI Express A ssert_IN Tx/Deassert _INTx messag es are not i nhibited by the BME bi t. 8.1.1 Interrupt Routing for Devices Behind a Bridge Given the legacy inter rupt shari ng scheme s hown in Ta b l e 4 , to get the best legacy interrupt performance (by re[...]

  • Page 33

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 33 PCI-X Layout Guidelines • Priority group for a master (i.e., whether a master is in low priority group o r high priority grou p). • Bus parking on last PCI agent or the bridge. By defaul t the arbiter parks t he bus on th e bridge and dr ives the A/D, C/BE# an d P AR lines to a know[...]

  • Page 34

    34 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI-X Layo ut Guidelines T able 7. PCI/PCI-X Frequency/Mode Stra ps Note: All signals s ampled on the rising ed ge of PERST # . 8.3.1 PCI Pullup Resistors Not Required PCI control signa ls on the 4121 0 Bridge do NOT requi re pullup r esistors on the adapte r card to ensure that they co [...]

  • Page 35

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 35 PCI-X Layout Guidelines B_CBE#[7 :4], B_DEVSEL#, B_FRA ME#, B_INT A#, B_INT B#, B_IN TC#, B_IN TD#, B_IRDY#, B_PERR#, B_ P AR, B_ GNT#[5:0], B_R EQ #[ 5:0], B_LOCK#, B_P AR64, B_REQ 6 4#, B_SE RR#, B_ STOP# , and B_ TRDY#. 8.4 PCI Clock Layou t Guidelines The PCI-X Addendum to the PC I [...]

  • Page 36

    36 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI-X Layo ut Guidelines Figure 17. PCI Clock Distribution and Matching Requireme nts B1499-04 PCI Device 1 PCI Device 2 PCI Device 3 a X0 A_CLKO0 PCI Bus A_CLKIN A_CLKO1 A_CLKO2 A_CLKO3 A_CLKO4 A_CLKO6 22 22 22 22 22 X3 X1 d X2 PCI Device 4 22 X4 PCI Device 5 Intel ® 41210 Bridge Notes[...]

  • Page 37

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 37 PCI-X Layout Guidelines T able 8. PCI-X Clock Layout Requirement s Summary Param e ter Routing Gui delines Signal Group PCI Clocks B_CLKO[6:0], A_CLK[6:0] Reference Pl ane Route over unbroken gr ound or power plane S t ripline T race Width 4 mils S tripline T race Sp acing: Separation b[...]

  • Page 38

    38 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI-X Layo ut Guidelines 8.5 PCI -X T o pology Layo ut Guidelines The PCI-X Addendum to the PC I Local Bus Specifica tion , Revision 1.0b compliant, reco mmends the followin g guideli nes for t he numb er of l oads for you r PCI-X des igns. A ny d eviation f rom t hese maximum values r e[...]

  • Page 39

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 39 PCI-X Layout Guidelines 8.6.1 Embedded PCI-X 133 MHz This section lists the ro uting recommenda tions fo r PCI-X 133 MHz without a slot. Figure 1 8 shows the bl ock diagr am of this t opol o gy and Ta b l e 1 0 descr ibes the ro uting recomm endations. Figure 18. Embedded PCI-X 133 MHz [...]

  • Page 40

    40 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI-X Layo ut Guidelines 8.6.2 Embedded PCI-X 100 MHz This section lists the embedded routing recommendations for PCI-X 100 MHz. Figur e 19 show s the block di agram of thi s topol ogy and Ta b l e 1 1 descr i bes the rout i ng re com mend atio ns . Figure 19. Embedded PCI-X 100 MH z T o[...]

  • Page 41

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 41 PCI-X Layout Guidelines 8.6.3 PCI-X 66 MHz Embedded T opo logy Figu re 20 and Ta b l e 1 2 provi de routing det ails for a topology w ith an embedded P CI-X 66 MHz application. Figure 20. PCI-X 66 MHz Embedded Routing T opology T able 12. PCI-X 66 MHz Embedded Routing Recommendations Pa[...]

  • Page 42

    42 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI-X Layo ut Guidelines 8.6.4 PCI 66 MHz Embedded T opology Figur e 21 an d Ta b l e 1 3 provide routi ng details f or a topolo gy with an embedded PCI 66 MHz design. P Figure 21. PCI 66 MHz Embedded T opology T able 13. PCI 66 MHz Embedded T able Parameter Routing Guidelin e for Lower [...]

  • Page 43

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 43 PCI-X Layout Guidelines 8.6.5 PCI 33 MHz Embedded Mode T opolog y Figu re 22 and Ta b l e 1 4 provi de routing det ails for a topology w ith an embedded P CI 33 MHz design. Figure 22. PCI 33 MHz Embedded Mode Routing T opology T able 14. PCI 33 MHz Embedded Routing Recommendations Param[...]

  • Page 44

    44 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI-X Layo ut Guidelines This page intentionally le ft blank.[...]

  • Page 45

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 45 PCI Express Layout 9 This section provid es an overview of the PC I-Express stackup r ecommended based o n Intel presimulation results. For addition a l information, refer to the Intel® 4121 0 Serial to Par allel PC I Bridge Developer’ s Manual or th e PCI Expr ess Specification , Re[...]

  • Page 46

    46 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI Express Layo ut 9.2 PCI-Express Layout Guidelin es The layout guidel ines for PCI-Express were deve loped for an adapter card topologies. The models and assumptions used in development of t hese guidelines were as follows: • Add-In Card S tackup: 60 Ω single- ended impeda nce •[...]

  • Page 47

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 47 PCI Ex press Layou t Receive Tr ace Length (Card edge finger to 41210 Bridge receiver pin 1.0” min - 6.0” max Length Matching Requirements: T otal allowable intra-pair length mis-m atch must not ex ceed 25 mi ls. Each routing segment should be matched as clos e as possible. T otal s[...]

  • Page 48

    48 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI Express Layo ut This page intentionally le ft blank.[...]

  • Page 49

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 49 Circuit Implementations 10 This chapt er describes 4 1210 Bridge circuit implementat ions. 10.1 41210 Bridg e Analog V olt age Filters The Intel® 41210 Serial to Parallel PCI Bridge requires several extern al analog voltage filter circuits to be placed on the system boar d, thr ee for [...]

  • Page 50

    50 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Circuit Implementations 10.1.1 PCI An alog V olt age Filters The following filter circuit is recommended fo r the PCI interface. Three separate, identical versions of this circuit should be placed on the system board, one for each VCCAPCI[2:0] pin on the Intel® 41210 Serial to Parallel [...]

  • Page 51

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 51 Circuit Implementations Figure 24. PCI Express Analog V oltage Filter Circuit Note: . • Place C as close as possible to p ackage pin. • R must be placed between VC C 15 and L. • Route VCCAPE and V SSAPE as diff erential traces. • VCCAPE and VSSAPE traces must be groun d referenc[...]

  • Page 52

    52 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Circuit Implementations Figure 25. Bandgap Analog V oltage Filter Circuit Note: . • Place C as close as pos sible to package p in. • R must be placed between the 2.5 V supply and L. • Route VCCBGPE and VSSBGPE as differ ential traces. • VCCBGPE and VSSBGPE traces must be ground r[...]

  • Page 53

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 53 Circuit Implementations 10.2 Intel® 41210 Serial to Parallel PCI Bridge Referenc e and Comp ensation Pins There are three compensation pins on Intel® 41210 Serial to Parallel PCI Bridge. PE_RCOMP[1:0] are two separate pins that provi de vo ltage compensation for the PCI Express interf[...]

  • Page 54

    54 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Circuit Implementations 10.2.1 SM Bu s The SMBus interface does not have con figuration regist ers. The SMBus address is set by the states of pins SMBUS[5] and SMBUS [3 :1] when PE RST# is asserted as described in Ta b l e 1 7 . Refer t o Section 2.4 f or details on how to use the SMBus [...]

  • Page 55

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 55 41210 Bridge Customer Reference Boards 11 This chapt er describes t he 41210 Bridge Custo mer Reference Board (CR B). 1 1.1 Board St a ck-up The proposed layout of the PCB is eight layers with the followin g stack up: • Sign a l #1 (T op / C omp o nent Si d e) • Ground Pl ane : GND [...]

  • Page 56

    56 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide 41210 B ridge Custome r Referenc e Boards 11 . 2 M a t e r i a l The following materials are us ed with the 41210 Brid ge CRB: • FR-4, 0.0 62 in. +/- .0 07, 1.0 oz Copper Power/G ND. • Full len gth PCI Raw C ard (3.3V Universal) 6.2” high x 7.00” l ong max with ½ inch cut away .[...]

  • Page 57

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 57 41210 Bridg e Customer Re ference Bo ards 1 1.4 Board Outline Figu re 27 provides the mechanical outline of the 41210 Bridge C RB. Figur e 27. Mechanic al Outline of the 41210 Bridge B2728 -01 U1 Intel fi 41210 Bridge[...]

  • Page 58

    58 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide 41210 B ridge Custome r Referenc e Boards This page intentionally left blank .[...]

  • Page 59

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 59 Design Guide Checklist 12 This checkl ist highlight s design consideratio ns that s hould be review ed prior t o manufacturing an adapter card that implemen ts the 41210 Brid ge prod uct. The items contained within this checklist attempt to address important connections to these devices[...]

  • Page 60

    60 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Design Guide Checklist T able 20. PCI/PCI-X Interface Signals Signals Recomm endations Reason/Impact X_AD[63:32] X_CB E[7:4]# X_DE VSEL# X_FRAM E# X_IRDY# X_TRDY# X_STOP# X_PERR# X_SERR# X_REQ [5:0]# X_GNT[5:0]# X_LOCK# X_P AR X_P AR64 X_ACK64# X_REQ 64# No external pullup resistors req [...]

  • Page 61

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 61 Design Guide Checklist A_M66E N B_M66E N Controls frequency of the PCI segment when running in conventional PCI mode (33 MHz or 66 MHz): 0 = 33 MHz PCI 1 = 66 MHz PCI • Pull-up using a 8.2K Ω resistor when the P CI bus is to operate at 66 MH z and not already pulled up by system boa[...]

  • Page 62

    62 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Design Guide Checklist T able 21. Miscellaneous Signals Signals Recommend ations Reason/Impact RSTIN# Used for debug purposes. C onnect to VCC33 through an 8.2K Ω pullup resistor for normal operation. A_STRAP0, A_STRAP1, A_STRAP2, A_STRAP6 , B_STRAP0, B_STRAP1, B_STRAP2, B_STRAP6 RESER[...]

  • Page 63

    Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 63 Design Guide Checklist T able 23. Power and Ground Signals Signa l Recommendat ions Reason/Im pa ct RCOM P 100 Ω ±1% (1/4 W) pulldown resistor to ground. The trace impedanc e of this signal sh ould be < 0.1 Ω. Analog compens ation pin for PCI. 0.75V nom inal. VCC15 Connect to 1.[...]

  • Page 64

    64 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Design Guide Checklist T able 24. JT AG Signals Signal Recomm endations Reason/Impact TCK If not used for JT AG , leave as No Connect Internal pull-up TDI If not use d for JT AG , leave as No Connect Internal pull-up TDO I f not used for J T AG , leav e as No Connect I nternal pull-up TM[...]