Intel 82555 manuel d'utilisation

82555 10/100 Mbps LAN Ph ysical La y e r Inter face Networking Sili con Datasheet Product Features ■ Optimal in tegration for lower cost solutions — Integrated 10/100 Mb ps single chip physical layer interf ace solution — Complete 10/100 Mbps MII compliance with MDI supp ort — Ful l dupl ex ope ration in 10 Mb ps and 100 Mbps mo des — IEE[...]

82555 — Networking Silicon ii Datasheet Re vi s ion His t ory ■ Low po wer consumptio n — T ypical total solution p o wer includi ng all resistors and magnetics: - 275 mA 100B ASE-TX - 230 mA 10B ASE-T - 250 mA Au to-Negotiation — 300 mA maxim um total solu t ion po wer in DTE (adapter) mod e — Po wer-do wn of 10B ASE-T/100B ASE- TX secti[...]

Datasheet iii Networking Silicon — 82555 Cont ents 1.0 INTRODUCTION ................... ............. .................... ............ .................... ............. ............... .......... 1 1.1 Functiona l Overview . ............. .................... ................... ............. ................... ............. ...... 1 1.2 Compl[...]

82555 — Networking Silicon iv Datasheet Contents 5.3.3 10BASE-T Error Detectio n and Reporti ng ......... ............. .................... ....... 22 5.4 10BASE- T Collision Detec tion.. .................... ............ .................... ............. ................... . 22 5.5 10BASE- T Link Integrity .................. .................[...]

Datasheet 1 Networking Silicon — 82555 1.0 In tr oduc tion The 82555 is a h ighly inte grated, phy sical layer interface solutio n designed for 1 0 and 100 Mbps Ethernet systems based on the IEEE 10B ASE-T and 100B ASE-TX specif icatio ns. 100B ASE-TX i s an IEEE 802.3 p hysical layer specif ication for use o ver two p a ir s o f Cat e gory 5 uns[...]

82555 — Net working Silicon 2 Datasheet The 82555 also complies with the IEEE 802.3u Auto-Ne gotiation and the IEEE 802.3x Full Duple x Flo w Control sections. Th e MA C interface on the 825 55 is a supers et of the IEEE 802.3u Media Independent In terface (MI I) standard.[...]

Datasheet 3 Networking Silicon — 82555 2.0 Arc hitectural Over view The 82555 is an adv anced co mbination of both di gital and analog logic which combine to p rovide a functional stack between the Med ia Independent In terface (MII) an d the wire through the magnetics. Figure 2 shows a gen eral bloc k diagram of t he 82555 co mponent. 2.1 100 Mb[...]

82555 — Net working Silicon 4 Datasheet • Receiv e: The 82555 takes recei ve analog ML T -3 data from the recei ve dif ferential pair and con verts it into a di gital 12 5 Mbps st ream, reco vering bot h clock an d data signals. 2.2 10 Mbps M ode The 82555 o perat i on in 1 0B ASE-T mode is similar to th e 82555 operation in 100BAS E-TX m ode. [...]

Datasheet 5 Networking Silicon — 82555 The 82555 p rovides a g lueless interfa ce to Intel componen ts such as the 82557 Fast E thernet Controller , as well as any MII compati ble device. Figure 4 shows a sch ematic-lev el diagram of the 82557 F as t Ethernet co ntroller implemen tation connected to the 8 2555 using the MI I interface. 2.3 Media [...]

82555 — Net working Silicon 6 Datasheet TXERR T ransmit Error (repeater mode only) From RIC TXC Y es T able 1. 82 555 MII Signal Name Description Direction Cloc k Reference MII Si gnal Supported by th e 82555?[...]

Datasheet 7 Networking Silicon — 82555 3.0 Pin Definitio ns All acti ve digital pins are defined to hav e tran sist or-to-transistor logic voltage le vels e xcept the X1 and X2 crystal signals. The transmit dif ferential and receiv e dif ferential pins are specif ied as analog output s and i nputs, r especti vel y . The fi gure be lo w sho w the [...]

82555 — Net working Silicon 8 Datasheet Pin allo cation is based o n a 100-l ead quad fl at package. Al l pin locations are base d on prin ted circuit board lay out and o ther desi gn const raints. 3.1 Pin T ypes 3.2 C lock Pins 3.3 T wisted P air Ethernet (TPE) Pins 3.4 Med ia Independent In terface (MII) Pins Pin T ype Description I This type o[...]

Datasheet 9 Networking Silicon — 82555 3.5 Media Access Contr ol/Repeater Interface Contr ol Pins RXC 90 O Receive Cloc k. The Receive Cloc k may be either 25 MHz or 2.5 MHz depending on the 82555’s operating speed (25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps). The Receive Clock is recovered directly from incoming data and is continuous into th[...]

82555 — Net working Silicon 10 Datasheet 3.6 LED Pins 3.7 External Bias Pins Note: The resistor v al ues described for the ex ternal bias pins are on ly recommended v alues and may requir e to be f ine tuned fo r v arious desi gns. TXRD Y (T OUT) 4 O This pin is multiple xed and can be used f or one of the f ollowing: T ransmit Ready . If full du[...]

Datasheet 11 Networking Silicon — 82555 3.8 Miscellaneous Contr ol Pins Symbol Pin T yp e Name and Function RESE T 1 I Reset. The Reset signal is activ e high and resets the 82555. A reset pulse width of at least 1 µ s should be used. FRC100 (MACTYP) 51 I T his pin is multiple xed and can be used for one of the follo wing: Force 1 00/10 Mbps. In[...]

82555 — Net working Silicon 12 Datasheet 3.9 P o wer and Ground Pins Symbol Pin T ype Name and Function VCC 7, 9, 15, 17, 19, 27, 29, 31, 36, 38, 40, 45, 58 , 62, 64, 66, 73, 75, 83, 88, 93, 98 I P o wer : +5 V ± 5% VSS 3, 8, 10, 14, 16, 18, 20, 26, 28, 30, 32, 35, 37, 39, 41, 46, 49, 53, 57, 61, 63, 65, 67, 72, 74, 78, 84, 89, 91, 94, 99 I Grou[...]

Datasheet 13 Networking Silicon — 82555 4.0 100B ASE-TX A dapter Mode Operatio n 4.1 100B ASE-TX T ransmit Cloc k Generation A 25 MHz crystal or a 25 MHz oscillator is used to dri ve the 8255 5’ s X1 and X2 pi ns. The 82555 deriv es its internal trans mit digit al clocks from this crys tal or oscillator inpu t. The T ransmit Cl ock signal is a [...]

82555 — Net working Silicon 14 Datasheet 4.2.2 100B A SE-TX Scramb ler and ML T -3 Encoder Data is s crambled i n 100B ASE-TX in o rder to red uce electromagnetic em issi ons during long transmissions of high-frequen cy data codes. The scrambler log ic accepts 5 bits from the 4B/5B encoder block an d presents the scrambled data to the ML T -3 enc[...]

Datasheet 15 Networking Silicon — 82555 maintained (either p ositiv e, n eg ativ e o r zero). When an NR Z “1” arri v es at th e input of the encoder , the ou tput ste ps to the next le vel. The orde r of steps is negative-zero- posit iv e- zero wh ich co ntinues periodically . The figure belo w illu strates thi s process. 4.2.3 100BASE-TX T [...]

82555 — Net working Silicon 16 Datasheet 4.2 .4 T ran smi t D riv er The transmit dif ferential lines are implemented with a d igital slope cont rolled current dri ver that meets the TP-PMD sp eci fications. Current is s unk from the isolation transfo rmer by the transmit differential pins. The conceptual transmi t differential wa veform for 100 [...]

Datasheet 17 Networking Silicon — 82555 4.3.1 Adaptive Equaliz er The distorted ML T -3 signal at the end of the wire is restored b y the equalizer . The equalizer performs adaptation based on the shape of the recei ved signal, equalizin g the signal to meet superior Data Dependent Jitter p e rformance. 4.3.2 Receive C loc k and Data Re covery Th[...]

82555 — Net working Silicon 18 Datasheet 4.5 100BASE -TX Link Integrity and Au to-Negotiation Solution The 82555’ s Auto-Negotiation func tio n automati cally co nfigures the device to the technology , media, and speed to operate with its link partner . Auto-Negotiation is widely described in IEEE specif ication 802.3u , Clause 28. The 8 2555 s[...]

Datasheet 19 Networking Silicon — 82555 The figure belo w illustrates an 8255 7/82 555/PHY -T4 solutio n in a block diagram . 4.6 A uto 10/100 Mbps Speed Se lection The MA C may either allow the 82555 to automatically select i ts operating speed or force the 82 555 into 10 Mbps or 100 Mbps mode. The Management Data Interf ace (MDI) can con t rol [...]

82555 — Net working Silicon 20 Datasheet[...]

Datasheet 21 Networking Silicon — 82555 5.0 10B ASE-T F unctionality in Adapter Mod e 5.1 10B ASE-T T ransmit Clock Generation The 20 MHz and 10 MHz clocks n eeded for 1 0B ASE-T are synthesized from th e e xtern al 25 MHz crystal or oscillator . The 82555 pro vides the transmit clock and recei ve clock to the MA C at 2.5 MHz. 5.2 10B ASE-T T ran[...]

82555 — Net working Silicon 22 Datasheet T wisted Pair Ethernet ( TPE) recei ver is greater than 585 mV and less than 3.1 V . The TP E recei ve buf fer disti nguish es valid recei ve data, link test pulses, and the idle condition, according to the requirement s of th e 10BAS E-T standa rd. The following line acti vity is determ ined to be inactiv[...]

Datasheet 23 Networking Silicon — 82555 5.7 10B ASE-T Full D uplex The 82555 s uppor ts 10 Mbps full dupl ex by di sabling the collision f unction, the sq uelch test , and the carrier sense transmit function. This allows the 82555 to transm it and recei ve simultaneously , achie ving up t o 20 Mbps of netw ork bandwi dth. The conf iguration can b[...]

82555 — Net working Silicon 24 Datasheet[...]

Datasheet 25 Networking Silicon — 82555 6.0 Repeater Mode The 82555 h as a compete set of r epeater features makin g it the ideal PHY for Class 1 ( MII) repeater designs. The 82 555 work s in repeater mod e when the RPT signal (pin 50) is high. The FRC100 signal (p in 51) dete rmines whic h type of repeater is s upported, ei ther 100B ASE-TX or 1[...]

82555 — Net working Silicon 26 Datasheet PHYs connected to the RIC. Signals TXEN, CRS, and P OR TEN are connected from each of th e 82555 devices to the specified RIC pin . The fi gure below illustrates an example of multipl e 82555s connected to a 25 M Hz (or 2.5 MHz) oscillator . Figure 9. Clock Signal Example X1 TXCLK CLK RI C PHY1 PHY2 PHY3 X[...]

Datasheet 27 Networking Silicon — 82555 7.0 Management Data Interface The 82555 p rovides status a nd accepts managem ent information thro ugh the Managemen t Data Interface (MDI) . This is accomplished through read and write operations to v arious registers in accordance with the IEEE 802.3u MII specification . 7.1 MDI Frame Structure Data read [...]

82555 — Net working Silicon 28 Datasheet The 82555 addres s can be conf igured to four 0 th rou gh 3 in DTE (adapter) mode and 0 throug h 31 in repeater mode. A special functions f o r swit ches allo ws 32 addresses to exist in rep eater mode. The management fram e structure is as follo w s: 7.2 M DI Registers MDI r egisters a re des cribed in th[...]

Datasheet 29 Networking Silicon — 82555 7.2.1.2 Regis ter 1: St atus Register Bit Defi nitions 11 P ower-Down This bit sets the 82555 int o a lo w pow er mode. 1 = P ower-down enab led 0 = P ower-down di sabled (normal operation) 0R W 10 Isolate This bit allows the 82555 to electr ically isolate the Media Independent Interf ace. When t he MII is [...]

82555 — Net working Silicon 30 Datasheet 7.2.1.3 Register 2: 82555 Id enti fier Register Bit Definitions 7.2.1.4 Register 3: 82555 Id enti fier Register Bit Definitions 7.2.1.5 Register 4: A uto-Negotiati on Ad ver tisement Register Bit Defi nitions 6 M anagement F rames Preamble Suppression 1 = 82555 will accept m anagement frames with preamble [...]

Datasheet 31 Networking Silicon — 82555 7.2.1.6 Regis ter 5: A uto-Negotiat ion Link P artner Ability Regi ster Bit Definitio ns 7.2.1.7 Regis ter 6: A uto-Negot iat ion Expansion Register Bit Definitions 7.2. 2 MD I Regist ers 8 - 15 Register s eight through f ifteen are reserv ed for IEEE. 7.2. 3 MD I Regist ers 16 - 31 Re gister num bers 16, 1[...]

82555 — Net working Silicon 32 Datasheet 7.2.3.1 Register 16: 82555 Sta tus and Contr ol Register Bit Definitions 7.2.3.2 Register 17: 82555 Special Contr ol Bit Definitions Bit(s) Name Description Default R/W 15 Flow Cont rol This bit enabl es PHY Base (Bay T echnologies) flow control. 1 = Enable PHY Base flow control 0 = Disab le PHY Base flow [...]

Datasheet 33 Networking Silicon — 82555 7.2.3.3 Regis ter 20: 10 0B ASE-TX Receive Disconnect Counter Bit Definition s 7.2.3.4 Regis ter 21: 10 0B ASE-TX Receive Erro r Frame Counte r Bit Definitions 13 F o rce T ransmit H- Pa tt e r n 1 = Force tr ansm it H-patter n 0 = Nor mal operation 0R W 12 F orce 34 T ransm it Pa tt e r n 1 = Force 34 t ra[...]

82555 — Net working Silicon 34 Datasheet 7.2.3.5 Register 22: Receive Symbol Err or Counter Bit Definitions 7.2.3.6 Register 23: 100B ASE-TX Receive Premature End of Frame Err o r Count er Bit Definitions 7.2.3.7 Register 24: 10B ASE-T Receive End of Frame Error Counter Bit Definitions 7.2.3.8 Register 25: 10B ASE-T T ransmit Jabber Detect Counte[...]

Datasheet 35 Networking Silicon — 82555 8.0 A u to-Negoti ation Function ality The 82555 s uppor ts Auto-Ne gotiation. Au to-Ne gotia tion is a scheme of au to-confi guratio n designed to man ag e interoperability in multifu nct ional LAN en v ironments. It allows two stations with “N” dif f erent modes of communication to establish a common [...]

82555 — Net working Silicon 36 Datasheet T o detect the correct technology , the two re gister fields should be ANDed tog ether to obtain the highest com mon deno minator . This v alue should then be us ed to map into a priority resoluti on table used by th e MA C dri ver to use the approp riate technology . The following is an outline of the Aut[...]

Datasheet 37 Networking Silicon — 82555 Negotiation or Parallel Detection with no data packets be in g transmitted. Co nnection is th en establ ished eit her by FLP exchange o r Pa rallel Detect ion. T he 82555 wi ll look for both FLPs and link integrity pulses. The following diagram illus trates this process. Figure 10. Auto-Negotiation and P ar[...]

82555 — Net working Silicon 38 Datasheet[...]

Datasheet 39 Networking Silicon — 82555 9.0 LED Descriptions The 82555 s uppor ts four LED pins to indicate li nk status , netw ork acti vity and network speed. • Link : This LED is of f (logic hi gh) unti l a v alid link has been detected. Aft er a v alid link has been detected, the LED will remain on (active- low). • Activity : This LED is [...]

82555 — Net working Silicon 40 Datasheet[...]

Datasheet 41 Networking Silicon — 82555 10.0 Reset and Miscella neous T est Modes 10.1 Reset When the 82555 R ESET signal is asserted (high), all internal circu its are reset. TXC and RXC should run continuousl y e ven though RESET is acti ve. The 825 55 may also b e reset through t he MDI reset bit. 10.2 Loopback When the loopback p in is being [...]

82555 — Net working Silicon 42 Datasheet The TOUT pin is controlled by dif ferent sources according to the active te st instruction. The TOUT signal is acti vated by the f alling edge of TCK. The T AP must be reset during po wer-up. Otherwise, the 82555 can w ake-up during h igh-Z mode or N AND T est, which can be harmful to th e board. The T AP [...]

Datasheet 43 Networking Silicon — 82555 11.0 Electrical Specifications and T iming P aram eters 11.1 Absolute Maxim um Ratings 11.2 General Operating Conditions 11.3 DC Characteristics 11.3.1 MII DC Chara cteristics 11.3. 2 10BASE-T V oltag e/Curren t DC Charac teris ti cs Symbol Parameter Description Min T yp Max Units T C Case temperature under[...]

82555 — Net working Silicon 44 Datasheet 11.3.3 100B ASE-TX V o ltage/ Current D C Charac teristics V ID A10 Input diff erential accept vol t age 5 MHz ≤ f ≤ 10 MHz ±585 ±3100 mV P V IDR10 Input diff erential reject v oltage 5 MHz ≤ f ≤ 10 MHz ±300 mV P V ICM10 Input common mode voltage V CC /2 V V OD10 Output dif ferential voltage RL [...]

Datasheet 45 Networking Silicon — 82555 11.4 A C Characteristics 11.4.1 MII Cloc k Specifi cations I CC100 c Current on all V CC pins 235 mA I CCT100T O T T otal supply current 275 mA a. Transmi tter curr ent is m easure d with a 1:1 tra nsformer on the cen ter tap . b. Transmi tter curr ent is m easure d with a 1:1 tra nsformer on the cen ter ta[...]

82555 — Net working Silicon 46 Datasheet 11.4.2 MII Timing P arameters Figure 14. MII Clocks A C Timing T1,T2,T3 1.5V T4,T5,T6 T4,T5,T6 Symbol P aram eter Condi tions Min T yp Max Units T7 T TXDV TXD[3:0] , TX EN, TXERR setup from the rising edge of T X C 15 25 ns T8 T TXH TXD [3:0], TXEN, TXERR hold time after the rising edge of TXC 0n s T9 T RX[...]

Datasheet 47 Networking Silicon — 82555 11.4.3 Repeater Mode Timing P arameters Figure 16. MII Receive Timing P arameters Figure 17. M II Timing P arameters: MDC/MDIO T9 T10 RXCLK RXD[3:0], RXER,RXDV Data Invalid Data Invalid Data Valid T11 T12 MDC MDIO (Input) Data Invalid Data Invalid Data Valid T13 MDIO (Output) Data Invalid Data Invalid Data [...]

82555 — Net working Silicon 48 Datasheet 11.4.4 T ransm it P acke t Timing P arameter s 11.4.5 Squelch T est Timing P a rameters Symbol Parameter Condi tions Min T yp Max Units T15 T XEN_S T TXC on first TXEN activ e to st art of frame 100 Mbps 10 12 bi ts T15a T XEN_ ST TXC on first TXEN active to st art of frame 10 Mbps 3.5 5 bits T16 T XEN_CRS[...]

Datasheet 49 Networking Silicon — 82555 11.4.6 Jabber Timing P arameter s 11.4.7 Receive P acket Tim ing Pa rameter s Figure 20. Squelch T e st Timing P a rameters TXEN COL TXCLK T20 T21 Symbol Parameter Conditio ns Min T yp Max Units T22 T JA B_ ON Jabber turn-on delay (TXEN asser ted to end of tr ansmit frame) 10 Mbps 26 ms T23 T JA B_ OF F Jab[...]

82555 — Net working Silicon 50 Datasheet 11.4.8 10BASE -T Normal Link Pulse (NLP) Timing P arameter s 11.4.9 Auto-Negotiation F ast Link Pulse (FLP) Timing P arameters T26a T R_CR SL End of receive frame to fall ing edge of CRS 10 Mbps 4.5 bits T27 T R_RX D VL E nd of receive frame to f alling edge of RXD V 100 Mbps 12 bits T27a T R_R XD VL End o[...]

Datasheet 51 Networking Silicon — 82555 11.4.10 Reset Timing P arameters 11.4.11 X1 Clock Spe c ifications T33 T FLP_B UR_NUM Number of pulses in one burst 17 33 T34 T FLP_B UR_WID FLP Burst width 2 ms T35 T FLP_BUR_PER FLP burst period 8 24 ms Symbol P arameter Conditions Min T yp Max Units Figure 24. Fast Link Pulse Timing Parameter s Fast Link[...]

82555 — Net working Silicon 52 Datasheet 11.4.12 100B A SE-TX T ransmitter A C Specificati on Figure 26. X1 Clock Specifications T38 2.5V T39 T39 0.4V 4.0V Symbol Parameter Condi tions Min T yp Max Units T40 T JIT TDP/TDN different ial output peak jitter HLS data 300 700 ps[...]

Datasheet 53 Networking Silicon — 82555 12.0 82555 P ac kag e Inf ormation This sectio n provides the ph ysical pac kaging info rmation for the 82555. T he 82555 is an 100- pin plastic Quad Flat Pack (QFP) de vice. P ackage attribu tes are provided in Ta b l e 7 and the dimens ions are sho wn in Figure 2 7 . Figure 27. Dimension Diagram for the 8[...]

82555 — Net working Silicon 54 Datasheet T Lead Angle 0.0 - 10.0 Y Coplanar ity - - 0.10 T able 7. Dime nsions for the 82555 QFP Symbol Description Min Norm Max[...]