Français dropdown-ico

Intel 845 manuel d'utilisation

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148

Aller à la page of

Les manuels d’utilisation similaires

Un bon manuel d’utilisation

Les règles imposent au revendeur l'obligation de fournir à l'acheteur, avec des marchandises, le manuel d’utilisation Intel 845. Le manque du manuel d’utilisation ou les informations incorrectes fournies au consommateur sont à la base d'une plainte pour non-conformité du dispositif avec le contrat. Conformément à la loi, l’inclusion du manuel d’utilisation sous une forme autre que le papier est autorisée, ce qui est souvent utilisé récemment, en incluant la forme graphique ou électronique du manuel Intel 845 ou les vidéos d'instruction pour les utilisateurs. La condition est son caractère lisible et compréhensible.

Qu'est ce que le manuel d’utilisation?

Le mot vient du latin "Instructio", à savoir organiser. Ainsi, le manuel d’utilisation Intel 845 décrit les étapes de la procédure. Le but du manuel d’utilisation est d’instruire, de faciliter le démarrage, l'utilisation de l'équipement ou l'exécution des actions spécifiques. Le manuel d’utilisation est une collection d'informations sur l'objet/service, une indice.

Malheureusement, peu d'utilisateurs prennent le temps de lire le manuel d’utilisation, et un bon manuel permet non seulement d’apprendre à connaître un certain nombre de fonctionnalités supplémentaires du dispositif acheté, mais aussi éviter la majorité des défaillances.

Donc, ce qui devrait contenir le manuel parfait?

Tout d'abord, le manuel d’utilisation Intel 845 devrait contenir:
- informations sur les caractéristiques techniques du dispositif Intel 845
- nom du fabricant et année de fabrication Intel 845
- instructions d'utilisation, de réglage et d’entretien de l'équipement Intel 845
- signes de sécurité et attestations confirmant la conformité avec les normes pertinentes

Pourquoi nous ne lisons pas les manuels d’utilisation?

Habituellement, cela est dû au manque de temps et de certitude quant à la fonctionnalité spécifique de l'équipement acheté. Malheureusement, la connexion et le démarrage Intel 845 ne suffisent pas. Le manuel d’utilisation contient un certain nombre de lignes directrices concernant les fonctionnalités spécifiques, la sécurité, les méthodes d'entretien (même les moyens qui doivent être utilisés), les défauts possibles Intel 845 et les moyens de résoudre des problèmes communs lors de l'utilisation. Enfin, le manuel contient les coordonnées du service Intel en l'absence de l'efficacité des solutions proposées. Actuellement, les manuels d’utilisation sous la forme d'animations intéressantes et de vidéos pédagogiques qui sont meilleurs que la brochure, sont très populaires. Ce type de manuel permet à l'utilisateur de voir toute la vidéo d'instruction sans sauter les spécifications et les descriptions techniques compliquées Intel 845, comme c’est le cas pour la version papier.

Pourquoi lire le manuel d’utilisation?

Tout d'abord, il contient la réponse sur la structure, les possibilités du dispositif Intel 845, l'utilisation de divers accessoires et une gamme d'informations pour profiter pleinement de toutes les fonctionnalités et commodités.

Après un achat réussi de l’équipement/dispositif, prenez un moment pour vous familiariser avec toutes les parties du manuel d'utilisation Intel 845. À l'heure actuelle, ils sont soigneusement préparés et traduits pour qu'ils soient non seulement compréhensibles pour les utilisateurs, mais pour qu’ils remplissent leur fonction de base de l'information et d’aide.

Table des matières du manuel d’utilisation

  • Page 1

    Intel ® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR Datasheet January 2002 Docum ent Number : 290725-002 R[...]

  • Page 2

    R 2 Intel ® 82845 MCH for SDR Datasheet Information in this document i s provided in connection with Intel ® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Term s and Conditions of Sale for such products, Inte l assumes no liabili[...]

  • Page 3

    R Intel ® 82845 MCH for SDR Datasheet 3 Contents 1 Introduction ................................................................................................................... ..... 11 1.1 Term inology and Notations ................................................................................... 11 1.2 Reference Docum ents .................[...]

  • Page 4

    R 4 Intel ® 82845 MCH for SDR Datasheet 3.5 Host-Hub Interf ace Bridge Devic e Registers (Devic e 0) ...................................... 43 3.5.1 VID—Vendor Identific ation Register (Devic e 0) .................................... 45 3.5.2 DID—Device Identific ation Register (Devic e 0) ..................................... 45 3.5.3 PCICMD?[...]

  • Page 5

    R Intel ® 82845 MCH for SDR Datasheet 5 3.6.11 SBUSN1—Secondary Bus Number Regis ter (Device 1) ...................... 86 3.6.12 SUBUSN1—Subordinate Bus Num ber Register (Device 1).................. 86 3.6.13 SMLT1—Sec ondary Master Latency Tim er Register (Device 1) ......... 87 3.6.14 IOBASE1—I/O Base Addr ess Register (Device 1) .......[...]

  • Page 6

    R 6 Intel ® 82845 MCH for SDR Datasheet 5.3 AGP Interface O verview ..................................................................................... 112 5.3.1 AGP Target O perations ....................................................................... 112 5.3.2 AGP Tr ansaction Ordering ......................................................[...]

  • Page 7

    R Intel ® 82845 MCH for SDR Datasheet 7 Figures Figure 1. Intel ® MCH Sim plified Block Diagram ................................................................. 20 Figure 2. PAM Register Attributes ..................................................................................... 60 Figure 3. Addressable Mem ory Space ........................[...]

  • Page 8

    R 8 Intel ® 82845 MCH for SDR Datasheet Revision History Revision Number Description Date -001 Initi al Releas e. Septem ber 2001 -002 • Changed the docum ent nam e to add the t erm “f or S DR”. • DW TC—DRAM W rite Therm al Managem ent Control Regis t er was incorrec t l y pl ac ed in Device 0. It s houl d be i n Devi ce 1. • DRTC—DR[...]

  • Page 9

    R Intel ® 82845 MCH for SDR Datasheet 9 Intel ® 82845 MCH Features ! Intel ® Pentium ® 4 Process or (478 pin packag e) Support  Enhanced Mode Scaleable Bus Protocol  2x Address, 4x Data  System Bus in terrupt delivery  400 MHz syst em bu s  System Bus Dyn am ic Bus In version (DBI)  32-bit sy stem bus addressin g  12 deep I[...]

  • Page 10

    R 10 Intel ® 82845 MCH for SDR Datasheet System Block Diagram Inte l ® 82801BA I/O C o ntro lle r H u b (IC H 2 ) Sys t e m Memo r y sys_blk PCI Bu s Inte l ® 82845 Memo r y C on troller H ub (MCH) 4x AG P Graphi cs Co nt ro ll er Hub Inte rfa ce 4 US B Por t s; 2 HC Ultra A TA /1 00 AC '97 Codec(s) (op tio n a l) AC' 97 2. 1 LP C I/F [...]

  • Page 11

    Introduction R Intel ® 82845 MCH for SDR Datasheet 11 1 Introduction The In tel ® 82845 Memory Controller Hu b (MCH) is des ign ed for us e w ith the Int el ® Pentium ® 4 processor in the 478-pi n packag e. The Intel ® 845 ch ipset con tains tw o m ain com ponents: th e 82845 Memory Controller Hu b (MCH) f or the h ost bridg e and th e Intel 8[...]

  • Page 12

    Introduction R 12 Intel ® 82845 MCH for SDR Datasheet Term Description GART Graphics A pert ure Re-map Table. This tabl e c ontains t he page re-map inf ormat i on us ed during AGP apert ure addres s trans l at ions. GTLB Graphics Trans lation Look -as ide Buff er. A cac he us ed to store f requently used GA RT entries. UP Uni-Proc essor. DBI Dyna[...]

  • Page 13

    Introduction R Intel ® 82845 MCH for SDR Datasheet 13 1.2 Reference Documents Document Do cument Number / Location Intel ® Pentium 4 Process or i n a 478 P in Pack age and Intel ® 845 Chi ps et Plat form for SDR Des i gn Gui de 298354 Intel ® 82801BA I/O Control l er Hub (I CH2 ) and Intel ® 82801BAM I/O Cont rol l er Hub (ICH2-M ) Datasheet 2[...]

  • Page 14

    Introduction R 14 Intel ® 82845 MCH for SDR Datasheet 1.3 Intel ® 845 Chipset Sy stem A rchitecture The MCH provides th e processor interf ace, sys tem mem ory interface, A GP interface, and h ub interface in an 845 chipset des ktop platform . T he processor interf ace supports th e Pentium 4 processor su bset of the Ext ended Mode of t he Scalab[...]

  • Page 15

    Introduction R Intel ® 82845 MCH for SDR Datasheet 15 1.4.1 Sy stem Bus Interface The MCH is optim ized for the Pentium 4 processor. The primary enhancem ents over the Com patible Mode P6 bu s protocol are: • Source sy nchronous double- pum ped address • Source sy nchronou s quad- pum ped data • Sy stem bus i nterru pt and si de-band s ign a[...]

  • Page 16

    Introduction R 16 Intel ® 82845 MCH for SDR Datasheet 1.4.3 Sy stem Memory Interface The MCH directly s upports on e chann el of PC133 SDRA M. The m emory interface supports Single Data R ate (SDR) devices w ith dens ities of 64 Mb, 128 Mb, 256 Mb, an d 512 Mb technology . T he m em ory in terface also su pports variable pag e sizes of 2 KB, 4 KB,[...]

  • Page 17

    Introduction R Intel ® 82845 MCH for SDR Datasheet 17 1.4.5 Hub Interface The 8-bit hub interf ace connects the MCH to the IC H2. All com m unication betw een the MCH an d the ICH2 occurs over the h ub interface. The h ub interface ru ns at 66 MHz / 266 MB/s. In addition to the norm al traffi c types , the follow ing comm unication also occurs ov [...]

  • Page 18

    Introduction R 18 Intel ® 82845 MCH for SDR Datasheet 1.4.7 Sy stem Interrupts The MCH su pports both Intel 8259 an d Penti um 4 processor in terru pt delivery mechani sm s. The serial A PIC int errupt m echanism is not supported. Intel 8259 support con sists of flu shin g inbou nd hub in terface w r ite buffers w hen an Interrupt Ackn ow ledge cy[...]

  • Page 19

    Signal Description R Intel ® 82845 MCH for SDR Datasheet 19 2 Signal Description This chapter provides a d e tailed d escription of the MCH signals. The signal descriptions are arranged in fun ctional groups according to th eir associated interf ace (see Figure 1). The states of all of the signals durin g reset are provided in the System Reset sec[...]

  • Page 20

    Signal Description R 20 Intel ® 82845 MCH for SDR Datasheet Figure 1. Intel ® MCH Simplified Block Diagram bl ock_di a_845 SCS[ 11: 0]# SMA[12 : 0] SBS[ 1: 0] SRAS# SCAS# SWE# SDQ[6 3:0 ] SCB[ 7: 0] SCKE[ 5: 0] RDCLKO RDCL KIN AGP Inte rfac e SBA[7 : 0] PI PE# S T[2 :0] RBF# WBF# A D _S T B [ 1:0 ], A D _ S T B [1 :0 ]# SBSTB, SBSTB# AGPRCOMP G_F[...]

  • Page 21

    Signal Description R Intel ® 82845 MCH for SDR Datasheet 21 2.1 Sy stem Bus Signals Signal Nam e Ty pe Description ADS# I/O AGTL+ A ddress S trobe: The syst em bus owner assert s ADS# t o indicat e t he f irst of two cycles of a request phas e. BNR# I/ O AGTL+ Block Next Request: B NR# i s used to bloc k the c urrent request bus owner from iss uin[...]

  • Page 22

    Signal Description R 22 Intel ® 82845 MCH for SDR Datasheet Signal Nam e Ty pe Description HD[63:0]# I /O AGTL+ Host Data: Thes e s ignals are c onnec ted to t he s ystem data bus. HD[63:0]# are t ransferred at a 4x rate. Not e that t he dat a s ignals are inverted on the s ystem bus. HDSTBP[ 3:0]# HDSTBN[ 3:0]# I/O AGTL+ Differential Ho st Data S[...]

  • Page 23

    Signal Description R Intel ® 82845 MCH for SDR Datasheet 23 2.2 SDR SDRA M Interface Signals Signal Nam e Ty pe Description SCS[11: 0]# O CMOS Chip Sele ct: These signals s elect t he particul ar S DRAM com ponent s during the act ive stat e. Note: There are two SCS# s i gnal s per SDRAM row. These si gnal s can be toggled on every ris i ng s yste[...]

  • Page 24

    Signal Description R 24 Intel ® 82845 MCH for SDR Datasheet 2.4 A GP Interface Signals 2.4.1 AGP A ddressing Signals Signal Nam e Ty pe Description PIPE# I AGP Pipelined Read: This si gnal i s assert ed by the AGP m ast er t o indicat e a full-width address is t o be enqueued on by t he target us i ng t he A D bus. One address is placed in t he A [...]

  • Page 25

    Signal Description R Intel ® 82845 MCH for SDR Datasheet 25 2.4.2 A G P Fl ow Control Signal s Signal Nam e Ty pe Description RBF# I AGP Read Buffer Full: RB F# i ndi c ates if the m as ter is ready t o ac cept previously reques t ed l ow priorit y read dat a. W hen RBF# is assert ed, the MCH is not allowed to ini t iate the ret urn low priority r[...]

  • Page 26

    Signal Description R 26 Intel ® 82845 MCH for SDR Datasheet 2.4.4 AGP Strobes Signals Signal Nam e Ty pe Description AD_STB0 I/ O (s/t/s) AGP A ddress/ Data Bus Strobe-0: This signal provi des tim ing for 2x and 4x data on AD[15: 0] and the C/B E [ 1:0]# s i gnal s . The agent t hat i s providing the data drives t his si gnal . AD_STB0# I/ O (s/t/[...]

  • Page 27

    Signal Description R Intel ® 82845 MCH for SDR Datasheet 27 Signal Nam e Ty pe Description G_DEVSEL # I/O s/t/s AGP Device Select: This s i gnal i ndi c ates that a FRAME#-based AG P t arget device has dec oded its addres s as t he t arget of t he c urrent acc es s. The MCH asserts G_DEVSEL# based on t he DRAM address range being acces s ed by a P[...]

  • Page 28

    Signal Description R 28 Intel ® 82845 MCH for SDR Datasheet 2.5 Clocks, Reset, and Miscellaneous Signals Signal Nam e Ty pe Description BCLK BCLK# I CMOS Differential Host Clock I n : These pins rec eive a different ial host c lock from t he external clock synthes i zer. Thi s cloc k is used by al l of the MCH logic t hat i s in the hos t c lock d[...]

  • Page 29

    Signal Description R Intel ® 82845 MCH for SDR Datasheet 29 2.6 Voltage Reference and Pow er Signals Signal Nam e T y pe Description HVREF Ref Host Reference Voltage: Ref erence voltage i nput for the dat a, address, and com m on cloc k signal s of the hos t A GTL+ interfac e. SDREF Ref SDRA M Reference Vol tage: Referenc e voltage input f or DQ, [...]

  • Page 30

    Signal Description R 30 Intel ® 82845 MCH for SDR Datasheet 2.7 Reset States During Reset Z Ti-state ISO Isolate inputs in inactive st ate S Strap i nput sam pled du ring as serti on or on th e de-as sertin g edg e of RS TIN# H Driven high L Driven low D Strong drive (to norm al value su pplied by core log ic if n ot otherw ise stated) I Input act[...]

  • Page 31

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 31 3 Register Description The MCH contains tw o sets of s oftw are accessi ble registers , accessed via th e host process or I/O address space: • Control regis ters I/O m apped into th e processor I/O space, w hich control access to PCI an d AGP conf iguration s pace (see Section 3.3). [...]

  • Page 32

    Register Desc ription R 32 Intel ® 82845 MCH for SDR Datasheet Term Description Reserved Registers In addition to res e rved bi t s within a regist er, the MCH cont ai ns address l oc ations i n the configurat ion space t hat are m ark ed “Reserved”. W hen a “Reserved” register l oc ation is read, a random value is ret urned. (“Reserved?[...]

  • Page 33

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 33 3.2.1 Standard PCI Bus Configuration M echanism The PCI Bus defin es a slot based "conf igu ration space" that allow s each dev ice to contain up to 8 fun ctions w ith each function containi ng u p to 256 8-bit config uration reg isters. The PCI specification def ines tw o bu[...]

  • Page 34

    Register Desc ription R 34 Intel ® 82845 MCH for SDR Datasheet Primary PCI and Downst ream Conf iguration M echani sm If the Bus Num b er in the CONF_ADDR is n on-zero, and is less than the v alue in the Host-A GP device’s Secondary Bu s Num ber register, or g reater than the v alue in th e Host-A GP device’s Subordinate Bus Number reg ister, [...]

  • Page 35

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 35 Bit Descripti ons 31 C onfiguration Enable (CFGE) . 0 = Disable. 1 = Enable. A c cess es to PCI c onfigurati on s pace are enabled. 30:24 Reserved. Thes e bi t s are read only and have a value of 0. 23:16 Bus Num b er. W hen Bus Num ber is program m ed t o 00h, the target of the conf i[...]

  • Page 36

    Register Desc ription R 36 Intel ® 82845 MCH for SDR Datasheet 3.3.2 CONF_DAT A —Configuration Data Register I/O Address : 0CFCh Default Value: 00000000h Access: R /W Size: 32 bits CONF_DATA is a 32 bit read/w rite wi ndow into conf iguration space. The portion of config uration space that is referenced by CONF_DATA is determin ed by the conten [...]

  • Page 37

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 37 3.4.1 DRAMWIDTH—DRA M Width Register Address O ffs et: 2Ch Default Value: 00h Access: R /W Size: 8 bits This register determ ines the w idth of SDRA M devices popu lated in each row of mem ory . Bit Descripti ons 7:6 Reserved. 5 R ow 5 W idth. W idt h of devices in Row 5 0 = 16-bit w[...]

  • Page 38

    Register Desc ription R 38 Intel ® 82845 MCH for SDR Datasheet 3.4.2 DQCMDSTR—Str ength Contr ol Register (SDQ and CM D Signal Groups) Memor y Address O ffs et: 30h Default Value: 00h Access: R /W Size: 8 bits This register controls the drive strength of the I/O buff ers for the DQ/DQS and CMD signal groups . Bit Descripti ons 7 Reserved. 6:4 CM[...]

  • Page 39

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 39 3.4.3 CKESTR—Strength Control Regi ster (SCKE Signal Gr oup) Memor y Address O ffs et: 31h Default Value: 00h Access: R /W Size: 8 bits This register controls the drive strength of the I/O buff ers for the CKE signal g roup. This group has tw o possible loadings depen ding on the w i[...]

  • Page 40

    Register Desc ription R 40 Intel ® 82845 MCH for SDR Datasheet 3.4.4 CSBSTR—Strength Control Regi ster (SCS# Signal Gr oup) Memor y Address O ffs et: 32h Default Value: 00h Access: R /W Size: 8 bits This register controls the drive strength of the I/O buffers f or the SCS# signal group. This group has tw o possible loadings depen ding on the w i[...]

  • Page 41

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 41 3.4.5 CKSTR—Strength Control Regi ster (Clock Signal Gr oup) Memor y Address O ffs et: 33h Default Value: 00h Access: R /W Size: 8 bits Thi s r egiste r cont rol s t he dr ive str e ngth of the I/O b uffers fo r the Cl o ck (C K ) signal gr oup inclu ding both th e CK an d CK# sig na[...]

  • Page 42

    Register Desc ription R 42 Intel ® 82845 MCH for SDR Datasheet 3.4.6 RCVENSTR—Strength Control Regi ster (RCVENOUT Signal Gr oup) Memor y Address O ffs et: 34h Default Value: 00h Access: R /W Size: 8 bits This register con trols the driv e streng th of th e I/O buff ers for the R eceive Enable Ou t sign al group (RDCLKO# signal). Bit Descripti o[...]

  • Page 43

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 43 3.5 Host-Hub Interface Bridge Dev ice Registers (Dev ice 0) Table 8 provides the regis ter address m ap for Device 0 PCI config uration space. A n “ s” in the Default Value colum n indicates that a strap determines the pow er-up default v alue for that bit. Table 8. In tel ® MCH C[...]

  • Page 44

    Register Desc ription R 44 Intel ® 82845 MCH for SDR Datasheet A ddress Offset Register Sy mbol Register Name Default Value A ccess 87–8Bh — Reserved. — — 8C–8Fh EAP Error Address Poi nt er 00000000h RO 90–96h PAM[0:6] Programm abl e A t tribute Map (7 Regis ters) 0000000000 0000h RO, R/ W 97h FDHC Fixed DRAM Hole Control 00h R/W 98–[...]

  • Page 45

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 45 3.5.1 VID—Vendor Identi fi cati on Regi ster (Device 0) Address O ff set: 00–01h Default Value: 8086h Attribute: RO Size: 16 bits The VID Register contains the v endor identification num ber. This 16-bit register combined w ith the DID Regis ter uniqu ely iden tifies an y PCI dev i[...]

  • Page 46

    Register Desc ription R 46 Intel ® 82845 MCH for SDR Datasheet 3.5.3 PCICM D—PCI Command Register (Device 0) Address O ff set: 04–05h Default: 0006h Access: R /W , RO Size 16 bits Since MCH Devi ce 0 does not phy sically reside on PCI0, man y of the bits are n ot implem ented. Bit Descripti ons 15:10 Reserved. 9 Fast Back-to-Back—RO. Not i m[...]

  • Page 47

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 47 3.5.4 PCISTS—PCI Status Register (Device 0) Address O ff set: 06–07h Default Value: 0090h Access: R O, R /W C Size: 16 bits PCISTS is a 16-bit statu s regist er that reports the occu rrence of error ev ents on Device 0s on the hub interf ace. Since MCH Devi ce 0 is the Host- to-h u[...]

  • Page 48

    Register Desc ription R 48 Intel ® 82845 MCH for SDR Datasheet 3.5.5 RID—Revision Identification Register (Device 0) Address O ff set: 08h Default Value: See table below Access: R O Size: 8 bits This register con tains th e revisi on num ber of the MCH Device 0. These bits are read only and writes to this reg ister have no eff ect. Bit Descripti[...]

  • Page 49

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 49 3.5.8 M LT—M aster Latency Timer Register (Device 0) Address O ffs et: 0Dh Default Value: 00h Access: R O Size: 8 bits The hub interf ace does not com prehend the con cept of Master L atency Timer. Therefore, th is register is not im plemented. Bit Descripti on 7:0 Hardwired to 00h. [...]

  • Page 50

    Register Desc ription R 50 Intel ® 82845 MCH for SDR Datasheet 3.5.10 A PBA SE—Aperture Base Configuration Register (Dev ice 0) Off set: 10–13h Default: 0000_0008h Access: R /W , RO Size: 32 bits The APBASE is a stan dard PCI Base Addres s regist er that is us ed to set the base of the Graphics Aperture. The stan dard PCI Config uration m echa[...]

  • Page 51

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 51 3.5.11 SVID—Subsy stem Vendor I dentification (Device 0) Off set: 2C–2Dh Default: 0000h Access: R /W O Size: 16 bits This value is used to identify the vendor of the subsy stem . Bit Descripti on 15:0 Subsy stem Vendor ID. (Default = 0000h). This f ield should be program m ed duri [...]

  • Page 52

    Register Desc ription R 52 Intel ® 82845 MCH for SDR Datasheet 3.5.14 A GPM —A GP Mi scel l aneous Configurati on Regi ster (Device 0) Address O ff set: 51h Default Value: 00h Access: R /W Size: 8 bits Bit Descripti ons 7:2 Reserved. 1 A perture A ccess Gl obal Enable (APEN). This bit is used t o prevent acc es s to t he graphi c s aperture from[...]

  • Page 53

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 53 3.5.16 DRA —DRA M Row Attribute Registers (Dev ice 0) Off set: 70–73h (DRA0–DRA3) Default: 00h Access: R /W Size: 8 bits The DRAM Row Attribute Regis ter defin es the page s izes to be us ed w hen access ing dif ferent pairs of row s. Each nibble of inf ormat ion in the DR A regi[...]

  • Page 54

    Register Desc ription R 54 Intel ® 82845 MCH for SDR Datasheet Bit Descripti on 7 Reserved. 6:4 Row A ttribute for Odd -Nu m b ered Ro w (RA ODD). This 3-bit field def i nes the page size of the corresponding row. 001 = 2 KB 010 = 4 KB 011 = 8 KB 100 = 16 KB Others = Res erved 3 Reserved. 2:0 Row At tribute f or Even- Numbered R ow (RA EVEN). This[...]

  • Page 55

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 55 3.5.17 DRT—DRA M Timing Register (Device 0) Off set: 78–7Bh Default: 00000010h Access: R /W Size: 32 bits Bit Descripti on 31:19 Reserved. 18:16 DRA M Idle Time r. This field determine s the numbe r of clocks the DRAM contro ller w ill remain in the idle s tate bef ore i t begi ns [...]

  • Page 56

    Register Desc ription R 56 Intel ® 82845 MCH for SDR Datasheet 3.5.18 DRC—DRA M Controll er M ode Register (Devi ce 0) Off set: 7C–7Fh Default: 00000000h Access: R /W , RO Size: 32 bits Bit Descripti on 31:30 Revision Number (REV)—R/W . Refl ec ts t he revision num ber of the f ormat us ed for SDRA M register def inition. Currently, t hi s f[...]

  • Page 57

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 57 Bit Descripti on 6:4 Mode Select (SM S )—R/W . These bit s selec t t he speci al operat i onal m ode of t he s ystem mem ory interf ac e. The spec i al m odes are int ended for init i al i zat i on at power up. 000 = Po st Reset state. W hen the MCH exits res et (power-up or otherwis[...]

  • Page 58

    Register Desc ription R 58 Intel ® 82845 MCH for SDR Datasheet 3.5.19 DERRSYN—DRA M Error Sy ndrome Register (Device 0) Address O ff set: 86h Default Value: 00h Access: R O Size: 8 bits This regist er is used to report th e ECC sy ndromes f or each quadw ord of a 32 byte-alig ned data quantity read from th e system memory array. Bit Descripti on[...]

  • Page 59

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 59 3.5.21 PA M[0:6]—Programmable A ttribute Map Registers (Device 0) Address O ff set: 90–96h (PAM0–PAM6) Default Value: 00h Attribute: R/W , RO Size: 8 bits The MCH allow s programm able mem ory at tributes on 13 Le gacy m emory segmen ts of variou s sizes in the 640 Kby tes to 1 M[...]

  • Page 60

    Register Desc ription R 60 Intel ® 82845 MCH for SDR Datasheet At the tim e that a hub interface or A GP accesses to the PA M region m ay occur, the targeted PA M segm ent mu st be program med to be both readabl e and w riteable. As an ex ample, cons ider BIOS that is implem ented on the expansion bu s. During th e initialization process, the BIOS[...]

  • Page 61

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 61 Table 9. PAM Regist er A ttributes PA M Reg A ttribute Bits Memory Segment Comments Offset PAM0[3:0] Reserved 90h PAM0[7:4] R R W E RE 0F0000h–0FFFFFh BIOS Area 90h PAM1[3:0] R R W E RE 0C0000h–0C3FFFh ISA Add-on B I OS 91h PAM1[7:4] R R W E RE 0C4000h–0C7FFFh ISA Add-on B I OS 9[...]

  • Page 62

    Register Desc ription R 62 Intel ® 82845 MCH for SDR Datasheet Extended System BIOS A rea (E0000h–EFFFFh) This 64 KB area is d ivided into four 16 KB segments th at can be assigned w ith diff erent attributes via PAM con trol regist er as defin ed by th e table above. System BIOS A rea ( F0000h–FFFFFh) This area is a sing le 64 KB segm ent, w [...]

  • Page 63

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 63 3.5.23 SM RAM—Sy stem M anagement RA M Control Register (Device 0) Address O ffs et: 9Dh Default Value: 02h Access: R/W , RO, R/W /L Size: 8 bits The SMRAMC reg ister cont rols how accesses to Compatible an d Extended SMRA M spaces are treated. The Open, Close, and Lock bits function[...]

  • Page 64

    Register Desc ription R 64 Intel ® 82845 MCH for SDR Datasheet 3.5.24 ESM RAMC—Extended Sy stem M gmt RA M Control Register (Device 0) Address O ff set: 9Eh Default Value: 38h Access: RO, R/W , R/W C, R/W /L Size: 8 bits The Extended SMRA M register con trols the con figu ration of Ex tended SMRAM s pace. The Extended SMRA M (E_SMRA M) mem ory p[...]

  • Page 65

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 65 3.5.25 A CA PID—A GP Capability Identifier R egister (Dev ice 0) Address O ff set: A0–A3h Default Value: 0020_0002h Access: R O Size: 32 bits This register provides standard identifier for AGP capability. Bit Descripti on 31:24 Reserved. 23:20 M ajor A GP Revision Numb er (M A JREV[...]

  • Page 66

    Register Desc ription R 66 Intel ® 82845 MCH for SDR Datasheet 3.5.26 A GPSTA T—A GP Status Register (Device 0) Address O ff set: A4–A7h Default Value: 1F00_0217h Access: R O Size: 32 bits This register reports AGP device capability/status. Bit Descripti on 31:24 Request Queue (RQ). This f i el d c ontains t he maxim um num ber of A GP com man[...]

  • Page 67

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 67 3.5.27 A GPCMD—A GP Command Register (Device 0) Address O ff set: A8–ABh Default Value: 0000_0000h Access: R /W Size: 32 bits This register provides control of the AGP operational parameters. Bit Descripti on 31:10 Reserved. 9 SideBand A ddress Enable (SBAEN). 0 = Disable. 1 = Enab[...]

  • Page 68

    Register Desc ription R 68 Intel ® 82845 MCH for SDR Datasheet 3.5.28 A GPCTRL—A GP Control Register (Device 0) Address O ff set: B0–B3h Default Value: 0000_0000h Access: R /W Size: 32 bits This register provides for additional control of the AGP interface. Bit Descripti on 31:8 Reserved. 7 GTLB Enable (GT LBEN). This bit provi des enable and [...]

  • Page 69

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 69 3.5.29 A PSIZE—A perture Size (Device 0) Address O ff set: B4h Default Value: 00h Access: R /W Size: 8 bits This register determ ines the effectiv e size of th e Graphics A perture used f or a particular MCH config uration. This regi ster can be updated by the MCH specific BIOS confi[...]

  • Page 70

    Register Desc ription R 70 Intel ® 82845 MCH for SDR Datasheet 3.5.30 A TTBA SE—Ap erture Translation Table Base Register (Device 0) Address O ff set: B8–BBh Default Value: 0000_0000h Access: R /W Size: 32 bits This register prov ides the st arting address of the Graph ics Apertu re Translation Table Base located in the sy stem m emory . T his[...]

  • Page 71

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 71 3.5.31 A MTT—A GP Interface Multi-Transaction Timer Register (Device 0) Address O ff set: BCh Default Value: 00h Access: R /W Size: 8 bits AMTT is an 8-bit register that controls the am ount of tim e that the MCH arbiter allow s A GP master to perform mu ltiple back-to-back transacti[...]

  • Page 72

    Register Desc ription R 72 Intel ® 82845 MCH for SDR Datasheet 3.5.32 LPTT—A GP Low Priority Transaction Timer Register (Device 0) Address O ff set: BDh Default Value: 00h Access: R /W Size: 8 bits LPTT is an 8-bit register sim ilar in fu nction to AMTT. T his register is us ed to control the min imu m ten ure on the AGP for low -priority data t[...]

  • Page 73

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 73 3.5.33 TOM—Top of Low Memory Register (Device 0) Address O ffs et: C4–C5h Default Value: 0100h Access: R /W Size: 16 bits This register con tains th e m axim um address below 4 GB that should be treated as a m em ory access. Note that th is regist er mu st be set to a valu e of 010[...]

  • Page 74

    Register Desc ription R 74 Intel ® 82845 MCH for SDR Datasheet 3.5.34 MCHCFG—M CH Configur ati on Regi ster (Device 0) Off set: C6–C7h Default: 0000h Access: R /W , RO Size: 16 bits Bit Descripti on 15:12 Reserved. 11 System Memory Frequency S elect. This bi t mus t be programm ed prior to m emory initializatio n. 0 = Reserved 1 = System Memor[...]

  • Page 75

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 75 3.5.35 ERRSTS—Error Status Register (Device 0) Address O ffs et: C8–C9h Default Value: 0000h Access: R /W C Size: 16 bits This register is used to report various error conditions via the hub interf ace m essages to ICH2. An SERR, SMI, or SCI error m essage m ay be g enerated via th[...]

  • Page 76

    Register Desc ription R 76 Intel ® 82845 MCH for SDR Datasheet Bit Descripti on 0 Si n g l e-bit DRAM ECC Error Flag (DS ERR). 0 = Sof tware must write a 1 t o clear thi s bit and unloc k the error logging m echanis m. 1 = A m em ory read dat a transf er had a s ingle-bit c orrectable error and t he correct ed dat a was sent f or t he ac cess . W [...]

  • Page 77

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 77 Bit Descripti on 4 SERR on A GP A ccess Outside of Graphics A perture (OOGF_SERR). 0 = Disable. 1 = Enable. Generat i on of the hub interf ac e SERR m essage i s enabled when an AGP acc es s occurs t o an address out s ide of the graphi c s aperture. 3 SERR on Inval i d A GP A ccess (I[...]

  • Page 78

    Register Desc ription R 78 Intel ® 82845 MCH for SDR Datasheet 3.5.37 SM ICM D—SM I Command Register (Device 0) Address Off set: CC–CDh Default Value: 0000h Access: R /W Size: 16 bits This register en ables variou s errors to gen erate a SMI mes sage v ia the hu b interface. Note: An error can generate on e and only one error messag e via th e[...]

  • Page 79

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 79 3.5.39 SKPD—Scratchpad Data Register (Device 0) Address O ffs et: DE–DFh Default Value: 0000h Access: R /W Size: 16 bits Bit Descripti on 15:0 Scratchpad [15:0]. These bits are R/W s t orage bi t s that have no ef fect on t he MCH funct ionality. 3.5.40 CA PID—Product Specific Ca[...]

  • Page 80

    Register Desc ription R 80 Intel ® 82845 MCH for SDR Datasheet 3.6 Bridge Registers (Dev ice 1) Table 10. provides the regis ter address m ap for Device 0 PCI config uration space. A n “ s” in the Default Value colum n indicates that a strap determines the pow er-up default v alue for that bit. Table 10. In tel ® MCH Co nfiguratio n Space (De[...]

  • Page 81

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 81 A ddress Offset S y mbol Name Default A ccess 58–5Fh DRTC DRA M Read Therm al Management Cont rol 0000000 0h R/W /L 59–FFh — Reserved — — 3.6.1 VID1—Vendor Identi fi cati on Regi ster (Device 1) Address O ff set: 00–01h Default Value: 8086h Attribute: RO Size: 16 bits The[...]

  • Page 82

    Register Desc ription R 82 Intel ® 82845 MCH for SDR Datasheet 3.6.3 PCICM D1—PCI-PCI Command Register (Device 1) Address O ff set: 04–05h Default: 0000h Access: R O, R /W Size 16 bits Bit Descripti ons 15:10 Reserved. 9 Fast Back-to-Back (FB2B)—RO. Not Im plem ent ed; Hardwired to 0. 8 SERR M essage E n abl e (SERRE1)—R/ W . This bit i s [...]

  • Page 83

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 83 3.6.4 PCISTS1—PCI-PCI Status Register (Device 1) Address O ff set: 06–07h Default Value: 00A0h Access: R O, R /W C Size: 16 bits PCISTS1 is a 1 6 -bit status register that reports the occurrence of error conditions associated w ith prim ary s ide of th e “v irtual ” PCI-PC I br[...]

  • Page 84

    Register Desc ription R 84 Intel ® 82845 MCH for SDR Datasheet 3.6.5 RID1—Revision Identification Register (Device 1) Address O ff set: 08h Default Value: See RID1 table below Access: R O Size: 8 bits This register con tains th e revisi on num ber of the MCH device 1. These bits are read only and writes to this reg ister have no eff ect. Bit Des[...]

  • Page 85

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 85 3.6.8 M LT1—M aster Latency Timer Register (Device 1) Address O ffs et: 0Dh Default Value: 00h Access: R /W Size: 8 bits This functionality is not applicable. It is describ e d here since these bits should be im plemented as a read/write to prevent stan dard PCI-PCI bridge configurat[...]

  • Page 86

    Register Desc ription R 86 Intel ® 82845 MCH for SDR Datasheet 3.6.11 SBUSN1—Secondary Bus Number Regi ster (Device 1) Off set: 19h Default: 00h Access: R /W Size: 8 bits This register identifies the bus nu mber assign ed to the second bus side of the “virtual” PCI-PCI bridge i.e. to AGP. T his number is program med by the PCI configu ration[...]

  • Page 87

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 87 3.6.13 SMLT1—Secondary Master Latency Timer Register (Device 1) Address O ff set: 1Bh Default Value: 00h Access: R /W Size: 8 bits This register controls the bus tenure of th e MCH on AGP. MLT is an 8-bit register that controls the am ount of tim e the MCH, as an AGP/PCI bus mas ter,[...]

  • Page 88

    Register Desc ription R 88 Intel ® 82845 MCH for SDR Datasheet 3.6.14 IOBA SE1—I/O Base A ddress Register (Device 1) Address O ffs et: 1Ch Default Value: F0h Access: R /W Size: 8 bits This register con trols the h osts to AG P I/O access routing based on the f ollow ing f ormu la: IO_BASE ≤ address ≤ Ι O_LIMIT Only upper 4 bits are program [...]

  • Page 89

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 89 3.6.16 SSTS1—Secondary PCI-PCI Status Register (Device 1) Address O ff set: 1E–1Fh Default Value: 02A0h Access: R O, R /W C Size: 16 bits SSTS1 is a 16 -bit status register th at reports the occurrence of error conditions associated with secondary side (i.e., AGP side) of the “ v[...]

  • Page 90

    Register Desc ription R 90 Intel ® 82845 MCH for SDR Datasheet 3.6.17 M BASE1—Memory Base A ddress Register (Device 1) Address O ff set: 20–21h Default Val u e: FFF0h Access: R /W Size: 16 bits This register con trols the h ost to AGP non -prefetch able m emory accesses routing based on the follo wing formula: MEMORY_BASE1 ≤ address ≤ MEMO[...]

  • Page 91

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 91 3.6.19 PM BASE1—Prefetchable Memory Base A ddress Register (Device 1) Address O ff set: 24–25h Default Val u e: FFF0h Access: R /W Size: 16 bits This register con trols the h ost to AGP pref etchable m emory accesses routing bas ed on the follo wing formula: PREFETCHABLE_MEMO RY_BA[...]

  • Page 92

    Register Desc ription R 92 Intel ® 82845 MCH for SDR Datasheet 3.6.21 BCTRL1—PCI-PCI Bridge Control Register (Device 1) Address O ff set: 3Eh Default: 00h Access: R O, R /W Size 8 bits This register prov ides exten sions to th e PCICMD1 regis ter that are specif ic to PCI-PCI bridges . BCTRL1 provides add itional control for the secondary interf[...]

  • Page 93

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 93 Bit Descripti ons 0 Parity Error Response Enable (PER_EN)—R/ W . Cont rols MCH’s res ponse to dat a phas e parity errors on AGP . 0 = Addres s and data pari t y errors on AGP are not report ed via the MCH hub interf ace SERR# mess aging mec hanis m. Ot her t ypes of error condit i [...]

  • Page 94

    Register Desc ription R 94 Intel ® 82845 MCH for SDR Datasheet 3.6.23 DWTC—DRA M Wri te Ther mal M anagement Control Register (Device 1) Address O ff set: 50–57h Default Value: 00h Access: R /W /L Size: 64 bits Bit Descripti ons 63:41 Reserved. 40:28 Global Write Hexword Threshold (GWHT). The 13-bit value in this f ield is m ulti pl i ed by 2 [...]

  • Page 95

    Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 95 3.6.24 DRTC—DRA M Read Thermal M anagement Control Register (Device 1) Address O ff set: 58–5Fh Default Value: 0000_0000_0000_0000h Access: R /W /L Size: 64 bits Bit Descripti ons 63:41 Reserved. 40:28 Global Read Hexword Threshold (GRHT ). The thirteen-bit value held i n t his fi [...]

  • Page 96

    Register Desc ription R 96 Intel ® 82845 MCH for SDR Datasheet This page is intentionally left blank.[...]

  • Page 97

    System Addres s Map R Intel ® 82845 MCH for SDR Datasheet 97 4 System Address M ap A sy stem based on the 845 chips et supports 4 GB of address able m emory space and 64 KB+3 of addressable I/O space. The I/O and m emory s paces are divided by sy stem configuration s oftw are into region s. The mem ory ranges are u sefu l either as s ys tem m emor[...]

  • Page 98

    System Addres s Map R 98 Intel ® 82845 MCH for SDR Datasheet Figure 4. DOS Comp atible A rea A ddress Map M onochrom e Display Adapter S pace Up per, Lower, Expans ion Card BIOS and Buffer Area 1 M B sys_add r_map_2 640 KB 704 KB 736 KB 768 KB 0A000 0h 0B000 0h 0B800 0h 0C 0000h St andar d PC I/ ISA Video M em ory ( SMM Memo r y ) Controll ed by P[...]

  • Page 99

    System Addres s Map R Intel ® 82845 MCH for SDR Datasheet 99 4.1.1 VGA and MDA M emory Space Video cards use th ese legacy address ranges to m ap a fram e buffer or a character- based video buff er. The address rang es in this mem ory space are: • VGAA 0_000A_0000 to 0_000A _FFFF • MDA 0_000B_0000 to 0_000B_7FFF • VGAB 0_000B_8000 to 0_000B_[...]

  • Page 100

    System Addres s Map R 100 Intel ® 82845 MCH for SDR Datasheet 4.1.2 PAM Memory Spaces The address ranges in this m emory space are: • PAMC0 0_000C_0000 to 0_000C_3FFF • PAMC4 0_000C_4000 to 0_000C_7FFF • PAMC 8 0_000C_8000 to _000C_BF FF • PAMCC 0_000C_C000 to 0_000C_FFFF • PAMD0 0_000D_0000 to 0_000D_3FF F • PAMD4 0_000D_4000 to 0_000[...]

  • Page 101

    System Addres s Map R Intel ® 82845 MCH for SDR Datasheet 101 4.1.4 TSEG SM M M emory Space The TSEG SMM space (T OM – T SEG to TOM) allows sy stem m anagement softw are to p artition a region of sy stem m em ory just below the top of low mem ory (TOM) that is acces sible only by sy stem manage men t sof tw are. This reg ion m ay be 128 KB, 256 [...]

  • Page 102

    System Addres s Map R 102 Intel ® 82845 MCH for SDR Datasheet 4.1.8 AGP A perture Space (Device 0 BA R) Pr o cesso rs and AGP d evice s c ommunicate thr ough a sp ecia l buffe r call e d the “gr aphi c s ape r ture ” (APBASE to A PBASE + APSIZE). This apertu re acts as a w indow in to main sy stem m emory and is defined by the A PBASE and APSI[...]

  • Page 103

    System Addres s Map R Intel ® 82845 MCH for SDR Datasheet 103 4.2.1 AGP DRA M Graphics Ap erture Memory -mapped, graphi cs data structu res can res ide in a Graphics Aperture to s ys tem m emory. This aperture is an addres s rang e defined by the APBASE and A PSIZE registers of the MC H device 0. The APBASE reg ister f ollow s the stan dard base a[...]

  • Page 104

    System Addres s Map R 104 Intel ® 82845 MCH for SDR Datasheet 4.3.1 SM M Space Definition Its addressed SMM space an d its DRA M SMM space defin e SMM space. The addressed SMM space is defin ed as the ran ge of bu s addresses used by the proces sor to access SMM space. Sy stem mem ory SMM space is defin ed as the rang e of phy sical system memory [...]

  • Page 105

    System Addres s Map R Intel ® 82845 MCH for SDR Datasheet 105 4.4 I/O A ddress Space The MCH does not support th e exis tence of any other I/O devices bes ide itself on th e sy stem bus . The MCH generates eith er hub in terface or AGP bus cycles for all processor I/O access es. The MCH contain s tw o internal reg isters in th e processor I/O spac[...]

  • Page 106

    System Addres s Map R 106 Intel ® 82845 MCH for SDR Datasheet 4.5.2 AGP Interface Decode Rules Cycles Initiate d Usi ng AGP FRA ME# Prot ocol The MCH does not support an y AGP FRA ME# access targetin g the h ub interface. The MCH claims A GP-initiated m emory read and w rite transactions decoded to the system m emory range or the Graphics Apertu r[...]

  • Page 107

    Functional Desc ription R Intel ® 82845 MCH for SDR Datasheet 107 5 Functional Description This chapter describes th e sy stem bus that con nects th e MCH to the processor, th e sy stem mem ory interface, th e AGP interface, th e MCH pow er and therm al managem ent, the MCH clocking , and the MCH sy stem reset an d power s equencin g. 5.1 Sy stem [...]

  • Page 108

    Functional Desc ription R 108 Intel ® 82845 MCH for SDR Datasheet 5.1.2 Sy stem Bus Interrupt Delivery The Pentiu m 4 proces sor su pports th e sy stem bus interru pt deliv ery; the A PIC serial bu s in terrupt delivery mechanis m i s not s upported. In terrupt- related m essag es are encoded on the s ys tem bus as “Int errupt Mess age Transacti[...]

  • Page 109

    Functional Desc ription R Intel ® 82845 MCH for SDR Datasheet 109 5.2 Sy stem Memory Interface The 845 chipset can be conf igu red to su pport PC133 SDR AM. 5.2.1 Single Data Rate (SDR) SDRAM Interface Overv iew The MCH integrates a sy stem m emory SDRAM controller w ith a 64-bit w ide interface and tw elve sy stem m emory clock signals (each at 1[...]

  • Page 110

    Functional Desc ription R 110 Intel ® 82845 MCH for SDR Datasheet 5.2.2.1 Configurat ion Mechanism For DIMMs Detection of the t ype of SDRA M ins talled on t he DIMM is s upported v ia a Serial Pres ence Detect mech anism as defi ned in the JEDEC 168- pin DIMM specification . This uses the SC L, SDA an d SA[2:0] pins on the DIMMs to detect th e ty[...]

  • Page 111

    Functional Desc ription R Intel ® 82845 MCH for SDR Datasheet 111 5.2.3 M emory Address Translation and Decoding The 845 MCH contains address decoders th at translate th e address receiv ed on the s ys tem bu s or the hub in terface. Decoding and translation of thes e addresses v ary w ith the four SDRA M types . Also, th e num ber of pages, page [...]

  • Page 112

    Functional Desc ription R 112 Intel ® 82845 MCH for SDR Datasheet 5.2.4 DRAM Performance Description The overall m emory perform ance is controlled by the DRA M Timin g (DRT) Regis ter, pipelining depth used in the MCH, m emory speed g rade, and the ty pe of SDRA M used in the sy stem. In addition, the exact perf orm ance in a sy stem is also depe[...]

  • Page 113

    Functional Desc ription R Intel ® 82845 MCH for SDR Datasheet 113 Table 15. A GP Commands Supported by the Intel ® MCH When A cting as an AGP Target MCH Host Bri dge AG P Comman d C/BE[3: 0]# Encoding Cy cle Destination Response as P CIx Target Read 0000 Syst em m em ory Low -priority read 0000 Hub interfac e Complet e with random dat a Hi-Priori[...]

  • Page 114

    Functional Desc ription R 114 Intel ® 82845 MCH for SDR Datasheet 5.3.2 AGP Transaction Ordering The MCH observ es trans action orderin g rul es as def ined by the AGP Interface Sp ecification, Revision 2.0 . 5.3.3 AGP Signal Lev els The 4x data tran sfers use 1.5 V s ignal ing levels as described by the AGP Interface Sp ecifica tio n, Revision 2.[...]

  • Page 115

    Functional Desc ription R Intel ® 82845 MCH for SDR Datasheet 115 Table 16. Data Rate Control Bits A GPCNTL .FWCE AG P C M D . FWPE AG P C M D . DRA TE [bit 2 ] AG P C M D . DRA TE [bit 1 ] AG P C M D . DRA TE [bit 0 ] MCH =>AGP Master W ri te Protocol 0 0 X X X 1x 1 1 0 0 1 1x 1 1 0 1 0 2x strobing 1 1 1 0 0 4x strobing 5.3.6 AGP FRA ME# Trans[...]

  • Page 116

    Functional Desc ription R 116 Intel ® 82845 MCH for SDR Datasheet C/BE[3: 0]# Intel ® MCH PCI Comma nd Encoding Cy cle Destination Response as a FRA ME# Targ et Dual Address Cycle 1101 N/A No res pons e Memory Read Line 1110 System Memory Read 1110 Hub interfac e No response Memory W rit e and Invalidat e 1111 Sys t em m em ory P os ts dat a 1111[...]

  • Page 117

    Functional Desc ription R Intel ® 82845 MCH for SDR Datasheet 117 MCH Retry/Disconnect Condi t ions The MCH generates retry /disconnect according to th e AGP Interface Specificatio n , Revisio n 2.0 rules w hen being accessed as a target from the AGP FRAME# device. Delayed T ransaction When an A GP FRAME#- to-sy stem m em ory read cy cle is retrie[...]

  • Page 118

    Functional Desc ription R 118 Intel ® 82845 MCH for SDR Datasheet 5.4.2 Sleep State Control • S0 (Awake): In this state all pow er planes are activ e. All of th e ACPI soft w are “C” st ates are embedded i n thi s state. • S1: T he recom men ded implem entation of S1 state is th e sam e as C2 state (Stop Grant), w hich is entered by the as[...]

  • Page 119

    Electrical Char acteristic s R Intel ® 82845 MCH for SDR Datasheet 119 6 Electrical Characteristics This chapter contain s the absolute m aximum operating ratings, pow er characteristics, and DC characteris tics f or the 82845 MCH. 6.1 A bsolute Maximum Ratings Table 1 8 lists the MCH’s m axim um environm ental stress ratings . Functional operat[...]

  • Page 120

    Electrical Char acteristic s R 120 Intel ® 82845 MCH for SDR Datasheet 6.3 Signal Groups The signal description includes the ty pe of buffer us ed for the particular signal: AGTL+ Open Drain AGTL+ interface s ignal. Ref er to the A GTL+ I/O Specification f or complete details. The MCH integrates most A GTL+ termination resistors. AGP A GP interfac[...]

  • Page 121

    Electrical Char acteristic s R Intel ® 82845 MCH for SDR Datasheet 121 Signal Group Signal Ty pe Signals (s) 1.5 V Core and A GP Voltage VCC1_5 (t) 1. 8 V Hub Int erf ace Voltage VCC1_8 (u) 3.3 V P C133 SDRAM I/O Voltag e VCCSM (v) CMOS Clock I nput 66IN (w) CMOS Cloc k Input B CLK , BCLK#[...]

  • Page 122

    Electrical Char acteristic s R 122 Intel ® 82845 MCH for SDR Datasheet 6.4 DC Characteristics Table 21. DC Ch aracteristics Symbol Signal Group Paramete r Min Ty p Max Unit Note s I/O Buffer Supply Voltage VCCSM (u) P C133 SDRA M I /O Voltage 3.135 3.3 3.465 V VCC1_8 (t) 1.8V I/O Supply Voltage 1.71 1.8 1.89 V VCC1_5 (s) Core and A GP Voltage 1.42[...]

  • Page 123

    Electrical Char acteristic s R Intel ® 82845 MCH for SDR Datasheet 123 Symbol Signal Group Paramete r Min Ty p Max Unit Note s C I/0 (k,m,p) Input Capacitance 4.65 5.37 pF 1.5 V Interface V IL (e,f) Input Low Voltage 0.4 x VCC1_5 V V IH (e,f) Input High Voltage 0.6 x VCC1_5 V V OL (e,g) Output Low Voltage 0.15 x VCC1_5 V V OH (e,g) Output H igh Vo[...]

  • Page 124

    Electrical Char acteristic s R 124 Intel ® 82845 MCH for SDR Datasheet This page is intentionally left blank.[...]

  • Page 125

    Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 125 7 Ballout and Package Information This chapter provides the MCH ballo ut and package information. The ballout footprint is show n in Figure 6 and Fig ure 7. These f igures repres ent the ballou t organi zed by ball n um ber. Table 22 provides the MCH ballout listed alphabeti[...]

  • Page 126

    Ballout and Package Information R 126 Intel ® 82845 MCH for SDR Datasheet Figure 6. Intel ® 82845 MCH Ballo ut Diagram (T op View —Left Side) 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AJ VSS VCC1_5 VT T VTT VTT VSS VSS AH SBA0 SBA1 G_GNT# VSS VSS VSS HD61# HD57# AG VCC1_5 SBA2 SBA3 ST 2 ST0 G_REQ# VTT VSS VTT VSS VT T VSS HD56# HD55# HD54# A[...]

  • Page 127

    Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 127 Figure 7. Intel ® 82845 MCH Ballo ut Diagram (T op View —Right Side) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VSS VSS VSS VSS VSS VSS AJ HD49# HD44# DBI2# HD24# HD31# HD25# HD20# AH HD52# HD 48# HD45 # HD42# HD4 3# HD38# HD27# HD 28# HD2 9# HD16# DBI1# HD22# H D17# VSS AG HD51# V[...]

  • Page 128

    Ballout and Package Information R 128 Intel ® 82845 MCH for SDR Datasheet Table 22. In tel ® 82845 MCH Ballo ut Listed Alphabetically by Signal Name Signal Name Ball # 66IN P22 AD_STB0 R24 AD_STB0# R23 AD_STB1 AC27 AD_STB1# AC28 ADS# V3 AGPREF AA21 BCLK# K8 BCLK J8 BNR# W 3 BPRI# Y7 BR0# V7 CPURST# A E17 DBSY# V5 DEFER# Y 4 DBI0# AD5 DBI1# AG 4 D[...]

  • Page 129

    Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 129 Signal Name Ball # HA6# U3 HA7# R3 HA8# P7 HA9# R2 HA10# P4 HA11# R6 HA12# P5 HA13# P3 HA14# N2 HA15# N7 HA16# N3 HA17# K4 HA18# M4 HA19# M3 HA20# L3 HA21# L5 HA22# K3 HA23# J2 HA24# M5 HA25# J3 HA26# L2 HA27# H4 HA28# N5 HA29# G2 HA30# M6 HA31# L7 HADSTB 0# R5 HADSTB 1# N6 [...]

  • Page 130

    Ballout and Package Information R 130 Intel ® 82845 MCH for SDR Datasheet Signal Name Ball # HD44# AH11 HD45# AG12 HD46# AE13 HD47# AF12 HD48# AG13 HD49# AH13 HD50# AC14 HD51# AF14 HD52# AG14 HD53# AE14 HD54# AG15 HD55# AG16 HD56# AG17 HD57# AH15 HD58# AC17 HD59# AF16 HD60# AE15 HD61# AH17 HD62# AD17 HD63# AE16 HDSTBN0# AD4 HDSTBP0# A D3 HDSTBN1# [...]

  • Page 131

    Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 131 Signal Name Ball # SBA4 AE28 SBA5 AE27 SBA6 AE24 SBA7 AE25 SB_STB AF27 SB_STB# AF26 SBS0 F17 SBS1 G17 SCAS# J25 SCK0 F13 SCK1 G1 3 SCK2 E2 SCK3 C2 SCK4 G1 5 SCK5 G1 4 SCK6 F3 SCK7 E3 SCK8 G1 6 SCK9 F15 SCK10 H 5 SCK11 G 5 SCKE0 G9 SCKE1 F4 SCKE2 G1 0 SCKE3 F5 SCKE4 G1 1 SCKE[...]

  • Page 132

    Ballout and Package Information R 132 Intel ® 82845 MCH for SDR Datasheet Signal Name Ball # SDQ33 E28 SDQ34 C28 SDQ35 D27 SDQ36 B27 SDQ37 F25 SDQ38 C25 SDQ39 E24 SDQ40 C24 SDQ41 E23 SDQ42 D22 SDQ43 E22 SDQ44 B21 SDQ45 C20 SDQ46 D18 SDQ47 E18 SDQ48 E14 SDQ49 C13 SDQ50 E12 SDQ51 F11 SDQ52 C11 SDQ53 E10 SDQ54 D10 SDQ55 B9 SDQ56 E9 SDQ57 D8 SDQ58 B7 [...]

  • Page 133

    Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 133 Signal Name Ball # VSS A3, A7, A 11, A15, A 19, A23, A27, D5, D9, D13, D17, D21, E1, E4, E 26, E29, F8, F12, F16, F20, F24, G26, H9, H11, H13, H15, H17, H19, H21, J1, J4, J 6, J 22, J26, J 29, K5, K 7, K27, L1, L4, L6, L8, L22, L24, L26, M23, N1, N4, N8, N13, N15, N17, N22, [...]

  • Page 134

    Ballout and Package Information R 134 Intel ® 82845 MCH for SDR Datasheet 7.1 Package Mechanical Information This section provides th e MCH packag e mech anical di men sions . The package is a 593 bal l FC-BGA. Figure 8. Intel ® MCH F C-BGA Package Dimensions (To p and Side View ) pkg_olga_ 593_top -si de U n it s = M illim et e r s 9.67 36.28 33[...]

  • Page 135

    Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 135 Figure 9. Intel ® MCH F C-BGA Package Dimensions (Bottom View ) pkg-MCH_olga_593_Bot D E G H K L P R U V Y N W M AA AB AC AD AE AF J F A AH AG AJ 1.270 B C T 10 16 20 35 7 9 11 13 15 17 19 46 1 8 81 2 1 4 22 21 24 23 26 25 28 27 29 1 2 17.780 35.560 1.270 17.780 35.560 N o [...]

  • Page 136

    Ballout and Package Information R 136 Intel ® 82845 MCH for SDR Datasheet This page is intentionally left blank.[...]

  • Page 137

    Testability R Intel ® 82845 MCH for SDR Datasheet 137 8 Testability In the MCH, testability for Autom ated Test Equipment (ATE) board-level testing h as been implem ented as an XOR chain. A n XOR- tree is a chain of XOR gates , each w ith one in put pin connected to it (see Fig ure 10). Figure 10. XOR T ree Chain Input XOR Out xor.vsd Input Input [...]

  • Page 138

    Testability R 138 Intel ® 82845 MCH for SDR Datasheet 8.2 XOR Chains Note: RSTIN#, TESTIN#, and all Rc omp bu ff ers are not part of any XOR chain. Table 23. XO R Chain 0 Chain 0 Ball Element # Signal Name Note Initial Logic Level AE6 1 HDSTBP1# Input 1 AD3 2 HDSTB P0# Input 1 V3 3 ADS# Input 1 U6 4 HREQ0# Input 1 U3 5 HA6# Input 1 U2 6 HREQ4# Inp[...]

  • Page 139

    Testability R Intel ® 82845 MCH for SDR Datasheet 139 Chain 0 Ball Element # Signal Name Note Initial Logic Level M5 31 HA24# I nput 1 K3 32 HA23# Input 1 K4 33 HA17# Input 1 J3 34 HA25# Input 1 L5 35 HA21# Input 1 H4 36 HA27# Input 1 M6 37 HA30# I nput 1 L7 38 HA31# Input 1 G2 39 HA29# Input 1 H6 40 SCS 11# Input 1 H3 41 RDCLKIN I nput 1 G3 42 RD[...]

  • Page 140

    Testability R 140 Intel ® 82845 MCH for SDR Datasheet Table 24. XO R Chain 1 Chain 1 Ball Element # Signal Name Note Initial Logic Level N6 1 HADSTDB1# Input 1 H7 2 SCS6# Input 1 G10 3 SCKE2 Input 1 G5 4 S CK11 I nput 1 F4 5 SCKE1 Input 1 F3 6 SCK6 Input 1 C2 7 SCK3 Input 1 B2 8 SDQ31 I nput 1 E2 9 SCK2 I nput 1 D3 10 SDQ63 Input 1 E3 11 S CK7 Inp[...]

  • Page 141

    Testability R Intel ® 82845 MCH for SDR Datasheet 141 Table 25. XO R Chain 2 Chain 2 Ball Element # Si gnal Name Note Ini ti al Logic Level D10 1 SDQ54 Input 1 C10 2 SDQ21 Input 1 C11 3 SDQ52 Input 1 F9 4 SDQ22 Input 1 B11 5 SDQ19 Input 1 B13 6 SDQ16 Input 1 G11 7 SCKE4 Input 1 C12 8 SDQ18 Input 1 F11 9 SDQ51 Input 1 C13 10 SDQ49 Input 1 D12 11 RS[...]

  • Page 142

    Testability R 142 Intel ® 82845 MCH for SDR Datasheet Table 26. XO R Chain 3 Chain 3 Ball El em ent # Signal Nam e Note I nitial Logi c Level G10 1 SCKE0 Input 1 G12 2 SMA12 Input 1 G15 3 SCK4 I nput 1 F13 4 SCK 0 Input 1 C14 5 SCB 3 Input 1 E14 6 SDQ48 Input 1 D14 7 SCB 7 Input 1 C15 8 SCB 6 Input 1 G17 9 SBCS1 Input 1 C16 10 SDQ64 I nput 1 D16 1[...]

  • Page 143

    Testability R Intel ® 82845 MCH for SDR Datasheet 143 Chain 3 Ball El em ent # Signal Nam e Note I nitial Logi c Level B25 35 SDQ6 Input 1 C25 36 SDQ38 I nput 1 C27 37 SDQ3 Input 1 D27 38 SDQ35 I nput 1 B27 39 SDQ36 I nput 1 C26 40 RSVD Input 1 F23 41 SDQ8 Input 1 E24 42 SDQ39 I nput 1 E25 43 SDQ5 Input 1 E27 44 SDQ1 Input 1 N24 45 HI_STB# Input 1[...]

  • Page 144

    Testability R 144 Intel ® 82845 MCH for SDR Datasheet Chain 4 Ball E l em ent # Signal Name Note Initial Logi c Level N27 20 HI _2 Input 1 M26 21 HI _4 Input 1 N25 22 HI_STB Input 1 L27 23 HI _7 Input 1 P25 24 HI_0 Input 1 P23 25 HI_3 Input 1 P24 26 HI_1 Input 1 R27 27 G_ADO Input 1 R28 28 G_AD1 Input 1 U27 29 G_AD6 Input 1 R25 30 G_AD3 Input 1 T2[...]

  • Page 145

    Testability R Intel ® 82845 MCH for SDR Datasheet 145 Chain 5 Ball Element # Signal Name Note Ini tial Logic Level W 24 8 G_TRDY # Input 1 AE23 9 W BF# Input 1 W 23 10 G_STOP # I nput 1 AA23 11 G_C/BE 3# Input 1 AA28 12 G_AD18 Input 1 Y26 13 G_AD17 Input 1 Y27 14 G_AD16 Input 1 AB27 15 G_AD20 Input 1 AB26 16 G_AD22 Input 1 AA25 17 G_AD26 Input 1 A[...]

  • Page 146

    Testability R 146 Intel ® 82845 MCH for SDR Datasheet Table 29. XO R Chain 6 Chain 6 Ball Element # Si gnal Name Note Initial Logi c Level AC27 1 AD_STB1 Input 1 AF27 2 S B_STB Input 1 AE17 3 CPURST# I nput 1 AD17 4 HD62# Input 1 AE16 5 HD63# Input 1 AH15 6 HD57# Input 1 AG15 7 HD54# Input 1 AF16 8 HD59# Input 1 AC16 9 HDS TBP3# Input 1 AE15 10 HD[...]

  • Page 147

    Testability R Intel ® 82845 MCH for SDR Datasheet 147 Chain 6 Ball Element # Si gnal Name Note Initial Logi c Level AC9 35 HD35# Input 1 AD9 36 HD37# Input 1 AH7 37 HD24# Input 1 AH5 38 HD31# Input 1 AG8 39 HD27# I nput 1 Y4 40 DEFE R# I nput 1 W 7 41 RS 1# Input 1 AE24 42 SBA6 Output N/A Table 30. XO R Chain 7 Chain 7 Ball E l em ent # SDR Ball n[...]

  • Page 148

    Testability R 148 Intel ® 82845 MCH for SDR Datasheet Chain 7 Ball E l em ent # SDR Ball name Note I nitial Logi c Level AC3 25 HD13# I nput 1 AB5 26 HD1# Input 1 AC5 27 HD5# Input 1 AA6 28 HD7# Input 1 AA5 29 HD2# Input 1 AB3 30 HD3# Input 1 AA3 31 HD6# Input 1 AB4 32 HD4# Input 1 AA2 33 HD0# Input 1 Y5 34 HIT# Input 1 Y7 35 BPRI# Input 1 W 6 36 [...]