Intel BX80646E31230V3 manuel d'utilisation

Intel ® Xeon ® Processor E3-1200 v3 Product Family Datasheet – Volume 1 of 2 June 2013 Order No.: 328907-001[...]

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Contents Revision History.................................................................................................................. 8 1.0 Introduction................................................................................................................. 9 1.1 Supported Technologies..................................................[...]

4.2 Processor Core Power Management......................................................................... 50 4.2.1 Enhanced Intel ® SpeedStep ® Technology Key Features..................................50 4.2.2 Low-Power Idle States............................................................................... 51 4.2.3 Requesting Low-Power Idle[...]

6.14 Processor Internal Pull-Up / Pull-Down Terminations................................................ 85 7.0 Electrical Specifications.............................................................................................. 86 7.1 Integrated Voltage Regulator.................................................................................. [...]

Tables 1 Terminology........................................................................................................... 12 2 Related Documents.................................................................................................. 15 3 Processor DIMM Support by Product...............................................................[...]

53 Processor Storage Specifications.............................................................................. 104 54 Processor Ball List by Signal Name........................................................................... 106 Contents—Processor Intel ® Xeon ® Processor E3-1200 v3 Product Family June 2013 Datasheet – Volume 1 of 2 Ord[...]

Revision History Revision Description Date 001 • Initial Release June 2013 Processor—Revision History Intel ® Xeon ® Processor E3-1200 v3 Product Family Datasheet – Volume 1 of 2 June 2013 8 Order No.: 328907-001[...]

1.0 Introduction The Intel ® Xeon ® processor E3-1200 v3 product family are 64-bit, multi-core processors built on 22-nanometer process technology. The processors are designed for a two-chip platform consisting of a processor and Platform Controller Hub (PCH). The processors are designed to be used with the Intel ® C220 Series chipset. See the f[...]

Figure 1. Platform Block Diagram Processor PCI Express* 3.0 Digital Display Interface (DDI) (3 interfaces) System Memory 1333 / 1600 MT/s 2 DIMMs / CH CH A CH B Intel ® Flexible Display Interface (Intel ® FDI) (x2) Direct Media Interface 2.0 (DMI 2.0) (x4) Note: 2 DIMMs / CH is not supported on all SKUs. Platform Controller Hub (PCH) SATA, 6 GB/s[...]

• Intel ® Advanced Encryption Standard New Instructions (Intel ® AES-NI) • PCLMULQDQ Instruction • Intel ® Secure Key • Intel ® Transactional Synchronization Extensions (Intel ® TSX) • PAIR – Power Aware Interrupt Routing • SMEP – Supervisor Mode Execution Protection Note: The availability of the features may vary between proce[...]

1.4 Thermal Management Support • Digital Thermal Sensor • Adaptive Thermal Monitor • THERMTRIP# and PROCHOT# support • On-Demand Mode • Memory Open and Closed Loop Throttling • Memory Thermal Throttling • External Thermal Sensor (TS-on-DIMM and TS-on-Board) • Render Thermal Throttling • Fan speed control with DTS 1.5 Package Suppo[...]

Term Description eDP Embedded Display Port EPG Electrical Power Gating EU Execution Unit FMA Floating-point fused Multiply Add instructions FSC Fan Speed Control HDCP High-bandwidth Digital Content Protection HDMI* High Definition Multimedia Interface HFM High Frequency Mode iDCT Inverse Discrete IHS Integrated Heat Spreader GFX Graphics GUI Graphi[...]

Term Description NCTF Non-Critical to Function. NCTF locations are typically redundant ground or non-critical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. ODT On-Die Termination OLTM Open Loop Thermal Management PCG Platform Compatibility Guide (PCG) (previously kn[...]

Term Description T CONTROL T CONTROL is a static value that is below the TCC activation temperature and used as a trigger point for fan speed control. When DTS > T CONTROL , the processor must comply to the TTV thermal profile. TDP Thermal Design Power: Thermal solution should be designed to dissipate this target power level. TDP is not the maxi[...]

Document Document Number / Location Advanced Configuration and Power Interface 3.0 http:// www.acpi.info/ PCI Local Bus Specification 3.0 http:// www.pcisig.com/ specifications PCI Express Base Specification, Revision 2.0 http:// www.pcisig.com DDR3 SDRAM Specification http:// www.jedec.org DisplayPort* Specification http://www.vesa.org Intel ® 64[...]

2.0 Interfaces 2.1 System Memory Interface • Two channels of DDR3/DDR3L Unbuffered Dual In-Line Memory Modules (UDIMM) with a maximum of two DIMMs per channel. • Single-channel and dual-channel memory organization modes • Data burst length of eight for all memory organization modes • Memory data transfer rates of 1333 MT/s and 1600 MT/s •[...]

2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3/DDR3L protocols with two independent, 64-bit wide channels each accessing one or two DIMMs. The type of memory supported by the processor is dependent on the PCH SKU in the target platform. Note: The IMC supports a maximum of two DDR3/DDR3L DIMMs per chann[...]

Raw Card Version DIMM Capacity DRAM Device Technology DRAM Organization # of DRAM Devices # of Physical Devices Ranks # of Row / Col Address Bits # of Banks Inside DRAM Page Size A 1 GB 1 Gb 128 M X 8 8 1 14/10 8 8K B 2 GB 1 Gb 128 M X 8 16 2 14/10 8 8K 4 GB 2 Gb 256 M X 8 16 2 15/10 8 8K 4 GB 4 Gb 512 M X 8 8 1 15/10 8 8K 8 GB 4 Gb 512 M X 8 16 2 [...]

Dual-Channel Mode – Intel ® Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode. Memory is divided into symmetric and asymmetric zones. The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is [...]

2.1.3.1 System Memory Frequency In all modes, the frequency of system memory is the lowest frequency of all memory modules placed in the system, as determined through the SPD registers on the memory modules. The system memory controller supports one or two DIMM connectors per channel. The usage of DIMM modules with different latencies is allowed, b[...]

2.2 PCI Express* Interface This section describes the PCI Express* interface capabilities of the processor. See the PCI Express Base* Specification 3.0 for details on PCI Express*. 2.2.1 PCI Express* Support The PCI Express* lanes (PEG[15:0] TX and RX) are fully-compliant to the PCI Express Base Specification, Revision 3.0 . The Intel ® Xeon ® pr[...]

• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering). • Peer segment destination posted write traffic (no peer-to-peer read traffic) in Virtual Channel 0: DMI -> PCI Express* Port 0 • 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros). ?[...]

Figure 3. PCI Express* Related Register Structures in the Processor PCI-PCI Bridge representing root PCI Express ports (Device 1 and Device 6) PCI Compatible Host Bridge Device (Device 0) PCI Express* Device PEG0 DMI PCI Express* extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the conventional [...]

Figure 4. PCI Express* Typical Operation 16 Lanes Mapping 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 X 16 Co ntroller Lane 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7 Lane 8 Lane 9 Lane 10 Lane 11 Lane 12 Lane 13 Lane 14 Lane 15 0 1 2 3 4 5 6 7 1 X 8 Controller 0 1 2 3 1 X 4 Cont ro ller 2.3 Direct Media In[...]

• 5 GT/s point-to-point DMI interface to PCH is supported. • Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of 500 MB/s given the 8b/10b encoding used to transmit data across this interface. Does not account for packet overhead and link maintenance. • Maximum theoretical bandwidth on interface of 2 GB/s in e[...]

2.4 Processor Graphics The processor graphics contains a generation 7.5 graphics core architecture. This enables substantial gains in performance and lower power consumption over previous generations. Up to 20 Execution Units are supported depending on the processor SKU. • Next Generation Intel Clear Video Technology HD Support is a collection of[...]

Figure 5. Processor Graphics Controller Unit Block Diagram 2.5.1 3D and Video Engines for Graphics Processing The Gen 7.5 3D engine provides the following performance and power-management enhancements. 3D Pipeline The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive. Al[...]

Vertex Shader (VS) Stage The VS stage performs shading of vertices output by the VF function. The VS unit produces an output vertex reference for every input vertex reference received from the VF unit, in the order received. Geometry Shader (GS) Stage The GS stage receives inputs from the VS stage. Compiled application-provided GS programs, specify[...]

Logical 128-Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The 128-bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations. The BLT engine can be used for the following: • Move rectangular blocks of data between memory locatio[...]

• The HDMI* interface supports HDMI with 3D, 4K, Deep Color, and x.v.Color. The DisplayPort* interface supports the VESA DisplayPort* Standard Version 1, Revision 2. • The processor supports High-bandwidth Digital Content Protection (HDCP) for high-definition content playback over digital interfaces. • The processor also integrates dedicated [...]

• Organizing pixels into frames • Optionally scaling the image to the desired size • Re-timing data for the intended target • Formatting data according to the port output standard DisplayPort* DisplayPort* is a digital communication interface that uses differential signaling to achieve a high-bandwidth bus interface designed to support conn[...]

TMDS data and clock channels. These channels are used to carry video, audio, and auxiliary data. In addition, HDMI carries a VESA DDC. The DDC is used by an HDMI Source to determine the capabilities and characteristics of the Sink. Audio, video, and auxiliary (control/status) data is transmitted across the three TMDS data channels. The video pixel [...]

Embedded DisplayPort* Embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort standard oriented towards applications such as notebook and All-In-One PCs. Digital Port D can be configured as eDP. Like DisplayPort, Embedded DisplayPort also consists of a Main Link, Auxiliary channel, and an optional Hot-Plug Detect signal. The eDP on t[...]

Table 7. Valid Three Display Configurations through the Processor Display 1 Display 2 Display 3 Maximum Resolution Display 1 Maximum Resolution Display 2 Maximum Resolution Display 3 HDMI HDMI DP 4096x2304 @ 24 Hz 2560x1600 @ 60 Hz 3840x2160 @ 60 Hz DVI DVI DP 1920x1200 @ 60 Hz 3840x2160 @ 60 Hz DP DP DP 3840x2160 @ 60 Hz VGA DP HDMI 1920x1200 @ 60[...]

2.7 Intel ® Flexible Display Interface (Intel ® FDI) • The Intel Flexible Display Interface (Intel FDI) passes display data from the processor (source) to the PCH (sink) for display through a display interface on the PCH. • Intel FDI supports 2 lanes at 2.7 GT/s fixed frequency. This can be configured to 1 or 2 lanes depending on the bandwidt[...]

Figure 9. Example for PECI Host-Clients Connection V TT Host / Originator Q1 nX Q2 1X PECI C PECI <10pF/Node Q3 nX V TT PECI Client Additional PECI Clients Interfaces—Processor Intel ® Xeon ® Processor E3-1200 v3 Product Family June 2013 Datasheet – Volume 1 of 2 Order No.: 328907-001 37[...]

3.0 Technologies This chapter provides a high-level description of Intel technologies implemented in the processor. The implementation of the features may vary between the processor SKUs. Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site: http://www.intel.com/tec[...]

• More reliable: Due to the hardware support, VMMs can now be smaller, less complex, and more efficient. This improves reliability and availability and reduces the potential for software conflicts. • More secure: The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting [...]

• Descriptor-Table Exiting — Descriptor-table exiting allows a VMM to protect a guest OS from internal (malicious software based) attack by preventing relocation of key system data structures like IDT (interrupt descriptor table), GDT (global descriptor table), LDT (local descriptor table), and TSS (task segment selector). — A VMM using this [...]

Figure 10. Device to Domain Mapping Structures Root entry 0 Root entry N Root entry 255 Context entry 0 Context entry 255 Context entry 0 Context entry 255 (Bus 255) (Bus N) (Bus 0) Root entry table (Dev 31, Func 7) (Dev 0, Func 1) (Dev 0, Func 0) Context entry Table For bus N Context entry Table For bus 0 Address Translation Structures for Domain [...]

• Memory controller and processor graphics comply with the Intel VT-d 1.2 Specification. • Two Intel VT-d DMA remap engines. — iGFX DMA remap engine — Default DMA remap engine (covers all devices except iGFX) • Support for root entry, context entry, and default context • 39-bit guest physical address and host physical address widths •[...]

Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment. The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment. Intel TXT is a set of extensions designed to provide a measured[...]

Intel recommends enabling Intel HT Technology with Microsoft Windows* 8 and Microsoft Windows* 7 and disabling Intel HT Technology using the BIOS for all previous versions of Windows* operating systems. For more information on Intel HT Technology, see http://www.intel.com/technology/platform-technology/hyper- threading/ . 3.4 Intel ® Turbo Boost T[...]

digital signal processing software. FMA improves performance in face detection, professional imaging, and high performance computing. Gather operations increase vectorization opportunities for many applications. In addition to the vector extensions, this generation of Intel processors adds new bit manipulation instructions useful in compression, en[...]

performance of fine-grain locking while actually programming using coarse-grain locks. Details on Intel TSX may be found in Intel ® Architecture Instruction Set Extensions Programming Reference. 3.8 Intel ® 64 Architecture x2APIC The x2APIC architecture extends the xAPIC architecture that provides key mechanisms for interrupt delivery. This exten[...]

• The semantics for accessing APIC registers have been revised to simplify the programming of frequently-used APIC registers by system software. Specifically, the software semantics for using the Interrupt Command Register (ICR) and End Of Interrupt (EOI) registers have been modified to allow for more efficient delivery and dispatching of interru[...]

4.0 Power Management This chapter provides information on the following power management topics: • Advanced Configuration and Power Interface (ACPI) States • Processor Core • Integrated Memory Controller (IMC) • PCI Express* • Direct Media Interface (DMI) • Processor Graphics Controller Figure 11. Processor Power States G0 - Working S0 [...]

4.1 Advanced Configuration and Power Interface (ACPI) States Supported This section describes the ACPI states supported by the processor. Table 9. System States State Description G0/S0 Full On Mode. G1/S3-Cold Suspend-to-RAM (STR). Context saved to memory (S3-Hot state is not supported by the processor). G1/S4 Suspend-to-Disk (STD). All power lost [...]

Table 13. Direct Media Interface (DMI) States State Description L0 Full on – Active transfer state. L0s First Active Power Management low power state – Low exit latency. L1 Lowest Active Power Management – Longer exit latency. L3 Lowest power state (power-off) – Longest exit latency. Table 14. G, S, and C Interface State Combinations Global[...]

• Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. • Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores. — Once the voltage is established, the[...]

Figure 13. Thread and Core C-State Entry and Exit C 1 C 1 E C 7 C 6 C 3 C 0 M WAIT (C 1 ), HLT C 0 M WAIT (C 7 ), P_ LV L4 I/O R e ad M WAIT (C 6 ), P_ LV L3 I/O R e ad M WAIT (C 3 ), P_ LV L2 I/O R e ad M WAIT (C 1 ), HLT (C 1 E Enabl e d ) While individual threads can request low power C-states, power saving actions only take place once the core [...]

Note: When P_LVLx I/O instructions are used, MWAIT sub-states cannot be defined. The MWAIT sub-state is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a wakeup on an interrupt, even if interrupts are masked by EFLAGS.IF. 4.2.4 Core C-State Rules Th[...]

Core C6 State Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6) instruction. Before entering core C6 state, the core will save its architectural state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts. During exit, the core is powered on and its architectural sta[...]

— For package C-states, the processor is not required to enter C0 state before entering any other C-state. — Entry into a package C-state may be subject to auto-demotion – that is, the processor may keep the package in a deeper package C-state than requested by the operating system if the processor determines, using heuristics, that the deepe[...]

Figure 14. Package C-State Entry and Exit C 0 C 1 C 6 C 7 C 3 Package C0 State This is the normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be [...]

Package C2 State Package C2 state is an internal processor state that cannot be explicitly requested by software. A processor enters Package C2 state when: • All cores and graphics have requested a C3 or deeper power state, but constraints (LTR, programmed timer events in the near future, and so on) prevent entry to any state deeper than C 2 stat[...]

Note: Package C6 state is the deepest C-state supported on discrete graphics systems with PCI Express Graphics (PEG). Package C7 state is the deepest C-state supported on integrated graphics systems (or switchable graphics systems during integrated graphics mode). However, in most configurations, package C6 will be more energy efficient than packag[...]

2. Active power-down (APD): This mode is entered if there are open pages when de- asserting CKE. In this mode the open pages are retained. Power-saving in this mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this mode is defined by tXP – small number of cycles. For this mode, DRAM DLL must be on. 3. PPD/DLL-off: In this [...]

4.3.2.2 Conditional Self-Refresh During S0 idle state, system memory may be conditionally placed into self-refresh state when the processor is in package C3 or deeper power state. Refer to Intel® Rapid Memory Power Management (Intel® RMPM) for more details on conditional self- refresh with Intel HD Graphics enabled. When entering the S3 – Suspe[...]

4.3.4 DDR Electrical Power Gating (EPG) The DDR I/O of the processor supports Electrical Power Gating (DDR-EPG) while the processor is at C3 or deeper power state. In C3 or deeper power state, the processor internally gates V DDQ for the majority of the logic to reduce idle power while keeping all critical DDR pins such as SM_DRAMRST#, CKE and VREF[...]

package, and the application demand for additional processor or graphics performance. The processor core control is maintained by an embedded controller. The graphics driver dynamically adjusts between P-States to maintain optimal performance, power, and thermals. The graphics driver will always try to place the graphics engine in the most energy e[...]

5.0 Thermal Management This chapter provides both component-level and system-level thermal management. Topics convered include processor thermal specifications, thermal profiles, thermal metrology, fan speed control, adaptive thermal monitor, THERMTRIP# signal, Ditital Thermal Sensor (DTS), Intel Turbo Boost Technology, package power control, power[...]

5.1 Thermal Metrology The maximum Thermal Test Vehicle (TTV) case temperatures (T CASE-MAX ) can be derived from the data in the appropriate TTV thermal profile earlier in this chapter. The TTV T CASE is measured at the geometric top center of the TTV integrated heat spreader (IHS). The following figure illustrates the location where T CASE tempera[...]

The Ψ CA point at DTS = -1 defines the minimum Ψ CA required at TDP considering the worst case system design T AMBIENT design point: Ψ CA = (T CASE-MAX – T AMBIENT-TARGET ) / TDP For example, for a 95 W TDP part, the T case maximum is 72.6 °C and at a worst case design point of 40 °C local ambient this will result in: Ψ CA = (72.6 – 40) /[...]

Table 18. Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above T CONTROL Processor TDP Ψ CA at DTS = T CONTROL 1, 2 At System T AMBIENT- MAX = 30 °C Ψ CA at DTS = -1 At System T AMBIENT-MAX = 40 °C Ψ CA at DTS = -1 At System T AMBIENT-MAX = 45 °C Ψ CA at DTS = -1 At System T AMBIENT- MAX = 50 °C 84 W 0.627 0.390 0.330 0.270 6[...]

Figure 17. Digital Thermal Sensor (DTS) Thermal Profile Definition Table 19. Thermal Margin Slope PCG Die Configuration (Native) Core + GT TDP (W) TCC Activation Temperature (°C) MSR 1A2h 23:16 Temperature Control Offset MSR 1A2h 15:8 Thermal Margin Slope (°C / W) 2013D 4+2 (4+2) 84 100 20 0.654 4+0 (4+2) 82 100 20 0.671 2013C 4+2 (4+2) 65 92 6 0[...]

Performance Targets The following table provides boundary conditions and performance targets as guidance for thermal solution design. Thermal solutions must be able to comply with the Maximum T CASE Thermal Profile. Table 20. Boundary Conditions, Performance Targets, and T CASE Specifications Processor PCG 2 Package TDP 3 Platform TDP 4 Heatsink 5 [...]

Processor PCG 2 Package TDP 3 Platform TDP 4 Heatsink 5 T LA , Airflow, RPM, Ѱ CA 6 Maximum T CASE Thermal Profile 7 T CASE-MAX @ Platform TDP 8 2C/GT2 35 W 1 2013A 35 W 35 W Active Short (DHA-D) 45.4 °C, 3000 RPM, 0.597 °C/W y = 0.51 * Power + 48.5 66.3 °C 4C/GT0 25 W 1 25 W 25 W ATCA Reference Heatsink 9 67 °C, 10 CFM, 0.565 °C/W y = 0.48 *[...]

method to use on a dynamic basis. BIOS is not required to select a specific method (as with previous-generation processors supporting TM1 or TM2). The temperature at which Adaptive Thermal Monitor activates the Thermal Control Circuit is factory calibrated and is not user configurable. Snooping and interrupt processing are performed in the normal m[...]

A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the TCC activation temperature. Once the temperature has dropped below the trip temperature and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system opera[...]

PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has exceeded its specification. If Adaptive Thermal Monitor is enabled (it must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generat[...]

Error and Thermal Protection Signals on page 83). THERMTRIP# activation is independent of processor activity. The temperature at which THERMTRIP# asserts is not user configurable and is not software visible. 5.8 Digital Thermal Sensor Each processor execution core has an on-die Digital Thermal Sensor (DTS) that detects the core's instantaneous[...]

5.9 Intel ® Turbo Boost Technology Thermal Considerations Intel Turbo Boost Technology allows processor cores and integrated graphics cores to run faster than the baseline frequency. During a turbo event, the processor can exceed its TDP power for brief periods. Turbo is invoked opportunistically and automatically as long as the processor is confo[...]

5.9.2 Package Power Control The package power control allows for customization to implement optimal turbo within platform power delivery and package thermal solution limitations. Table 21. Intel ® Turbo Boost Technology 2.0 Package Power Control Settings MSR: Address: MSR_TURBO_POWER_LIMIT 610h Control Bit Default Description POWER_LIMIT_1 (PL1) 1[...]

Power_Limit_2 for up to approximately 1.5 the Turbo Time Parameter. See the appropriate processor Thermal Mechanical Design Guidelines for more information (see Related Documents section). If the power value and/or Turbo Time Parameter is changed during runtime, it may take a period of time (possibly up to approximately 3 to 5 times the Turbo Time [...]

6.0 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type. Notation Signal Type I Input pin O Output pin I/O Bi-directional Input/Output pin The signal description also includes the type[...]

Signal Name Description Direction / Buffer Type SA_DQ[63:0] Data Bus: Channel A data signal interface to the SDRAM data bus. I/O DDR3/DDR3L SA_ECC_CB[7:0] ECC Data Lines: Data Lines for ECC Check Byte. I/O DDR3/DDR3L SA_MA[15:0] Memory Address: These signals are used to provide the multiplexed row and column address to the SDRAM. O DDR3/DDR3L SA_CK[...]

Signal Name Description Direction / Buffer Type SB_CKE[3:0] Clock Enable: (1 per rank). These signals are used to: • Initialize the SDRAMs during power-up. • Power-down SDRAM ranks. • Place all SDRAM ranks into and out of self-refresh during STR. O DDR3/DDR3L SB_CS#[3:0] Chip Select: (1 per rank). These signals are used to select particular S[...]

6.3 Reset and Miscellaneous Signals Table 26. Reset and Miscellaneous Signals Signal Name Description Direction / Buffer Type CFG[19:0] Configuration Signals: The CFG signals have a default value of '1' if not terminated on the board. • CFG[1:0]: Reserved configuration lane. A test point may be placed on the board for these lanes. • C[...]

Signal Name Description Direction / Buffer Type SM_DRAMRST# DRAM Reset: Reset signal from processor to DRAM devices. One signal common to all channels. O CMOS TESTLO_x TESTLO should be individually connected to V SS through a resistor. Note: 1. PCIe bifurcation support varies with the processor and PCH SKUs used. 6.4 PCI Express*-Based Interface Si[...]

6.6 Direct Media Interface (DMI) Table 29. Direct Media Interface (DMI) – Processor to PCH Serial Interface Signal Name Description Direction / Buffer Type DMI_RXP[3:0] DMI_RXN[3:0] DMI Input from PCH: Direct Media Interface receive differential pair. I DMI DMI_TXP[3:0] DMI_TXN[3:0] DMI Output to PCH: Direct Media Interface transmit differential [...]

Signal Name Description Direction / Buffer Type TDO Test Data Out: This signal transfers serial test data out of the processor. This signal provides the serial output needed for JTAG specification support. O Open Drain TMS Test Mode Select: This is a JTAG specification supported signal used by debug tools. I GTL TRST# Test Reset: This signal resets[...]

6.10 Power Sequencing Table 33. Power Sequencing Signal Name Description Direction / Buffer Type SM_DRAMPWROK SM_DRAMPWROK Processor Input : This signal connects to the PCH DRAMPWROK. I Asynchronous CMOS PWRGOOD The processor requires this input signal to be a clean indication that the V CC and V DDQ power supplies are stable and within specificati[...]

6.13 Ground and Non-Critical to Function (NCTF) Signals Table 36. Ground and Non-Critical to Function (NCTF) Signals Signal Name Description Direction / Buffer Type VSS Processor ground node GND VSS_NCTF Non-Critical to Function: These pins are for package mechanical reliability. — 6.14 Processor Internal Pull-Up / Pull-Down Terminations Table 37[...]

7.0 Electrical Specifications This chapter provides the processor electrical specifications including integrated voltage regulator (VR), V CC Voltage Identification (VID), reserved and unused signals, signal groups, Test Access Points (TAP), and DC specifications. 7.1 Integrated Voltage Regulator A new feature to the processor is the integration of[...]

Table 38. VR 12.5 Voltage Identification B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex V CC 0 0 0 0 0 0 0 0 00h 0.0000 0 0 0 0 0 0 0 1 01h 0.5000 0 0 0 0 0 0 1 0 02h 0.5100 0 0 0 0 0 0 1 1 03h 0.5200 0 0 0 0 0 1 0 0 04h 0.5300 0 0 0 0 0 1 0 1 05h 0.5400 0 0 0 0 0 1 1 0 06h 0.5500 0 0 0 0 0 1 1 1 07h 0.5600 0 0 0 0 1 0 0 0 08h [...]

B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex V CC 0 1 0 0 0 0 1 0 42h 1.1500 0 1 0 0 0 0 1 1 43h 1.1600 0 1 0 0 0 1 0 0 44h 1.1700 0 1 0 0 0 1 0 1 45h 1.1800 0 1 0 0 0 1 1 0 46h 1.1900 0 1 0 0 0 1 1 1 47h 1.2000 0 1 0 0 1 0 0 0 48h 1.2100 0 1 0 0 1 0 0 1 49h 1.2200 0 1 0 0 1 0 1 0 4Ah 1.2300 0 1 0 0 1 0 1 1 4Bh 1.2400 0 1 0 0[...]

B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex V CC 1 0 0 0 0 1 1 0 86h 1.8300 1 0 0 0 0 1 1 1 87h 1.8400 1 0 0 0 1 0 0 0 88h 1.8500 1 0 0 0 1 0 0 1 89h 1.8600 1 0 0 0 1 0 1 0 8Ah 1.8700 1 0 0 0 1 0 1 1 8Bh 1.8800 1 0 0 0 1 1 0 0 8Ch 1.8900 1 0 0 0 1 1 0 1 8Dh 1.9000 1 0 0 0 1 1 1 0 8Eh 1.9100 1 0 0 0 1 1 1 1 8Fh 1.9200 1 0 0 1[...]

B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex V CC 1 1 0 0 1 0 1 0 CAh 2.5100 1 1 0 0 1 0 1 1 CBh 2.5200 1 1 0 0 1 1 0 0 CCh 2.5300 1 1 0 0 1 1 0 1 CDh 2.5400 1 1 0 0 1 1 1 0 CEh 2.5500 1 1 0 0 1 1 1 1 CFh 2.5600 1 1 0 1 0 0 0 0 D0h 2.5700 1 1 0 1 0 0 0 1 D1h 2.5800 1 1 0 1 0 0 1 0 D2h 2.5900 1 1 0 1 0 0 1 1 D3h 2.6000 1 1 0 1[...]

7.4 Reserved or Unused Signals The following are the general types of reserved (RSVD) signals and connection guidelines: • RSVD – these signals should not be connected • RSVD_TP – these signals should be routed to a test point • RSVD_NCTF – these signals are non-critical to function and may be left un- connected Arbitrary connection of [...]

Signal Group Type Signals Single ended CMOS Output SM_DRAMRST# DDR3/DDR3L Data Signals 2 Single ended DDR3/DDR3L Bi- directional SA_DQ[63:0], SB_DQ[63:0] Differential DDR3/DDR3L Bi- directional SA_DQSP[7:0], SA_DQSN[7:0], SB_DQSP[7:0], SB_DQSN[7:0] DDR3/DDR3L Reference Voltage Signals DDR3/DDR3L Output SM_VREF, SA_DIMM_VREFDQ, SB_DIMM_VREFDQ Testab[...]

Signal Group Type Signals Other SKTOCC#, PCI Express* Graphics Differential PCI Express Input PEG_RXP[15:0], PEG_RXN[15:0] Differential PCI Express Output PEG_TXP[15:0], PEG_TXN[15:0] Single ended Analog Input PEG_RCOMP Digital Media Interface (DMI) Differential DMI Input DMI_RXP[3:0], DMI_RXN[3:0] Differential DMI Output DMI_TXP[3:0], DMI_TXN[3:0][...]

7.8 Voltage and Current Specifications Table 40. Processor Core Active and Idle Mode DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note 1 Operational VID VID Range 1.65 2013D: 1.75 2013C: 1.75 2013B: 1.75 2013A: 1.75 1.86 V 2 Idle VID (package C6/C7) VID Range 1.5 1.6 1.65 V 2 R_DC_LL Loadline slope within the VR regulatio[...]

Symbol Parameter Min Typ Max Unit Note 1 P MAX 2013D PCG P MAX — — 153 W 9 P MAX 2013C PCG P MAX — — 121 W 9 P MAX 2013B PCG P MAX — — 99 W 9 P MAX 2013A PCG P MAX — — 83 W 9 Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updat[...]

Table 42. VCCIO_OUT, VCOMP_OUT, and VCCIO_TERM Symbol Parameter Typ Max Units Notes VCCIO_OUT Termination Voltage 1.0 — V ICCIO_OUT Maximum External Load — 300 mA VCOMP_OUT Termination Voltage 1.0 — V 1 VCCIO_TERM Termination Voltage 1.0 — V 2 Notes: 1. VCOMP_OUT may only be used to connect to PEG_RCOMP and DP_RCOMP. 2. Internal processor p[...]

Symbol Parameter Min Typ Max Units Notes 1 R ON_DN(CTL) DDR3/DDR3L Control Buffer pull-down Resistance 19 25 31 Ω 5, 11, 13 R ON_UP(RST) DDR3/DDR3L Reset Buffer pull-up Resistance 40 80 130 Ω — R ON_DN(RST) DDR3/DDR3L Reset Buffer pull-up Resistance 40 80 130 Ω — I LI Input Leakage Current (DQ, CK) 0 V 0.2*V DDQ 0.8*V DDQ — — 0.7 mA — [...]

Table 45. Embedded DisplayPort* (eDP) Group DC Specifications Symbol Parameter Min Typ Max Units V IL HPD Input Low Voltage 0.02 — 0.21 V V IH HPD Input High Voltage 0.84 — 1.05 V V OL eDP_DISP_UTIL Output Low Voltage 0.1*V CC — — V V OH eDP_DISP_UTIL Output High Voltage 0.9*V CC — — V R UP eDP_DISP_UTIL Internal pull-up 100 — — Ω [...]

Symbol Parameter Min Max Units Notes 1 V IH Input High Voltage (other GTL) V CCIO_TERM * 0.72 — V 2, 4 R ON Buffer on Resistance (CFG/BPM) 16 24 Ω — R ON Buffer on Resistance (other GTL) 12 28 Ω — I LI Input Leakage Current — ±150 μA 3 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.[...]

Symbol Definition and Conditions Min Max Units Notes 1 V n Negative-Edge Threshold Voltage 0.275 * V CCIO_TERM 0.500 * V CCIO_TERM V — V p Positive-Edge Threshold Voltage 0.550 * V CCIO_TERM 0.725 * V CCIO_TERM V — C bus Bus Capacitance per Node N/A 10 pF — C pad Pad Capacitance 0.7 1.8 pF — Ileak000 leakage current at 0 V — 0.6 mA — Il[...]

8.0 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array package that interfaces with the motherboard using the LGA1150 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surfac[...]

mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load- bearing surface for thermal and mechanical solution. Table 50. Processor Loading Specifications Parameter Minimum Maximum Notes Static Compressive Load — 600 N [135 lbf] 1, 2, 3 Dynamic[...]

Table 52. Processor Materials Component Material Integrated Heat Spreader (IHS) Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Copper 8.7 Processor Markings The following figure shows the top-side markings on the processor. This diagram aids in the identification of the processor. Figure 21. Processor Top-Side Mar[...]

Figure 22. Processor Package Land Coordinates 8.9 Processor Storage Specifications The following table includes a list of the specifications for device storage in terms of maximum and minimum temperatures and relative humidity. These conditions should not be exceeded in storage or transportation. Table 53. Processor Storage Specifications Parameter[...]

Parameter Description Minimum Maximum Notes RH sustained storage The maximum device storage relative humidity for a sustained period of time. 60% @ 24 °C 5, 6 TIME sustained storage A prolonged or extended period of time; typically associated with customer shelf life. 0 Months 6 Months 6 Notes: 1. Refers to a component device that is not assembled[...]

9.0 Processor Ball and Signal Information This chapter provides processor ball information. The following table provides the ball list by signal name. Table 54. Processor Ball List by Signal Name Signal Name Ball # BCLKN V4 BCLKP V5 BPM#0 G39 BPM#1 J39 BPM#2 G38 BPM#3 H37 BPM#4 H38 BPM#5 J38 BPM#6 K39 BPM#7 K37 CATERR# M36 CFG_RCOMP H40 CFG0 AA37 C[...]

Signal Name Ball # FDI0_TX0N1 C13 FDI0_TX0P0 A14 FDI0_TX0P1 B13 IST_TRIGGER C39 IVR_ERROR R36 PECI N37 PEG_RCOMP P3 PEG_RXN0 F15 PEG_RXN1 E14 PEG_RXN10 F6 PEG_RXN11 G5 PEG_RXN12 H6 PEG_RXN13 J5 PEG_RXN14 K6 PEG_RXN15 L5 PEG_RXN2 F13 PEG_RXN3 E12 PEG_RXN4 F11 PEG_RXN5 G10 PEG_RXN6 F9 PEG_RXN7 G8 PEG_RXN8 D4 PEG_RXN9 E5 PEG_RXP0 E15 PEG_RXP1 D14 PEG_[...]

Signal Name Ball # RSVD M38 RSVD N35 RSVD P33 RSVD R33 RSVD R34 RSVD T34 RSVD T35 RSVD T8 RSVD U8 RSVD W8 RSVD Y8 RSVD_TP A4 RSVD_TP AV1 RSVD_TP AW2 RSVD_TP B3 RSVD_TP C2 RSVD_TP D1 RSVD_TP H16 RSVD_TP J10 RSVD_TP J12 RSVD_TP J13 RSVD_TP J16 RSVD_TP J8 RSVD_TP K11 RSVD_TP K12 RSVD_TP K13 RSVD_TP K8 RSVD_TP N36 RSVD_TP N38 RSVD_TP P37 SA_BS0 AV12 SA[...]

Signal Name Ball # SA_DQ6 AF37 SA_DQ60 AG2 SA_DQ61 AG3 SA_DQ62 AE2 SA_DQ63 AE1 SA_DQ7 AF40 SA_DQ8 AH40 SA_DQ9 AH39 SA_DQSN0 AE38 SA_DQSN1 AJ38 SA_DQSN2 AN38 SA_DQSN3 AU36 SA_DQSN4 AW5 SA_DQSN5 AP2 SA_DQSN6 AK2 SA_DQSN7 AF2 SA_DQSN8 AU32 SA_DQSP0 AE39 SA_DQSP1 AJ39 SA_DQSP2 AN39 SA_DQSP3 AV36 SA_DQSP4 AV5 SA_DQSP5 AP3 SA_DQSP6 AK3 SA_DQSP7 AF3 SA_DQ[...]

Signal Name Ball # SB_DQ36 AR13 SB_DQ37 AP13 SB_DQ38 AM13 SB_DQ39 AM12 SB_DQ4 AD34 SB_DQ40 AR9 SB_DQ41 AP9 SB_DQ42 AR6 SB_DQ43 AP6 SB_DQ44 AR10 SB_DQ45 AP10 SB_DQ46 AR7 SB_DQ47 AP7 SB_DQ48 AM9 SB_DQ49 AL9 SB_DQ5 AD35 SB_DQ50 AL6 SB_DQ51 AL7 SB_DQ52 AM10 SB_DQ53 AL10 SB_DQ54 AM6 SB_DQ55 AM7 SB_DQ56 AH6 SB_DQ57 AH7 SB_DQ58 AE6 SB_DQ59 AE7 SB_DQ6 AG34[...]

Signal Name Ball # VCC B25 VCC B27 VCC B29 VCC B31 VCC B33 VCC B35 VCC C24 VCC C25 VCC C26 VCC C27 VCC C28 VCC C29 VCC C30 VCC C31 VCC C32 VCC C33 VCC C34 VCC C35 VCC D25 VCC D27 VCC D29 VCC D31 VCC D33 VCC D35 VCC E24 VCC E25 VCC E26 VCC E27 VCC E28 VCC E29 VCC E30 VCC E31 VCC E32 VCC E33 VCC E34 VCC E35 continued... Signal Name Ball # VCC F23 VCC[...]

Signal Name Ball # VCC M13 VCC M15 VCC M17 VCC M19 VCC M21 VCC M23 VCC M25 VCC M27 VCC M29 VCC M33 VCC M8 VCC P8 VCC_SENSE E40 VCCIO_OUT L40 VCOMP_OUT P4 VDDQ AJ12 VDDQ AJ13 VDDQ AJ15 VDDQ AJ17 VDDQ AJ20 VDDQ AJ21 VDDQ AJ24 VDDQ AJ25 VDDQ AJ28 VDDQ AJ29 VDDQ AJ9 VDDQ AT17 VDDQ AT22 VDDQ AU15 VDDQ AU20 VDDQ AU24 VDDQ AV10 VDDQ AV11 VDDQ AV13 VDDQ AV[...]

Signal Name Ball # VSS AH36 VSS AH4 VSS AH5 VSS AH8 VSS AJ11 VSS AJ14 VSS AJ16 VSS AJ18 VSS AJ19 VSS AJ22 VSS AJ23 VSS AJ26 VSS AJ27 VSS AJ30 VSS AJ31 VSS AJ32 VSS AJ33 VSS AJ34 VSS AJ35 VSS AJ36 VSS AJ37 VSS AJ40 VSS AJ5 VSS AJ8 VSS AK1 VSS AK10 VSS AK11 VSS AK12 VSS AK13 VSS AK14 VSS AK18 VSS AK19 VSS AK24 VSS AK25 VSS AK26 VSS AK27 continued... [...]

Signal Name Ball # VSS AR14 VSS AR16 VSS AR17 VSS AR18 VSS AR19 VSS AR20 VSS AR21 VSS AR22 VSS AR23 VSS AR24 VSS AR27 VSS AR30 VSS AR31 VSS AR32 VSS AR33 VSS AR34 VSS AR35 VSS AR36 VSS AR37 VSS AR38 VSS AR39 VSS AR40 VSS AR5 VSS AT1 VSS AT10 VSS AT11 VSS AT12 VSS AT13 VSS AT14 VSS AT15 VSS AT16 VSS AT2 VSS AT24 VSS AT25 VSS AT26 VSS AT27 continued.[...]

Signal Name Ball # VSS D24 VSS D26 VSS D28 VSS D30 VSS D32 VSS D34 VSS D36 VSS D37 VSS D5 VSS D6 VSS D7 VSS D9 VSS E10 VSS E18 VSS E20 VSS E22 VSS E23 VSS E3 VSS E36 VSS E38 VSS E6 VSS E7 VSS E8 VSS F1 VSS F12 VSS F14 VSS F16 VSS F19 VSS F21 VSS F22 VSS F24 VSS F26 VSS F28 VSS F30 VSS F32 VSS F34 continued... Signal Name Ball # VSS F36 VSS F4 VSS F[...]

Signal Name Ball # VSS L36 VSS L38 VSS L6 VSS L7 VSS L8 VSS L9 VSS M1 VSS M12 VSS M14 VSS M16 VSS M18 VSS M20 VSS M22 VSS M24 VSS M26 VSS M28 VSS M30 VSS M32 VSS M34 VSS M35 VSS M37 VSS M4 VSS M40 VSS M5 VSS M6 VSS M7 VSS M9 VSS N1 VSS N2 VSS N3 VSS N33 VSS N34 VSS N39 VSS N4 VSS N6 VSS N7 continued... Signal Name Ball # VSS N8 VSS P2 VSS P34 VSS P[...]