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Intel S3420GP manuel d'utilisation

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Table des matières du manuel d’utilisation

  • Page 1

    Intel Server Board S3420 ® GP T echnical Product S pecification Intel order numbe Revision 1.0 August 2009 Enterprise Platforms and Services Division r E65697-003[...]

  • Page 2

    Revision History IntelP®P Server Board S3420GP TPS Revision History Date Revis ion Number Modifications Feb. 2009 0.3 Initial version May 2009 0.5 Update July. 2009 0.9 Update POST error code and diagram Aug. 2009 1.0 Update MT BF Revision 1.0 Intel order number E65697-003 ii[...]

  • Page 3

    IntelP®P Server Board S3420GP TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel ® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel [...]

  • Page 4

    Table of Contents IntelP®P Server Board S3420GP TPS Table of Contents 1. Introduction ................................................................................................................... ....... 2 1.1 Chapter Outline ........................................................................................................ 2 1.2 Server[...]

  • Page 5

    IntelP®P Server Board S3420GP TPS Table of Contents 3.6.5 Keyboard and Mouse Support ............................................................................... 26 3.6.6 Wake-up Control .................................................................................................... 27 3.7 Video Support .....................................[...]

  • Page 6

    Table of Contents IntelP®P Server Board S3420GP TPS 6.3.1 Intel ® Remote Management Module 3 (Intel ® RMM3) Connector .......................... 66 6.3.2 LCP / IPMB Header ............................................................................................... 67 6.3.3 HSBP Header ..........................................................[...]

  • Page 7

    IntelP®P Server Board S3420GP TPS Table of Contents 9.4.2 Standby Outputs .................................................................................................... 89 9.4.3 Remote Sense ....................................................................................................... 89 9.4.4 Voltage Regulation ....................[...]

  • Page 8

    List of Figures IntelP®P Server Board S3420GP TPS List of Figures Figure 1. Intel ® Server Board S3420GPLX Picture ....................................................................... 3 Figure 2. Intel ® Server Board S3420GP Layout ............................................................................ 4 Figure 3. Intel ® Server Board S[...]

  • Page 9

    IntelP®P Server Board S3420GP TPS List of Figures Figure 33. Setup Utility – Network Device Order Screen Display ............................................... 62 Figure 34. Setup Utility – Boot Manager Screen Display ............................................................ 63 Figure 35. Jumper Blocks (J1A2, J1F1, J1F3, J1F2 and J1F5) ...[...]

  • Page 10

    List of Tables IntelP®P Server Board S3420GP TPS List of Tables Table 1. Intel ® Server Board S3420GP Feature Set ..................................................................... 1 Table 2. Major Board Components ............................................................................................... 5 Table 3. Standard Platform DIMM [...]

  • Page 11

    IntelP®P Server Board S3420GP TPS List of Tables Table 33. SSI Processor Power Connector Pin-out (J9C1) ........................................................ 66 Table 34. Intel ® RMM3 Connector Pin-out (J2C1) ...................................................................... 66 Table 35. LPC / IPMB Header Pin-out (J1H2) ...................[...]

  • Page 12

    List of Tables IntelP®P Server Board S3420GP TPS Table 67. POST Progress Code LED Example ........................................................................ 109 Table 68. Diagnostic LED POST Code Decoder ...................................................................... 109 Table 69. POST Error Messages and Handling .....................[...]

  • Page 13

    IntelP®P Server Board S3420GP TPS List of Tables <This page intentionally left blank.> Revision 1.0 Intel order number E65697-003 xiii[...]

  • Page 14

    Introduction IntelP®P Server Board S3420GP TPS 1. Introduction This Technical Product Specification (TPS) provides board specific information detailing the features, functionality, and high-level architecture of the Intel ® Server Board S3420GP. In addition, you can obtain design-level information for specific subsystems by ordering the External [...]

  • Page 15

    IntelP®P Server Board S3420GP TPS Overview 2. Overview The Intel ® Server Board S3420GP is a monolithic printed circuit board (PCB) with features designed to support entry-level severs. It has three board SKUs: S3420GPLX, S3420GPLC, and S3420GPV. 2.1 Intel ® Server Board S3420GP Feature Set Table 1. Intel ® Server Board S3420GP Feature Set Feat[...]

  • Page 16

    Overview IntelP®P Server Board S3420GP TPS Feature Description Add-in PCI Card, PCI Express* Card • Intel® Server Board S3420GPLX  Slot1: One 5V PCI 32 bit / 33 MHz connector.  Slot2: One PCI Express* G en1 x4 (x1 throughput) connector.  Slot3: One PCI Express* G en1 x8 (x4 throughput) connector.  Slot4: One PCI Express* G en2 x8 (x[...]

  • Page 17

    IntelP®P Server Board S3420GP TPS Overview 2.2 Server Board Layout Figure 1. Intel ® Server Board S3420GPLX Picture Revision 1.0 Intel order number E65697-003 3[...]

  • Page 18

    Overview IntelP®P Server Board S3420GP TPS 2.2.1 Server Board Connector and Component Layout The following figure shows the board layout of the server board. Each connector and major component is identified by a number or letter, and 2 provides the description. AF003290 CC DD AB C D EF G H I J K LM N O P Q R S T U V W X Y Z A A BB Figure 2. Intel [...]

  • Page 19

    IntelP®P Server Board S3420GP TPS Overview Table 2. Major Board Components Description Description A Slot 1, 32 Mbit/33 MHz PCI Q System FAN2 and System FAN 3 B Slot 2, PCI Express* Gen1 x1 (x4 connector) (Intel Server Board S3420GPLX only) R CPU connector C Intel RMM3 Connector(Intel Server Board S CPU Fan connector S3420GPLX only) D Gen2 complia[...]

  • Page 20

    Overview IntelP®P Server Board S3420GP TPS 2.2.2 Intel ® Server Board S3420GP Mechanical Drawings Figure 3. Intel ® Server Board S3420GP – Key Connector and LED Indicator IDENTIFICATION Revision 1.0 Intel order number E65697-003 6[...]

  • Page 21

    IntelP®P Server Board S3420GP TPS Overview Figure 4. Intel ® Server Board S3420GP – Hole and Component Positions Revision 1.0 Intel order number E65697-003 7[...]

  • Page 22

    Overview IntelP®P Server Board S3420GP TPS Figure 5. Intel ® Server Board S3420GP – Major Connector Pin Location (1 of 2) Revision 1.0 Intel order number E65697-003 8[...]

  • Page 23

    IntelP®P Server Board S3420GP TPS Overview Figure 6. Intel ® Server Board S3420GP –Major Connector Pin Location (2 of 2) Revision 1.0 Intel order number E65697-003 9[...]

  • Page 24

    Overview IntelP®P Server Board S3420GP TPS Figure 7. Intel ® Server Board S3420GP – Primary Side Keepout Zone Revision 1.0 Intel order number E65697-003 10[...]

  • Page 25

    IntelP®P Server Board S3420GP TPS Overview Figure 8. Intel ® Server Board S3420GP – Secondary Side Keepout Zone Revision 1.0 Intel order number E65697-003 11[...]

  • Page 26

    Overview IntelP®P Server Board S3420GP TPS 2.2.3 lowing f t of the rear I/O components for the server board. Server Board Rear I/O Layout The fol igure shows the layou A Serial Port A C NIC Port 1 (1 Gb) and Dual USB Port Connector B Video D NIC port 2 (1 Gb) and Dual USB Port Connector Figure 9. Intel ® Server Board S3420GP Rear I/O Lay out Revi[...]

  • Page 27

    IntelP®P Server Board S3420GP TPS Functional Architecture 3 nct . Fu ional Architecture The architecture and design of the Intel ® Server Board S3420GP is based on the Intel ® 3420 Chipset. The chipset is designed for systems based on the Intel ® Xeon ® processor in the FC- LGA 1156 socket package. The chipset contains two main components: [...]

  • Page 28

    Functional Architecture IntelP®P Server Board S3420GP TPS 61 2 FLASH FLASH LPC SERIAL 1 SATA-II PCI32 6 onboard 9.6" S3420GPLC Block Diagram ATX - 12" x Not 1. Video integr ated into BMC. es: PORT 80 RMII VIDEO SATA FLASH FLASH BMC Boot SPI Flash Intel ® 3420 Chipset Intel ® 3420 Chipset Zoar IBMC 82574 Ch A Ch B DDR3 (Ch B) PCIe G en2[...]

  • Page 29

    IntelP®P Server Board S3420GP TPS Functional Architecture The server 3.1.2 Intel Turbo Boost Technology Inte Boost certain processors in the Intel ® Xeon ® Processor ster than the marked frequency if the processor is operating below power, temperature, and current limits. This results in increased performance for both multi-threaded and n Intel [...]

  • Page 30

    Functional Architecture IntelP®P Server Board S3420GP TPS frequency can be 1066/1333 MHz. All RDIMMs and UDIMMs include ECC (Error Correction Code) operation. Various speeds and memory technologies are supported. RAS (Reliability, Availability, and Serviceability) is not supported on the Intel ® Server Board S3420GP. 3.2.1 Memory Sizing and Confi[...]

  • Page 31

    IntelP®P Server Board S3420GP TPS Functional Architecture Memory BIST, the system acts as if no memory is available, beeping and halting with itialization process is unable to properly perform the DQ/DQS training on a memory channel, the BIOS emits a beep code and displays POST Diagnostic LED code 0xEA momentarily during the beeping. If an two qua[...]

  • Page 32

    Functional Architecture IntelP®P Server Board S3420GP TPS offered by the Intel ® S3420 I/O Hub and a variably-sized Memory Mapped I/O region for the PCI Express* functions. 3.2.3.2 High-Memory Reclaim When 4 GB or more o f physical memory is installed (physical memory is the memory installed 3 DIMM mory is lost. However, the Intel ® 3420 chipset[...]

  • Page 33

    IntelP®P Server Board S3420GP TPS Functional Architecture 3.2.5.1 TableMemory Subsystem Operating Frequency Determinat The rules for determining the operating frequency of the memory channels are simple, but not necessarily straightforward. There are several limitin ion g factors, including the number of DIMMs R), or ponent – the slowest DIMM or[...]

  • Page 34

    Functional Architecture IntelP®P Server Board S3420GP TPS You must observe the following general rules when selecting and configuring memory to obtain the best performance from the system. 1. DDR3 RDIMMs must always be populated using a fill-farthest method . 2. DDR3 UDIMMs must always be populated on DIMM A1/A2/B1/B2. 3. Intel ® Xeon ® 3400 Ser[...]

  • Page 35

    IntelP®P Server Board S3420GP TPS Functional Architecture 3.3 Intel ® 3420 Chipset PCH The Intel ® 3420 Chipset component is the Platform Controller Hub (PCH). The PCH is designed for use with Intel ® processor in a UP server platform. The role of the PCH in Intel ® Server Board S3420GP is to manage the flow of information between its eleven i[...]

  • Page 36

    Functional Architecture IntelP®P Server Board S3420GP TPS When operating with two PCI Express* controllers, each controller can operate at either 2.5 GT/s or 5.0 GT/s. The PCI Express* architecture is specified in three layers: Transaction Layer, Data Link Layer, and Physical Layer. The partitioning in the component is not necessarily along these [...]

  • Page 37

    IntelP®P Server Board S3420GP TPS Functional Architecture The BIOS supports USB 2.0 mode of operation, and as such supports USB 1.1 and USB 2.0 re-boot phase, the BIOS automatically supports the hot addition and hot removal of US e device is hot plugged, the BIOS detects the device insertion, initializes the device, and makes it available to the u[...]

  • Page 38

    Functional Architecture IntelP®P Server Board S3420GP TPS  12 10-bit ADCs  Eight Fan Tachometers  Four PWMs  JTAG Master 50 Serial Ports  Serial IRQ Support The Pilot II contains an integrated KVMS subsystem and graphics controller with the following or keyboard, mouse, and storage devices  raphics memory interface  Up to 1600[...]

  • Page 39

    IntelP®P Server Board S3420GP TPS Functional Architecture ARM926EJ-S 16K D & I Cache Interrupt Controller Fan Tach (12) PWM (4) ADC Thermal USB 1.1 & USB 2.0 LPC Master, JTAG Master, & SPI FLash UART (3) GPIO KCS BT & Mailboxes System Wakeup Control LPC Interface Graphics Controller BMC & KVMS Subsystem BMC & KVMS Subsystem[...]

  • Page 40

    Functional Architecture IntelP®P Server Board S3420GP TPS • Give the customer the option to add a dedica the product. ted management 100 Mbit LAN interface to o support ble 5. Optional RMM3 Advanced Management Board Features • Provide additional flash space, enabling the Advanced Management functions t WS-MAN and CIMON. Ta Feature Description [...]

  • Page 41

    IntelP®P Server Board S3420GP TPS Functional Architecture 3.6.6 The super I/O contains functionality that allows various events to power on and power off the system 3.7 The server board includes a video controller in an on-board Server Engines* Integrated Baseboard Management Controller along with 64 MB of video DDR2 SDRAM. The SVGA subsystem supp[...]

  • Page 42

    Functional Architecture IntelP®P Server Board S3420GP TPS Onboard Video Enabled Disabled Onboard video controller. Warning: System video is completely disabled if this option is disabled and an add-in video adapter is not installed. Dual Monitor Video Disabled an add-in video adapter are enabled for system Enabled If enabled, both the onboard vide[...]

  • Page 43

    IntelP®P Server Board S3420GP TPS Functional Architecture  NIC 2 MAC address – Assigned the NIC 1 MAC address +1 g three MAC addresses assigned to it at  NIC 1 MAC address C 1 MAC address +1 igned to it at the Intel factory: ® ® I/O Acceleration Technology. 3.9.1 Dir C 3.1 The Int Tec o ists of technology components that support the virt[...]

  • Page 44

    Platform Management IntelP®P Server Board S3420GP TPS 4. Plat form Management The platform management subsystem is based on the Integrated BMC features of the ServerEngines* Pilot II. The onboard platform management subsystem consists of firmware. The following n communication buses, sensors, system BIOS , and server management diagram provides an[...]

  • Page 45

    IntelP®P Server Board S3420GP TPS Platform Management  ccess to a SEL. System event log (SEL) device functionality: The Integrated BMC supports and provides a  Sensor device record (SDR) repository device functionality: The Integrated BMC em SDRs. Integrated BMC provides IPMI and report system health. t mode (SMM). AN protocol (RMCP, RMCP+) [...]

  • Page 46

    Platform Management IntelP®P Server Board S3420GP TPS  Power unit management: Support for power unit sensor. The Integrated Baseboard anagement Controller (Integrated BMC) handles power-good dropout conditions. DIMM temperature monitoring: New sens ors and M  improved acoustic management using c  (  Dynamic Host Configuration Protocol [...]

  • Page 47

    IntelP®P Server Board S3420GP TPS Platform Management 4.2.2.3 Availa Up to two remote KVM sessions are supported. The default inactivity timeout is 30 minutes; r, chan b l system remote KVM is not deactiv KVM sessions persist across system reset but not across an AC power loss. 4.2.3 Media Redirection The embedded web server provides a Java applet[...]

  • Page 48

    Platform Management IntelP®P Server Board S3420GP TPS 4.2.4 Web Services for Management (WS-MAN) hentication Protocol (LDAP) l for us ords and sessions are not d Webserver The te authentication is handled by IPMI user names and passwords. Base functionality for the embedd    w  The e See p 4.3 M ssential platform functionality. This Ma[...]

  • Page 49

    IntelP®P Server Board S3420GP TPS BIOS User Interface 5. BIOS User Interface 5.1 n The ostic Screen displays in o ot is enabled in the BIOS setup, a logo splash screen displays. By default, is enabled in the BIOS lays during POST, press <Esc> de the logo and display the d o is not present in the flash Boot is disabled in the system configura[...]

  • Page 50

    BIOS User Interface IntelP®P Server Board S3420GP TPS z Localization - The BIOS Setup uses the Unicode standard and is capable of displaying setup forms all languages urrently included in the Unico server board BIOS is only available in English. z Console Redirection - The BIOS Setup is functional through various terminal emulation standards. This[...]

  • Page 51

    IntelP®P Server Board S3420GP TPS BIOS User Interface Table 10. BIOS Setup: Keyboard Command Bar Key Option Description <Enter> Execute The < Enter> key is used to activate sub -menus w hen the select ed feature is a sub- or to display a pick list if a selected option has a value field, or to select a -field for multi-valued features l[...]

  • Page 52

    BIOS User Interface IntelP®P Server Board S3420GP TPS 5.3.1.4 Menu Selection Bar The Menu Selection Bar is located at the top of the BIOS Setup Utility screen. It displays the major menu selections available to the user. By using the left and right arrow keys, the user can select the menus listed here. Some menus are hidden and become available by[...]

  • Page 53

    IntelP®P Server Board S3420GP TPS BIOS User Interface Main Advance d Security Serv er Management Boot Options Boot Manager Logged in as <Administrator or User> Platform ID <Platform Identification String> System BIOS Version SXXXX.86B.xx.yy.zzzz Build Date <MM/DD/YYYY> Memory Total Memory <How much memory is installed> Quie[...]

  • Page 54

    BIOS User Interface IntelP®P Server Board S3420GP TPS Setup Item Options Help Text Comments Size Informa total phy the syste physical l memory installed tion only. Displays the sical memory installed in m, in MB or GB. The term memory indicates the tota discovered in the form of DDR3 DIMMs. Quiet Boot Enabled Disabled [Enabled] – Display the log[...]

  • Page 55

    IntelP®P Server Board S3420GP TPS BIOS User Interface Main Advance d Sec rity u Serv er Management Boot Options Boot Manager ► Processor Configuration ► Memory Configuration ► Mass Storage Controller Configuration ► Serial Port Configuration ► USB Configuration ► PCI Configuration ► System Acoustic and Performance Configuration Figur[...]

  • Page 56

    BIOS User Interface IntelP®P Server Board S3420GP TPS Advanced Processor Configuration Processor Socket CPU 1 Processor ID <CPUID> Processor Frequency <Proc Freq> Microcode Revision <Rev data> L1 Cache RAM Size of Cache L2 Cache RAM Size of Cache L3 Cache RAM Size of Cache Processor 1 Version <ID string from Processor 1> Cu[...]

  • Page 57

    IntelP®P Server Board S3420GP TPS BIOS User Interface Setup Item Options Help Text Comments Microcode Revision ion of Information only. Revis the loaded microcode. L1 Cache RAM . Size of the . Information only Processor L1 Cache L2 C of the ache RAM Information only. Size Processor L2 Cache L3 Cache RAM . Size of the . Information only Processor L[...]

  • Page 58

    BIOS User Interface IntelP®P Server Board S3420GP TPS Setup Item Options Help Text Comments Coherency Support Enable/Disable Intel ® VT-d Coherency support. Only visible w hen Intel ® Virtualization Technology for Directed I/O is enabled. Enabled Disabled ATS Support Enabled Disabled Enable/Disable Intel ® VT-d Address Transl upport. Only visib[...]

  • Page 59

    IntelP®P Server Board S3420GP TPS BIOS User Interface Advanced Memory Configuration Total Memory <Total Physical Memory Installed in System> Effective Memory <Total Effective Memory> Current Configuration <Independent > Current Memory Speed <Speed that installed memory is running at.> ► DIMM Information DIMM_A1 Install d/[...]

  • Page 60

    BIOS User Interface IntelP®P Server Board S3420GP TPS Setup Item Comments Current Memo ory ry Information only. Displays the speed the mem Speed is running at. DIMM_ XY MM socket present on the board. Each DIMM socket field reflects one of the following possible his ed in a the BIOS to optimize memory configuration. Failed : The DDR3 DIMM installe[...]

  • Page 61

    IntelP®P Server Board S3420GP TPS BIOS User Interface Setup Item Options Help Text Comments Intel AID Enabled or Disable the Intel ® SAS Unavailable if the SAS Module (AXX4SASMOD) is not present. is option is not lable on some models. ® Entry SAS R Enabled Module Entry RAID Module Note: avai Disabled Th Configure Intel ® Entry LSI® Inte R Inte[...]

  • Page 62

    BIOS User Interface IntelP®P Server Board S3420GP TPS Advanced Serial Port Configuration Enabled /Disabled Serial A Enable s 3F8h / 2F8h / 3E8h / 2E8h Addres 3 or 4 IRQ Serial B Enable Enabled /Disabled Address 3F8h / 2F8h / 3E8h / 2E8h IRQ 3 or 4 Figure 20. Setup Utility – Serial Po rt Configuration Screen Display Table 16. Setup Utility – Se[...]

  • Page 63

    IntelP®P Server Board S3420GP TPS BIOS User Interface Advanced USB Configuration Detected USB Devices <Total USB Devices in Sy stem> USB Controller Enabled / Disabled Legacy USB Support Enabled / Disabled / Auto Port 60/64 Emulation Enabled / Disabled Make USB Devices Non-Bootable Enabled / Disabled USB Mass Storage Device Configuration / 2 [...]

  • Page 64

    BIOS User Interface IntelP®P Server Board S3420GP TPS Setup Item Options Help Text Comments Device timeout 20 sec 30 sec 40 sec Storag t. Setting to a larger storage device to be ready, if needed. er is Reset 10 sec USB Mass e device Start Unit command timeou value prov ides more time for a mass Grayed out if the USB Controll disabled. One line fo[...]

  • Page 65

    IntelP®P Server Board S3420GP TPS BIOS User Interface Table 18. Setup Utility – PCI Configuration Screen Fields Setup Item Options Help Text Comments Ma mize Memory bel Enabled abled If enabled. the BIOS maximizes usage of memory below 4 GB limiting PCIE Extended Configuration Space to 64 buses. xi ow 4GB Dis for OS without PAE by Memory abo Ena[...]

  • Page 66

    BIOS User Interface IntelP®P Server Board S3420GP TPS Advanced System Acoust rfor ic and Pe mance Configuration Set Throttling Mode Auto / CLTT / OLTT Altitude 300m or less / 301m-900m / 901m – 15 m 00m / Higher than 1500 Set Fan Profile Performance , Acoustic Figure 23. Se S c and Performance Configuration Screen Display Table 19. Setup Utility[...]

  • Page 67

    IntelP®P Server Board S3420GP TPS BIOS User Interface Setup Item Options Help Text Comments Set Fan Profile Performance Acoustic [Performance] - Fan control provides primary system cooling before attempting to throttle memory. [Acou emo erm This option is grayed out if CLTT is is option is not available on s stic] - The system will favor using thr[...]

  • Page 68

    BIOS User Interface IntelP®P Server Board S3420GP TPS Setup Item Options Help Text Comments S Passw et Administrator [123aBcD] d i used to control change access in BIOS Setup Utility. Only alphanumeric characters can be used. Maximum length is 7 characters. It is case sensitive. Note: Administrator password must be set in order to use the user acc[...]

  • Page 69

    IntelP®P Server Board S3420GP TPS BIOS User Interface Main Advance d Security Server Management Boot Options Boot Manager Assert NMI on SERR Enabled / Disabled Assert NMI on PERR Enabled / Disabled Resume on AC Power Loss Stay Off / Last state / Reset Clear System Event Log Enabled / Disabled FRB-2 Enable Enabled / Disabled O/S Boot Watchdog Timer[...]

  • Page 70

    BIOS User Interface IntelP®P Server Board S3420GP TPS Setup Item Options Help Text Comments O Timer na ed Disabled If enabled, with the timeout value selected. If the OS does not complete booting before the timer expires, the BMC resets the s Requires OS support or Intel Management Software /S Boot Watchdog E bl the BIOS programs the wa tchdog tim[...]

  • Page 71

    IntelP®P Server Board S3420GP TPS BIOS User Interface Table 22. Setup Utility – Console Re direction Configuration Fields Setup Item Options Help T ext Console Redirection Disabled Console redirection allows a serial port to be used for server abled] - No console redirection. or console redirection. [Serial Port B] - Configure serial port B for [...]

  • Page 72

    BIOS User Interface IntelP®P Server Board S3420GP TPS Server Management System Information Board Part Number Board Serial Number System Part Number System Serial Number Chassis Number Part Chassis Serial Number BMC Firmware Revision HSC Firmware Revision ME Firmware Revision SDR Revision UUID Figure 27. Setup Utility – Serv er Management System [...]

  • Page 73

    IntelP®P Server Board S3420GP TPS BIOS User Interface Main Advance d Security Server Management Boot Options Boot Manager System Boot Timeout <0 - 65535> Boot Option #1 <Available Boot devi ces> Boot Option #2 <Available Boot devi ces> Boot Option #x <Available Boot dev ices> Hard Disk Order CDROM Order Network Device Order[...]

  • Page 74

    BIOS User Interface IntelP®P Server Board S3420GP TPS Setup Item Options Help Text Comments Ne ork Device Order Set the order of this group. tw the legacy devices in Visible when one or more of these devices are available in the system. BEV Device Order Set the order of the legacy devices in this group. Visible when one or more of these devices ar[...]

  • Page 75

    IntelP®P Server Board S3420GP TPS BIOS User Interface Setup Item Options Help Text Delete Boot Option Select one to Delete Remove an EFI boot option from the Internal EFI Shell boot order. 5.3.2.6.2 Hard Disk Order Screen The Hard Disk Order screen allows the user to control the hard disks. To access this screen from the Main screen, choose Boot O[...]

  • Page 76

    BIOS User Interface IntelP®P Server Board S3420GP TPS Setup Item Options Help Text CDROM #1 Available Legacy devices for this Device Set system boot order by selecting the boot option for this position. group. CDROM #2 Available Legacy devices Set system boot order by selecting the boot option for this position. for this Device group. 5.3.2.6.4 Fl[...]

  • Page 77

    IntelP®P Server Board S3420GP TPS BIOS User Interface Table 29. Setup Utility etw ork Device O – N rder Fields Setup Item Options Help Text Netw vice #1 Available Legacy devices for this Devic group. Set ng the boot option for this position. ork De e system boot order by selecti Netw vice #2 Available Legacy devic for this Devic group. Set by se[...]

  • Page 78

    BIOS User Interface IntelP®P Server Board S3420GP TPS • Moving the clear system configuration jumper. • IPMI command (se ystem and the BIOS Setup loads user set defaults instead of The recommended steps to load the BIOS defaults are: 1. Power 2. Move the Clear CMOS jumper from pins 1-2 to pins 2-3. 3. Mov he Cl jumper from pin -3 to 4. Pow up [...]

  • Page 79

    IntelP®P Server Board S3420GP TPS Conn ector/Header Locations and Pin-outs 6. Connector / Header Locations and Pin-out s 6.1 The fol jumper corresp . Board Connector Matrix Board Connector Information lowing section provides detailed information regarding all connectors, headers, and s on the server board. It lists all connector types available on[...]

  • Page 80

    Connector/Header Locations and Pin-out s IntelP®P Server Board S3420GP TPS  One SSI-compliant 2x4 pin power connector (J9C1), which provides 12-V power to the CPU VRD. The following tables define the connector pin-outs. Tab ebo ctor Pin-out (J9A1) le 32. Bas ard Pow er Conne Pin Signal Color Pin Signal Color 1 +3.3 Vdc Orange 13 +3.3 Vdc Orange[...]

  • Page 81

    IntelP®P Server Board S3420GP TPS Conn ector/Header Locations and Pin-outs Pin Signal Name Pin Signal Name 1 P3V3_AUX 2 RMII_IBMC_RMM3_MDIO 3 P3V3_AUX 4 RMII_IBMC_RMM3_MDC 5 GND 6 RMII_IBMC_RMM3_RXD1 7 GND 8 RMII_IBMC_RMM3_RXD0 9 GND 10 RMII_IBMC_RMM3_CRS_DV 11 GND 12 CLK_50M_RMM3 13 GND 14 RMII_IBMC_RMM3_RX_ER 15 GND 16 RMII_IBMC N _RMM3_TX_E 17 [...]

  • Page 82

    Connector/Header Locations and Pin-out s IntelP®P Server Board S3420GP TPS 2 SGPIO Load Signal SGPIO_LOAD 3 SGPIO_DAT AOUT0 S IO Da GP ta Out 4 SGPIO_DAT AOUT1 S IO Da GP ta In 6.4 Front Control Panel Connector The server board provides a 24-pin SSI front panel connector (J1C1) for use with Intel ® and third-party chassis. The following table pro[...]

  • Page 83

    IntelP®P Server Board S3420GP TPS Conn ector/Header Locations and Pin-outs power state signals from the chipset and de-asserts PS_PWR_ON to the power supply. As a safety mechanism, if the BIOS fails to service the request, the Integrated BMC automatically pow ff 4 to 5 se  Power Button — n to ating If an ACPI operating system is running, pres[...]

  • Page 84

    Connector/Header Locations and Pin-out s IntelP®P Server Board S3420GP TPS Table 39. System Status LED Indicator States Color State Criticality Description Green Solid on Ok Sy stem booted and ready Green ~1 Hz blink Degraded System degra on d asserted. on erted. on ed. an ystem cooling maintained. his ndant sy stems.  Pow r supply predictive f[...]

  • Page 85

    IntelP®P Server Board S3420GP TPS Conn ector/Header Locations and Pin-outs 6.5 I/O Connectors 6.5.1 VGA Connector The following table details the pin-out definition of the VGA connector (J7A1). Table 40. VGA Connector Pin-out (J7A1) Pin Sig me nal Na Description 1 V_IO_R_C Red (analog color signal R) ONN 2 V_IO_G_C Green (analog color signal G) ON[...]

  • Page 86

    Connector/Header Locations and Pin-out s IntelP®P Server Board S3420GP TPS Pin Signa l Name Pin Signal Name 1 P5V_USB_PWR75 H_11 2 USB_PC _FB_DN 3 SB_ U PCH_11_FB_DP 4 GND 5 5V_ B_DN P USB_PWR75 6 USB_PCH_10_F 7 USB_PCH_10_F B_DP 8 GND 9 P1V8_PHY_VCT_R 10 NIC1_MDIP< 0> 11 NIC1_MDIN<0> 12 NIC1_MDIP<1> 13 NIC1_MDIN<1> 14 NIC2[...]

  • Page 87

    IntelP®P Server Board S3420GP TPS Conn ector/Header Locations and Pin-outs Table 45. External Serial A Port Pin-out (J8A1) Pin Signal Name Description 1 SPA_DCD DCD (carrier detect) 2 SPA_SIN_L RXD (receive data) 3 SPA_SOUT _N TXD (Transmit data) 4 SPA_DT R DT R (Data terminal ready) 5 GND Ground 6 SPA_DSR DSR (data set ready) 7 SPA_RT S RTS (requ[...]

  • Page 88

    Connector/Header Locations and Pin-out s IntelP®P Server Board S3420GP TPS Table 47. Internal USB Connector Pin-out ( J1E1, J1D1) Pin Signal Name Description 1 USB2_VBUS4 USB power (port 4) 2 USB2_VBUS5 USB power (port 5) 3 USB_ICH_P4N_CONN USB port 4 negative signal 4 USB_ICH_P5N_CONN USB port 5 negative signal 5 USB_ICH_P4P_CONN USB port 4 posit[...]

  • Page 89

    IntelP®P Server Board S3420GP TPS Conn ector/Header Locations and Pin-outs 6.6 PCI Express* Slot / PCI Slot / Riser Card Slot / A PCI-E Riser card will enable a PCI-E add-on card to be accommodated in the 1U chassis. The following table shows the pin-out for this riser slot. Table 50. Pin-out of adaptive riser slot / PCI Express slot 6 Pin Signal [...]

  • Page 90

    Connector/Header Locations and Pin-out s IntelP®P Server Board S3420GP TPS B39 GND GND A39 PERP5 P2E_CPU_S6_RXN<2> B40 GND GND A40 PERN5 P2E_CPU_S6_RXP<2> B41 PETP6 P2E_CPU_C_S6_TXP<1> A41 GND GND B42 PETN6 P2E_CPU_C_S6_T XN<1> A42 GND GND B43 GND GND A43 PERP6 P2E_CPU_S6_RXN<1> B44 GND GND A44 PERN6 P2E_CPU_S6_RXP<[...]

  • Page 91

    IntelP®P Server Board S3420GP TPS Conn ector/Header Locations and Pin-outs Three PCI Express* x8 connectors (J2B2, J3B1 and J4B2) Pin Signal Pin Signal Pin Signal Pin Signal A1 PRSNT1# B1 +12V A26 HSIP[2] B26 GND A2 +12V B2 +12V A27 GND B27 HSOP[3] A3 +12V B3 RESERVED A28 GND B28 HSON[3] A4 GND B4 GND A29 HSIP[3] B29 GND A5 JTAG2/TCk B5 SMCLK A30 [...]

  • Page 92

    Connector/Header Locations and Pin-out s IntelP®P Server Board S3420GP TPS Pin# Signal Pin# Signal Pin# Signal Pin# Signal A5 JTAG2 B5 SMCLK A21 PERP1 B21 GND A6 JTAG3 B6 SMDAT A22 PERN1 B22 GND A7 JTAG4 B7 GND A23 GND B23 PETP2 A8 JTAG5 B8 +3.3V A24 GND B24 PETN2 A9 +3.3V B9 JTAG1 A25 PERP2 B25 GND A10 +3.3V B10 3.3VAUX A26 PERN2 B26 GND A11 PERS[...]

  • Page 93

    IntelP®P Server Board S3420GP TPS Conn ector/Header Locations and Pin-outs Pin # Signal Pin # Signal Pin # Signal Pin # Signal B26 C/BE[3]# A26 IDSEL B57 Ground A57 AD[02] B27 AD[23] A27 +3.3V B 58 AD[01] A58 AD[00] B28 Ground A28 AD[22] B59 V_IO A59 V_IO B29 AD[21] A29 AD[20] B60 ACK64# A60 REQ64# B30 AD[19] A30 Ground B61 +5V A61 + 5V B31 + 3.3V[...]

  • Page 94

    Jumper Blocks IntelP®P Server Board S3420GP TPS 7. Jumper Blocks The server board has several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server board. Figure 35. Jumper Blocks (J1A2, J1F1, J1F3, J1F2 and J1F5) Table 52. Server Board Jumpers (J1F1, J1F2, J1F3, J1F5, J1A2) Jumper Name Pins System [...]

  • Page 95

    IntelP®P Server Board S3420GP TPS Jumper Blocks Jumper Name Pins System Results Force Update 2-3 Integrated BMC Firmware Force Update Mode – Enabled 7.1 CMOS Clear and Password Reset Usage Procedure The CMOS Clear (J1F5) and Password Reset (J1F2) recovery features are designed such that the desired operation can be achieved with minimal system d[...]

  • Page 96

    Jumper Blocks IntelP®P Server Board S3420GP TPS 7. Open the chassis and move the jumper back to the default position (covering pins 1 and 2). 8. Close the server chassis. 9. Power up the server. The password is now cleared and can be reset by going into the BIOS setup. 7.2 Integrated BMC Force Update Procedure When performing the standard Integrat[...]

  • Page 97

    IntelP®P Server Board S3420GP TPS Jumper Blocks firmware update process fails due to ME not being in the proper update state, the server board provides an Integrated BMC Force Update jumper (J1F1), which forces the ME into the proper update state. The following procedure should be completed in the event the standard ME firmware update process fail[...]

  • Page 98

    Intel® Light Guided Diagnostics IntelP®P Server Board S3420GP TPS 8. Intel ® Light Guided Diagnostics The server board has several on-board diagnostic LEDs to assist in troubleshooting board-level issues. This section shows where each LED is located on the server board and describes the function of each LED. 8.1 System Status LED The server boar[...]

  • Page 99

    IntelP®P Server Board S3420GP TPS Intel® Light Guided Diagnostics 8.2 Post Code Diagnostic LEDs During the system boot process, the BIOS executes several platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code on the POST code diagnostic[...]

  • Page 100

    Design and Environmental Specifications IntelP®P Server Board S3420GP TPS 9. Design and Environment al Specifications 9.1 Intel ® Server Board S3420GP Design Specifications The operation of the server board at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditi[...]

  • Page 101

    IntelP®P Server Board S3420GP TPS Design and Environmental Specifications 9.3 Server Board Power Requirements This section provides power supply design guidelines for a system using the Intel ® Server Board S3420GP, including voltage and current specifications, and power supply on/off sequencing characteristics. The following diagram shows the po[...]

  • Page 102

    Design and Environmental Specifications IntelP®P Server Board S3420GP TPS 9.3.1 Processor Power Support The server board supports the Thermal Design Power (TDP) guideline for Intel ® Xeon ® processor. The Flexible Motherboard Guidelines (FMB) were also followed to help determine the suggested thermal and current design values for anticipating fu[...]

  • Page 103

    IntelP®P Server Board S3420GP TPS Design and Environmental Specifications 9.4.1 Grounding The grounds of the power supply output connector pins provide the power return path. The output connector ground pins are connected to the safety ground (power supply enclosure). This grounding is designed to ensure passing the maximum allowed common mode noi[...]

  • Page 104

    Design and Environmental Specifications IntelP®P Server Board S3420GP TPS +5 VSB 0.5 A 0.25 A/ µ sec 20 µ F Notes: 1. Step loads on each 12 V output may happen simultaneously and should be tested that way. 9.4.6 Capacitive Loading The power supply is stable and meets all requirements with the following capacitive loading ranges. Table 60. Capaci[...]

  • Page 105

    IntelP®P Server Board S3420GP TPS Design and Environmental Specifications  The output voltages must rise from 10% to within regulation limits (T vout_rise ) within 5 ms to 70 ms, except for 5 VSB, in which case it is allowed to rise from 1.0 ms to 25 ms.  The +3.3 V, +5 V, and +12 V output voltages should start to rise approximately at the s[...]

  • Page 106

    Design and Environmental Specifications IntelP®P Server Board S3420GP TPS Table 63. Turn On/Off Timing Item Description Minimum Maximum Units T sb_on_delay Delay from AC being applied to 5 VSB being within regulation. N/A 1500 Msec T ac_on_delay Delay from AC being applied to all output voltages being within regulation. N/A 2500 Msec T vout_holdup[...]

  • Page 107

    IntelP®P Server Board S3420GP TPS Design and Environmental Specifications 9.4.11 Residual Voltage Immunity in Standby Mode The power supply is immune to any residual voltage placed on its outputs (typically, a leakage voltage through the system from standby output) up to 500 mV. There is no additional heat generated nor stressing of any internal c[...]

  • Page 108

    Design and Environmental Specifications IntelP®P Server Board S3420GP TPS +5 V 5.7 6.2 +12 V 13.3 14.5 -12 V -13.3 -14.5 +5 VSB 5.7 6.5 Revision 1.0 Intel order number E65697-003 94[...]

  • Page 109

    IntelP®P Server Board S3420GP TPS Regulatory and Certification Information 10. Regulatory and Certification Information 10.1 Product Regulatory Compliance Intended Application –This product is to be evaluated and certified as Information Technology Equipment (ITE), which may be installed in offices, schools, computer rooms, and similar commercia[...]

  • Page 110

    Regulatory and Certification Information IntelP®P Serv er Board S3420GP TPS  FCC/ICES-003 Class A Attestation (USA/Canada)  C-Tick Declaration of Conformity (Australia)  MED Declaration of Conformity (New Zealand)  BSMI Declaration (Taiwan)  RRL Certification (Korea)  GOST – Listed on one System License (Russia)  Belarus –[...]

  • Page 111

    IntelP®P Server Board S3420GP TPS Regulatory and Certification Information Revision 1.0 Intel order number E65697-003 97 10.2 Product Regulatory Compliance Markings The server board is provided with the following regulatory marks . Regulatory Compliance Region Marking UL Mark USA/Canada CE Mark Europe EMC Marking (Class A) Canada CANADA ICES-003 C[...]

  • Page 112

    Regulatory and Certification Information IntelP®P Serv er Board S3420GP TPS Revision 1.0 Intel order number E65697-003 98 Other Recycling Package Marking (Marked on packaging label) Other Recycling Package Marks Other Recycling Package Marking (Marked on packaging label) CA. Lithium Perchlorate insert Perchlorate Material – Special handling may [...]

  • Page 113

    IntelP®P Serv 10.3 10.3.1 This device complies with Part 15 of the FCC Rules. Operation is subject to two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Intel Corporation 5200 N.E. Elam Young Parkway Hillsboro, OR [...]

  • Page 114

    Regulatory 100 10.3.2 ICES-003 Cet appareil numérique respecte les limites bruits radioélectriques applicables aux appareils numériques de Classe B prescrites dans la norme sur le matériel brouilleur: “Appareils Numériques”, NMB-003 édictée par le Ministre Canadian des Communications. English translation of the notice above: This digital[...]

  • Page 115

    IntelP®P Serv 10.3.5 BSMI The BSMI Certification Marking and EMC warning is located on the outside rear area of the product. 10.3.6 RRL Following is the English translation of the notice above: 10.3.7 CNCA er Board S3420GP TPS Regulatory and Certification Information Revision 1.0 Intel order number E65697-003 101 (Taiwan) (Korea) RRL certification[...]

  • Page 116

    Appendix A: Integration and Usage Tips 102 IntelP®P Server Board S3420GP TPS Revision 1.0 Intel order number E65697-003 Appendix A: Integration and Usage Tips  When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-Volt standby is still present even thoug[...]

  • Page 117

    IntelP®P Server Board S3420GP TPS Appendix B: Integrated BMC Sensor Tables Appendix B: Integrated BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platf[...]

  • Page 118

    Appendix B: Integrated BMC Sensor Tables IntelP®P Server Board S3420GP TPS  Rearm Sensors The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indi cates the type supported by the sensor. The fol[...]

  • Page 119

    IntelP®P Server Board S3420GP TPS Appendix B: Integrated BMC Sensor Tables Revision 1.0 Intel order number E65697-003 105 Table 66. Integrated BMC Core Sensors Sensor Name 3 Sensor # Platform A pplicabilit y Sensor Type Event / Reading Type Event Offset Triggers Contrib. To System Status A ssert / De- assert Readabl e Value / Offsets Event Data Re[...]

  • Page 120

    Appendix B: Integrated BMC Sensor Tables 106 IntelP®P Server Board S3420GP TPS Revision 1.0 Intel order number E65697-003 Sensor Name 3 Sensor # Platform A pplicabilit y Sensor Type Event / Reading Type Event Offset Triggers Contrib. To System Status A ssert / De- assert Readabl e Value / Offsets Event Data Rearm Stand -by BB +1.1V P1 Vccp 11h All[...]

  • Page 121

    IntelP®P Server Board S3420GP TPS Appendix B: Integrated BMC Sensor Tables Revision 1.0 Intel order number E65697-003 107 Sensor Name 3 Sensor # Platform A pplicabilit y Sensor Type Event / Reading Type Event Offset Triggers Contrib. To System Status A ssert / De- assert Readabl e Value / Offsets Event Data Rearm Stand -by BB +5.0V 19h All Voltage[...]

  • Page 122

    Appendix B: Integrated BMC Sensor Tables 108 IntelP®P Server Board S3420GP TPS Revision 1.0 Intel order number E65697-003 Sensor Name 3 Sensor # Platform A pplicabilit y Sensor Type Event / Reading Type Event Offset Triggers Contrib. To System Status A ssert / De- assert Readabl e Value / Offsets Event Data Rearm Stand -by Fan Tach Sensors 30h– [...]

  • Page 123

    IntelP®P Server Board S3420GP TPS Appendix C: POST Code Diagnostic LED Decoder Appendix C: POST Code Diagnostic LED Decoder During the system boot process, the BIOS ex ecutes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST [...]

  • Page 124

    Appendix C: POST Code Diagnostic LED Decoder IntelP®P Server Board S3420GP TPS MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED #7 #6 #5 #4 #3 #2 #1 #0 Host Processor 0x04h X X X X X O X X Early processor initialization (flat 32.asm) where sy stem BSP is selected 0x10h X X X O X X X X Pow er-on initialization of the host processor (Boot Strap Processor) 0x11h [...]

  • Page 125

    IntelP®P Server Board S3420GP TPS Appendix C: POST Code Diagnostic LED Decoder Diagnostic LED Decoder O = On, X=Off Upper Nibble Lower Nibble MSB LSB Checkpoint 8h 4h 2h 1h 8h 4h 2h 1h LED #7 #6 #5 #4 #3 #2 #1 #0 Description 0x93h O X X O X X O O Enabling the keyboard 0x94h O X X O X O X X Clearing keyboard input buffer 0x95h O X X O X O X O Reser[...]

  • Page 126

    Appendix C: POST Code Diagnostic LED Decoder IntelP®P Server Board S3420GP TPS Diagnostic LED Decoder O = On, X=Off Upper Nibble Lower Nibble MSB LSB Checkpoint 8h 4h 2h 1h 8h 4h 2h 1h LED #7 #6 #5 #4 #3 #2 #1 #0 Description Pre-EFI Initialization Module (PEIM) / Recov ery 0x30h X X O O X X X X Crisis recovery has been initiated because of a user [...]

  • Page 127

    IntelP®P Server Board S3420GP TPS Appendix D: POST Code Errors Appendix D: POST Code Errors Whenever possible, the BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to t[...]

  • Page 128

    Appendix D: POST Code Errors IntelP®P Server Board S3420GP TPS Error Code Error Message Response 8111 Processor 02 internal error (IERR) on last boot Pause 8120 Processor 01 thermal trip error on last boot Pause 8121 Processor 02 thermal trip error on last boot Pause 8130 Processor 01 disabled Pause 8131 Processor 02 disabled Pause 8140 Processor [...]

  • Page 129

    IntelP®P Server Board S3420GP TPS Appendix D: POST Code Errors Error Code Error Message Response 8549 DIMM_C2 Disabled. Pause 854A DIMM_C3 Disabled. Pause 854B DIMM_C4 Disabled. Pause 854C DIMM_D1 Disabled. Pause 854D DIMM_D2 Disabled. Pause 854E DIMM_D3 Disabled. Pause 854F DIMM_D4 Disabled. Pause 8560 DIMM_A1 Component encountered a Serial Pres [...]

  • Page 130

    Appendix D: POST Code Errors IntelP®P Server Board S3420GP TPS Error Code Error Message Response 85A7 DIMM_B4 Uncorrectable E CC error encountered. Pause 85A8 DIMM_C1 Uncorrectable ECC error encountered. Pause 85A9 DIMM_C2 Uncorrectable ECC error encountered. Pause 85AA DIMM_C3 Uncorrectable E CC error encountered. Pause 85AB DIMM_C4 Uncorrectable[...]

  • Page 131

    IntelP®P Server Board S3420GP TPS Appendix D: POST Code Errors Error Code Error Message Response 0xA500 ATA/ATPI AT A bus SMAR T not supported. No Pause 0xA501 ATA/AT PI ATA SMART is disabled. No Pause 0xA5A0 PCI Express* component encountered a PERR error. No Pause 0xA5A1 PCI Express* component encountered a SERR error. Halt 0xA5A4 PCI Express* I[...]

  • Page 132

    Appendix E: Supported IntelP®P Server Chassis IntelP®P Server Board S3420GP TPS Revision 1.0 Intel order number E65697-003 118 Appendix E: Supported Intel P ® P Server Chassis The Intel P ® P Server Board S3420GP is supported in the following Intel server chassis:  Intel P ® P Server Chassis SR1630  Intel P ® P Server Chassis SC5650UP[...]

  • Page 133

    IntelP®P Server Board S3420GP TPS Glossary Revision 1.0 Intel order number E65697-003 119 Glossary This appendix contains important terms used in this document. For ease of use, numeric entries are listed first (for example, “82460GX”) follow ed by alpha entries (for example, “AGP 4x”). Acronyms are followed by non-acronyms. Term Definitio[...]

  • Page 134

    Glossary IntelP®P Serv er Board S3420GP TPS Revision 1.0 Intel order number E65697-003 120 Term Definition ICH I/O Controller Hub ICMB Intelligent Chassis Management Bus IERR Internal Error IFB I/O and Firmware Bridge ILM Independent Loading Mechanism IMC Integrated Memory Controller INTR Interrupt I/OAT I/O Acceleration Technology IOH I/O Hub IP [...]

  • Page 135

    IntelP®P Server Board S3420GP TPS Glossary Revision 1.0 Intel order number E65697-003 121 Term Definition PSMI Power Supply Management Interface PWM Pulse-Width Modulation QPI QuickPath Interconnect RAM Random Access Memory RASUM Reliability, Availability, Se rviceability , Usability, and Manageability RISC Reduced Instruction Set Computing RMII R[...]

  • Page 136

    Reference Documents IntelP®P Server Board S3420GP TPS Revision 1.0 Intel order number E65697-003 122 Reference Documents Refer to the following documents for additional information:  Intel P ® P Server Board S3420GP BIOS External Product Specification  Intel P ® P Server Board S3420GP Common Core Integrated BMC External Product Specificati[...]